Scanning signal line drive circuit and display device including the same

Abstract

To suppress the occurrence of a display defect due to hot carrier deterioration of a thin film transistor in a scanning signal line drive circuit in a display device including a GDM panel having a high drive voltage.SOLUTION: A scanning line drive circuit as a GDM circuit is composed of a plurality of cascade-connected unit circuits and is operated by a multi-phase clock signal in which pulses partially overlap. An n-th stage unit circuit includes: an internal node; a diode-connected set transistor connected to a set input terminal; a reset transistor including a drain terminal connected to the internal node, a source terminal connected to a reset state voltage terminal, and a gate terminal connected to the reset input terminal; and an output circuit including an output transistor connected to a clock input terminal and a capacitor. A scanning signal G(n-2) is given to the set input terminal, a scanning signal G(n+2) is given to the reset input terminal, and a scanning signal G(n+1) is given to the reset state voltage terminal VR, respectively.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The following disclosure relates to a display device, and more particularly to a scanning signal line driving circuit for driving scanning signal lines arranged in a display unit of the display device. [Background technology]

[0002] Active matrix display devices have been known in the past, each having a display section including a plurality of data signal lines (also called "data lines"), a plurality of scanning signal lines (also called "gate lines") intersecting the plurality of data signal lines, and a plurality of pixel formation sections arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines. Such active matrix display devices include a data signal line drive circuit (also called a "data driver" or "source driver") for driving the plurality of data signal lines and a scanning signal line drive circuit (also called a "gate driver") for driving the plurality of scanning signal lines. The scanning signal line drive circuit applies a plurality of scanning signals to the plurality of scanning signal lines so that the plurality of scanning signal lines are sequentially selected during each frame period. The data signal line drive circuit applies a plurality of data signals representing an image signal to be displayed to the plurality of data signal lines in conjunction with this sequential selection of the plurality of scanning signal lines. This provides a plurality of pixel data constituting image data representing an image to be displayed to the plurality of pixel formation sections, respectively.

[0003] In active matrix display devices, scanning signal line driver circuits have traditionally been mounted as integrated circuit (IC) chips on the periphery of a substrate constituting a display panel including the display unit. However, in recent years, scanning signal line driver circuits have increasingly been formed directly on the substrate. Such scanning signal line driver circuits are called "monolithic gate drivers" or "GDM circuits," and display panels incorporating such scanning signal line driver circuits are called "gate driver monolithic panels" or "GDM panels." In GDM panels, scanning signals are input to the display unit (the display area) from a gate driver, which serves as the scanning signal line driver circuit formed in the frame area. In such GDM panels, the gate driver can be formed on a small area of ​​glass by using thin-film transistors (hereinafter abbreviated as "TFTs") with a channel layer formed of an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide), allowing for a narrower frame. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-181083 Summary of the Invention [Problem to be solved by the invention]

[0005] The monolithic gate driver (GDM circuit) is formed using thin film transistors (TFTs) on a substrate that constitutes a display panel. In display panels such as liquid crystal panels that include such GDM circuits, i.e., gate driver monolithic panels, the TFTs included in the GDM circuit can suffer from degradation of their characteristics due to voltage stress and other factors. In particular, when the GDM circuit is driven at a high voltage for high-frequency operation, the voltage stress applied to the TFTs increases, causing degradation of the TFT characteristics known as hot carrier degradation, which can lead to display defects. In recent years, the trend toward larger display panels and higher drive frequencies has led to increased drive voltages, increasing the likelihood of display defects caused by hot carrier degradation of the TFTs.

[0006] Therefore, in a display device including a gate driver monolithic panel with a high driving voltage, it is required to suppress the occurrence of display defects caused by hot carrier degradation of TFTs in a scanning signal line driving circuit. [Means for solving the problem]

[0007] (1) A scanning signal line driving circuit according to some embodiments of the present invention is a scanning signal line driving circuit that drives a plurality of scanning signal lines arranged in a display unit of a display device, a plurality of unit circuits connected in cascade to form a shift register; each unit circuit is configured to determine a state of the unit circuit based on a set signal and a reset signal given as input signals; an internal node selectively holding voltages of first and second logic levels that indicate the state of each of the unit circuits; a set circuit that applies a voltage of the first logic level to the internal node when the set signal is active; a reset circuit that applies a voltage of the second logic level to the internal node when the reset signal is active; the reset circuit includes a reset transistor having a drain terminal connected to the internal node, a source terminal, and a gate terminal to which the reset signal is applied; The shift register is configured such that, in each unit circuit, when the reset signal changes from an inactive state to an active state, an active voltage level corresponding to the active state of the reset signal is maintained, and a voltage signal that changes from the active voltage level to the second logic level before the reset signal changes from the active state to the inactive state is applied to the source terminal of the reset transistor as a reset state voltage signal.

[0008] (2) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes the configuration of (1) above, the shift register operates based on a multiphase clock signal; the multiphase clock signal is composed of a plurality of clock signals that cyclically correspond to the plurality of unit circuits; a pulse of one of two adjacent clock signals among the plurality of clock signals partially overlaps with a pulse of the other of the two adjacent clock signals; the plurality of unit circuits respectively correspond to the plurality of scanning signal lines; Each unit circuit is an output circuit including an output transistor that is in an on state when the internal node holds a voltage of the first logic level and that is in an off state when the internal node holds a voltage of the second logic level; a clock input terminal for receiving a corresponding one of the plurality of clock signals; an output terminal connected to a corresponding one of the plurality of scanning signal lines and connected to the clock input terminal via the output transistor; the output circuit outputs a scanning signal based on the corresponding clock signal from the output terminal to the corresponding scanning signal line; The shift register is configured such that, in each unit circuit, a scanning signal output from a unit circuit subsequent to the current stage is applied to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from an output circuit in a unit circuit subsequent to the current stage is applied to the gate terminal of the reset transistor as the reset signal.

[0009] (3) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes the configuration of (2) above, The number of phases k of the multi-phase clock signal is an integer equal to or greater than 3, and the duty ratio D of the multi-phase clock signal is expressed by the following inequality: 1 / k <D≦1-1 / k Fulfilling The shift register is configured such that, in each unit circuit, a scanning signal output from the unit circuit one stage before the current stage or a signal equivalent to the scanning signal is supplied to the set circuit as the set signal, a scanning signal output from the unit circuit one stage after the current stage is supplied to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from the unit circuit two stages after the current stage is supplied to the gate terminal of the reset transistor as the reset signal.

[0010] (4) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes the configuration of (2) above, The number of phases k of the multiphase clock signal is an integer equal to or greater than 4, and the duty ratio D is expressed by the following inequality: 1 / k <D≦1-2 / k Fulfilling The shift register is configured such that, in each unit circuit, a scanning signal output from the unit circuit two stages before the current stage or a signal equivalent to the scanning signal is supplied to the set circuit as the set signal, a scanning signal output from the unit circuit one stage after the current stage is supplied to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from the unit circuit two stages after the current stage is supplied to the gate terminal of the reset transistor as the reset signal.

[0011] (5) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes the configuration of (2) above, The shift register is configured such that in each unit circuit, a scanning signal output from a unit circuit in a previous stage or a signal equivalent to the scanning signal is given to the set circuit as the set signal.

[0012] (6) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes any one of the configurations (1) to (5) above, The set circuit includes a transistor in a diode-connected configuration having a drain terminal and a gate terminal to which the set signal is applied and a source terminal connected to the internal node.

[0013] (7) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes any one of the configurations (1) to (6) above, The reset transistor is a thin film transistor.

[0014] (8) Furthermore, a scanning signal line driving circuit according to some embodiments of the present invention includes the configuration of (7) above, The reset transistor is a thin film transistor in which a channel layer is formed of an oxide semiconductor.

[0015] (9) Furthermore, a display device according to some embodiments of the present invention includes the scanning signal line drive circuit according to any one of (1) to (8), The scanning signal line driving circuit and the display section are integrally formed on the same substrate. [Effects of the Invention]

[0016] In some of the above embodiments of the present invention, a scanning signal line drive circuit that drives a plurality of scanning signal lines arranged in a display unit of a display device includes a shift register formed of a plurality of cascade-connected unit circuits. Each unit circuit is configured to determine a state of the unit circuit based on a set signal and a reset signal provided as input signals, and includes an internal node that selectively holds voltages of first and second logic levels indicating the state of the unit circuit, a set circuit that provides a voltage of the first logic level to the internal node when the set signal is active, and a reset circuit that provides a voltage of the second logic level to the internal node when the reset signal is active. The shift register is configured so that a reset-state voltage signal is provided to the source terminal of the reset transistor, and the reset-state voltage signal maintains an active voltage level corresponding to the active state of the reset signal when the reset signal changes from an inactive state to an active state, and changes from the active voltage level to the second logic level before the reset signal changes from the active state to the inactive state. According to this configuration, in a unit circuit in which a voltage of the first logic level is held at the internal node, when the gate-source voltage of the reset transistor changes from an off state to an on state in response to a transition of the reset-state voltage signal from the active voltage level to the second logic level, the drain-source voltage of the reset transistor is small at the point in time when the gate-source voltage of the reset transistor reaches a value close to the threshold voltage of the reset transistor (see FIG. 10 ). Furthermore, when the gate-source voltage of the reset transistor exceeds its threshold voltage during this transition, the reset transistor turns on, thereby discharging the internal node and changing its voltage toward the second logic level, and then the drain-source voltage also decreases. Therefore, according to some of the above-described embodiments of the present invention, even when the scan signal driving circuit is realized as a monolithic gate driver that drives a display unit at a high driving voltage, hot carrier degradation of the reset transistor is suppressed or mitigated, thereby preventing display defects caused by hot carrier degradation. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a block diagram showing the overall configuration of a display device according to a first embodiment. [Figure 2] FIG. 3 is a circuit diagram showing an electrical configuration of a pixel formation portion in the first embodiment. [Figure 3] FIG. 2 is a circuit diagram for explaining a configuration of a scanning signal line driving circuit in the first embodiment. [Figure 4] FIG. 4 is a signal waveform diagram for explaining the operation of the scanning signal line driving circuit in the first embodiment. [Figure 5] FIG. 3 is a circuit diagram showing a configuration of a unit circuit of a scanning signal line driving circuit in the first embodiment. [Figure 6] FIG. 6 is a signal waveform diagram for explaining the operation of the unit circuit of FIG. 5 according to the first embodiment. [Figure 7] FIG. 10 is a circuit diagram showing the configuration of a unit circuit of a conventional scanning signal line driving circuit. [Figure 8] 10A and 10B are signal waveform diagrams for explaining the operation of the unit circuit of the conventional scanning signal line driving circuit. [Figure 9] 10A and 10B are diagrams for explaining problems in the unit circuits of the conventional scanning signal line driving circuit. [Figure 10] FIG. 4 is a diagram for explaining the effect of the first embodiment. [Figure 11] FIG. 10 is a circuit diagram illustrating the configuration of a scanning signal line driving circuit in a display device according to a second embodiment. [Figure 12] FIG. 10 is a signal waveform diagram for explaining the operation of the scanning signal line driving circuit in the second embodiment. [Figure 13] FIG. 10 is a circuit diagram showing a configuration of a unit circuit of a scanning signal line driving circuit in the second embodiment. [Figure 14] FIG. 14 is a signal waveform diagram for explaining the operation of the unit circuit of FIG. 13 according to the second embodiment. [Figure 15] FIG. 10 is a signal waveform diagram for explaining conditions that should be satisfied by k-phase clock signals used in the scanning signal line driving circuit according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that, although all transistors in this embodiment are N-channel, the present invention is not limited to this. Furthermore, in an N-channel transistor, the one of the two conduction terminals with the higher potential is the drain terminal and the one with the lower potential is the source terminal. However, in this specification, even if the potentials of the two conduction terminals are reversed during operation, one of the two conduction terminals will be fixedly referred to as the "drain terminal" and the other as the "source terminal." Furthermore, in this specification, unless otherwise specified, "connection" means "electrical connection," and includes not only direct connection but also indirect connection via another element, within the scope of the present invention.

[0019] <1. First embodiment> <1.1 Overall configuration and operation overview> FIG. 1 is a block diagram showing the overall configuration of a display device 100 according to a first embodiment. The display device 100 is an active matrix liquid crystal display device, and as shown in FIG. 1, includes a display control circuit 200, a data signal line drive circuit 300, a scanning signal line drive circuit 400, and a display unit 500 that constitutes a liquid crystal panel 600 as a display panel. In this embodiment, the scanning signal line drive circuit 400 and the display unit 500 are formed on the same substrate (on an active matrix substrate, which is one of the two substrates included in the liquid crystal panel 600). In other words, the scanning signal line drive circuit 400 is a monolithic gate driver (GDM circuit).

[0020] The display unit 500 is provided with a plurality (M) of data signal lines DL1 to DLM, a plurality (N) of scanning signal lines GL1 to GLN intersecting the plurality of data signal lines DL1 to DLM, and a plurality (M×N) of pixel formation portions Ps(i, j) (i=1 to N, j=1 to M) arranged in a matrix along the plurality of data signal lines DL1 to DLM and the plurality of scanning signal lines GL1 to GLN. Each pixel formation portion Ps(i, j) corresponds to one of the plurality of data signal lines DL1 to DLM and one of the plurality of scanning signal lines GL1 to GLN.

[0021] 2 is a circuit diagram showing the electrical configuration of one pixel formation portion Ps(i,j) in the display unit 500. As shown in FIG. 2, each pixel formation portion Ps(i,j) comprises an N-channel thin film transistor (TFT) 10 as a pixel switching element, the gate terminal of which is connected to a corresponding scanning signal line GLi and the source terminal of which is connected to a corresponding data signal line DLj, a pixel electrode Ep connected to the drain terminal of the transistor 10, a common electrode Ec as a counter electrode provided in common to the plurality of pixel formation portions Ps(i,j) (i=1 to N, j=1 to M), and a liquid crystal layer provided in common to the plurality of pixel formation portions Ps(i,j) (i=1 to N, j=1 to M) and sandwiched between the pixel electrode Ep and the common electrode Ec. A pixel capacitance Cp is formed by a liquid crystal capacitance Clc formed by the pixel electrode Ep and the common electrode Ec.

[0022] In this embodiment, the thin-film transistor 10 in the pixel formation portion Ps(i,j) is a thin-film transistor (oxide TFT) using an oxide semiconductor such as IGZO for its channel layer, but is not limited thereto. For example, the thin-film transistor 10 may be a thin-film transistor using amorphous silicon for its channel layer (a-Si TFT) or a thin-film transistor using low-temperature polysilicon for its channel layer (LTPS-TFT). Furthermore, the liquid crystal panel 600 serving as the display panel in this embodiment is a GDM panel in which a pixel circuit made of elements formed on a TFT substrate in the pixel formation portion Ps constituting the display unit 500 and a scanning signal line drive circuit are integrally formed. The transistor in the pixel formation portion Ps(i,j) and the transistor included in the scanning signal line drive circuit are thin-film transistors whose channel layers are formed of the same type of semiconductor.

[0023] The display control circuit 200 receives an externally applied image signal DAT and timing control signal TG, and outputs a digital video signal DV, a data-side control signal SCT for controlling the operation of the data signal line drive circuit 300, and a scan-side control signal GCT for controlling the scan signal line drive circuit 400. The data-side control signal SCT includes a data start pulse signal, a data clock signal, a latch strobe signal, etc. The scan-side control signal GCT includes a gate start pulse signal, a gate clock signal, etc. In this embodiment, the scan signal line drive circuit 400 operates in accordance with a four-phase gate clock signal (hereinafter simply referred to as a "four-phase clock signal") consisting of first to fourth clock signals CK1 to CK4.

[0024] The data signal line driving circuit 300 applies data signals D1 to DM to the data signal lines DL1 to DLM, respectively, based on the digital video signal DV and the data-side control signal SCT from the display control circuit 200. At this time, the data signal line driving circuit 300 sequentially holds the digital video signal DV indicating the voltage to be applied to each data signal line DL at the timing when a pulse of the data clock signal is generated. Then, the held digital video signal DV is converted into an analog voltage at the timing when a pulse of the latch strobe signal is generated. The converted analog voltage is simultaneously applied to all the data signal lines DL1 to DLM as the data signals D1 to DM.

[0025] The scanning signal line driving circuit 400 is disposed on one end side of the scanning signal lines GL1 to GLN and applies scanning signals G(1) to G(N) to the scanning signal lines GL1 to GLN, respectively, based on a scanning-side control signal GCT from the display control circuit 200. As a result, active scanning signals (high-level scanning signals in this embodiment) are sequentially applied to the scanning signal lines GL1 to GLN in each frame period, and the application of active scanning signals to each scanning signal line GL1i (i = 1 to N) is repeated every frame period. Note that in the configuration shown in FIG. 1, the scanning signal line driving circuit 400 is realized as a single circuit and disposed on one side of the display unit 500, but the scanning signal line driving circuit 400 may also be configured to be separated and disposed on one side and the other side of the display unit 500. This also applies to other embodiments described later.

[0026] A backlight unit (not shown) is provided on the rear side of the display panel 600, which irradiates the rear of the display panel 600 with backlight. This backlight unit is also driven by the display control circuit 200, but may be driven by other methods. Note that if the display panel 600 is a reflective liquid crystal panel, the backlight unit is not necessary.

[0027] In this manner, data signals D1 to DM are applied to the data signal lines DL1 to DLM, and scanning signals G(1) to G(N) are applied to the scanning signal lines GL1 to GLN. A predetermined common voltage Vcom is supplied to the common electrode Ec from a power supply circuit (not shown). A signal for driving the backlight is also supplied to the backlight. By driving the data signal lines DL1 to DLM, scanning signal lines GL1 to GLN, common electrode Ec, and backlight in the display unit 500, pixel data based on the digital video signal DV is written to each pixel formation portion Ps(i,j), and light is irradiated from the backlight onto the back surface of the display panel 600, whereby an image represented by an externally applied image signal DAT is displayed on the display unit 500.

[0028] 1.2 Configuration and operation of the scanning signal line driving circuit In this embodiment, as shown in FIG. 1, N×M pixel formation portions Ps(1,1) to PS(N,M) are provided in the display unit 500. Hereinafter, M pixel formation portions Ps(i,1) to Ps(i,M) arranged in the direction of extension of the scanning signal lines GLi among these N×M pixel formation portions Ps(1,1) to PS(N,M) will be referred to as a "pixel row" or simply as a "row" (i = 1 to N). The scanning signal line driving circuit 400 in this embodiment is configured with a shift register that operates with a four-phase clock signal. Hereinafter, the circuits constituting each stage of this shift register will be referred to as a "unit circuit" (the same applies to other embodiments). This shift register 401 includes N unit circuits 4(1) to 4(N) that correspond one-to-one to the N pixel rows Pix(1,1) to Pix(1,M), Pix(2,1) to Pix(2,M), ..., Pix(N,1) to Pix(N,M).

[0029] Fig. 3 is a circuit diagram illustrating a schematic configuration of a shift register 401 that constitutes the scanning signal line driving circuit 400 in this embodiment, and Fig. 4 is a signal waveform diagram illustrating the operation of the scanning signal line driving circuit 400 that is constituted by the shift register 401 shown in Fig. 3. The configuration and operation of this scanning signal line driving circuit 400 will be described below with reference to Figs. 3 and 4.

[0030] <1.2.1 Configuration of the scanning signal line driver circuit> The N unit circuits 4(1) to 4(N) included in the shift register 401 constituting the scanning signal line driving circuit 40 are cascade-connected as shown in FIG. 3 , and each unit circuit 4(i) (i = 1 to N) has a clock input terminal CK, a set input terminal S, a reset input terminal R, a reset-state voltage terminal VR, and an output terminal Q. Hereinafter, signals to be applied to the clock input terminal CK, the set input terminal S, the reset input terminal R, and the reset-state voltage terminal VR will be referred to as the clock signal CK, the set signal S, the reset signal R, and the reset-state voltage signal VR, respectively, and a signal to be output from the output terminal Q will be referred to as the stage output signal Q (here, the same symbol will be used for both the terminal and the signal to be applied to or output from the terminal). Note that dummy unit circuits may be cascade-connected from the Nth stage onward to generate the reset signal R and the reset-state voltage signal VR to be input to the unit circuits 4(n) (n≦N) up to the Nth stage. This also applies to other embodiments.

[0031] In this embodiment, the gate start pulse signal from the display control circuit 200 is composed of a first start pulse signal SP1 and a second start pulse signal SP2, each including one pulse per frame period, as shown in Fig. 4. As shown in Fig. 3, the first start pulse signal SP1 and the second start pulse signal SP2 are respectively provided to the set input terminals S of the first-stage unit circuit 4(1) and the second-stage unit circuit 4(2) in the shift register 401. The first to fourth clock signals CK1 to CK4 shown in Fig. 4, which constitute a four-phase clock signal, correspond cyclically to the unit circuits 4(1), 4(2), 4(3), ... connected in cascade in the shift register 401, and a corresponding clock signal from the first to fourth clock signals CK1 to CK4 is provided to the clock input terminal CK of each unit circuit 4(i). Furthermore, the N-stage unit circuits 4(1) to 4(N) correspond to N scanning signal lines GL1 to GLN, respectively, and the output terminal Q of each unit circuit (i) is connected to the corresponding scanning signal line GL(i) among the N scanning signal lines GL1 to GLN. Therefore, the stage output signal Q of the n-th stage unit circuit (n) is applied to the n-th scanning signal line GLn as a scanning signal G(n). For ease of explanation, even when n=1 or 2, it is assumed below that in the unit circuit 4(n), the output terminal Q of the unit circuit 4(n-2) two stages before is connected to the set input terminal S, and the scanning signal G(n-2), which is the stage output signal Q of the unit circuit 4(n-2) two stages before, is applied to the set input terminal S.

[0032] As shown in Figure 3, in the nth unit circuit 4(n) (1≦n≦N), the output terminal Q of the unit circuit 4(n-2) two stages earlier is connected to the set input terminal S, the output terminal Q of the unit circuit 4(n+2) two stages later is connected to the reset input terminal R, and the output terminal Q of the unit circuit 4(n+1) in the next stage (one stage later) is connected to the reset state voltage terminal VR.

[0033] <1.2.2 Unit circuit> 5 is a circuit diagram showing the configuration of an n-th stage unit circuit 4(n) in this embodiment (1≦n≦N). As shown in Fig. 5, the unit circuit 4(n) includes three N-channel transistors T1 to T3 (all of the transistors T1 to T3 are oxide TFTs, hereinafter referred to as "output transistor T1," "set transistor T2," and "reset transistor T3") that function as switching elements, and one capacitor C1. In this unit circuit 4(n), the clock signal corresponding to the unit circuit 4(n) among the first to fourth clock signals CK1 to CK4 is supplied to the clock input terminal CK as the input clock signal CKp, the scanning signal G(n-2) output from the unit circuit 4(n-2) two stages before is supplied to the set input terminal S, the scanning signal G(n+2) output from the unit circuit 4(n+2) two stages after is supplied to the reset input terminal R, the scanning signal G(n+1) output from the unit circuit 4(n+1) of the next stage is supplied to the reset state voltage terminal VR, and the stage output signal Q is output from the output terminal of the unit circuit 4(n) as the scanning signal G(n) and applied to the nth scanning signal line GLn.

[0034] The unit circuit 4(n) has an internal node NA that selectively holds a high-level (H level) voltage as a first logic level indicating the state of the unit circuit 4(n) and a low-level (L level) voltage as a second logic level indicating the state of the unit circuit 4(n). When the voltage of the first logic level is held at the internal node NA, the unit circuit 4(n) is in a set state, and when the voltage of the second logic level is held at the internal node NA, the unit circuit 4(n) is in a reset state. As shown in FIG. 5, the set transistor T2 has a drain terminal connected to the set input terminal S and a source terminal connected to the internal node NA, and its gate terminal is connected to the drain terminal, forming a diode-connected configuration. The reset transistor T3 has a drain terminal connected to the internal node NA, a source terminal connected to the reset state voltage terminal VR, and a gate terminal connected to the reset input terminal R. The output transistor T1 has a drain terminal connected to the clock input terminal CK, a source terminal connected to the output terminal Q, and a gate terminal connected to the internal node NA. The capacitor C1 has a first terminal connected to the source terminal and a second terminal connected to the gate terminal of the output transistor T1, respectively, and functions as a so-called bootstrap capacitance. In the unit circuit 4(n), the set transistor T2 in a diode connection configuration forms a set circuit 42, the reset transistor T3 forms a reset circuit 43, and the output transistor T1 and capacitor C1 form an output circuit 41. The set circuit 42 is not limited to the configuration shown in Fig. 5, and may be configured to supply a high-level voltage to the internal node NA only when the signal applied to the set input terminal S is high.

[0035] <1.2.3 Operation of the scanning signal line driver circuit> Fig. 6 is a signal waveform diagram for explaining the operation of the unit circuit 4(n) shown in Fig. 5. Hereinafter, the operation of the scanning signal line driving circuit 400 will be explained with reference to Fig. 6 as well as Fig. 4.

[0036] 6, in the unit circuit 4(n), at time t1, the scanning signal G(n-2) as the set signal S, the scanning signal G(n+2) as the reset signal R, the scanning signal G(n+1) as the reset state voltage signal VR, the voltage of the internal node NA, and the scanning signal G(n) as the stage output signal Q are all at the L level. At this time, the transistors T1 to T3 are all in the off state.

[0037] When a clock signal CK and a scanning signal G(n-2) as a set signal S as shown in FIG. 6 are applied to the clock input terminal CK and the set input terminal S, respectively, a voltage of H level as a first logic level is applied from the set input terminal S to the internal node NA via the diode-connected set transistor T2 during the period from time t2 to time t3 (period t2 to t3). As a result, the voltage of the internal node NA becomes H level as the first logic level, and the output transistor T1 is turned on. When the transistor T1 is turned on, the input clock signal CKp applied to the clock input terminal CK is output from the output terminal Q as the scanning signal G(n). This scanning signal G(n) changes from L level to H level at time t3, which pushes up the voltage of the internal node NA via the capacitor C1 to a voltage higher than H level. As a result, the output transistor T1 is turned on completely, and the voltage of the scanning signal G(n) output to the scanning signal line GLn becomes H level completely, and the scanning signal line GLn is selected.

[0038] Then, at time t4, the input clock signal CKp changes from H level to L level, causing the scanning signal G(n) output from the output terminal Q to change from H level to L level, discharging the scanning signal line GLn and setting it to a non-selected state. In addition, the voltage of the internal node NA drops in response to the change of the scanning signal G(n) from H level to L level.

[0039] In this way, the scanning signal G(n) output from the unit circuit 4(n) becomes H level during the period t3 to t4 and remains L level until the time corresponding to time t3 in the next frame period. As described above, the first to fourth clock signals CK1 to CK4 as shown in FIG. 4 correspond cyclically to the unit circuits 4(1), 4(2), 4(3), 4(4)... in the scanning signal line driving circuit 400 (FIG. 3), and each unit circuit 4(i) is supplied with a corresponding clock signal from the first to fourth clock signals CK1 to CK4 as an input clock signal CKp. As a result, in adjacent unit circuits 4(i) and 4(i+1), the pulses of the clock signals input thereto partially overlap (see FIG. 4), and as a result, the pulses of the output scanning signals G(i) and G(i+1) also partially overlap. Therefore, in unit circuits 4(1), 4(2), 4(3), 4(4), ..., the voltages of internal nodes NA(1), NA(2), NA(3), NA(4), ... and scanning signals G(1), G(2), G(3), G(4), ... as stage output signals Q change as shown in Figure 4. In Figure 4, "NA(i)" indicates the voltage of internal node NA in unit circuit 4(i) of the i-th stage.

[0040] As described above, a clock signal is input to each unit circuit 4(i) (i=1, 2, 3, 4, ...) in the scanning signal line driving circuit 400. Therefore, in the nth unit circuit 4(n) shown in FIG. 5, as shown in FIG. 6, the pulse of the nth scanning signal G(n), which is the stage output signal Q, partially overlaps with the pulse of the n+1th scanning signal G(n+1) supplied to the reset state voltage terminal VR, and the pulse of the n+1th scanning signal G(n+1) partially overlaps with the n+2th scanning signal G(n+2) supplied to the reset input terminal R.

[0041] 4 and 6, the first clock signals CK1 to CK4 are shifted in phase by 1 / 4 cycle, and the duty ratio, which is the ratio of the H-level period (pulse duration) to the clock cycle, is 1 / 2. Therefore, in the unit circuit 4(n), as shown in Fig. 6, at time t34, which is 1 / 4 cycle after the scanning signal G(n), which is the stage output signal Q, changes from L level to H level at time t3, the scanning signal G(n+1) supplied to the reset state voltage terminal VR changes from L level to H level, and at time t4, which is 1 / 4 cycle after time t34, the scanning signal G(n), which is the stage output signal Q, changes to L level, and the scanning signal G(n+2) supplied to the reset input terminal R changes from L level to H level. Then, at time t45, which is 1 / 4 of a cycle after time t4, the scanning signal G(n+1) applied to the reset state voltage terminal VR changes to L level, and at time t5, which is 1 / 4 of a cycle after time t45, the scanning signal G(n+2) applied to the reset input terminal R changes to L level.

[0042] During the process in which the scanning signals G(n+1) and G(n+2) applied to the reset state voltage terminal VR and reset input terminal R of the unit circuit 4(n), respectively, change as described above, at time t4, the scanning signal G(n+2) serving as the reset signal R changes from L level to H level. At this time, the reset transistor T3 maintains its OFF state because the scanning signal G(n+1) serving as the reset state voltage signal VR applied to its source terminal is H level. As a result, the voltage of the internal node NA remains H level as the first logic level even after time t4 has passed. Thereafter, at time t45, the scanning signal G(n+1) serving as the reset state voltage signal VR applied to its source terminal changes to L level, and the scanning signal G(n+2) serving as the reset signal R applied to its gate terminal is H level, so the reset transistor T3 changes to the ON state. As a result, the internal node NA is discharged and its voltage changes to L level as the second logic level. After that, at time t5, the scanning signal G(n+2) as the reset signal R given to the gate terminal of the reset transistor T3 changes to the L level, thereby turning the reset transistor T3 off.

[0043] <1.2.4 Problems with conventional scanning signal line driving circuits> Next, before describing the effects of the scanning signal line driving circuit 400 according to this embodiment as described above, problems with conventional scanning signal line driving circuits will be described with reference to FIGS.

[0044] 7 is a circuit diagram showing the configuration of an n-th stage unit circuit 4a(n) in a conventional scanning signal line drive circuit (hereinafter referred to as the "conventional example"). Like the unit circuit 4(n) in this embodiment (see FIG. 5), this unit circuit 4a(n) also has a clock input terminal CK, a set input terminal S, a reset input terminal R, a reset state voltage terminal VR, and an output terminal Q, and is equipped with three N-channel transistors T1 to T3 (an output transistor T1, a set transistor T2, and a reset transistor T3) as switching elements connected as shown in FIG. 7, and one capacitor C1. However, in the n-th unit circuit 4(n) of this embodiment, the scan signal G(n+1) output from the next unit circuit is applied to the reset state voltage terminal VR, and the scan signal G(n+2) output from the unit circuit two stages later is applied to the reset input terminal R, whereas in the unit circuit 4a(n) of the conventional example, the low-level power supply voltage VSS, which is a fixed voltage, is applied to the reset state voltage terminal VR, and the scan signal G(n+3) output from the unit circuit three stages later is applied to the reset input terminal R. Similar to the unit circuit 4(n) of this embodiment, the set input terminal S of the unit circuit 4a(n) of the conventional example is applied with the scan signal G(n-2) output from the unit circuit two stages earlier. Note that, like this embodiment, the scan signal line driving circuit of the conventional example also operates by a four-phase clock signal consisting of first to fourth clock signals CK1 to CK4 shown in FIG. 4.

[0045] Fig. 8 is a signal waveform diagram for explaining the operation of the n-th stage unit circuit 4a(n) in the conventional example shown in Fig. 7. As shown in Fig. 7, in this unit circuit 4a(n), the voltage of the internal node NA and the scanning signal G(n), which is the stage output signal Q, change from time t1 to time t4 in the same way as in the unit circuit 4(n) in this embodiment (see Fig. 6).

[0046] At time t4, the input clock signal CKp changes from H level to L level, causing the scanning signal G(n) output from the output terminal Q to change from H level to L level. In addition, the voltage of the internal node NA decreases in response to the change of the input clock signal CKp from H level to L level.

[0047] At time t45, a time equivalent to one-quarter of the cycle of the input clock signal CKp has elapsed since time 4, the scanning signal G(n+3) applied to the reset input terminal R changes from L level to H level. Since the source terminal of the reset transistor T3 is supplied with the low-level power supply voltage VSS, i.e., a fixed voltage equivalent to L level as the second logic level, via the reset state voltage terminal VR, at time t45, the reset transistor T3 changes from OFF state to ON state in response to the change of the scanning signal G(n+3) serving as the reset signal R from L level to H level. This discharges the internal node NA, causing its voltage to change to L level as the second logic level. Thereafter, at time t56, the reset transistor T3 turns OFF as the scanning signal G(n+3) serving as the reset signal R changes to L level.

[0048] Figure 9 is a diagram for explaining the problems with the unit circuit 4a(n) in the conventional example, and shows the changes in the voltage applied between the gate and source of the reset transistor T3 (hereinafter simply referred to as the "gate-source voltage") Vgs and the voltage applied between the drain and source of the reset transistor T3 (hereinafter simply referred to as the "drain-source voltage") Vds during the above-mentioned operation of the unit circuit 4a(n) around time t45 (the period before and after the reset transistor T3 changes from the off state to the on state) (see the area surrounded by the dotted ellipse in Figure 8). In Figure 9, the thick solid line represents the gate-source voltage Vgs, and the thick dotted line represents the drain-source voltage Vds.

[0049] The reset transistor T3 has a source terminal supplied with a low-level power supply voltage VSS. The voltage of the internal node NA connected to its drain terminal is high immediately before the scanning signal G(n+3) applied to its gate terminal changes from low to high. Therefore, as shown in Figure 9, when the scanning signal G(n+3) serving as the reset signal R changes from low to high, the drain-source voltage Vds becomes large at the point where the gate-source voltage Vgs approaches the threshold voltage Vth of the reset transistor T3. This places a strong stress on the reset transistor T3, potentially preventing proper discharge of the internal node NA and resulting in display defects. Specifically, high-energy carriers accelerated by the high electric field inside the TFT serving as the reset transistor T3 are injected into the gate oxide, causing fluctuations in the TFT's characteristics (a phenomenon known as "hot carrier degradation"). As a result, the internal node NA may not be properly discharged, resulting in display defects. As display panels such as liquid crystal panels become larger and operate at higher frequencies, the driving voltage tends to increase, making it important to address the problem of hot carrier degradation.

[0050] JP 2015-181083 A describes a drive circuit that functions as a shift register in a display device or the like, and this drive circuit is configured to reduce the value of the negative bias voltage applied to the thin film transistor (TFT) used for the set operation by charging the internal node in each stage of the shift register, in order to reduce deterioration of the TFT, so as not to place a large stress on the TFT. However, this publication does not describe a configuration for reducing hot carrier deterioration of the TFT corresponding to the reset transistor T3.

[0051] <1.3 Effects> As described above, the scanning signal line driving circuit 400 of this embodiment operates based on first to fourth clock signals CK1-CK4 as shown in FIG. 4. As shown in FIG. 4, each unit circuit 4(n) outputs a scanning signal G(n) as a stage output signal Q (n=1, 2, 3, ...) so that pulses in the scanning signals G(i) and G(i+1) to be applied to adjacent scanning signal lines partially overlap. Unlike the unit circuit 4a(n) of the conventional example, the unit circuit 4(n) that outputs this scanning signal G(n) receives a scanning signal G(n+1) from the unit circuit of the next stage (one stage later) as a reset state voltage signal VR to the source terminal of the reset transistor T3, and receives a scanning signal G(n+2) from the unit circuit of the second stage later as a reset signal R to the gate terminal of the reset transistor T3, as shown in FIG. This embodiment can suppress or mitigate hot carrier degradation, which is a problem in the conventional example. This point will be explained below with reference to FIG. 10.

[0052] 10 is a diagram for explaining the effect of this embodiment, and shows the changes in the gate-source voltage Vgs and the drain-source voltage Vds of the reset transistor T3 in the period around time t45 (the period before and after the reset transistor T3 changes from the off state to the on state) in the operation of the unit circuit 4(n) in this embodiment as already described and shown in FIG. 6 (see the portion surrounded by the dotted ellipse in FIG. 10). In FIG. 10, too, the thick solid line indicates the gate-source voltage Vgs, and the thick dotted line indicates the drain-source voltage Vds.

[0053] In this embodiment, the scanning signal G(n+1) provided to the unit circuit 4(n) from the next unit circuit as the reset state voltage signal VR changes from L level to H level at time t34, as shown in FIG. 6, and remains H level until time t45. The drain and source terminals of the reset transistor T3 are connected to the internal node NA and the reset state voltage terminal VR, respectively (FIG. 5). Therefore, the drain-source voltage Vds is a sufficiently small value near zero from time t4, when the voltage of the internal node NA drops to H level as the input clock signal CKp changes from H level to L level, until time t45, when the reset transistor T3 changes to the ON state and the internal node NA starts discharging. At time t4, the scanning signal G(n+2) provided to the gate terminal of the reset transistor T3 as the reset signal R changes from L level to H level. However, the reset transistor T3 remains in the OFF state because the scanning signal G(n+1) provided to its source terminal as the reset state voltage signal VR is H level. Then, at time t45, the scanning signal G(n+1) applied to the source terminal of the reset transistor T3 as the reset state voltage signal VR changes from H level to L level. This causes the gate-source voltage Vgs of the reset transistor T3 to exceed the threshold voltage Vth of the reset transistor T3, causing the reset transistor T3 to change from OFF state to ON state. As a result, the internal node NA is discharged, and its voltage changes to L level, which is the second logic level. The scanning signal G(n+2) applied to the gate terminal of the reset transistor T3 as the reset signal R is H level from time t4 to time t5. At time t45, between times t4 and t5, the scanning signal G(n+1) applied to the source terminal of the reset transistor T3 as the reset state voltage signal VR changes from H level to L level. Therefore, when the gate-source voltage Vgs reaches a value close to the threshold voltage Vth of the reset transistor T3 as the scanning signal G(n+1) changes from H level to L level, the drain-source voltage Vds is small.Furthermore, during this process, when the gate-source voltage Vgs exceeds the threshold voltage Vth of the reset transistor T3, the reset transistor T3 turns on, discharging the internal node NA and changing its voltage toward the L level (second logic level), and then the drain-source voltage Vds also decreases.

[0054] Due to this operation, the gate-source voltage Vgs and drain-source voltage Vds of the reset transistor T3 change as shown in FIG. 10 during a period around time t45 (the period before and after the reset transistor T3 changes from an OFF state to an ON state). As shown in FIG. 10, when the gate-source voltage Vgs reaches a value close to the threshold voltage Vth of the reset transistor T3 during the process of the reset transistor T3 changing from an OFF state to an ON state, the drain-source voltage Vds is small. According to this embodiment, even when a gate driver monolithic panel with a high drive voltage is used as the liquid crystal panel 600, hot carrier degradation of the TFT serving as the reset transistor T3 in the scanning signal line drive circuit 400 is suppressed or mitigated, thereby making it possible to prevent display defects caused by hot carrier degradation.

[0055] In this embodiment, the set input terminal S of a unit circuit 4(n) is supplied with the scanning signal G(n-2) output from the unit circuit 4(n-2) two stages before the unit circuit 4(n) (see FIG. 5), but instead, the set input terminal S may be supplied with the scanning signal G(n-1) output from the unit circuit 4(n-1) one stage before the unit circuit 4(n). Even with this configuration, the scanning signal line driving circuit 400 operates in substantially the same way, and the same effects can be obtained.

[0056] 2. Second embodiment Next, a display device according to a second embodiment will be described. The display device according to this embodiment is also an active matrix liquid crystal display device, and its overall configuration is the same as that of the first embodiment, as shown in FIG. 1. The electrical configuration of each pixel formation portion Ps(i,j) is also the same as that of the first embodiment, as shown in FIG. 1. Also in this embodiment, the scanning signal line drive circuit is a monolithic driver (GDM circuit). However, the scanning signal line drive circuit in this embodiment differs from the scanning signal line drive circuit in the first embodiment (see FIGS. 3 and 4) in that it operates using a three-phase clock signal. This differs from the scanning signal line drive circuit in the first embodiment, which operates using a four-phase clock signal. Below, the scanning signal line drive circuit in this embodiment will be described, and detailed descriptions of other parts will be omitted. Note that, in the configuration of the display device according to this embodiment, parts that are the same as or correspond to those in the first embodiment will be denoted by the same reference numerals.

[0057] Fig. 11 is a circuit diagram illustrating a schematic configuration of a shift register 402 that constitutes the scanning signal line driving circuit 400 in this embodiment, and Fig. 12 is a signal waveform diagram illustrating the operation of the scanning signal line driving circuit 400 that is constituted by the shift register 402 shown in Fig. 11. The configuration and operation of this scanning signal line driving circuit 400 will be described below with reference to Figs. 11 and 12.

[0058] The shift register 402 that constitutes the scanning signal line driving circuit 400 in this embodiment operates based on a three-phase clock signal composed of the first to third clock signals CK1 to CK3 as shown in FIG. 12. In the shift register 402, the first to third clock signals CK1 to CK3 correspond cyclically to the unit circuits 4(1), 4(2), 4(3),... in the shift register 402, and the corresponding clock signal among the first to third clock signals CK1 to CK3 is input to each unit circuit 4(i). For this reason, as shown in FIG. 11, the connection relationship between the signal lines that transmit the first to third clock signals CK1 to CK3 and each unit circuit 4(i) (i = 1, 2, 3,...) is different from that of the shift register 401 in the first embodiment. In addition to this, the set signal S (the signal given to the set input terminal S) input to each unit circuit 4(i) is also different (details will be described later). However, except for these points, the internal connection configuration of the shift register 402 is the same as that of the shift register 401 in the first embodiment (see FIG. 3).

[0059] In the first to third clock signals CK1 to CK3 used in the shift register 402 in this embodiment, the duty ratio D is a real number satisfying 1 / 3 < D < 2 / 3. As shown in FIG. 12, pulses partially overlap between two adjacent clock signals CKq and CKq+1 among the first to third clock signals CK1 to CK3 (q is an integer such that 1 ≤ q ≤ 3. However, when q = 3, CKq+1 is replaced with CK1). However, each unit circuit 4(i) in this embodiment operates substantially the same as each unit circuit 4(i) in the first embodiment described below (i = 1 to N). For this reason, also in this embodiment, as shown in FIG. 12, the voltage of the internal node NA(i) of each unit circuit 4(i) and the scanning signal G(i) output from each unit circuit 4(i) change in the same manner as in the first embodiment (see FIG. 4).

[0060] FIG. 13 is a circuit diagram showing an example of the configuration of an n-th unit circuit 4(n) in this embodiment (1≦n≦N). This unit circuit 4(n) has a configuration similar to that of the unit circuit 4(n) in the first embodiment (see FIG. 5). The signals applied to the reset input terminal R and the reset state voltage terminal VR are also similar to those of the unit circuit 4(n) in the first embodiment. The input clock signal CKp applied to the clock input terminal CK is also similar to that of the unit circuit 4(n) in the first embodiment, except that the input clock signal CKp is one of the first to third clock signals constituting a three-phase clock signal. However, as shown in FIG. 13, the set input terminal S is applied with a scanning signal G(n−1), which is the output signal of the preceding unit circuit 4(n−1). In this respect, this embodiment differs from the first embodiment in that the set input terminal S is applied with a scanning signal G(n−2), which is the output signal of the unit circuit 4(n−2) two stages earlier (see FIG. 5). 11, a start pulse signal SP is given to the set input terminal S of the first-stage unit circuit 4(1) of the shift register 402 constituting the scanning signal line driving circuit 400 (see FIG. 12), and a scanning signal G(1) output from the first-stage unit circuit 4(1) is given to the set input terminal S of the second-stage unit circuit 4(2). However, for the sake of convenience in the following explanation, even when n=1, it is assumed that in a unit circuit 4(n), the output terminal Q of the immediately preceding unit circuit 4(n-1) is connected to the set input terminal S, and the scanning signal G(n-1), which is the stage output signal Q of the immediately preceding unit circuit 4(n-1), is given to the set input terminal S.

[0061] Fig. 14 is a signal waveform diagram for explaining the operation of the unit circuit 4(n) in this embodiment shown in Fig. 13. As shown in Fig. 14, the scanning signal G(n-1) as the set signal S in this unit circuit 4(n), the voltage of the internal node NA, the scanning signal G(n) as the stage output signal Q, the scanning signal G(n+2) as the reset signal R, and the scanning signal G(n+1) as the reset state voltage signal VR have some differences in timing compared to the first embodiment (see Fig. 6) due to differences in the duty ratio of the input clock signal CKp and the set signal S, but they essentially change in the same way as the first embodiment.

[0062] Therefore, in this embodiment, as in the first embodiment, the gate-source voltage Vgs and drain-source voltage Vds of the reset transistor T3 change as shown in FIG. 10. That is, when the gate-source voltage Vgs reaches a value close to the threshold voltage Vth of the reset transistor T3 in the process of the reset transistor T3 changing from the off state to the on state, the drain-source voltage Vds is small. As a result, in this embodiment as well, hot carrier degradation of the reset transistor T3 is suppressed or mitigated, and the same effect as in the first embodiment is obtained.

[0063] 3. Third Embodiment Next, a display device according to a third embodiment will be described. The display device according to this embodiment is also an active matrix liquid crystal display device, and its overall configuration is as shown in FIG. 1, similar to the first embodiment, and the electrical configuration of each pixel formation portion Ps(i,j) is also as shown in FIG. 2, similar to the first embodiment. Also in this embodiment, the scanning signal line drive circuit is a monolithic driver (GDM circuit). Below, the scanning signal line drive circuit in this embodiment will be described, and detailed descriptions of other parts will be omitted. Note that, in the configuration of the display device according to this embodiment, parts that are the same as or correspond to those in the first embodiment will be assigned the same reference numerals.

[0064] The scanning signal line drive circuit in the first embodiment uses a four-phase clock signal, while the scanning signal line drive circuit in the second embodiment uses a three-phase clock signal, and the number of phases of the clock signal is specified by a specific numerical value. In contrast, in the scanning signal line drive circuit in this embodiment, the number of phases of the clock signal is specified in a generalized form. That is, in the scanning signal line drive circuit in this embodiment, the number of phases of the clock signal used is indicated by a variable "k."

[0065] Regarding the shift registers constituting the scanning signal line driving circuit 400 in this embodiment, a shift register (hereinafter referred to as a "first example shift register") having a configuration basically similar to that of the shift register 401 in the first embodiment (see FIGS. 3 and 5) and a shift register (hereinafter referred to as a "second example shift register") having a configuration basically similar to that of the shift register 402 in the second embodiment (see FIGS. 11 and 13) will be considered. Both the first and second example shift registers operate with k-phase clock signals consisting of first to k-th clock signals CK1 to CKk, and in the shift registers, the first to k-th clock signals CK1 to CKk correspond cyclically to unit circuits 4(1), 4(2), 4(3), 4(4)..., and a corresponding clock signal from the first to k-th clock signals CK1 to CKk is input to each unit circuit 4(i). However, in the shift register of the first example, like the shift register 401 in the first embodiment, the set input terminal S of each unit circuit 4(n) in the nth stage is supplied with a scanning signal G(n-2) output from the unit circuit 4(n-2) two stages earlier (see FIG. 5 ), whereas in the shift register of the second example, like the shift register 402 in the second embodiment, the set input terminal S of each unit circuit 4(n) in the nth stage is supplied with a scanning signal G(n-1) output from the unit circuit 4(n-1) one stage earlier, which is the difference between the two. Hereinafter, the duty ratio of the k-phase clock signal used in this embodiment is defined as D, and we will consider the conditions under which the unit circuits 4(n) included in the shift register of the first example operate substantially similarly to the unit circuits 4(n) included in the shift register 401 in the first embodiment, and the conditions under which the unit circuits 4(n) included in the shift register of the second example operate substantially similarly to the unit circuits 4(n) included in the shift register 402 in the second embodiment.

[0066] <3.1 Using the shift register in the first example> The configuration of the nth stage unit circuit 4(n) in the shift register of the first example is the same as that of the first embodiment, and the signals given to the set input terminal S, reset input terminal R, and reset state voltage terminal VR of the unit circuit 4(n) are also the same as those of the first embodiment (see FIG. 5).

[0067] 5 in the first example shift register using k-phase clock signals, in this unit circuit 4(n), when the output transistor T1 is in the on state, a pulse of the input clock signal CKp is output as a pulse of the scanning signal G(n), which is the stage output signal Q. Therefore, as in the first embodiment, in order to partially overlap the pulse of the scanning signal G(n+1) provided to the source terminal of the reset transistor T3 as the reset state voltage signal VR and the pulse of the scanning signal G(n+2) provided to the gate terminal of the reset transistor T3 as the reset signal R, it is necessary to partially overlap the pulses of two adjacent clock signals CKq and CKq+1 among the first to k-th clock signals CK1 to CKk (q is an integer satisfying the condition 1≦q≦3, where CKq+1 is replaced with CK1 when q=3), as shown in FIG. To achieve this, the number of phases k and the duty ratio D must satisfy the following formula, as can be seen from the waveforms of the clock signals CK1 and CK2 shown in Fig. 15. In Fig. 15, the first clock signal CK1 is the input clock signal CKp, and the period of the k-phase clock signal is Tck=1. 1 / k <D …(1)

[0068] 15, the unit circuit 4(n) changes from the reset state to the set state at the rising edge tb1 of the scanning signal G(n-2) applied to its set input terminal S from the unit circuit 4(n-2) two stages earlier, and changes from the set state to the reset state at the falling edge td of the scanning signal G(n+1) applied to its reset state voltage terminal VR from the unit circuit 4(n+1) in the next stage (one stage later). Therefore, the unit circuit 4(n) is in the set state from time tb1 to time td (the voltage of the internal node NA is maintained at the first logic level), and during this set state period tb1 to td, only one pulse of the input clock signal CKp=CK1 must be output from the output terminal Q via the output transistor T1 as a pulse of the scanning signal G(n). For this purpose, it is necessary that the period tb1 to td of the set state does not overlap with either the pulse immediately before or immediately after the one pulse in the input clock signal CKp=CK1.

[0069] In the example shown in FIG. 15, among the pulses of the input clock signal CKp=CK1, the pulse that rises at time tc corresponds to the one pulse, and the pulse that falls at time ta corresponds to the immediately preceding pulse. Therefore, in order to prevent the set state period tb1 to td of the unit circuit 4(n) from overlapping with the immediately preceding pulse, the following formula must be satisfied (see the waveform of the input clock signal CKp=CK1 and the waveform of the voltage at the internal node NA(n) shown in FIG. 15): 1-D≧2 / k …(2) Furthermore, among the pulses of the input clock signal CKp=CK1, the pulse that rises at time te corresponds to the immediately following pulse, so in order to prevent the set state period tb1 to td of the unit circuit 4(n) from overlapping with the immediately following pulse, the following formula must be satisfied (see the waveforms of the input clock signal CKp=CK1 and the voltage of the internal node NA(n) shown in FIG. 15): 1 / k+D≦Tck=1 …(3) Rewriting the above equation (2), D≦1-2 / k and rewriting the above equation (3) gives D ≤ 1 - 1 / k Therefore, since 1 - 2 / k < 1 - 1 / k, if the following inequality is satisfied, during the period tb1 to td of the set state of the unit circuit 4(n), only the pulse of the input clock signal CKp = CK1 that rises at time tc is included among the pulses of the input clock signal CKp = CK1, and neither the pulse immediately before nor the pulse immediately after it is included. D ≤ 1 - 2 / k …(4)

[0070] For the shift register of the first example to operate in the same manner as the shift register 401 in the first embodiment, the following equation needs to be satisfied from the above equations (1) and (4). 1 / k < D ≤ 1 - 2 / k …(5) When k = 1, 2, or 3, there is no duty ratio (0 < D < 1) that satisfies the above equation (5), but when k is an integer of 4 or more, there is a duty ratio that satisfies the above equation (5).

[0071] From the above, when k is an integer of 4 or more (when the number of phases of the clock signal is 4 or more), the shift register of the first example operates in the same manner as the shift register 401 in the first embodiment by using a k-phase clock signal having a duty ratio that satisfies the above equation (5). Therefore, in the unit circuit 4(n) included in the shift register of the first example, the gate-source voltage Vgs and the drain-source voltage Vds of the reset transistor T3 change as shown in FIG. 10 in the process in which the reset transistor T3 changes from the off state to the on state. As a result, also in the present embodiment using the shift register of the first example, hot carrier degradation of the reset transistor T3 is suppressed or mitigated, and the same effect as in the first embodiment can be obtained.

[0072] From the viewpoint of the stability of the operation as a shift register, it is preferable to determine the number of phases k and the duty ratio of the clock signal so as to satisfy the following inequality instead of the above equation (5). 1 / k < D < 1 - 2 / k …(6)

[0073] <3.2 Using the shift register in the second example> The configuration of the nth stage unit circuit 4(n) in the second example shift register is the same as that in the second embodiment, and the signals applied to the set input terminal S, reset input terminal R, and reset state voltage terminal VR in the unit circuit 4(n) are also the same as those in the second embodiment (see FIG. 13).

[0074] 13, in the second example shift register using k-phase clock signals, in this unit circuit 4(n), when the output transistor T1 is in the on state, a pulse of the input clock signal CKp is output as a pulse of the scanning signal G(n), which is the stage output signal Q. Therefore, as in the second embodiment, in order to partially overlap the pulse of the scanning signal G(n+1) provided to the source terminal of the reset transistor T3 as the reset state voltage signal VR and the pulse of the scanning signal G(n+2) provided to the gate terminal of the reset transistor T3 as the reset signal R, it is necessary to partially overlap the pulses of two adjacent clock signals CKq and CKq+1 among the first to k-th clock signals CK1 to CKk (q is an integer satisfying the condition 1≦q≦3, where CKq+1 is replaced with CK1 when q=3), as shown in FIG. For this purpose, similarly to the shift register of the first example, the number of phases k and the duty ratio D must satisfy the following formula (see FIG. 15). 1 / k <D …(7)

[0075] Furthermore, unlike the shift register of the first example, the unit circuit 4(n) changes from the reset state to the set state at time tb2 when the scanning signal G(n-1) applied to its set input terminal S from the immediately preceding unit circuit 4(n-1) rises (see the thick dotted waveform for the voltage of the internal node NA(n) in FIG. 15), and changes from the set state to the reset state at time td when the scanning signal G(n+1) applied to its reset state voltage terminal VR from the immediately succeeding unit circuit 4(n+1). Therefore, the unit circuit 4(n) is in the set state from time tb2 to time td (the voltage of the internal node NA is maintained at the first logic level), and during this set state period tb2 to td, only one pulse of the input clock signal CKp=CK1 must be output from the output terminal Q via the output transistor T1 as a pulse of the scanning signal G(n). For this purpose, it is necessary that the period tb2 to td of the set state does not overlap with either the pulse immediately before or immediately after the one pulse in the input clock signal CKp=CK1.

[0076] In the example shown in FIG. 15, the pulse that rises at time tc among the pulses of the input clock signal CKp=CK1 corresponds to the one pulse in question, and as can be seen from the waveform of the input clock signal CKp=CK1 and the waveform of the voltage of the internal node NA(n) (waveform shown by the thick dotted line) shown in FIG. 15, the following formula must be satisfied in order to prevent the set state period tb2 to td of the unit circuit 4(n) from overlapping with the immediately preceding pulse. 1-D≧1 / k …(8) Furthermore, in order to prevent the set state period tb2 to td of the unit circuit 4(n) from overlapping with the pulse immediately following the pulse in the input clock signal CKp=CK1, the following formula must be satisfied (see the waveform of the input clock signal CKp=CK1 and the voltage waveform of the internal node NA(n) shown in Figure 15). 1 / k+D≦Tck=1 …(9) It must be satisfied. By rewriting the above formulas (8) and (9), in both cases, D ≤ 1 - 1 / k. Therefore, if the following inequality is satisfied, only one pulse of the input clock signal CKp = CK1 is included in the period tb2 to td of the set state of the unit circuit 4(n). D ≤ 1 - 1 / k …(10)

[0077] For the shift register of the second example to operate in the same manner as the shift register 402 in the above second embodiment, the following formula needs to be satisfied based on the above formulas (7) and (10). 1 / k < D ≤ 1 - 1 / k …(11) When k = 1 or 2, there is no duty ratio (0 < D < 1) that satisfies the above formula (11), but when k is an integer of 3 or more, there is a duty ratio that satisfies the above formula (11).

[0078] From the above, the shift register of the second example, when k is an integer of 3 or more (when the number of phases of the clock signal is 3 or more), by using a k-phase clock signal having a duty ratio D that satisfies the above formula (11), it operates basically in the same manner as the shift register 402 in the above second embodiment. For this reason, in the unit circuit 4(n) included in the shift register of the second example, the gate-source voltage Vgs and the drain-source voltage Vds of the reset transistor T3 change as shown in FIG. 10 in the process of the reset transistor T3 changing from the off state to the on state. Thereby, also in this embodiment using the shift register of the second example, hot carrier degradation of the reset transistor T3 is suppressed or alleviated, and the same effect as the above second embodiment is obtained.

[0079] From the viewpoint of the stability of the operation as a shift register, it is preferable to determine the number of phases k of the clock signal and the duty ratio so as to satisfy the following inequality instead of the above formula (11). 1 / k < D < 1 - 1 / k …(12)

[0080] <4. Modified Example> The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

[0081] In each of the above embodiments, in order to suppress hot carrier degradation of the reset transistor T3 included in the unit circuit 4(n) in the scanning signal line driving circuit 400, the drain-source voltage Vds is prevented from becoming large when the gate-source voltage Vgs becomes close to the threshold voltage Vth of the reset transistor T3 during the process of the reset transistor T3 changing from the off state to the on state (see FIG. 10 ). For example, in the first and second embodiments, the scanning signal line driving circuit 400 is configured such that, in the unit circuit 4(n), a scanning signal G(n+2) is applied as a reset signal R to the gate terminal of the reset transistor T3 from the unit circuit 4(n+2) two stages later, and a scanning signal G(n+1) is applied as a reset state voltage signal VR to the source terminal of the reset transistor T3 from the unit circuit 4(n+1) one stage later ( FIGS. 5 and 13 ). However, the reset signal R and the reset state voltage signal VR to be applied to the gate terminal and source terminal of the reset transistor T3, respectively, are not limited to the scanning signals G(n+2) and G(n+1). That is, the reset signal R and the reset state voltage signal VR can be selected so that when the reset signal R to be applied to the gate terminal of the reset transistor T3 changes from the L level to the H level, the reset state voltage signal VR to be applied to the source terminal of the reset transistor T3 remains at the H level, and the reset state voltage signal VR changes from the H level to the L level (second logic level) before the reset signal R changes from the H level to the L level. More generally, the reset signal R and the reset state voltage signal VR can be selected so that when the reset signal R to be applied to the gate terminal of the reset transistor T3 changes from the inactive state to the active state, the reset state voltage signal VR to be applied to the source terminal of the reset transistor T3 remains at the active state, and the reset state voltage signal VR changes from the active state to the inactive state before the reset signal R changes from the active state to the inactive state.The voltage level indicating the active state of the reset state voltage signal VR is equal to the voltage level indicating the active state of the reset signal R, and the voltage level indicating the inactive state of the reset state voltage signal VR is equal to the voltage level (second logic level) indicating the reset state of the internal node NA.

[0082] In addition, in each of the above embodiments, the transistors such as the reset transistor T3 included in the unit circuit 4(n) are N-channel transistors, but P-channel transistors may be used instead. Even when P-channel transistors are used, a shift register that operates substantially in the same way as the shift register in each of the above embodiments can be realized by reversing the potential relationship in the circuit configuration in each of the above embodiments.

[0083] While the above description has been given using a liquid crystal display device as an example of an embodiment, the present invention is not limited thereto and can be applied to other types of display devices, such as organic electroluminescence (EL) display devices, as long as they are active matrix display devices. When the display device according to the above embodiment is an active matrix organic EL display device, the pixel formation unit Ps(i,j) shown in FIG. 2 includes an organic EL element (also called an organic light emitting diode (OLED)), a storage capacitor, a TFT as a drive transistor, and a TFT as a write control switching element, instead of the TFT 10 as a pixel switching element and the liquid crystal capacitor Clc. In this case, the voltage of the data signal line DL(j), i.e., the voltage of the data signal D(j), is written and stored in the storage capacitor via the write control switching element that is turned on / off by the scanning signal line GL(i), and the drive transistor supplies a current to the organic EL element according to the voltage stored in the storage capacitor. This causes the organic EL element to emit light at a brightness according to the voltage written in the storage capacitor. [Explanation of symbols]

[0084] 100...display device 200...Display control circuit 300...Data signal line driving circuit 400 ...Scanning signal line driving circuit 500...Display section 600...LCD panel (display panel) 401, 402 ... shift register 4(i)...Unit circuit (i=1,2,3,...) 41...Output circuit 42...Set circuit 43...Reset circuit CK: Clock input terminal S...Set input terminal, set signal R...Reset input terminal, reset signal VR: Reset state voltage terminal, reset state voltage signal Q...Output terminal, stage output signal T1: Output transistor T2: Set transistor T3: Reset transistor C1...Capacitor NA...internal node G(i)...Scanning signal (i=1~N) CKp: Input clock signal CKq...qth clock signal (q=1, 2, ..., k)

Claims

1. A scanning signal line drive circuit that drives a plurality of scanning signal lines arranged in a display unit of a display device, a plurality of unit circuits connected in cascade to form a shift register; each unit circuit is configured to determine a state of the unit circuit based on a set signal and a reset signal given as input signals; an internal node selectively holding voltages of first and second logic levels indicating the state of each unit circuit; a set circuit that applies a voltage of the first logic level to the internal node when the set signal is active; a reset circuit that applies a voltage of the second logic level to the internal node when the reset signal is active; the reset circuit includes a reset transistor having a drain terminal connected to the internal node, a source terminal, and a gate terminal to which the reset signal is applied; the shift register is configured in each unit circuit to maintain an active voltage level corresponding to the active state of the reset signal when the reset signal changes from an inactive state to an active state, and a voltage signal that changes from the active voltage level to the second logic level before the reset signal changes from the active state to the inactive state is applied to the source terminal of the reset transistor as a reset state voltage signal.

2. the shift register operates based on a multiphase clock signal; the multiphase clock signal is composed of a plurality of clock signals that cyclically correspond to the plurality of unit circuits; a pulse of one of two adjacent clock signals among the plurality of clock signals partially overlaps with a pulse of the other of the two adjacent clock signals; the plurality of unit circuits respectively correspond to the plurality of scanning signal lines; Each unit circuit is an output circuit including an output transistor that is in an on state when the internal node holds a voltage of the first logic level and that is in an off state when the internal node holds a voltage of the second logic level; a clock input terminal for receiving a corresponding one of the plurality of clock signals; an output terminal connected to a corresponding one of the plurality of scanning signal lines and connected to the clock input terminal via the output transistor; the output circuit outputs a scanning signal based on the corresponding clock signal from the output terminal to the corresponding scanning signal line; 2. The scanning signal line driving circuit according to claim 1, wherein the shift register is configured such that, in each unit circuit, a scanning signal output from a unit circuit subsequent to the current unit circuit is applied to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from a unit circuit subsequent to the current unit circuit is applied to the gate terminal of the reset transistor as the reset signal.

3. The number of phases k of the multiphase clock signal is an integer equal to or greater than 3, and the duty ratio D of the multiphase clock signal is expressed by the following inequality: 1 / k<D≦1-1 / k Fulfilling 3. The scanning signal line driving circuit according to claim 2, wherein the shift register is configured such that, in each unit circuit, a scanning signal output from a unit circuit one stage before the current stage or a signal equivalent to the scanning signal is provided to the set circuit as the set signal, a scanning signal output from a unit circuit one stage after the current stage is provided to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from a unit circuit two stages after the current stage is provided to the gate terminal of the reset transistor as the reset signal.

4. The number of phases k of the multiphase clock signal is an integer equal to or greater than 4, and the duty ratio D is expressed by the following inequality: 1 / k<D≦1-2 / k Fulfilling 3. The scanning signal line driving circuit according to claim 2, wherein the shift register is configured such that, in each unit circuit, a scanning signal output from a unit circuit two stages before the current stage or a signal equivalent to the scanning signal is provided to the set circuit as the set signal, a scanning signal output from a unit circuit one stage after the current stage is provided to the source terminal of the reset transistor as the reset state voltage signal, and a scanning signal output from a unit circuit two stages after the current stage is provided to the gate terminal of the reset transistor as the reset signal.

5. 3. The scanning signal line driving circuit according to claim 2, wherein the shift register is configured such that, in each unit circuit, a scanning signal output from a unit circuit in a previous stage of the shift register or a signal corresponding to the scanning signal is provided to the set circuit as the set signal.

6. 6. The scanning signal line driving circuit according to claim 1, wherein the set circuit includes a transistor in a diode-connected configuration having a drain terminal and a gate terminal to which the set signal is applied and a source terminal connected to the internal node.

7. 6. The scanning signal line driving circuit according to claim 1, wherein the reset transistor is a thin film transistor.

8. 8. The scanning signal line driving circuit according to claim 7, wherein the reset transistor is a thin film transistor having a channel layer formed of an oxide semiconductor.

9. A scanning signal line driving circuit according to any one of claims 1 to 5, The display device, wherein the scanning signal line driving circuit and the display section are integrally formed on the same substrate.

Images