Array substrate and display device

Abstract

To achieve high resolution.SOLUTION: An array substrate 21 includes first wiring 26, second wiring 27α, a first electrode 24Cα, and a first insulating film 33. The first wiring 26 includes a first wiring structure 26A formed of a first conductive film, a second wiring structure 26B formed of the first conductive film, and a first connection electrode 26C formed of a second conductive film. The second wiring 27α is formed of the second conductive film, and the first electrode 24Cα is formed of the second conductive film. The first wiring structure 26A has a first end portion 26A1, and the second wiring structure 26B has a second end portion 26B1 that is away from the first end portion 26A1 in a second direction and on the same side as the first electrode 24Cα, and is sandwiched between the second wiring 27α and the first electrode 24Cα in a first direction. The first connection electrode 26C extends so as to straddle the first end portion 26A1 and the second end portion 26B1.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device that are capable of achieving high definition. [Background technology]

[0002] A known example of an array substrate provided in a liquid crystal panel is that described in Patent Document 1 below. The array substrate described in Patent Document 1 includes a light-transmitting substrate, switching elements provided on the light-transmitting substrate, gate electrode wiring having a separated separating portion connected to the switching elements, and a conductive portion provided in a layer different from the gate electrode wiring and electrically connecting the separated portions in the gate electrode wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-134446 Summary of the Invention [Problem to be solved by the invention]

[0004] In the array substrate described in Patent Document 1, the conductive portion is made of the same material as the signal electrode wiring and the drain electrode of the switching element. Therefore, to avoid a short circuit between the conductive portion and the signal electrode wiring, a sufficient distance must be provided between the conductive portion and the signal electrode wiring. Similarly, to avoid a short circuit between the conductive portion and the drain electrode, a sufficient distance must be provided between the conductive portion and the drain electrode. As a result, a distance equal to the sum of the two distances mentioned above and the length of the conductive portion must be provided between the signal electrode wiring and the drain electrode, which poses a problem when arranging pixels at a narrow pitch, i.e., when achieving high resolution.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to achieve higher definition. [Means for solving the problem]

[0006] (1) An array substrate according to the technology described in this specification includes a first wiring extending along a first direction, a second wiring extending along a second direction intersecting the first direction, a first electrode spaced apart from the first wiring in the second direction and spaced apart from the second wiring in the first direction, and a first insulating film, wherein the first wiring has a first wiring component made of a first conductive film disposed below the first insulating film, a second wiring component made of a portion of the first conductive film different from the first wiring component, and a first connection electrode made of a second conductive film disposed above the first insulating film, and the second wiring has a portion of the second conductive film different from the first connection electrode. the first electrode is made of a portion of the second conductive film that is different from the first connection electrode and the second wiring, the first wiring component has a first end, the second wiring component has a second end that is spaced from the first end on the same side as the first electrode in the second direction and is sandwiched between the second wiring and the first electrode in the first direction, the first connection electrode extends to straddle the first end and the second end, and the first insulating film is provided with a first contact hole that is arranged to overlap the first end and the first connection electrode, and a second contact hole that is arranged to overlap the second end and the first connection electrode.

[0007] (2) In addition to (1) above, the array substrate may have the first wiring configuration extending along the first direction, and the second wiring configuration having a main body portion extending along the first direction and in the same straight line as the first wiring configuration, and a bent portion bent from the main body portion and extending to the second end.

[0008] (3) In addition to the above (2), the array substrate may be arranged such that the bent portion is sandwiched between the first connection electrode and the second wiring in the first direction.

[0009] (4) In addition to any one of (1) to (3), the array substrate may be arranged such that the first end and the second end overlap each other in the first direction.

[0010] (5) Furthermore, in addition to any one of (1) to (4), the array substrate may also include a first switching element having the first electrode and a first pixel electrode connected to the first electrode, the first switching element having a second electrode consisting of a part of the first wiring configuration, the first pixel electrode having a first connection portion connected to the first electrode and a first pixel electrode body arranged on the opposite side of the first wiring from the first connection portion in the second direction, and the first connection electrode may be arranged sandwiched between the first wiring configuration and the first pixel electrode body in the second direction.

[0011] (6) In addition to any one of (1) to (5), the array substrate may further include a first switching element having the first electrode, a first pixel electrode connected to the first electrode, a second insulating film arranged below the first pixel electrode, and a common electrode arranged below the second insulating film and overlapping with the first pixel electrode, wherein the first switching element has a second electrode consisting of a part of the first wiring component, and the common electrode has an opening surrounding the first electrode and an overlapping portion overlapping with the first connection electrode.

[0012] (7) In addition to (6), the array substrate may be configured such that the common electrode has a first slit in the opening extending along the first direction toward the first connection electrode, and a second slit extending along the first direction to the opposite side of the first connection electrode and being longer than the first slit.

[0013] (8) In addition to any one of (1) to (7), the array substrate further includes a first switching element having the first electrode, a first pixel electrode connected to the first electrode, a third wiring extending along the second direction and spaced apart from the second wiring on the opposite side of the first electrode in the first direction, a third electrode spaced apart from the first wiring on the same side as the first electrode in the second direction and sandwiched between the second wiring and the third wiring in the first direction, a second switching element having the third electrode, and a pixel electrode connected to the third electrode. and a second pixel electrode, wherein the first switching element has a second electrode consisting of a part of the first wiring configuration, the second switching element has a fourth electrode consisting of a part of the second wiring configuration, the third wiring consists of a part of the second conductive film that is different from the first connection electrode, the second wiring, and the first electrode, the third electrode consists of a part of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, and the third wiring, and the second wiring configuration may intersect with each of the second wiring and the third wiring via the first insulating film.

[0014] (9) In addition to the above (8), the array substrate further includes a fourth wiring extending along the second direction and disposed with the first pixel electrode sandwiched between the fourth wiring and the second wiring in the first direction; a fifth wiring extending along the second direction and disposed with a gap between the third wiring and the fifth wiring on the opposite side of the second wiring in the first direction; a sixth wiring extending along the second direction and disposed with a gap between the fifth wiring and the third wiring in the first direction; and a sixth wiring disposed with a gap between the first wiring and the fifth wiring on the same side as the first electrode in the second direction and disposed with a gap between the first wiring and the fifth wiring in the first direction. a fifth electrode sandwiched between the fifth wiring and the sixth wiring in the first direction, a third switching element having the fifth electrode, a third pixel electrode sandwiched between the fifth wiring and the sixth wiring in the first direction and connected to the fifth electrode, and a signal supply unit that supplies image signals to each of the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring, wherein the first wiring comprises a third wiring configuration unit that is made up of a portion of the first conductive film that is different from the first wiring configuration unit and the second wiring configuration unit, and the first connection electrode and the second wiring in the second conductive film. the fourth wiring is made up of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, and the second connection electrode; the fifth wiring is made up of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, and the fourth wiring; the sixth wiring is made up of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, the fourth wiring, and the and a portion different from the fifth wiring, the fifth electrode being made up of a portion of the second conductive film different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, the fourth wiring, the fifth wiring, and the sixth wiring, the second wiring configuration portion having a third end located opposite to the second end, the third wiring configuration portion having a fourth end spaced apart from the third end on the same side as the fifth electrode in the second direction and sandwiched between the fifth wiring and the fifth electrode in the first direction, the second connection electrode being made up of a portion of the second conductive film different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, the fourth wiring, the fifth wiring, and the sixth wiring, the second wiring configuration portion having a fourth end spaced apart from the third end on the same side as the fifth electrode in the second direction and sandwiched between the fifth wiring and the fifth electrode in the first direction,The first insulating film extends across the third end and the fourth end, and is provided with a third contact hole overlapping the third end and the second connection electrode, and a fourth contact hole overlapping the fourth end and the second connection electrode; the first switching element has a sixth electrode made of a part of the fourth wiring, and a first semiconductor portion made of a semiconductor material and connected to the first electrode and the sixth electrode; the third switching element has a seventh electrode made of a part of the second wiring component, an eighth electrode made of a part of the sixth wiring, and a third semiconductor portion made of a semiconductor material and connected to the fifth electrode and the eighth electrode; and the signal supply unit may supply the image signal to at least the fourth wiring and the image signal to the sixth wiring with opposite polarities.

[0015] (10) A display device according to the technology described in this specification includes an array substrate according to any one of (1) to (9) above, and an opposing substrate arranged opposite the array substrate with a gap therebetween. [Effects of the Invention]

[0016] According to the technology described in this specification, high definition can be achieved. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, and a flexible substrate that constitute a liquid crystal display device according to a first embodiment; [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1. [Figure 3] FIG. 1 is a circuit diagram showing the electrical configuration of an array substrate that constitutes a liquid crystal panel according to a first embodiment. [Figure 4] FIG. 1 is a plan view showing a pixel arrangement of an array substrate according to a first embodiment; [Figure 5] 5 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vv in FIG. 4 . [Figure 6] 6 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vi-vi in ​​FIG. 4 . [Figure 7] FIG. 2 is an enlarged plan view of the vicinity of the connection electrodes in the array substrate according to the first embodiment; [Figure 8] 8 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line VIII-VIII in FIG. 7. [Figure 9] FIG. 10 is a plan view of a liquid crystal panel, a driver, and a flexible substrate that constitute a liquid crystal display device according to a second embodiment. [Figure 10] FIG. 10 is a plan view showing a pixel arrangement of an array substrate according to a second embodiment. [Figure 11] 10 in a cross section of the liquid crystal panel according to the second embodiment. [Figure 12] FIG. 10 is a plan view showing a pixel arrangement on an array substrate according to a third embodiment. [Figure 13] FIG. 10 is a plan view showing a pixel arrangement of an array substrate according to a fourth embodiment. [Figure 14] FIG. 10 is a plan view schematically illustrating a pixel arrangement for a plurality of pixel rows on an array substrate according to a fourth embodiment, and also illustrating the polarities of image signals supplied to pixel electrodes during a certain frame period. [Figure 15] FIG. 10 is a plan view schematically illustrating a pixel arrangement for a plurality of pixel rows on an array substrate according to a fifth embodiment, and also illustrating the polarities of image signals supplied to pixel electrodes during a certain frame period. [Figure 16] FIG. 13 is a plan view showing a pixel arrangement of an array substrate according to a sixth embodiment. [Figure 17] FIG. 10 is a plan view showing a pixel arrangement in a pixel row different from that shown in FIG. 6 on an array substrate according to a sixth embodiment; [Figure 18] FIG. 13 is a plan view schematically illustrating a pixel arrangement for a plurality of pixel rows on an array substrate according to a sixth embodiment, and showing the polarities of image signals supplied to pixel electrodes during a certain frame period. [Figure 19] FIG. 13 is a plan view schematically illustrating a pixel arrangement for a plurality of pixel rows on an array substrate according to a seventh embodiment, and showing the polarities of image signals supplied to pixel electrodes during a certain frame period. DETAILED DESCRIPTION OF THE INVENTION

[0018] <Embodiment 1> Embodiment 1 will be described with reference to Figs. 1 to 8. In this embodiment, a liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is depicted as being in the direction shown in each drawing. Also, the upper side of Figs. 2, 5, 6, and 8 is the front side, and the lower side of each drawing is the back side.

[0019] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The central portion of the main surface of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion of the main surface of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed.

[0020] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21 together. The front side of the pair of substrates 20, 21 is the counter substrate 20, and the back side is the array substrate 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of glass substrates. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20, 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20, 21. The seal portion 23 is formed in a rectangular frame shape so as to surround the liquid crystal layer 22. A polarizing plate 14 is attached to the outer surface of each of the substrates 20, 21.

[0021] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and a driver 12 and a flexible substrate 13 for supplying various signals are mounted on the exposed portion 21A.

[0022] The driver 12 is an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) technology. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in FIGS. 1 and 2, the driver 12 is disposed adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the display area AA and the flexible substrate 13 (described below). The driver 12 has a horizontally elongated rectangular shape in plan view. The driver 12 can supply various signals to the source lines 27 and other signals provided on the array substrate 21. The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board).

[0023] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA of the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix (row and column) with multiple TFTs 24 and multiple pixel electrodes 25 spaced apart along the X-axis and Y-axis directions. Gate wiring (scanning wiring, first wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged around these TFTs 24 and pixel electrodes 25, intersecting each other at right angles (intersecting). The gate wiring 26 extends along the X-axis direction (first direction), with multiple gate wirings arranged at intervals along the Y-axis direction. The source wiring 27 extends roughly along the Y-axis direction (second direction), with multiple source wirings arranged at intervals along the X-axis direction. The TFT 24 has a gate electrode 24A connected to the gate line 26, a source electrode 24B connected to the source line 27, a drain electrode 24C connected to the pixel electrode 25, and a semiconductor portion 24D connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate line 26. This scanning signal includes a potential higher than the threshold voltage of the TFT 24. Then, a potential related to an image signal supplied to the source electrode 24B by the source line 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate line 26 and the source line 27.

[0024] The detailed planar configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 4. First, as shown in FIG. 4, the gate lines 26 extend generally linearly along the X-axis direction, with their line widths varying along the way. Specifically, the gate lines 26 are narrower at the portions where they intersect with the source lines 27 and the semiconductor portions 24D of the TFTs 24, and wider at the portions adjacent to the drain electrodes 24C of the TFTs 24. The source lines 27 extend generally along the Y-axis direction as a whole, and more specifically, have a portion parallel to the Y-axis direction (hereinafter referred to as a parallel portion) and a portion slightly inclined with respect to the Y-axis direction (hereinafter referred to as an inclined portion). The portions of the source lines 27 that intersect with the gate lines 26 are parallel portions, and the remaining portions are inclined portions. The pixel electrodes 25 each have a pixel electrode main body 25A that is vertically elongated in plan view, and a connection portion 25B that is connected to the drain electrodes 24C of the TFTs 24. The pixel electrode main body 25A has both longitudinal edges that are slightly inclined with respect to the Y-axis direction and are parallel to the inclined portions of the source wiring 27. The pixel electrode main body 25A has a plurality of slits 25A1 that are parallel to the inclined portions of the source wiring 27 and are arranged at intervals in the X-axis direction. The connection portion 25B extends from the pixel electrode main body 25A along the Y-axis direction toward the gate wiring 26 side (the lower side in FIG. 4) that is connected to the TFT 24 having the drain electrode 24C to be connected. The connection portion 25B has a vertically elongated rectangular shape in a plan view.

[0025] The detailed planar configuration of the TFT 24 will be described. As shown in FIG. 4, the gate electrode 24A constituting the TFT 24 is formed by a portion of the gate wiring 26 that overlaps with the semiconductor portion 24D. The source electrode 24B is formed by a portion of the source wiring 27 that overlaps with the semiconductor portion 24D and is connected to the semiconductor portion 24D. The source wiring 27 is partially widened, and this widened portion constitutes the source electrode 24B. The source electrode 24B is disposed farther from the gate wiring 26 in the Y-axis direction than the drain electrode 24C. The drain electrode 24C has a vertically elongated rectangular shape in a plan view and is disposed approximately midway between two adjacent source wirings 27 in the X-axis direction. The drain electrode 24C is disposed so as to overlap with the connection portion 25B of the pixel electrode 25 in a plan view and is connected to the connection portion 25B. The drain electrode 24C is also connected to the semiconductor portion 24D, which will be described next.

[0026] As shown in FIG. 4, the semiconductor portion 24D is routed so as to be bent multiple times (three times) along the way from the source electrode 24B to the drain electrode 24C. One end of the semiconductor portion 24D overlaps with and is connected to the source electrode 24B, and the other end overlaps with and is connected to the drain electrode 24C. The semiconductor portion 24D extends from one end along the Y-axis direction to overlap with the source wiring 27 over a predetermined length, bends at a position beyond the gate wiring 26, and extends along the X-axis direction toward the drain electrode 24C (to the right in FIG. 4). The semiconductor portion 24D then bends again and extends along the Y-axis direction toward the drain electrode 24C (upper side in FIG. 4), bends again at a position beyond the gate wiring 26, and extends away from the source electrode 24B in a direction oblique to the X-axis and Y-axis directions, until it reaches the drain electrode 24C. In this way, the semiconductor portion 24D has a folded-back portion located halfway between one end and the other end, and intersects twice with the gate wiring 26. Therefore, the gate wiring 26 has two overlapping portions with one semiconductor portion 24D, that is, two gate electrodes 24A. One TFT 24 has two gate electrodes 24A.

[0027] The configuration of the display area AA of the counter substrate 20 constituting the liquid crystal panel 11 will be described with reference to FIG. 5. As shown in FIG. 5, the display area AA of the counter substrate 20 is provided with a large number of color filters 28 at positions overlapping the pixel electrodes 25 of the array substrate 21. The color filters 28 are arranged in an alternating pattern along the X-axis direction, with three colors—red (R), green (G), and blue (B)—exhibiting red, green (G), and blue (B). Each of the three color filters 28 extends along the Y-axis direction, forming a generally striped arrangement overall. The overlapping color filters 28 and pixel electrodes 25 form a pixel PX, which is a display unit. In this liquid crystal panel 11, the three color filters 28 arranged along the X-axis direction and the three pixel electrodes 25 facing each color filter 28 form three-color pixels GPX, BPX, and RPX, respectively. The three-color pixels GPX, BPX, and RPX include a red pixel RPX that exhibits red, a green pixel GPX that exhibits green, and a blue pixel BPX that exhibits blue. In the liquid crystal panel 11, display pixels capable of displaying a color of a predetermined gradation are formed by three color pixels GPX, BPX, and RPX adjacent to each other along the X-axis direction.

[0028] As shown in FIG. 5, the display area AA of the counter substrate 20 is provided with a black matrix 29 that separates (at boundaries) adjacent pixels PX in the X-axis and Y-axis directions. The black matrix 29 is also provided in the non-display area NAA in addition to the display area AA. The black matrix 29 is formed in a lattice pattern so as to overlap with the TFTs 24, gate lines 26, and source lines 27 in the display area AA, but is generally solid in the non-display area NAA. An overcoat film 30 is provided above the color filters 28 and the black matrix 29. The overcoat film 30 is provided in a solid pattern over almost the entire surface of the counter substrate 20. The overcoat film 30 is made of an organic material such as acrylic resin (e.g., PMMA), and functions to smooth out any unevenness that occurs below the overcoat film 30. Note that an alignment film is formed on the innermost surface (top layer) of each of the substrates 20 and 21 that contacts the liquid crystal layer 22 to align the liquid crystal molecules contained in the liquid crystal layer 22.

[0029] Here, the various films laminated on the inner surface side of the array substrate 21 will be described with reference to Fig. 6. As shown in Fig. 6, the array substrate 21 has at least a first metal film (light-shielding film), a base coat film 31, a semiconductor film, a gate insulating film 32, a second metal film (first conductive film), a first interlayer insulating film (first insulating film) 33, a third metal film (second conductive film), a first planarizing film 34, a first transparent electrode film, a second interlayer insulating film (second insulating film) 35, a second transparent electrode film, and an alignment film laminated thereon in this order from the lower layer side (glass substrate side).

[0030] The first metal film, the second metal film, and the third metal film each have electrical conductivity and light-shielding properties. They may be single-layer films made of one metal material selected from Cu (copper), Ti (titanium), Al (aluminum), Mo (molybdenum), W (tungsten), etc., or multi-layer films or alloys made of different metal materials. The first metal film may be a single-layer film made of MoW (molybdenum tungsten), for example, and have a thickness of approximately 50 nm. The first metal film constitutes the light-shielding portion 37 described below. The second metal film may be a single-layer film made of MoW, for example, and have a thickness greater than that of the first metal film, for example, approximately 400 nm. The second metal film constitutes a portion of the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The third metal film may be a multi-layer film made of Ti / Al / Ti, for example, and have thicknesses of approximately 50 nm / 300 nm / 50 nm. The third metal film constitutes a part of the gate line 26, the source line 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes the common electrode 36, which will be described later, etc. The first transparent electrode film is made of, for example, ITO, and may have a thickness of, for example, about 50 nm. The second transparent electrode film constitutes the pixel electrode 25, etc. The second transparent electrode film is made of, for example, ITO, and may have a thickness of, for example, about 50 nm, the same as that of the first transparent electrode film.

[0031] The semiconductor film is made of a thin film of continuous grain silicon (CG silicon), a type of polycrystalline silicon thin film. CG silicon thin films are formed, for example, by adding a metal material to an amorphous silicon thin film and then performing a short-term heat treatment at a low temperature of approximately 550°C or less, which gives the silicon crystals continuous atomic arrangement at the grain boundaries. The semiconductor film constitutes the semiconductor portion 24D of the TFT 24.

[0032] The semiconductor film according to this embodiment is partially reduced in resistance by a resistance reduction process during the manufacturing process, and as a result, the semiconductor portion 24D includes a low-resistance region 24D1. The region of the semiconductor portion 24D that is not subjected to the resistance reduction process is the non-low-resistance region 24D2. Note that in FIG. 6 and other figures, the low-resistance region 24D1 in the semiconductor portion 24D is illustrated as a shaded region. The non-low-resistance region 24D2 in the semiconductor portion 24D allows charge movement only under specific conditions (when a scanning signal is supplied to the gate electrode 24A). In other words, the non-low-resistance region 24D2 functions as a channel region under specific conditions. The non-low-resistance region 24D2 is a portion of the semiconductor portion 24D that overlaps with the gate electrode 24A in a plan view. The low-resistance region 24D1 is a portion of the semiconductor portion 24D that does not overlap with the gate electrode 24A in a plan view. The low-resistance region 24D1 has an extremely low resistivity, for example, 1 / 10000000000 to 1 / 100, compared to the non-low-resistance region 24D2, allowing charge transfer at all times and functioning as a conductor. The semiconductor film is subjected to a resistance reduction process using the gate electrode 24A as a mask after the gate wiring 26 (including the gate electrode 24A) made of the second metal film is formed during the manufacturing process of the array substrate 21. The resistance reduction process selectively reduces the resistance of the semiconductor film in the portions not covered by the gate electrode 24A (non-overlapping portions, exposed portions), while not reducing the resistance of the portions covered by the gate electrode 24A (overlapping portions, non-exposed portions). Examples of the resistance reduction process include plasma treatment using gases such as NH3, H2, N2, and He, and annealing. The low-resistance region 24D1 includes a first low-resistance region 24D1 (source region) connected to the source electrode 24B, a second low-resistance region 24D1 (drain region) connected to the drain electrode 24C, and a third low-resistance region 24D1 connected to two non-low-resistance regions 24D2.

[0033] The base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 35 are each made of SiN. xThe base coat film 31 is a single layer film or a multilayer film made of an inorganic material such as silicon nitride (SiN) or silicon dioxide (SiO2). As shown in FIG. 6, the base coat film 31 is interposed between the first metal film and the semiconductor film, and keeps the light-shielding portion 37 (described later) and the semiconductor portion 24D in an insulated state. The base coat film 31 is also a base for the semiconductor film, and can prevent impurities from the glass substrate constituting the array substrate 21 from diffusing into the semiconductor film. The base coat film 31 is made of, for example, SiO2 / SiN x The first interlayer insulating film 33 is a laminated film made of, for example, SiO2 and may have a thickness of, for example, about 200 nm / 20 nm. The gate insulating film 32 is interposed between the semiconductor film and the second metal film, and keeps, for example, the gate electrode 24A and the semiconductor portion 24D in an insulating state. The gate insulating film 32 is a single layer film made of, for example, SiO2 and may have a thickness of, for example, about 130 nm. The first interlayer insulating film 33 is interposed between the second metal film and the third metal film, and keeps, for example, the intersection between the gate wiring 26 and the source wiring 27 in an insulating state. The first interlayer insulating film 33 is, for example, a laminated film made of, for example, SiO2 / SiN x The second interlayer insulating film 35 is interposed between the first transparent electrode film and the second transparent electrode film, and keeps the pixel electrode 25 and a common electrode 36 (described later) in an insulated state. The second interlayer insulating film 35 is made of, for example, SiN x The film may be a single layer made of the above, and the film thickness may be, for example, about 200 nm.

[0034] As shown in FIG. 6, the first planarization film 34 is interposed between the third metal film and the first transparent electrode film, and keeps the source lines 27 and the like insulated from a common electrode 36 (described later). The first planarization film 34 is made of an organic material such as PMMA (acrylic resin). The first planarization film 34 has a thickness of, for example, about 2.3 μm, which is much larger than the thicknesses of the base coat film 31, the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 35. The first planarization film 34 flattens the inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side).

[0035] The common electrode 36 will now be described. The common electrode 36, made of a first transparent electrode film, has an overall size equivalent to the display area AA. As shown in FIG. 5, the common electrode 36 is disposed below all of the pixel electrodes 25, with a second interlayer insulating film 35 interposed therebetween. A common potential (reference potential) is supplied to the common electrode 36. When the pixel electrodes 25 are charged to a potential based on an image signal transmitted to the source line 27 as the TFTs 24 are driven based on the scanning signal transmitted through the gate line 26, a potential difference is generated between the pixel electrodes 25 and the common electrode 36. This generates a fringe electric field (oblique electric field) between the opening edge of the slit 25A1 in the pixel electrode 25 and the common electrode 36, which includes a component normal to the main surface of the array substrate 21 in addition to a component along the main surface of the array substrate 21. Therefore, the orientation of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this fringe electric field, and a predetermined display can be achieved based on the orientation of the liquid crystal molecules. That is, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0036] Next, the relationship between the cross-sectional configuration of the TFT 24 and the above-described films of the array substrate 21 will be described with reference to FIG. 6 . As shown in FIG. 6 , the TFT 24 is a so-called top-gate type, in which the gate electrode 24A is disposed above the non-low-resistance region 24D2 of the semiconductor portion 24D via the gate insulating film 32. As shown in FIG. 6 , the array substrate 21 is provided with a light-shielding portion 37 made of a first metal film and overlapping the non-low-resistance region 24D2 of the semiconductor portion 24D. Because the light-shielding portion 37 is disposed below the non-low-resistance region 24D2 of the semiconductor portion 24D, it can block light irradiated from the backlight device onto the non-low-resistance region 24D2 of the semiconductor portion 24D from below. This suppresses fluctuations in the characteristics of the TFT 24 that may occur when light is irradiated onto the non-low-resistance region 24D2 of the semiconductor portion 24D. The light-shielding portion 37 has a rectangular shape in a plan view. The two light-shielding portions 37 are arranged at positions spaced apart in the X-axis direction so as to overlap the two non-low-resistance regions 24D2 provided in one semiconductor portion 24D.

[0037] As shown in FIG. 6 , a source contact hole CHS is formed in the first interlayer insulating film 33, which is interposed between one end of the semiconductor portion 24D of the TFT 24 and the source electrode 24B, at a position overlapping the two. One end of the semiconductor portion 24D and the source electrode 24B are connected through the source contact hole CHS in the first interlayer insulating film 33. A drain contact hole CHD is formed in the first interlayer insulating film 33, which is interposed between the other end of the semiconductor portion 24D and the drain electrode 24C, at a position overlapping the two. The other end of the semiconductor portion 24D and the drain electrode 24C are connected through the drain contact hole CHD in the first interlayer insulating film 33. The drain contact hole CHD is biased toward the source electrode 24B in the X-axis direction (left side in FIG. 4 ) and toward the pixel electrode body 25A in the Y-axis direction (upper side in FIG. 4 ) with respect to the center of the drain electrode 24C in a plan view.

[0038] As shown in FIG. 6 , an intermediate electrode 38 made of a part of the first transparent electrode film is provided at a position overlapping both the drain electrode 24C of the TFT 24 and the connection portion 25B of the pixel electrode 25. The intermediate electrode 38 is located midway between the drain electrode 24C and the pixel electrode 25 in the Z-axis direction. The intermediate electrode 38 has a rectangular shape in a plan view, and its size in the X-axis direction is equal to that of the drain electrode 24C, but its size in the Y-axis direction is smaller than that of the drain electrode 24C. A first pixel contact hole CHP1 is opened and provided in the first planarization film 34 interposed between the drain electrode 24C and the intermediate electrode 38 at a position overlapping the drain electrode 24C and the intermediate electrode 38. The intermediate electrode 38 is connected to the drain electrode 24C through the first pixel contact hole CHP1. A second pixel contact hole CHP2 is opened and provided in the second interlayer insulating film 35 interposed between the intermediate electrode 38 and the connection portion 25B of the pixel electrode 25 at a position overlapping the connection portion 25B of the intermediate electrode 38 and the pixel electrode 25. The connection portion 25B of the pixel electrode 25 is connected to the intermediate electrode 38 through the second pixel contact hole CHP2. In this way, the pixel electrode 25 is connected to the drain electrode 24C via the intermediate electrode 38.

[0039] As shown in FIGS. 4 and 6 , the intermediate electrode 38 described above is island-shaped and physically separated from the common electrode 36, which is formed from another portion of the same first transparent electrode film. Specifically, the common electrode 36 has an opening 36A surrounding the intermediate electrode 38. The opening 36A has a generally rectangular frame shape in a plan view. The opening 36A has a first slit 36A1 extending to one side (the right side in FIG. 4 ) along the X-axis direction and a second slit 36A2 extending to the other side (the left side in FIG. 4 ) along the X-axis direction. The opening 36A configured in this manner prevents short-circuiting between the common electrode 36 and the intermediate electrode 38 and also avoids localized charge buildup caused by electric field concentration between the common electrode 36 and the pixel electrode 25 when the pixel electrode 25 is energized for a long period of time.

[0040] Here, as shown in FIG. 4, of the three source wirings 27 aligned along the X-axis direction, the source wiring 27 located at the center of FIG. 4 is referred to as the "first source wiring (second wiring) 27α," the source wiring 27 located at the right end of FIG. 4 is referred to as the "second source wiring (third wiring) 27β," and the source wiring 27 located at the left end of FIG. 4 is referred to as the "third source wiring (fourth wiring) 27γ." Of the two pixel electrodes 25 aligned along the X-axis direction, the pixel electrode 25 sandwiched between the first source wiring 27α and the third source wiring 27γ in the X-axis direction is referred to as the "first pixel electrode 25α," and the pixel electrode 25 sandwiched between the first source wiring 27α and the second source wiring 27β in the X-axis direction is referred to as the "second pixel electrode 25β." Furthermore, the pixel electrode body 25A included in the first pixel electrode 25α is referred to as the "first pixel electrode body 25Aα," and the connection portion 25B included in the first pixel electrode 25α is referred to as the "first connection portion 25Bα." Of the two TFTs 24 aligned along the X-axis direction, the TFT 24 connected to the first pixel electrode 25α is referred to as the "first TFT (first switching element) 24α," and the TFT 24 connected to the second pixel electrode 25β is referred to as the "second TFT (second switching element) 24β." Furthermore, the gate electrode 24A of the first TFT 24α is referred to as the "first gate electrode (second electrode) 24Aα," the source electrode 24B of the first TFT 24α is referred to as the "first source electrode (sixth electrode) 24Bα," the drain electrode 24C of the first TFT 24α is referred to as the "first drain electrode (first electrode) 24Cα," and the semiconductor portion 24D of the first TFT 24α is referred to as the "first semiconductor portion 24Dα." Furthermore, the gate electrode 24A provided in the second TFT 24β is referred to as the "second gate electrode (fourth electrode) 24Aβ", the source electrode 24B provided in the second TFT 24β is referred to as the "second source electrode 24Bβ", the drain electrode 24C provided in the second TFT 24β is referred to as the "second drain electrode (third electrode) 24Cβ", and the semiconductor portion 24D provided in the second TFT 24β is referred to as the "second semiconductor portion 24Dβ".

[0041] 4, the first TFT 24α and the second TFT 24β are driven based on scanning signals supplied to the first gate electrode 24Aα and the second gate electrode 24Aβ by the gate wiring 26. An image signal supplied from the driver 12 to the third source wiring 27γ is supplied from the first source electrode 24Bα to the first drain electrode 24Cα via the first semiconductor portion 24Dα, and the first pixel electrode 25α is charged to a potential related to the image signal. An image signal supplied from the driver 12 to the second source wiring 27β is supplied from the second source electrode 24Bβ to the second drain electrode 24Cβ via the second semiconductor portion 24Dβ, and the second pixel electrode 25β is charged to a potential related to the image signal.

[0042] As shown in FIGS. 7 and 8, the gate wiring 26 according to this embodiment has a divided structure and includes at least a first wiring portion 26A, a second wiring portion 26B, and a first connection electrode 26C. Note that in FIG. 7, the portion made of the second metal film and the portion made of the third metal film are shown with different hatching. The first wiring portion 26A and the second wiring portion 26B are each made of a portion of the second metal film and extend along the X-axis direction. In contrast, the first connection electrode 26C is made of a portion of the third metal film, extends along the Y-axis direction, and is connected to the first wiring portion 26A and the second wiring portion 26B.

[0043] As shown in FIG. 7, the first wiring portion 26A is disposed adjacent to the second wiring portion 26B on the left side of FIG. 7, and the second wiring portion 26B is disposed adjacent to the first wiring portion 26A on the right side of FIG. 7. The boundary between the first wiring portion 26A and the second wiring portion 26B is located between the first source wiring 27α and the third source wiring 27γ in the X-axis direction, more specifically, between the first drain electrode 24Cα and the first source wiring 27α in the X-axis direction. Of the two ends of the first wiring portion 26A in the X-axis direction, the end located on the second wiring portion 26B side (the right side in FIG. 7) is defined as a first end 26A1. The first end 26A1 is located between the first drain electrode 24Cα (the first connection portion 25Bα and the intermediate electrode 38) and the first source wiring 27α in the X-axis direction. Specifically, the first end 26A1 is disposed closer to the first drain electrode 24Cα than the first source wiring 27α in the X-axis direction. Of both end portions of the second wiring configuration portion 26B in the X-axis direction, the end portion located on the first wiring configuration portion 26A side (the left side in FIG. 7) is defined as the second end 26B1. The second end 26B1 is disposed between the first drain electrode 24Cα and the first source wiring 27α in the X-axis direction. Specifically, the second end 26B1 is disposed closer to the first source wiring 27α than the first drain electrode 24Cα in the X-axis direction. The second end 26B1 is disposed on the same side (upper side in FIG. 7) as the first drain electrode 24Cα in the Y-axis direction, with a gap between them. In detail, the second end 26B1 is sandwiched between the first end 26A1 and the first pixel electrode body 25Aα of the first pixel electrode 25α in the Y-axis direction, and is positioned closer to the first pixel electrode body 25Aα than the first end 26A1.

[0044] 7 and 8, one end of the first connection electrode 26C overlaps the first end 26A1 of the first wiring portion 26A, and the other end overlaps the second end 26B1 of the second wiring portion 26B. The first connection electrode 26C extends generally along the Y-axis direction to straddle the first end 26A1 of the first wiring portion 26A and the second end 26B1 of the second wiring portion 26B. More specifically, the first connection electrode 26C protrudes from the first end 26A1 along the X-axis direction toward the first source wiring 27α, is bent, and then extends toward the second end 26B1 along the Y-axis direction to reach the second end 26B1. The first interlayer insulating film 33 is provided with a first contact hole CH1 that overlaps both the first end 26A1 of the first wiring component 26A and one end of the first connection electrode 26C, and a second contact hole CH2 that overlaps both the second end 26B1 of the second wiring component 26B and the other end of the first connection electrode 26C.

[0045] The gate wiring 26 having the above-described configuration can provide the following actions and effects. That is, in manufacturing the array substrate 21, at the stage where the second metal film is formed and patterned, the first wiring component 26A and the second wiring component 26B that constitute the gate wiring 26 are provided. At this time, the first wiring component 26A and the second wiring component 26B are not connected to each other. Therefore, compared to a case where the gate wiring is made only of the second metal film and the first wiring component and the second wiring component are connected, electrostatic discharge due to peeling electrification is less likely to occur in the first wiring component 26A and the second wiring component 26B. After the second metal film is patterned, a first interlayer insulating film 33 is deposited and patterned. This results in a first contact hole CH1 formed in the first interlayer insulating film 33 at a position overlapping the first end 26A1 of the first wiring component 26A, and a second contact hole CH2 formed in the first interlayer insulating film 33 at a position overlapping the second end 26B1 of the second wiring component 26B. A third metal film is then deposited and patterned, resulting in the formation of a first source wiring 27α, a first drain electrode 24Cα, a first connection electrode 26C, and the like. As shown in FIG. 8 , the first connection electrode 26C is connected to the first end 26A1 of the first wiring component 26A through the first contact hole CH1 and to the second end 26B1 of the second wiring component 26B through the second contact hole CH2. The first wiring component 26A, the second wiring component 26B, and the first connection electrode 26C are interconnected to form the gate wiring 26.

[0046] 7 and 8, the first connection electrode 26C extends across the first end 26A1 and the second end 26B1, which is spaced apart from the first end 26A1 on the same side as the first drain electrode 24Cα in the Y-axis direction and is sandwiched between the first source wiring 27α and the first drain electrode 24Cα in the X-axis direction, so that the distance between the first connection electrode 26C and the first drain electrode 24Cα in the X-axis direction and the distance between the first connection electrode 26C and the first source wiring 27α in the X-axis direction can be sufficiently secured while the distance between the first drain electrode 24Cα and the first source wiring 27α in the X-axis direction can be reduced, which is advantageous for achieving high definition.

[0047] 7, the second end 26B1 of the first connection electrode 26C, which overlaps the other end, is sandwiched between the first end 26A1 and the first pixel electrode main body 25Aα of the first pixel electrode 25α in the Y-axis direction, so that the first connection electrode 26C can be said to be sandwiched between the first wiring component 26A and the first pixel electrode main body 25Aα in the Y-axis direction. In this way, the first connection electrode 26C is disposed so as not to overlap with the first pixel electrode 25α, thereby reducing parasitic capacitance that may occur between the gate wiring 26 and the first pixel electrode 25α.

[0048] In this embodiment, as shown in FIG. 7 , the first end 26A1 and the second end 26B1 are arranged to partially overlap each other in the X-axis direction. Specifically, the edge of the first end 26A1 on the first source wiring 27α side in the X-axis direction overlaps the edge of the second end 26B1 on the first drain electrode 24Cα side in the X-axis direction. In this manner, the arrangement space in the X-axis direction of the first connection electrode 26C extending across the first end 26A1 and the second end 26B1 is smaller than in a case where the first end and the second end do not overlap in the X-axis direction. This allows the distance between the first drain electrode 24Cα and the first source wiring 27α to be further reduced, which is more suitable for achieving high definition.

[0049] As shown in FIG. 7, the first wiring portion 26A according to this embodiment extends linearly along the X-axis direction, its line width varying midway, and includes at least a wide portion 26A2 and a narrow portion 26A3 that is narrower than the wide portion 26A2. The wide portion 26A2 is disposed adjacent to the first drain electrode 24Cα with a gap in the Y-axis direction, and includes the first end portion 26A1 at the end opposite the narrow portion 26A3 in the X-axis direction. The wide portion 26A2 extends away from the first drain electrode 24Cα in the Y-axis direction (the lower side in FIG. 7). Therefore, of the two side edges of the first wiring portion 26A, the edge opposite the first drain electrode 24Cα in the Y-axis direction is curved, while the edge adjacent to the first drain electrode 24Cα in the Y-axis direction (the upper side in FIG. 7) is linear. The narrow portion 26A3 is disposed on the opposite side of the wide portion 26A2 from the second wiring portion 26B in the X-axis direction, and intersects with the third source wiring 27γ and the first semiconductor portion 24Dα.

[0050] As shown in FIG. 7, the second wiring portion 26B has a main body portion 26B2 that is collinear with the first wiring portion 26A and a bent portion 26B3 that is bent from the main body portion 26B2 and extends to the second end portion 26B1. Specifically, the main body portion 26B2 extends linearly along the X-axis direction, and similar to the first wiring portion 26A, its line width varies along the way. The main body portion 26B2 has at least a wide portion 26B2A and two narrow portions 26B2B that are narrower than the wide portion 26B2A. Of these, the wide portion 26B2A is adjacent to the second drain electrode 24Cβ with a gap in the Y-axis direction. The wide portion 26B2A extends away from the narrow portion 26B2B in the Y-axis direction (toward the bottom in FIG. 7). Therefore, of both side edges of the main body portion 26B2, the side edge opposite to the second drain electrode 24Cβ side in the Y-axis direction is curved, whereas the side edge on the second drain electrode 24Cβ side in the Y-axis direction (the upper side in FIG. 7) is straight and located on the same straight line as the side edge on the first drain electrode 24Cα side of the first wiring component 26A. In this way, the first wiring component 26A and the main body portion 26B2 of the second wiring component 26B extend along the X-axis direction and are aligned with each other, which reduces the influence of the gate wiring 26 on the arrangement of other structures (e.g., the TFT 24, the pixel electrode 25, etc.) compared to a case where the first wiring component and the main body portion are displaced in the Y-axis direction.

[0051] 7, one narrow portion 26B2B of the two narrow portions 26B2B included in the second wiring portion 26B is disposed closer to the first wiring portion 26A than the main body portion 26B2 in the X-axis direction and intersects with the first source wiring 27α and the second semiconductor portion 24Dβ. The other narrow portion 26B2B of the two narrow portions 26B2B is disposed on the opposite side of the main body portion 26B2 from the first wiring portion 26A in the X-axis direction and intersects with the second source wiring 27β. In this way, the second wiring portion 26B is disposed so as to intersect with each of the first source wiring 27α and the second source wiring 27β via the first interlayer insulating film 33. That is, since the second wiring configuration portion 26B has an undivided structure at least between the first source wiring 27α and the second source wiring 27β in the X-axis direction, a connection structure accompanying the division is not required, compared to a case in which the second wiring configuration portion is divided between the first source wiring 27α and the second source wiring 27β and the divided portions are connected to each other by a connection electrode, which is advantageous in improving yield.

[0052] As shown in FIG. 7, the bent portion 26B3 has the same width as the narrow portion 26B2B of the main body portion 26B2. The bent portion 26B3 extends generally along the Y-axis direction to straddle the end of the main body portion 26B2 on the first end 26A1 side and the second end 26B1. More specifically, the bent portion 26B3 includes a first bent portion 26B3A extending from the end of the main body portion 26B2 on the first end 26A1 side along the Y-axis direction toward the second end 26B1 side (upper side in FIG. 7), and a second bent portion 26B3B extending from the end of the first bent portion 26B3A in a direction oblique to the X-axis and Y-axis directions. The first bent portion 26B3A is parallel to the first connection electrode 26C and is positioned slightly spaced apart from the first connection electrode 26C in the X-axis direction. The second bent portion 26B3B intersects the first connection electrode 26C and is connected to the second end 26B1. The second end 26B1 is wider than the bent portion 26B3 and has approximately the same width as the wide portion 26B2A of the main body portion 26B2. The first connection electrode 26C has both end portions overlapping the first end 26A1 and the second end 26B1 that are wider than the central portion. The central portion of the first connection electrode 26C that is connected to both end portions has approximately the same width as the narrow portions 26A3 and 26B2B. Thus, the bent portion 26B3 is disposed between the first connection electrode 26C and the first source wiring 27α in the X-axis direction. This ensures a sufficient distance between the first end 26A1 and the bent portion 26B3 in the X-axis direction. This makes it less likely that a short circuit will occur between the first wiring configuration 26A and the second wiring configuration 26B when the second metal film is deposited and patterned during the manufacture of the array substrate 21, thereby increasing the reliability of suppressing electrostatic discharge.

[0053] As described above, the array substrate 21 of this embodiment includes the gate wiring (first wiring) 26 extending along the first direction, the first source wiring (second wiring) 27α extending along the second direction intersecting the first direction, the first drain electrode (first electrode) 24Cα arranged at a distance from the gate wiring 26 in the second direction and at a distance from the first source wiring 27α in the first direction, and the first interlayer insulating film (first insulating film) 33. The gate wiring 26 has a first wiring component 26A made of a second metal film (first conductive film) arranged on the lower side of the first interlayer insulating film 33, a second wiring component 26B made of a part of the second metal film different from the first wiring component 26A, and a first connection electrode 26C made of a third metal film (second conductive film) arranged on the upper side of the first interlayer insulating film 33. The first source wiring 27α is connected to the first connection electrode 26C of the third metal film. the first wiring component 26A has a first end 26A1; the second wiring component 26B has a second end 26B1 spaced from the first end 26A1 on the same side as the first drain electrode 24Cα in the second direction and sandwiched between the first source wiring 27α and the first drain electrode 24Cα in the first direction; the first connection electrode 26C extends to straddle the first end 26A1 and the second end 26B1; and the first interlayer insulating film 33 is provided with a first contact hole CH1 overlapping the first end 26A1 and the first connection electrode 26C, and a second contact hole CH2 overlapping the second end 26B1 and the first connection electrode 26C.

[0054] During the manufacture of the array substrate 21, after the second metal film is deposited and patterned, the first wiring component 26A and the second wiring component 26B that constitute the gate wiring 26 are provided. Because the first wiring component 26A and the second wiring component 26B are disconnected from each other, electrostatic discharge due to peeling charge is less likely to occur in the first wiring component 26A and the second wiring component 26B than if they were connected. After that, after the first interlayer insulating film 33 is deposited and patterned, a first contact hole CH1 is formed in the first interlayer insulating film 33 at a position overlapping the first end 26A1 of the first wiring component 26A, and a second contact hole CH2 is formed in the first interlayer insulating film 33 at a position overlapping the second end 26B1 of the second wiring component 26B. After that, after the third metal film is deposited and patterned, the first source wiring 27α, the first drain electrode 24Cα, the first connecting electrode 26C, and the like are provided. The first connection electrode 26C is connected to a first end 26A1 of the first wiring portion 26A through a first contact hole CH1, and is connected to a second end 26B1 of the second wiring portion 26B through a second contact hole CH2. The first wiring portion 26A, the second wiring portion 26B, and the first connection electrode 26C are connected to each other and form the gate wiring 26.

[0055] The first connection electrode 26C extends across the first end 26A1 and the second end 26B1, which is spaced apart from the first end 26A1 on the same side as the first drain electrode 24Cα in the second direction and is sandwiched between the first source wiring 27α and the first drain electrode 24Cα in the first direction. This makes it possible to reduce the distance between the first drain electrode 24Cα and the first source wiring 27α while ensuring a sufficient distance between the first connection electrode 26C and the first drain electrode 24Cα and between the first connection electrode 26C and the first source wiring 27α. This is advantageous for achieving high definition.

[0056] The first wiring component 26A extends in the first direction, and the second wiring component 26B has a main body 26B2 that extends in the first direction and is collinear with the first wiring component 26A, and a bent portion 26B3 that is bent from the main body 26B2 and extends to the second end 26B1. Because the first wiring component 26A and the main body 26B2 of the second wiring component 26B extend in the first direction and are collinear with each other, the influence of the gate wiring 26 on the arrangement of other structures can be reduced. Furthermore, the bent portion 26B3, which is bent from the main body 26B2, is connected to the second end 26B1, thereby connecting the main body 26B2 and the second end 26B1.

[0057] Furthermore, the bent portion 26B3 is disposed between the first connection electrode 26C and the first source wiring 27α in the first direction. This allows a sufficient gap to be provided in the first direction between the first end 26A1 and the bent portion 26B3. This makes it less likely that a short circuit will occur between the first wiring component 26A and the second wiring component 26B when the second metal film is formed and patterned during the manufacture of the array substrate 21, thereby increasing the reliability of suppressing electrostatic discharge.

[0058] Furthermore, the first end 26A1 and the second end 26B1 are arranged to overlap each other in the first direction. In this manner, the arrangement space in the first direction of the first connection electrode 26C extending to straddle the first end 26A1 and the second end 26B1 is smaller than in a case where the first end and the second end do not overlap in the first direction. This allows the distance between the first drain electrode 24Cα and the first source wiring 27α to be further reduced, which is more suitable for achieving higher definition.

[0059] The pixel electrode 25α further includes a first TFT (first switching element) 24α having a first drain electrode 24Cα and a first pixel electrode 25α connected to the first drain electrode 24Cα, the first TFT 24α having a first gate electrode (second electrode) 24Aα formed of a part of the first wiring configuration 26A, the first pixel electrode 25α having a first connection portion 25Bα connected to the first drain electrode 24Cα and a first pixel electrode body 25Aα disposed on the opposite side of the first connection portion 25Bα from the gate wiring 26 in the second direction, the first connection electrode 26C being sandwiched between the first wiring configuration 26A and the first pixel electrode body 25Aα in the second direction. The first TFT 24α is driven based on a signal supplied to the first gate electrode 24Aα by the gate wiring 26, and is capable of supplying a potential from the first drain electrode 24Cα to the first pixel electrode 25α. The first connection electrode 26C is arranged sandwiched between the first wiring component 26A and the first pixel electrode main body 25Aα in the second direction, and is arranged so as not to overlap with the first pixel electrode 25α, thereby reducing the parasitic capacitance that may occur between the gate wiring 26 and the first pixel electrode 25α.

[0060] Furthermore, a first TFT 24α having a first drain electrode 24Cα, a first pixel electrode 25α connected to the first drain electrode 24Cα, a second source wiring (third wiring) 27β extending along the second direction and arranged at an interval on the opposite side of the first drain electrode 24Cα in the first direction with respect to the first source wiring 27α, a second drain electrode (third electrode) 24Cβ spaced apart from the gate wiring 26 on the same side as the first drain electrode 24Cα in the second direction and sandwiched between the first source wiring 27α and the second source wiring 27β in the first direction, a second TFT (second switching element) 24β having the second drain electrode 24Cβ, and a second pixel electrode 25α connected to the second drain electrode 24Cβ. 25β, the first TFT 24α has a first gate electrode 24Aα consisting of a part of the first wiring configuration portion 26A, the second TFT 24β has a second gate electrode (fourth electrode) 24Aβ consisting of a part of the second wiring configuration portion 26B, the second source wiring 27β consists of a part of the third metal film that is different from the first connection electrode 26C, the first source wiring 27α, and the first drain electrode 24Cα, the second drain electrode 24Cβ consists of a part of the third metal film that is different from the first connection electrode 26C, the first source wiring 27α, the first drain electrode 24Cα, and the second source wiring 27β, and the second wiring configuration portion 26B intersects with the first source wiring 27α and the second source wiring 27β via the first interlayer insulating film 33. The first TFT 24α is driven based on a signal supplied to the first gate electrode 24Aα by the gate wiring 26, and can supply a potential from the first drain electrode 24Cα to the first pixel electrode 25α. The second TFT 24β is driven based on a signal supplied to the second gate electrode 24Aβ by the gate wiring 26, and can supply a potential from the second drain electrode 24Cβ to the second pixel electrode 25β. The second wiring component 26B intersects with each of the first source wiring 27α and the second source wiring 27β via the first interlayer insulating film 33. In other words, the second wiring component 26B has an undivided structure at least between the first source wiring 27α and the second source wiring 27β in the first direction. Therefore, compared to a case in which the second wiring component is divided between the first source wiring 27α and the second source wiring 27β and the divided portions are connected by a connecting electrode, no connecting structure is required for the division.This is advantageous in improving yield.

[0061] The liquid crystal panel (display device) 11 according to this embodiment includes the above-described array substrate 21 and a counter substrate 20 disposed opposite to and spaced apart from the array substrate 21. The liquid crystal panel 11 configured in this manner can achieve high definition.

[0062] <Embodiment 2> A second embodiment will be described with reference to Figures 9 to 11. In this second embodiment, a touch panel function is added. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0063] As shown in FIG. 9, the liquid crystal panel 111 according to this embodiment has both a display function for displaying an image and a touch panel function for detecting a position (input position) at which a user inputs based on the displayed image. A touch panel pattern for realizing the touch panel function is integrated (in-cell) into the liquid crystal panel 111. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. The touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 39 arranged in a matrix on the main surface of the liquid crystal panel 111. The touch electrodes 39 are arranged in a display area AA of the liquid crystal panel 111. Therefore, the display area AA of the liquid crystal panel 111 substantially coincides with a touch area (position input area) where an input position can be detected, and the non-display area NAA substantially coincides with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface of liquid crystal panel 111 to input a position based on the image in display area AA of liquid crystal panel 111 that is visually recognized, capacitance is formed between the finger and touch electrode 39. As a result, the capacitance detected at touch electrode 39 near the finger changes as the finger approaches, and becomes different from that of touch electrode 39 farther away from the finger, making it possible to detect the input position based on this.

[0064] As shown in FIG. 9 , the touch electrodes 39 are formed by dividing the common electrode 136. Specifically, the common electrode 136 has partition slits that form a grid in a plan view. The partition slits divide the common electrode 136 into a grid pattern, thereby forming a plurality of electrically independent touch electrodes 39. The plurality of touch electrodes 39 arranged in a grid pattern are separated by the partition slits. Note that the specific number of touch electrodes 39 can be changed as appropriate, in addition to the number shown in FIG. 6 . The touch electrode 39 has a substantially rectangular shape in a plan view, with each side measuring approximately several millimeters. Therefore, the size of the touch electrode 39 in a plan view is much larger than that of the pixel PX, and the touch electrode 39 is arranged in an area that spans multiple pixels PX in the X-axis direction and the Y-axis direction.

[0065] As shown in FIGS. 10 and 11 , a plurality of touch wirings (position detection wirings) 40 connected to a plurality of touch electrodes 39 are provided on the inner surface of the display area AA of the array substrate 121. The touch wirings 40 extend along the Y-axis direction parallel to the source wirings 127 and are arranged so as to overlap the source wirings 127 in a plan view. The plurality of touch wirings 40 are individually connected to the plurality of touch electrodes 39. Ends of the plurality of touch wirings 40 opposite to the touch electrodes 39 to which they are connected are each connected to a driver 112 (see FIG. 9 ). A common signal (reference potential signal) related to the display function and a touch signal (position detection signal) related to the touch function are supplied to the touch wirings 40 from the driver 112 at different timings (in a time-division manner). The timing when the common signal is supplied from the driver 112 to the touch wirings 40 is a display period, and the timing when the touch signal is supplied from the driver 112 to the touch wirings 40 is a sensing period (position detection period). During the display period, a common signal is supplied to all the touch wirings 40, so that all the touch electrodes 39 have a reference potential and function as the common electrode 136.

[0066] As shown in FIG. 11 , the array substrate 121 has a fourth metal film provided above the first planarization film 134, and a second planarization film 41 provided above the fourth metal film and below the first transparent electrode film. The fourth metal film constitutes the touch wiring 40. The fourth metal film may have a similar configuration to the third metal film. Specifically, the fourth metal film may be a laminated film of Ti / Al / Ti or the like, in that order from bottom to top, with thicknesses of approximately 50 nm / 300 nm / 50 nm. Like the first planarization film 34, the second planarization film 41 may be made of an organic material such as PMMA (acrylic resin) with a thickness of approximately 2.3 μm. The second planarization film 41 is interposed between the third metal film and the first transparent electrode film, and keeps the touch wiring 40 and the common electrode 136 (touch electrode 39) insulated from each other. In addition, in the second planarization film 41, at a position where it overlaps both the touch wiring 40 and the touch electrode 39 to which the touch wiring 40 is connected, a contact hole (not shown) is opened to connect the two.

[0067] As shown in FIG. 10, the common electrode 136 according to this embodiment is configured such that the second slit 136A2 included in the opening 136A is longer in the X-axis direction than the first slit 136A1. Specifically, the first slit 136A1 is shorter in the X-axis direction than the first slit 36A1 (see FIG. 7) described in the first embodiment. On the other hand, the second slit 136A2 is longer in the X-axis direction than the second slit 36A2 (see FIG. 7) described in the first embodiment. The sum of the lengths of the first slit 136A1 and the second slit 136A2 in the X-axis direction is approximately equal to the sum of the lengths of the first slit 36A1 and the second slit 36A2 described in the first embodiment. Therefore, the opening area of ​​the opening 136A according to this embodiment is approximately equal to that of the opening 36A (see FIG. 7) described in the first embodiment, ensuring a sufficient opening area. Here, the partition slit separating two touch electrodes 39 adjacent to each other in the Y-axis direction is configured by connecting the first slit 136A1 and the second slit 136A2 included in each opening 136A adjacent to each other in the X-axis direction. Therefore, a difference in opening area occurs between the opening 136A that forms the partition slit and the opening 136A that does not form the partition slit. This difference in opening area may cause a difference in parasitic capacitance between the touch electrode 39 and the wiring (gate wiring 126 or source wiring 127) that is disposed near the opening 136A. In this regard, as described above, the opening 136A according to this embodiment has an opening area that is substantially equal to that of the opening 36A described in the first embodiment (see FIG. 7 ), ensuring a sufficient opening area. This makes it difficult for the difference in parasitic capacitance to occur, thereby making it difficult for display unevenness to be visually recognized.

[0068] As shown in FIG. 10, the common electrode 136 is arranged such that the second slit 136A2 included in the opening 136A does not overlap the second end 126B1 and the first connection electrode 126C. That is, the length of the second slit 136A2 in the X-axis direction extends from the main body of the opening 136A to a position just before the second end 126B1 and the first connection electrode 126C. Accordingly, as shown in FIG. 11, the common electrode 136 has an overlapping portion 136B that overlaps the second end 126B1 and the other end of the first connection electrode 126C. With this configuration, the overlapping portion 136B can shield an electric field that may occur between the first connection electrode 126C and the first pixel electrode 125α. This is advantageous for maintaining the potential of the first pixel electrode 125α.

[0069] As described above, this embodiment includes a first TFT 124α having a first drain electrode 124Cα, a first pixel electrode 125α connected to the first drain electrode 124Cα, a second interlayer insulating film (second insulating film) 135 disposed below the first pixel electrode 125α, and a common electrode 136 disposed below the second interlayer insulating film 135 so as to overlap with the first pixel electrode 125α, wherein the first TFT 124α has a first gate electrode 124Aα formed of a part of the first wiring component 126A, and the common electrode 136 has an opening 136A surrounding the first drain electrode 124Cα and an overlapping portion 136B overlapping with the first connection electrode 126C. The first TFT 124α is driven based on a signal supplied to the first gate electrode 124Aα by the gate wiring 126, and can supply a potential from the first drain electrode 124Cα to the first pixel electrode 125α. An electric field is generated between the charged first pixel electrode 125α and the common electrode 136 overlapping it via the second interlayer insulating film 135. The opening 136A of the common electrode 136 is arranged to surround the first drain electrode 124Cα, thereby reducing parasitic capacitance that may occur between the common electrode 136 and wiring (including the gate wiring 126 and the first source wiring 127α) located near the first drain electrode 124Cα. The common electrode 136 has an overlapping portion 136B that overlaps the first connection electrode 126C, which can shield an electric field that may occur between the first connection electrode 126C and the first pixel electrode 125α. This is advantageous for maintaining the potential of the first pixel electrode 125α.

[0070] Furthermore, the common electrode 136 is configured such that the opening 136A has a first slit 136A1 extending along the first direction toward the first connection electrode 126C and a second slit 136A2 extending along the first direction toward the opposite side of the first connection electrode 126C and longer than the first slit 136A1. The length of the first slit 136A1 of the opening 136A extending along the first direction toward the first connection electrode 126C is limited so as not to overlap with the first connection electrode 126C (so as to ensure overlapping portion 136B). In contrast, the second slit 136A2 of the opening 136A extending along the first direction toward the opposite side of the first connection electrode 126C is longer than the first slit 136A1. Therefore, even if the length of the first slit 136A1 is limited, a sufficient opening area of ​​the opening 136A can be ensured.

[0071] <Embodiment 3> A third embodiment will be described with reference to Fig. 12. In this third embodiment, the configuration of the TFT 224 is changed from that of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0072] 12, in the TFT 224 according to this embodiment, the semiconductor portion 224D is arranged so as to be bent (twice along the way) from the source electrode 224B to the drain electrode 224C. Specifically, the semiconductor portion 224D extends along the Y-axis direction from one end overlapping the source electrode 224B so as to overlap the source wiring 227 for a predetermined length, bent at a position beyond the gate wiring 226, and extends along the X-axis direction toward the drain electrode 224C (to the right in FIG. 12). Then, the semiconductor portion 224D is bent again and extends along the Y-axis direction toward the drain electrode 224C (upper side in FIG. 12) to reach the drain electrode 224C. Accordingly, the drain electrode 224C is arranged to be biased toward the source electrode 224B (left side in FIG. 12) that constitutes the same TFT 224 in the X-axis direction. For example, the first drain electrode 224C constituting the first TFT 224α is disposed closer to the third source wiring 227γ in the X-axis direction than the first source wiring 227α. As the drain electrode 224C is unevenly distributed in the X-axis direction, the distance between two adjacent source wirings 227 in the X-axis direction and the short side dimension of the pixel electrode 225 become smaller than those in the first embodiment (see FIG. 7). This allows the arrangement pitch of the pixels PX to be narrowed, which is suitable for achieving even higher resolution.

[0073] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 13 or 14. In this fourth embodiment, the configuration of the gate wiring 326 and the like is changed from that of the third embodiment. Note that redundant descriptions of the structure, action, and effects similar to those of the first and third embodiments will be omitted.

[0074] 13 , the gate wiring 326 according to this embodiment has at least a third wiring portion 326D and a second connection electrode 326E in addition to a first wiring portion 326A, a second wiring portion 326B, and a first connection electrode 326C. Like the first wiring portion 326A and the second wiring portion 326B, the third wiring portion 326D is made of a part of the second metal film and extends along the X-axis direction. In contrast, like the first connection electrode 326C, the second connection electrode 326E is made of a part of the third metal film and extends along the Y-axis direction, and is connected to the second wiring portion 326B and the third wiring portion 326D.

[0075] Here, as shown in FIG. 13, the five source wirings 327 lined up along the X-axis direction include a third source wiring 327γ that intersects with the first wiring configuration portion 326A, and a first source wiring 327α and a second source wiring 327β that intersect with the second wiring configuration portion 326B. The source wiring 327 that is arranged on the opposite side of the first source wiring 327α in the X-axis direction (the right side of FIG. 13) from the second source wiring 327β and spaced apart is referred to as the “fourth source wiring (fifth wiring) 327δ,” and the source wiring 327 that is arranged on the side of the second source wiring 327β in the X-axis direction (the left side of FIG. 13) and spaced apart from the fourth source wiring 327δ is referred to as the “fifth source wiring (sixth wiring) 327ε.” The four pixel electrodes 325 aligned along the X-axis direction include a first pixel electrode 325α and a second pixel electrode 325β, but the pixel electrode 325 sandwiched between the fourth source wiring 327δ and the fifth source wiring 327ε in the X-axis direction is referred to as the “third pixel electrode 325γ,” and the pixel electrode 325 sandwiched between the second source wiring 327β and the fifth source wiring 327ε in the X-axis direction is referred to as the “fourth pixel electrode 325δ.” Furthermore, the pixel electrode body 325A included in the third pixel electrode 325γ is referred to as the “third pixel electrode body 325Aγ,” and the connection portion 325B included in the third pixel electrode 325γ is referred to as the “third connection portion 325Bγ.” The five TFTs 524 arranged along the X-axis direction include a first TFT 324α and a second TFT 324β, and the TFT 324 connected to the third pixel electrode 325γ is referred to as a “third TFT (third switching element) 324γ.” In addition, the gate electrode 324A provided in the third TFT 324γ is referred to as a “third gate electrode (seventh electrode) 324Aγ,” the source electrode 324B provided in the third TFT 324γ is referred to as a “third source electrode (eighth electrode) 324Bγ,” the drain electrode 324C provided in the third TFT 324γ is referred to as a “third drain electrode (fifth electrode) 324Cγ,” and the semiconductor portion 324D provided in the third TFT 324γ is referred to as a “third semiconductor portion 324Dγ.” Of these, the third drain electrode 324Cγ is spaced apart from the gate wiring 326 on the same side (upper side in Figure 13) as the first drain electrode 324Cα in the Y-axis direction, and is sandwiched between the fourth source wiring 327δ and the fifth source wiring 327ε in the X-axis direction.

[0076] 13, the third TFT 324γ, together with the first TFT 324α and the second TFT 324β, is driven based on a scanning signal supplied to the third gate electrode 324Aγ by the gate wiring 326. An image signal supplied from the driver 12 to the fifth source wiring 327ε is supplied from the third source electrode 324Bγ to the third drain electrode 324Cγ via the third semiconductor portion 324Dγ, and the third pixel electrode 325γ is charged to a potential related to the image signal.

[0077] As shown in FIG. 13, the third wiring configuration portion 326D is disposed adjacent to the second wiring configuration portion 326B on the right side of FIG. 13. The boundary between the second wiring configuration portion 326B and the third wiring configuration portion 326D is located between the fourth source wiring 327δ and the fifth source wiring 327ε in the X-axis direction, more specifically, between the third drain electrode 324Cγ and the fourth source wiring 327δ in the X-axis direction. Of the two ends of the second wiring configuration portion 326B in the X-axis direction, the end located on the opposite side to the second end 326B1 (the third wiring configuration portion 326D side, right side in FIG. 13) is defined as the third end 326B4. The third end 326B4 is disposed between the third drain electrode 324Cγ and the fourth source wiring 327δ in the X-axis direction. Specifically, the third end 326B4 is disposed closer to the third drain electrode 324Cγ in the X-axis direction than the fourth source wiring 327δ. Of the two ends of the third wiring configuration portion 326D in the X-axis direction, the end located on the second wiring configuration portion 326B side (the left side in FIG. 13) is defined as the fourth end 326D1. The fourth end 326D1 is disposed between the third drain electrode 324Cγ and the fourth source wiring 327δ in the X-axis direction. Specifically, the fourth end 326D1 is disposed closer to the fourth source wiring 327δ in the X-axis direction than the third drain electrode 324Cγ. The fourth end 326D1 is disposed with a gap between it and the third end 326B4 on the same side (upper side in FIG. 13) as the third drain electrode 324Cγ in the Y-axis direction. In detail, the fourth end 326D1 is sandwiched between the third end 326B4 and the third pixel electrode body 325Aγ of the third pixel electrode 325γ in the Y-axis direction, and is positioned closer to the third pixel electrode body 325Aγ than the third end 326B4.

[0078] 13, one end of the second connection electrode 326E overlaps the third end 326B4 of the second wiring portion 326B, and the other end overlaps the fourth end 326D1 of the third wiring portion 326D. The second connection electrode 326E extends generally along the Y-axis direction to straddle the third end 326B4 of the second wiring portion 326B and the fourth end 326D1 of the third wiring portion 326D. More specifically, the second connection electrode 326E protrudes from the third end 326B4 along the X-axis direction toward the fourth source wiring 327δ, is bent, and then extends along the Y-axis direction toward the fourth end 326D1 and reaches the fourth end 326D1. The first interlayer insulating film 33 is provided with a third contact hole CH3 that overlaps both the third end 326B4 of the second wiring component 326B and one end of the second connection electrode 326E, and a fourth contact hole CH4 that overlaps both the fourth end 326D1 of the third wiring component 326D and the other end of the second connection electrode 326E.

[0079] The gate wiring 326 having the above-described configuration can provide the following actions and effects. That is, in manufacturing the array substrate 321, at the stage where the second metal film is deposited and patterned, a first wiring configuration portion 326A, a second wiring configuration portion 326B, and a third wiring configuration portion 326D that constitute the gate wiring 326 are provided. At this time, the first wiring configuration portion 326A, the second wiring configuration portion 326B, and the third wiring configuration portion 326D are not connected to one another. Therefore, compared to a case where the gate wiring is made only of the second metal film and the first wiring configuration portion, the second wiring configuration portion, and the third wiring configuration portion are connected, electrostatic discharge due to peeling electrification is less likely to occur in the first wiring configuration portion 326A, the second wiring configuration portion 326B, and the third wiring configuration portion 326D. After the second metal film is patterned, the first interlayer insulating film 33 is deposited and patterned. In addition to the first contact hole CH1 and the second contact hole CH2, the first interlayer insulating film 33 is provided with a third contact hole CH3 at a position overlapping the third end 326B4 of the second wiring portion 326B and a fourth contact hole CH4 at a position overlapping the fourth end 326D1 of the third wiring portion 326D. Then, the third metal film is deposited and patterned, providing the source wirings 327α-327ε, the drain electrodes 324Cα-324Cγ, and the connection electrodes 326C, 326E. The second connection electrode 326E is connected to the third end 326B4 of the second wiring portion 326B through the third contact hole CH3 and to the fourth end 326D1 of the third wiring portion 326D through the fourth contact hole CH4. The first wiring component 326A, the second wiring component 326B, the third wiring component 326D, the first connection electrode 326C, and the second connection electrode 326E are connected to one another and form the gate wiring 326.

[0080] 13, the second connection electrode 326E extends across the third end 326B4 and the fourth end 326D1, which is spaced apart from the third end 326B4 on the same side as the third drain electrode 324Cγ in the Y-axis direction and is sandwiched between the fourth source wiring 327δ and the third drain electrode 324Cγ in the X-axis direction, so that the distance between the third drain electrode 324Cγ and the fourth source wiring 327δ in the X-axis direction can be reduced while the distance between the second connection electrode 326E and the third drain electrode 324Cγ in the X-axis direction and the distance between the second connection electrode 326E and the fourth source wiring 327δ in the X-axis direction are sufficiently secured. This is advantageous for achieving higher definition. Like the second wiring component 326B, the third wiring component 326D has a main body 326D2 that is collinear with the second wiring component 326B and a bent portion 326D3 that is bent from the main body 326D2 and extends to the fourth end 326D1. The main body 326D2 and bent portion 326D3 of the third wiring component 326D have the same configuration as the main body 326B2 and bent portion 326B3 of the second wiring component 326B, and detailed description thereof will be omitted. Similarly to the first connection electrode 326C, the second connection electrode 326E is disposed between the second wiring component 326B and the third pixel electrode main body 325Aγ in the Y-axis direction. Similarly to the first end 326A1 and the second end 326B1, the third end 326B4 and the fourth end 326D1 are arranged to partially overlap with each other in the X-axis direction.

[0081] As shown in FIG. 13 , the second wiring configuration portion 326B has an undivided structure between the first source wiring 327α and the fifth source wiring 327ε in the X-axis direction. That is, the second wiring configuration portion 326B intersects with the first source wiring 327α, the second source wiring 327β, and the fifth source wiring 327ε. Therefore, neither the first connection electrode 326C nor the second connection electrode 326E is provided in a pixel PX including a second pixel electrode 325β sandwiched between the first source wiring 327α and the second source wiring 327β, all of which intersect with the second wiring configuration portion 326B. Similarly, neither the first connection electrode 326C nor the second connection electrode 326E is provided in a pixel PX including a fourth pixel electrode 325δ sandwiched between the second source wiring 327β and the fifth source wiring 327ε, all of which intersect with the second wiring configuration portion 326B. In contrast, a first connection electrode 326C is arranged in a pixel PX including a first pixel electrode 325α sandwiched between a third source wiring 327γ that intersects with the first wiring configuration portion 326A and a second source wiring 327β that intersects with the second wiring configuration portion 326B. Similarly, a second connection electrode 326E is arranged in a pixel PX including a third pixel electrode 325γ that is sandwiched between a fifth source wiring 327ε that intersects with the second wiring configuration portion 326B and a fourth source wiring 327δ that intersects with the third wiring configuration portion 326D. In other words, if the pixel PX in which the first connection electrode 326C is arranged is located at the "nth position (n: an integer equal to or greater than 1)" in the display area AA, counting from the left end of FIG. 13, the pixel PX in which the second connection electrode 326E is arranged can be said to be located at the "(n+2)th position" in the display area AA, counting from the left end of FIG. 13. Therefore, the color filters 28 facing the first pixel electrode 325α and the third pixel electrode 325γ have the same color. For example, if the first pixel electrode 325α faces a red color filter 28 and forms a red pixel RPX, the third pixel electrode 325γ also faces a red color filter 28 and forms a red pixel RPX. Note that when the first pixel electrode 325α and the third pixel electrode 325γ each form a red pixel RPX, the second pixel electrode 325β forms a green pixel GPX, and the fourth pixel electrode 325δ forms a blue pixel BPX.

[0082] The polarity of each pixel electrode 325 will be described with reference to FIG. 14. In FIG. 14, the pixel electrodes 325 and gate lines 326 are both illustrated schematically, and the positive and negative polarities of each pixel electrode 325 are indicated by the symbols "+" and "-." Although the source lines 327 are not illustrated in FIG. 14, they are present between two pixel electrodes 325 adjacent to each other in the X-axis direction. Also, in FIG. 14, the pixel electrodes 325 constituting the red pixel RPX, the pixel electrodes 325 constituting the green pixel GPX, and the pixel electrodes 325 constituting the blue pixel BPX are illustrated with different hatching. As shown in FIG. 14, the pixel electrodes 325 are charged to a potential whose polarity is based on the image signal supplied from the driver 12 (see FIG. 1) to the source lines 327. The driver 12 supplies image signals of alternately opposite polarities to the multiple source lines 327 arranged along the X-axis direction. Specifically, when the polarity of the image signal supplied to the odd-numbered source wirings 327 counting from one end position in the X-axis direction in the display area AA is "+", the polarity of the image signal supplied to the even-numbered source wirings 327 counting from one end position in the X-axis direction in the display area AA is "-". Conversely, when the polarity of the image signal supplied to the odd-numbered source wirings 327 counting from one end position in the X-axis direction in the display area AA is "-", the polarity of the image signal supplied to the even-numbered source wirings 327 counting from one end position in the X-axis direction in the display area AA is "+". In this way, the driver 12 performs inversion driving (line inversion driving) that periodically inverts the polarities of the image signals supplied to the odd-numbered source wirings 327 and the even-numbered source wirings 327 among the multiple source wirings 327 aligned along the X-axis direction.

[0083] 14 illustrates an example in which the first pixel electrode 325α and the third pixel electrode 325γ each constitute a red pixel RPX, the second pixel electrode 325β constitutes a green pixel GPX, and the fourth pixel electrode 325δ constitutes a blue pixel BPX. The first pixel electrode 325α, which constitutes the red pixel RPX and is provided with the first connection electrode 326C, is charged to a potential with a polarity based on the image signal supplied to the third source line 327γ. The third pixel electrode 325γ, which constitutes the red pixel RPX and is provided with the second connection electrode 326E, is charged to a potential with a polarity based on the image signal supplied to the fifth source line 327ε. When the third source line 327γ is located at an odd position counting from one end position in the X-axis direction in the display area AA, the fifth source line 327ε is located at an even position counting from one end position in the X-axis direction in the display area AA. Therefore, the polarities of the image signals supplied from the driver 12 to the third source line 327γ and the fifth source line 327ε are opposite to each other, and the polarities of the first pixel electrode 325α and the third pixel electrode 325γ are also opposite to each other.

[0084] Here, potential fluctuations occur in the gate wiring 326 due to the input of signals for driving each TFT 324. These potential fluctuations in the gate wiring 326 can affect the potential of each pixel electrode 325 due to parasitic capacitance occurring between the gate wiring 326 and each pixel electrode 325. Specifically, when the potential of the gate wiring 326 falls from high to low, the parasitic capacitance occurring between the gate wiring 326 and each pixel electrode 325 causes a negative level shift in the potential (Vd) of the pixel electrode 325. This level shift is called a pull-in voltage (ΔVd). At this time, the pixel electrode 325, which is set to a potential (positive potential) associated with a positive image signal, has a small potential difference from the high potential of the gate wiring 326, so the TFT 324 turns off shortly after the above-mentioned level shift occurs. On the other hand, the pixel electrode 325, which is set to a potential corresponding to a negative image signal (negative potential), has a large potential difference with the high potential of the gate line 326, so it takes a certain amount of time for the TFT 324 to turn off after the level shift occurs. Therefore, during the time until the TFT 324 turns off, the pixel electrode 325 is recharged, shifting its potential to the positive side, resulting in a decrease in the pull-in voltage. Thus, a difference in pull-in voltage occurs between the pixel electrode 325 set to a positive potential and the pixel electrode 325 set to a negative potential. In addition, the first pixel electrode 325α and the third pixel electrode 325γ are located closer to the first connection electrode 326C and the second connection electrode 326E than the second pixel electrode 325β and the fourth pixel electrode 325δ, so the potential level shift due to the parasitic capacitance between the gate line 326 and each pixel electrode 325 is larger. For this reason, if the potentials of the first pixel electrode 325α and the third pixel electrode 325γ were of the same polarity, streaky display irregularities might be easily visible. In contrast, the driver 12 supplies image signals of opposite polarities to at least the third source line 327γ and the fifth source line 327ε, so that the first pixel electrode 325α and the third pixel electrode 325γ have opposite polarities to each other in a charged state.Therefore, even if the potential level shift caused by the parasitic capacitance between the gate line 326 and each pixel electrode 325 is larger in the first pixel electrode 325α and the third pixel electrode 325γ than in the second pixel electrode 325β and the fourth pixel electrode 325δ, streaky display unevenness is less likely to be visible.

[0085] 14, the gate wiring 326 according to this embodiment is configured so that all of the wiring components 326A, 326B, and 326D intersect with every three source wirings 327. Therefore, the number of wiring components 326A, 326B, and 326D that make up the gate wiring 326 is set to about 1 / 3 of the number of pixels PX that are aligned along the X-axis direction, and the number of connection electrodes 326C and 326E that make up the gate wiring 326 is also set to about 1 / 3 of the number of pixels PX that are aligned along the X-axis direction.

[0086] As described above, according to this embodiment, there are provided a third source wiring (fourth wiring) 327γ extending along the second direction and arranged with the first pixel electrode 325α sandwiched between it and the first source wiring 327α in the first direction, a fourth source wiring (fifth wiring) 327δ extending along the second direction and arranged at an interval on the opposite side of the first source wiring 327α from the second source wiring 327β in the first direction, a fifth source wiring (sixth wiring) 327ε extending along the second direction and arranged at an interval on the second source wiring 327β side in the first direction from the fourth source wiring 327δ, a third drain electrode (fifth electrode) 324Cγ that is spaced apart from the gate wiring 326 in the second direction on the same side as the first drain electrode 324Cα and that is sandwiched between the fourth source wiring 327δ and the fifth source wiring 327ε in the first direction; a third TFT (third switching element) 324γ that has the third drain electrode 324Cγ; a third pixel electrode 325γ that is sandwiched between the fourth source wiring 327δ and the fifth source wiring 327ε in the first direction and is connected to the third drain electrode 324Cγ; and a driver (signal supply unit) 12 that supplies an image signal to each of the line 327γ, the fourth source line 327δ, and the fifth source line 327ε. The gate line 326 has a third wiring configuration portion 326D that is made up of a portion of the second metal film that is different from the first wiring configuration portion 326A and the second wiring configuration portion 326B, and a second connection electrode 326E that is made up of a portion of the third metal film that is different from the first connection electrode 326C, the first source line 327α, the first drain electrode 324Cα, and the second source line 327β. The third source line 327γ is made up of a portion of the third metal film that is different from the first connection electrode 326C. , the first source wiring 327α, the first drain electrode 324Cα, the second source wiring 327β, and the second connection electrode 326E, the fourth source wiring 327δ is made up of a portion of the third metal film different from the first connection electrode 326C, the first source wiring 327α, the first drain electrode 324Cα, the second source wiring 327β, the second connection electrode 326E, and the third source wiring 327γ, the fifth source wiring 327ε is made up of a portion of the third metal film different from the first connection electrode 326C, the first source wiring 327α, the first drain electrode 324Cα, the second source wiring 327β, the second connection electrode 326E,The third wiring configuration portion 326B is made of a portion different from the third source wiring 327γ and the fourth source wiring 327δ, the third drain electrode 324Cγ is made of a portion different from the first connection electrode 326C, the first source wiring 327α, the first drain electrode 324Cα, the second source wiring 327β, the second connection electrode 326E, the third source wiring 327γ, the fourth source wiring 327δ, and the fifth source wiring 327ε, and the second wiring configuration portion 326B is made of a portion different from the third connection electrode 326C, the first source wiring 327α, the first drain electrode 324Cα, the second source wiring 327β, the second connection electrode 326E, the third source wiring 327γ, the fourth source wiring 327δ, and the fifth source wiring 327ε located on the opposite side to the second end 326B1. The third wiring configuration portion 326D has a fourth end 326D1 that is spaced apart from the third end 326B4 on the same side as the third drain electrode 324Cγ in the second direction and is sandwiched between the fourth source wiring 327δ and the third drain electrode 324Cγ in the first direction, the second connection electrode 326E extending to straddle the third end 326B4 and the fourth end 326D1, and the first interlayer insulating film 33 has a first end 326B4 and a second connection electrode 326D1. The third TFT 324α has a first source electrode (sixth electrode) 324Bα formed of a part of the third source wiring 327γ, and a first semiconductor portion 324Dα made of a semiconductor material and connected to the first drain electrode 324Cα and the first source electrode 324Bα. γ has a third gate electrode (seventh electrode) 324Aγ consisting of a part of the second wiring component 326B, a third source electrode (eighth electrode) 324Bγ consisting of a part of the fifth source wiring 327ε, and a third semiconductor portion 324Dγ made of a semiconductor material and connected to the third drain electrode 324Cγ and the third source electrode 324Bγ, and the driver 12 supplies at least the image signal supplied to the third source wiring 327γ and the image signal supplied to the fifth source wiring 327ε with opposite polarities.

[0087] The second connection electrode 326E is connected to the third end 326B4 of the second wiring portion 326B through the third contact hole CH3 and to the fourth end 326D1 of the third wiring portion 326D through the fourth contact hole CH4. The second connection electrode 326E extends across the third end 326B4 and the fourth end 326D1, which is spaced apart from the third end 326B4 on the same side as the third drain electrode 324Cγ in the second direction and is sandwiched between the fourth source wiring 327δ and the third drain electrode 324Cγ in the first direction. This allows the distance between the third drain electrode 324Cγ and the fourth source wiring 327δ to be reduced while ensuring sufficient distance between the second connection electrode 326E and the third drain electrode 324Cγ and the distance between the second connection electrode 326E and the fourth source wiring 327δ. This is advantageous for achieving high definition.

[0088] When the first TFT 324α is driven based on a signal supplied to the first gate electrode 324Aα by the gate wiring 326, an image signal supplied to the first source electrode 324Bα by the third source wiring 327γ is supplied to the first drain electrode 324Cα via the first semiconductor portion 324Dα. The first pixel electrode 325α connected to the first drain electrode 324Cα is charged to a potential with a polarity based on the image signal supplied to the third source wiring 327γ. When the third TFT 324γ is driven based on a signal supplied to the third gate electrode 324Aγ by the gate wiring 326, an image signal supplied to the third source electrode 324Bγ by the fifth source wiring 327ε is supplied to the third drain electrode 324Cγ via the third semiconductor portion 324Dγ. The third pixel electrode 325γ connected to the third drain electrode 324Cγ is charged to a potential with a polarity based on the image signal supplied to the fifth source wiring 327ε.

[0089] Here, potential fluctuations occur in the gate wiring 326 due to input of signals for driving each TFT 324. These potential fluctuations in the gate wiring 326 affect the potential of each pixel electrode 325 due to parasitic capacitance generated between the gate wiring 326 and each pixel electrode 325, resulting in a negative level-shifted pull-in voltage. This pull-in voltage tends to decrease in pixel electrodes 325 with negative potentials compared to pixel electrodes 325 with positive potentials. In particular, the first pixel electrode 325α and the third pixel electrode 325γ are closer to the first connection electrode 326C and the second connection electrode 326E than the second pixel electrode 325β, so the potential level shift caused by the parasitic capacitance generated between the gate wiring 326 and each pixel electrode 325 is greater. Therefore, if the potentials of the first pixel electrode 325α and the third pixel electrode 325γ were the same polarity, streaky display irregularities might be more visible. In contrast, the driver 12 supplies at least the image signal to the third source line 327γ and the image signal to the fifth source line 327ε with opposite polarities, so that the first pixel electrode 325α and the third pixel electrode 325γ have opposite polarities when charged. Therefore, even if the potential level shift caused by the parasitic capacitance between the gate line 326 and each pixel electrode 325 is larger in the first pixel electrode 325α and the third pixel electrode 325γ than in the second pixel electrode 325β and the fourth pixel electrode 325δ, streaky display unevenness is less likely to be visible.

[0090] <Embodiment 5> Embodiment 5 will be described with reference to Fig. 15. In this embodiment 5, the arrangement of the third pixel electrode 425γ is changed from that of the above-described embodiment 4, and the configuration of the gate line 426 is also changed. Note that redundant explanations of the structure, actions, and effects similar to those of the above-described embodiment 4 will be omitted.

[0091] 15, similar to FIG. 14, the pixel electrodes 425 and the gate lines 426 are each illustrated schematically, and the positive and negative polarities of each pixel electrode 425 are indicated by the symbols "+" and "-." Note that, similar to FIG. 14, the source lines 27 are not illustrated in FIG. 15, but are present between two pixel electrodes 425 adjacent to each other in the X-axis direction. Also, in FIG. 15, the pixel electrodes 425 constituting the red pixel RPX, the pixel electrodes 425 constituting the green pixel GPX, and the pixel electrodes 425 constituting the blue pixel BPX are illustrated with different hatching. Note that FIG. 15 illustrates a case in which the first pixel electrode 425α and the third pixel electrode 425γ each constitute the red pixel RPX, the second pixel electrode 425β constitutes the green pixel GPX, and the fourth pixel electrode 425δ constitutes the blue pixel BPX.

[0092] As shown in FIG. 15, the third pixel electrode 425γ according to this embodiment is disposed at a position spaced apart from the first pixel electrode 425α by a distance equivalent to eight pixel electrodes 425 (including the second pixel electrode 425β and the fourth pixel electrode 425δ) in the X-axis direction. Accordingly, the second wiring configuration portion 426B is configured to intersect with nine source wirings 27 (including the first source wiring 27α, the second source wiring 27β, the third source wiring 27γ, and the fourth source wiring 27δ (see FIG. 13)). Generally, the number of source wirings 27 intersected by the second wiring configuration portion 426B is defined as "3m (m: odd number)," and in this embodiment, "m" is "3." Note that in the fourth embodiment, the number of source wirings 27 intersected by the second wiring configuration portion 426B is the case where "m" of the above-mentioned "3m" is "1." Therefore, in this embodiment, if the third source wiring 27γ that supplies an image signal to the first pixel electrode 425α is located at an odd position counting from one end position in the X-axis direction in the display area AA, the fifth source wiring 27ε that supplies an image signal to the third pixel electrode 425γ will be located at an even position counting from one end position in the X-axis direction in the display area AA.

[0093] The driver 12 performs line inversion driving, as in the above-described embodiment 4. Therefore, the polarities of the image signals supplied from the driver 12 to the third source line 27γ and the fifth source line 27ε are reversed, and the polarities of the first pixel electrode 425α and the third pixel electrode 425γ are also reversed. As a result, in this embodiment as well, as in the above-described embodiment 4, it is possible to obtain the effect of making it difficult to visually recognize display unevenness caused by potential fluctuations in the gate line 426.

[0094] As shown in FIG. 15 , the gate wiring 426 according to this embodiment is configured such that all wiring components 426A, 426B, and 426D intersect with nine source wirings 27. Therefore, the number of wiring components 426A, 426B, and 426D constituting the gate wiring 426 is approximately 1 / 9 of the number of pixels PX aligned along the X-axis direction, and the number of connection electrodes 426C and 426E constituting the gate wiring 426 is also approximately 1 / 9 of the number of pixels PX aligned along the X-axis direction. Since the number of connection electrodes 426C and 426E is thus reduced compared to the fourth embodiment, the number of connection points between the wiring components 426A, 426B, and 426D and the connection electrodes 426C and 426E is also reduced, thereby suppressing a decrease in yield due to connection defects at the connection points. Furthermore, the first pixel electrodes 425α and the third pixel electrodes 425γ are arranged such that their positions in the X-axis direction are shifted for each adjacent pixel row.

[0095] <Embodiment 6> A sixth embodiment will be described with reference to Figures 16 to 18. In this sixth embodiment, the pixel arrangement and the like are changed from those of the fifth embodiment. Note that redundant explanations of the structure, actions, and effects similar to those of the fifth embodiment will be omitted.

[0096] As shown in FIGS. 16 and 17 , the array substrate 521 according to this embodiment has a configuration in which the pixel arrangement is horizontally reversed for adjacent pixel rows. The pixel arrangement shown in FIG. 16 is the same as the pixel arrangement shown in FIG. 4 and is a pixel arrangement for pixel rows located at even-numbered (odd-numbered) positions from one end position in the Y-axis direction in the display area AA. In FIG. 16 , the TFTs 524 are configured so that image signals are supplied to pixel electrodes 525 adjacent to the right side of the source wiring 527 from one end position in the Y-axis direction in the display area AA. In contrast, the pixel arrangement shown in FIG. 17 is a pixel arrangement for pixel rows located at odd-numbered (even-numbered) positions from one end position in the Y-axis direction in the display area AA. In FIG. 17 , the TFTs 524 are configured so that image signals are supplied to pixel electrodes 525 adjacent to the left side of the source wiring 527. Therefore, the image signal supplied to the source wiring 527 is supplied to pixel electrodes 525 that form different pixel columns on the left and right in pixel rows adjacent to each other in the Y-axis direction. In this embodiment, the source wiring 527 is configured to be repeatedly bent in a zigzag pattern. In addition, in Fig. 17, the second wiring component 526B is located on the left side of the first wiring component 526A.

[0097] 18, similarly to FIG. 14, the pixel electrodes 525 and the gate wiring 526 are all illustrated schematically, and the positive and negative polarities of each pixel electrode 525 are indicated by the symbols "+" and "-". Note that, similarly to FIG. 14, the source wiring 527 is not illustrated in FIG. 18, but is present between two pixel electrodes 525 adjacent to each other in the X-axis direction. Also, in FIG. 18, the pixel electrode 525 constituting the red pixel RPX, the pixel electrode 525 constituting the green pixel GPX, and the pixel electrode 525 constituting the blue pixel BPX are illustrated with different hatching.

[0098] 18, the third pixel electrode 525γ according to this embodiment is disposed at a position spaced apart from the first pixel electrode 525α by a distance equivalent to eight pixel electrodes 525 (including the second pixel electrode 525β and the fourth pixel electrode 525δ) in the X-axis direction. Accordingly, the second wiring configuration portion 526B is configured to intersect with nine source wirings 527 (including the first source wiring 527α, the second source wiring 527β, the third source wiring 527γ, and the fourth source wiring 527δ (see FIG. 13)).

[0099] As in the fourth and fifth embodiments, the driver 12 periodically inverts the polarity of the image signals supplied to the odd-numbered source wirings 527 and the even-numbered source wirings 527 among the multiple source wirings 527 arranged along the X-axis direction. Therefore, as shown in FIG. 18 , the pixel electrodes 525 adjacent to each other in the X-axis direction and the pixel electrodes 525 adjacent to each other in the Y-axis direction have opposite polarities. That is, in this embodiment, the driver 12 performs Z-inversion driving. As in the fourth and fifth embodiments, the polarities of the image signals supplied from the driver 12 to the third source wiring 527γ and the fifth source wiring 527ε are opposite, and the polarities of the first pixel electrode 525α and the third pixel electrode 525γ are also opposite. As a result, as in the fourth and fifth embodiments, this embodiment also achieves the effect of making display unevenness caused by potential fluctuations in the gate wiring 526 less visible.

[0100] In this embodiment, the colors of the pixels PX constituted by the first pixel electrodes 525α and the third pixel electrodes 525γ differ depending on the pixel row. Fig. 18 illustrates a case where, in the pixel rows located odd-numbered (even-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrodes 525α and the third pixel electrodes 525γ each constitute blue pixels BPX, and in the pixel rows located even-numbered (odd-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrodes 525α and the third pixel electrodes 525γ each constitute red pixels RPX.

[0101] 18, the gate wiring 526 according to this embodiment is configured so that all wiring components 526A, 526B, and 526D intersect with every nine source wirings 527. Therefore, the number of wiring components 526A, 526B, and 526D constituting the gate wiring 526 is approximately 1 / 9 of the number of pixels PX aligned along the X-axis direction, and the number of connection electrodes 526C and 526E constituting the gate wiring 526 is also approximately 1 / 9 of the number of pixels PX aligned along the X-axis direction. Furthermore, the first pixel electrodes 525α and the third pixel electrodes 525γ are arranged such that their arrangements in the X-axis direction are shifted for each adjacent pixel row.

[0102] <Embodiment 7> Embodiment 7 will be described with reference to Fig. 19. In this embodiment 7, the color of the pixel PX configured by the first pixel electrode 625α and the third pixel electrode 625γ is changed from that of embodiment 6. Note that redundant explanations of the structure, operation, and effects similar to those of embodiment 6 will be omitted.

[0103] 19, similar to FIG. 14, the pixel electrodes 625 and the gate lines 626 are all illustrated schematically, and the positive and negative polarities of each pixel electrode 625 are indicated by the symbols "+" and "-". Note that, similar to FIG. 14, the source lines 27 are not illustrated in FIG. 19, but are present between two pixel electrodes 625 adjacent to each other in the X-axis direction. Also, in FIG. 19, the pixel electrodes 625 constituting the red pixel RPX, the pixel electrodes 625 constituting the green pixel GPX, and the pixel electrodes 625 constituting the blue pixel BPX are illustrated with different hatching.

[0104] 19, in the present embodiment, in the pixel row located odd-numbered (even-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrode 625α and the third pixel electrode 625γ each constitute a green pixel GPX, and in the pixel row located even-numbered (odd-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrode 625α and the third pixel electrode 625γ each constitute a red pixel RPX. In the present embodiment, as in the above-described embodiments 4 to 6, it is possible to obtain the effect that display unevenness caused by potential fluctuations in the gate wiring 626 is less visible.

[0105] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0106] (1) The first wiring components 26A, 126A, 326A, 426A, and 526A may have a main body and a bent portion, similar to the second wiring components 26B, 326B, 426B, and 526B. That is, the first wiring components 26A, 126A, 326A, 426A, and 526A may have a bent portion bent from the main body and connected to the first end 26A1, 326A1.

[0107] (2) The second wiring component 26B, 326B, 426B, 526B may not have the bent portion 26B3, 326B3. In this case, the first wiring component 26A, 126A, 326A, 426A, 526A and the second wiring component 26B, 326B, 426B, 526B may be arranged offset in the Y-axis direction, and the first connection electrode 26C, 126C, 326C, 426C may be provided so as to straddle the first end 26A1, 326A1 and the second end 26B1, 126B1, 326B1, which are spaced apart in the Y-axis direction. In this case, the TFTs and pixel electrodes adjacent to the first wiring configurations 26A, 126A, 326A, 426A, 526A in the Y-axis direction and the TFTs 24, 224, 324, 524 and pixel electrodes 25, 225, 325, 425, 525, 625 adjacent to the second wiring configurations 26B, 326B, 426B, 526B in the Y-axis direction are arranged offset in the Y-axis direction.

[0108] (3) In addition to the above (1) and (2), the specific planar shapes and arrangements of each wiring component 26A, 126A, 326A, 426A, 526A, 26B, 326B, 426B, 526B, 326D, 426D, 526D and each connection electrode 26C, 126C, 326C, 426C, 326E, 426E constituting the gate wiring 26, 126, 226, 326, 426, 526, 626 may be changed as appropriate to those shown in the drawings.

[0109] (4) In addition to the configurations described in embodiments 4 to 7, the specific number of source wirings 327, 527 that intersect with the second wiring components 326B, 426B, 526B can be changed as appropriate. That is, the number of source wirings 327, 527 that intersect with the second wiring components 326B, 426B, 526B may be "3m (m: an odd number of 5 or more)."

[0110] (5) In the configurations described in embodiments 6 and 7, in pixel rows located odd-numbered (even-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrodes 525α, 625α and the third pixel electrodes 525γ, 625γ may each constitute a blue pixel BPX, and in pixel rows located even-numbered (odd-numbered) from one end position in the Y-axis direction in the display area AA, the first pixel electrodes 525α, 625α and the third pixel electrodes 525γ, 625γ may each constitute a green pixel GPX.

[0111] (6) In the configurations described in the sixth and seventh embodiments, all of the first pixel electrodes 525α, 625α and third pixel electrodes 525γ, 625γ may form a pixel PX that exhibits a single color (red, green, or blue).

[0112] (7) The intermediate electrode 38 may be omitted. In this case, the connection portions 25B and 325B of the pixel electrodes 25, 225, 325, 425, 525, and 625 are directly connected to the drain electrodes 24C, 124C, 224C, and 324C. The openings 36A and 136A of the common electrodes 36 and 136 include portions that overlap with the drain electrodes 24C, 124C, 224C, and 324C.

[0113] (8) The specific planar shapes and arrangements of the openings 36A, 136A provided in the common electrodes 36, 136 can be changed as appropriate to those shown in the drawings.

[0114] (9) The configuration described in the first embodiment can be combined with the configurations described in the fourth to seventh embodiments.

[0115] (10) The configuration described in the second embodiment can be combined with the configurations described in the fourth to seventh embodiments.

[0116] (11) In the configuration described in the second embodiment, the touch panel pattern may be a mutual capacitance type other than a self-capacitance type.

[0117] (12) The drivers 12 and 112 may be mounted on the flexible substrate 13 by COF (Chip On Film) mounting.

[0118] (13) The material of the semiconductor film that constitutes the semiconductor portions 24D, 224D, and 324D may be an amorphous silicon material, an oxide semiconductor material, or the like.

[0119] (14) The configuration of the TFTs 24, 224, 324, and 524 may be a bottom gate type, a double gate type, or the like, other than the top gate type shown in the drawings.

[0120] (15) The pixel electrodes 25, 225, 325, 425, 525, and 625 may be made of a first transparent electrode film, and the common electrodes 36 and 136 may be made of a second transparent electrode film. In this case, it is preferable to form slits in the common electrodes 36 and 136 for alignment control.

[0121] (16) The planar shape of the liquid crystal panels 11, 111 may be a vertically long rectangle, a square, a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like.

[0122] (17) The display mode of the liquid crystal panel 11, 111 may be VA mode, IPS mode, or the like in addition to FFS mode.

[0123] (18) The liquid crystal panels 11 and 111 may be of a reflective or semi-transmissive type in addition to a transmissive type. If the liquid crystal panels 11 and 111 are of a reflective type, the backlight device can be omitted.

[0124] (19) Display panels other than the liquid crystal panels 11 and 111 (such as organic EL display panels) may be used. [Explanation of symbols]

[0125] 11,111...liquid crystal panel (display device), 12,112...driver (signal supply unit), 20...opposing substrate, 21,321,521...array substrate, 24α,324α...first TFT (first switching element), 24Aα,124Aα,324Aα...first gate electrode (second electrode), 24Bα,324Bα...first source electrode (sixth electrode), 24Cα,124Cα,324Cα...first drain electrode (first electrode), 24Dα,324Dα...first semiconductor portion, 24β,324β...second TFT (second switching element), 24Aβ...second gate gate electrode (fourth electrode), 24Cβ...second drain electrode (third electrode), 25α, 125α, 325α, 425α, 525α, 625α...first pixel electrode, 25Aα...first pixel electrode body, 25Bα...first connection portion, 25β, 325β, 425β, 525β, 625β...second pixel electrode, 26, 126, 226, 326, 426, 526, 626...gate wiring (first wiring), 26A, 126A, 326A, 426A, 526A...first wiring configuration portion, 26A1, 326A1...first end portion, 26B, 326B, 426B, 526B...second Wiring configuration portion, 26B1, 126B1, 326B1... second end portion, 26B2, 326B2... main body portion, 26B3, 326B3... bending portion, 26C, 126C, 326C, 426C... first connection electrode, 27α, 227α, 327α, 427α... first source wiring (second wiring), 27β, 327β, 427β... second source wiring (third wiring), 27γ, 227γ, 327γ, 427γ... third source wiring (fourth wiring), 33... first interlayer insulating film (first insulating film), 35, 135... second interlayer insulating film (second insulating film), 36, 136... common electrode, 3 6A, 136A... opening, 36A1, 136A1... first slit, 36A2, 136A2... second slit, 136B... overlapping portion, 324γ... third TFT (third switching element), 324Aγ... third gate electrode (seventh electrode), 324Bγ... third source electrode (eighth electrode), 324Cγ... third drain electrode (fifth electrode), 324Dγ... third semiconductor portion, 325γ, 425γ, 525γ, 625γ... third pixel electrode, 326B4... third end portion, 326D, 426D, 526D... third wiring configuration portion, 326D1... fourth end portion, 326E,426E...second connection electrode, 327δ...fourth source wiring (fifth wiring), 327ε...fifth source wiring (sixth wiring), CH1...first contact hole, CH2...second contact hole, CH3...third contact hole, CH4...fourth contact hole,

Claims

1. a first wiring extending along a first direction; a second wiring extending along a second direction intersecting the first direction; a first electrode arranged at a distance from the first wiring in the second direction and at a distance from the second wiring in the first direction; a first insulating film; the first wiring has a first wiring component made of a first conductive film disposed on a lower layer side of the first insulating film, a second wiring component made of a portion of the first conductive film different from the first wiring component, and a first connection electrode made of a second conductive film disposed on an upper layer side of the first insulating film, the second wiring is made of a portion of the second conductive film that is different from the first connection electrode, the first electrode is made of a portion of the second conductive film that is different from the first connection electrode and the second wiring, the first wiring component has a first end, the second wiring configuration portion has a second end portion that is spaced apart from the first end portion on the same side as the first electrode in the second direction and is sandwiched between the second wiring and the first electrode in the first direction, the first connection electrode extends across the first end and the second end, An array substrate, wherein the first insulating film is provided with a first contact hole that is arranged to overlap the first end and the first connection electrode, and a second contact hole that is arranged to overlap the second end and the first connection electrode.

2. the first wiring component extends along the first direction, 2. The array substrate according to claim 1, wherein the second wiring configuration has a main body portion extending along the first direction and in the same straight line as the first wiring configuration, and a bent portion bent from the main body portion and extending to the second end portion.

3. The array substrate according to claim 2 , wherein the bent portion is disposed between the first connection electrode and the second wiring in the first direction.

4. The array substrate according to claim 1 , wherein the first end and the second end are arranged to overlap each other in the first direction.

5. a first switching element having the first electrode; a first pixel electrode connected to the first electrode; the first switching element has a second electrode formed of a part of the first wiring component, the first pixel electrode has a first connection portion connected to the first electrode, and a first pixel electrode body arranged on an opposite side of the first connection portion to the first wiring in the second direction, 4. The array substrate according to claim 1, wherein the first connection electrode is disposed between the first wiring configuration portion and the first pixel electrode body in the second direction.

6. a first switching element having the first electrode; a first pixel electrode connected to the first electrode; a second insulating film disposed below the first pixel electrode; a common electrode disposed below the second insulating film so as to overlap the first pixel electrode; the first switching element has a second electrode formed of a part of the first wiring component, 4. The array substrate according to claim 1, wherein the common electrode has an opening that surrounds the first electrode and an overlapping portion that overlaps the first connection electrode.

7. 7. The array substrate of claim 6, wherein the common electrode is configured such that the opening has a first slit extending along the first direction toward the first connection electrode, and a second slit extending along the first direction to the opposite side of the first connection electrode and being longer than the first slit.

8. a first switching element having the first electrode; a first pixel electrode connected to the first electrode; a third wiring extending along the second direction and disposed at an interval from the second wiring on an opposite side to the first electrode in the first direction; a third electrode spaced apart from the first wiring on the same side as the first electrode in the second direction and sandwiched between the second wiring and the third wiring in the first direction; a second switching element having the third electrode; a second pixel electrode connected to the third electrode; the first switching element has a second electrode formed of a part of the first wiring component, the second switching element has a fourth electrode formed of a part of the second wiring component, the third wiring is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, and the first electrode, the third electrode is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, and the third wiring, 4. The array substrate according to claim 1, wherein the second wiring configuration portion intersects with the second wiring and the third wiring via the first insulating film.

9. a fourth wiring extending along the second direction and arranged with the first pixel electrode sandwiched between the fourth wiring and the second wiring in the first direction; a fifth wiring extending along the second direction and arranged at an interval with respect to the third wiring on the opposite side of the second wiring in the first direction; a sixth wiring extending along the second direction and arranged at a distance from the fifth wiring on the third wiring side in the first direction; a fifth electrode that is spaced apart from the first wiring on the same side as the first electrode in the second direction and is sandwiched between the fifth wiring and the sixth wiring in the first direction; a third switching element having the fifth electrode; a third pixel electrode sandwiched between the fifth wiring and the sixth wiring in the first direction and connected to the fifth electrode; a signal supply unit that supplies an image signal to each of the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring, the first wiring has a third wiring component consisting of a portion of the first conductive film that is different from the first wiring component and the second wiring component, and a second connection electrode consisting of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, and the third wiring, the fourth wiring is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, and the second connection electrode, the fifth wiring is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, and the fourth wiring, the sixth wiring is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, the fourth wiring, and the fifth wiring, the fifth electrode is made of a portion of the second conductive film that is different from the first connection electrode, the second wiring, the first electrode, the third wiring, the second connection electrode, the fourth wiring, the fifth wiring, and the sixth wiring, the second wiring component has a third end located on the opposite side to the second end, the third wiring configuration portion has a fourth end portion that is spaced apart from the third end portion on the same side as the fifth electrode in the second direction and is sandwiched between the fifth wiring and the fifth electrode in the first direction, the second connection electrode extends across the third end and the fourth end, the first insulating film is provided with a third contact hole arranged to overlap the third end portion and the second connection electrode, and a fourth contact hole arranged to overlap the fourth end portion and the second connection electrode, the first switching element has a sixth electrode made of a part of the fourth wiring, and a first semiconductor portion made of a semiconductor material and connected to the first electrode and the sixth electrode, the third switching element has a seventh electrode made of a part of the second wiring component, an eighth electrode made of a part of the sixth wiring, and a third semiconductor portion made of a semiconductor material and connected to the fifth electrode and the eighth electrode, 9. The array substrate according to claim 8, wherein the signal supply section supplies the image signal to at least the fourth wiring and the image signal to the sixth wiring with opposite polarities.

10. An array substrate according to any one of claims 1 to 3; a counter substrate disposed opposite to the array substrate with a gap therebetween.

Images