Nitride semiconductor device, semiconductor module and method for manufacturing nitride semiconductor device

Abstract

To reduce the effects of electromagnetic waves in a nitride semiconductor device.SOLUTION: A nitride semiconductor device 10 includes a first sealing resin 60, and GaN chip 20A and GaN chip 20B provided spaced apart from each other in the Y direction in the first sealing resin 60. An electromagnetic wave shield 70 is provided between the GaN chip 20A and the GaN chip 20B in the Y direction within the first sealing resin 60.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device, a semiconductor module, and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] A semiconductor device is known that includes a substrate on which a conductive layer is formed and a plurality of switching elements mounted on the substrate, with the plurality of switching elements electrically connected to the conductive layer by wires (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-182330

[0004] [overview] There is room for improvement in reducing the effects of electromagnetic waves in nitride semiconductor devices.

[0005] A nitride semiconductor device according to one embodiment of the present disclosure includes a first sealing resin, and a first GaN chip and a second GaN chip spaced apart from each other in a first direction perpendicular to a thickness direction of the first sealing resin, and an electromagnetic wave shield is provided in the first sealing resin between the first GaN chip and the second GaN chip in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating an exemplary internal structure of the nitride semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic plan view of one GaN chip in the nitride semiconductor device of FIG. [Figure 4]FIG. 4 is a back view of the nitride semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic plan view of the GaN transistor of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the GaN transistor taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the nitride semiconductor device taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the nitride semiconductor device taken along line F8-F8 in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 10] FIG. 10 is a circuit diagram of the nitride semiconductor device of FIG. [Figure 11] FIG. 11 is a schematic plan view showing the internal structure of an exemplary semiconductor module according to the first embodiment. [Figure 12] FIG. 12 is an enlarged view of the nitride semiconductor device and its periphery in the semiconductor module of FIG. [Figure 13] FIG. 13 is a rear view of the semiconductor module of FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the semiconductor module taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a circuit diagram showing a part of the circuit configuration of the semiconductor module of FIG. [Figure 16] 16A to 16C are schematic cross-sectional views illustrating exemplary manufacturing steps for the nitride semiconductor device of FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 21]FIG. 21 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 28] FIG. 28 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 31] FIG. 31 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 32] FIG. 32 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 33] FIG. 33 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 34] FIG. 34 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 35] FIG. 35 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 36] FIG. 36 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 37] FIG. 37 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 38] FIG. 38 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 39] FIG. 39 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 40] FIG. 40 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 41] FIG. 41 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 42] FIG. 42 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 43] FIG. 43 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 44] FIG. 44 is a schematic cross-sectional view showing an exemplary manufacturing step subsequent to FIG. [Figure 45] FIG. 45 is a schematic plan view showing an exemplary manufacturing step subsequent to FIG. [Figure 46] FIG. 46 is a schematic plan view of an illustrative nitride semiconductor device according to the second embodiment. [Figure 47] FIG. 47 is a schematic cross-sectional view of the nitride semiconductor device taken along line F47-F47 in FIG. [Figure 48] FIG. 48 is a schematic cross-sectional view showing an enlargement of the driver chip and its periphery in FIG. [Figure 49] FIG. 49 is a back view of the nitride semiconductor device of FIG. [Figure 50] FIG. 50 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. [Figure 51] FIG. 51 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. [Figure 52] FIG. 52 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. [Figure 53] FIG. 53 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. [Figure 54] FIG. 54 is a back view of the nitride semiconductor device of the modified example. [Figure 55] FIG. 55 is a back view of the nitride semiconductor device of the modified example. [Figure 56]FIG. 56 is a perspective view of a nitride semiconductor device according to a modified example. [Figure 57] FIG. 57 is an exemplary schematic plan view showing the internal structure of the nitride semiconductor device of FIG. [Figure 58] FIG. 58 is a back view of the nitride semiconductor device of FIG. [Figure 59] FIG. 59 is a plan view of a nitride semiconductor device according to a modified example. [Figure 60] FIG. 60 is a back view of the nitride semiconductor device of FIG. [Figure 61] FIG. 61 is a schematic cross-sectional view of the nitride semiconductor device taken along line F61-F61 in FIG. [Figure 62] FIG. 62 is a schematic cross-sectional view of a GaN transistor in a nitride semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the nitride semiconductor device and semiconductor module of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Overall configuration of nitride semiconductor device] The overall configuration of a nitride semiconductor device 10 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 schematically shows a perspective view of the nitride semiconductor device 10 according to the first embodiment. Figure 2 schematically shows a planar structure of the nitride semiconductor device 10 of Figure 1. Note that in Figure 2, the internal configuration of the nitride semiconductor device 10 is schematically shown by dashed lines. Furthermore, in Figure 2, electromagnetic wave shields 70 (first to sixth electromagnetic wave shields 70A to 70F), which will be described later, are omitted.

[0012] 1, the nitride semiconductor device 10 includes a rectangular, flat-plate-shaped first sealing resin 60 and an external wiring layer 50 exposed from the first sealing resin 60. Here, the thickness direction of the first sealing resin 60 is referred to as the "Z direction." Two directions perpendicular to the Z direction that are perpendicular to each other are referred to as the "X direction" and the "Y direction." In this specification, "plan view" refers to viewing the nitride semiconductor device 10 from the thickness direction (Z direction) of the first sealing resin 60.

[0013] The first sealing resin 60 has a rectangular shape with the X direction as its longitudinal direction and the Y direction as its lateral direction in a plan view. The first sealing resin 60 has a sealing surface 60S and a sealing back surface 60R facing opposite each other in the Z direction, and first to fourth sealing side surfaces 60A to 60D connecting the sealing surface 60S and the sealing back surface 60R. In the example of FIG. 1, both the sealing surface 60S and the sealing back surface 60R are formed as planes perpendicular to the Z direction. In one example, the first to fourth sealing side surfaces 60A to 60D are planes perpendicular to the sealing surface 60S and the sealing back surface 60R. The first sealing side surface 60A and the second sealing side surface 60B constitute both end surfaces of the first sealing resin 60 in the X direction, and the third sealing side surface 60C and the fourth sealing side surface 60D constitute both end surfaces of the first sealing resin 60 in the Y direction.

[0014] The external wiring layer 50 is exposed from the sealing surface 60S. The external wiring layer 50 is provided on the sealing surface 60S. The external wiring layer 50 functions as an external connection terminal that is electrically connected to wiring on a circuit board when the nitride semiconductor device 10 is mounted on, for example, a circuit board.

[0015] The external wiring layer 50 includes a connection wiring layer 51, a source wiring layer 52, a drain wiring layer 53, a first gate wiring layer 54, and a second gate wiring layer 55. A plurality of connection wiring layers 51, a source wiring layer 52, a drain wiring layer 53, a first gate wiring layer 54, and a second gate wiring layer 55 are provided (three in the example of FIG. 1). The connection wiring layer 51, the source wiring layer 52, the drain wiring layer 53, the first gate wiring layer 54, and the second gate wiring layer 55 are provided spaced apart from each other in a direction perpendicular to the thickness direction (Z direction) of the first sealing resin 60. In the example of FIG. 1, three sets of the connection wiring layer 51, the source wiring layer 52, the drain wiring layer 53, the first gate wiring layer 54, and the second gate wiring layer 55, which are arranged spaced apart from each other in the Y direction, are arranged spaced apart from each other in the X direction. In a plan view, the drain wiring layer 53, the first gate wiring layer 54, the connection wiring layer 51, the second gate wiring layer 55, and the source wiring layer 52 are arranged in this order from the fourth sealing side surface 60D toward the third sealing side surface 60C.

[0016] In plan view, the multiple connection wiring layers 51 are disposed at the center in the Y direction of the first sealing resin 60. The multiple connection wiring layers 51 are aligned with each other in the Y direction and spaced apart from each other in the X direction. Each connection wiring layer 51 is formed in a rectangular shape in plan view.

[0017] In a plan view, the multiple source wiring layers 52 are arranged at an end of the first sealing resin 60 closer to the third sealing side surface 60C in the Y direction. The multiple source wiring layers 52 are arranged aligned with each other in the Y direction and spaced apart from each other in the X direction. Each source wiring layer 52 is formed in a strip shape extending in the X direction in a plan view.

[0018] In a plan view, the plurality of drain wiring layers 53 are arranged at an end of the first sealing resin 60 closer to the fourth sealing side surface 60D in the Y direction. The plurality of drain wiring layers 53 are aligned with each other in the Y direction and spaced apart from each other in the X direction. Each drain wiring layer 53 is formed in a strip shape extending in the X direction in a plan view.

[0019] In a plan view, the multiple first gate wiring layers 54 are arranged closer to the third sealing side surface 60C in the Y direction than the multiple drain wiring layers 53. The multiple first gate wiring layers 54 are arranged spaced apart from each other in the X direction while being aligned with each other in the Y direction. Each first gate wiring layer 54 is formed in a substantially U-shape that opens toward the third sealing side surface 60C in a plan view. The multiple first gate wiring layers 54 are arranged closer to the fourth sealing side surface 60D in the Y direction than the multiple connection wiring layers 51. Each connection wiring layer 51 is arranged so that a portion thereof enters a recess of the multiple first gate wiring layers 54 in a plan view.

[0020] As shown in FIG. 2, the nitride semiconductor device 10 includes a plurality of (six in the first embodiment) GaN (gallium nitride) chips 20A-20F. Each of the GaN chips 20A-20F includes a GaN transistor 22 (see FIG. 5). The GaN chips 20A-20F are provided in a first sealing resin 60, spaced apart from one another in a first direction (Y direction) perpendicular to the Z direction. In the example of FIG. 2, three pairs of GaN chips adjacent to one another in the first direction (Y direction) are arranged spaced apart from one another in a second direction (X direction). More specifically, a pair of GaN chips 20A and 20B, a pair of GaN chips 20C and 20D, and a pair of GaN chips 20E and 20F adjacent to one another in the Y direction are arranged spaced apart from one another in the X direction. Here, the "first direction" is the X direction in the first embodiment. The "second direction" is a direction perpendicular to both the thickness direction (Z direction) of the first sealing resin 60 and the first direction (X direction), and is the Y direction in the first embodiment. In addition, in the first embodiment, the GaN chip 20A is an example of a "first GaN chip," and the GaN chip 20B is an example of a "second GaN chip."

[0021] In a plan view, the GaN chips 20A, 20C, and 20E are arranged spaced apart from one another in the X direction while being aligned with one another in the Y direction. In a plan view, the GaN chips 20B, 20D, and 20F are arranged spaced apart from one another in the X direction while being aligned with one another in the Y direction. In a plan view, the GaN chips 20A, 20C, and 20E are arranged closer to the fourth sealing side surface 60D than the GaN chips 20B, 20D, and 20F. In a plan view, the GaN chip 20A is arranged closer to the first sealing side surface 60A than the GaN chips 20C and 20E. The GaN chip 20E is arranged closer to the second sealing side surface 60B than the GaN chips 20A and 20C. The GaN chip 20C is arranged between the GaN chip 20A and the GaN chip 20E in the X direction. In a plan view, the GaN chip 20B is arranged closer to the first sealing side surface 60A than the GaN chips 20D and 20F. The GaN chip 20F is disposed closer to the second sealing side surface 60B than the GaN chips 20B and 20D. The GaN chip 20D is disposed between the GaN chip 20B and the GaN chip 20F in the X direction.

[0022] [GaN chip structure] (Planar structure of GaN chip) The planar structure of the GaN chips 20A to 20F will be described with reference to Figures 2 and 3. Note that the GaN chips 20B to 20F have the same configuration as the GaN chip 20A, and therefore description thereof will be omitted.

[0023] As shown in FIG. 3, the GaN chip 20A includes a chip front surface 20S, a chip back surface 20R (see FIG. 4) opposite the chip front surface 20S, and four chip side surfaces, first to fourth chip side surfaces 20PA to 20PD, connecting the chip front surface 20S and the chip back surface 20R. The first chip side surface 20PA and the second chip side surface 20PB constitute both end surfaces of the GaN chip 20A in the X direction. The first chip side surface 20PA is the chip side surface of the GaN chip 20A closer to the first sealing side surface 60A, and the second chip side surface 20PB is the chip side surface of the GaN chip 20A closer to the second sealing side surface 60B. The third chip side surface 20PC and the fourth chip side surface 20PD constitute both end surfaces of the GaN chip 20A in the Y direction. The third chip side surface 20PC is the chip side surface of the GaN chip 20A closer to the third sealing side surface 60C, and the fourth chip side surface 20PD is the chip side surface of the GaN chip 20A closer to the fourth sealing side surface 60D.

[0024] In one example, second chip side surface 20PB of GaN chip 20A faces first chip side surface 20PA of GaN chip 20C in the X direction. Third chip side surface 20PC of GaN chip 20A faces fourth chip side surface 20PD of GaN chip 20B in the Y direction. Here, third chip side surface 20PC of GaN chip 20A is an example of a "first opposing surface," and fourth chip side surface 20PD of GaN chip 20B is an example of a "second opposing surface."

[0025] The GaN chip 20A includes a substrate 21. The substrate 21 is formed in a rectangular plate shape with the thickness direction in the Z direction. The substrate 21 has a substrate front surface 21S and a substrate back surface 21R (see FIG. 5 for both) facing opposite sides in the Z direction. The substrate back surface 21R forms the chip back surface 20R. In one example, the substrate back surface 21R is flush with the sealing back surface 60R of the first sealing resin 60. Therefore, it can be said that the chip back surface 20R is flush with the sealing back surface 60R. In one example, the substrate back surface 21R and the sealing back surface 60R are both ground, so that the substrate back surface 21R and the sealing back surface 60R become flush with each other. Therefore, the substrate back surface 21R and the sealing back surface 60R have grinding marks.

[0026] The substrate 21 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. The substrate 21 may be a semiconductor substrate. In one example, the substrate 21 may be a Si substrate. The substrate 21 may be a p-type Si substrate having an electrical resistivity of, for example, 0.001 Ωmm to 0.5 Ωmm (or 0.01 Ωmm to 0.1 Ωmm). In other words, a conductive substrate may be used as the substrate 21. The thickness of the substrate 21 may be, for example, 200 μm to 1500 μm. The thickness of the substrate 21 may be defined as the distance in the Z direction between the substrate front surface 21S and the substrate back surface 21R.

[0027] The GaN chip 20A includes a source pad 35, a drain pad 36, and a gate pad 37 provided on a substrate 21. The drain pad 36 is disposed at an end of the GaN chip 20A closer to the fourth sealing side surface 60D of the first sealing resin 60. In plan view, the drain pad 36 is formed in a strip shape extending in the Y direction.

[0028] The source pad 35 is disposed at a distance from the drain pad 36 in the Y direction, closer to the third sealing side surface 60C (see FIG. 2). In other words, the source pad 35 is disposed at the end of the GaN chip 20A closer to the GaN chip 20B (see FIG. 2). In a plan view, the source pad 35 is formed in a strip shape extending in the Y direction.

[0029] A plurality of gate pads 37 (two in this embodiment) are provided. The two gate pads 37 are distributed and disposed on both sides of the source pad 35 in the X direction. Each gate pad 37 is disposed adjacent to the source pad 35 in the X direction. In a plan view, the gate pad 37 is formed in a rectangular shape with the Y direction as the longitudinal direction and the X direction as the lateral direction.

[0030] In plan view, a cell region 38 in which a plurality of GaN transistors 22 (see FIG. 5) are formed is provided between the source pad 35 and the drain pad 36 of the GaN chip 20A in the Y direction. In plan view, the cell region 38 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction.

[0031] (Connection structure between GaN chip and external wiring layer) 2, in a plan view, the source pad 35 of the GaN chip 20A is disposed at a position overlapping the connection wiring layer 51. In the example of FIG. 2, the length of the source pad 35 in the Y direction is longer than the length of the connection wiring layer 51 in the Y direction. The source pad 35 is electrically connected to the connection wiring layer 51.

[0032] In a plan view, the drain pad 36 of the GaN chip 20A is disposed at a position overlapping the drain wiring layer 53. In the example of FIG. 2, the length of the drain pad 36 in the Y direction is longer than the length of the drain wiring layer 53 in the Y direction. The drain pad 36 is electrically connected to the drain wiring layer 53.

[0033] In a plan view, each of the two gate pads 37 is disposed at a position overlapping the first gate wiring layer 54. The gate pads 37 are electrically connected to the first gate wiring layer 54. A portion of the first gate wiring layer 54 is disposed at a position overlapping the cell region 38 (see FIG. 3) in a plan view.

[0034] 2, GaN chips 20B, 20D, and 20F differ from GaN chips 20A, 20C, and 20E in the manner of connection with external wiring layer 50. On the other hand, GaN chips 20B, 20D, and 20F have the same manner of connection with external wiring layer 50. Therefore, only the manner of connection with external wiring layer 50 of GaN chip 20B will be described, and a description of the manner of connection with external wiring layer 50 of GaN chips 20D and 20F will be omitted.

[0035] The drain pad 36 of the GaN chip 20B is disposed at a position overlapping the connection wiring layer 51 in a plan view. The drain pad 36 is electrically connected to the connection wiring layer 51. That is, the drain pad 36 of the GaN chip 20B is electrically connected to the source pad 35 of the GaN chip 20A by the connection wiring layer 51.

[0036] The source pad 35 of the GaN chip 20B is disposed at a position overlapping the source wiring layer 52 in a plan view. The source pad 35 is electrically connected to the source wiring layer 52. In the example of FIG. 2, the length of the source pad 35 in the Y direction is longer than the length of the source wiring layer 52 in the Y direction.

[0037] Each of the multiple (two in this embodiment) gate pads 37 of the GaN chip 20B is disposed at a position overlapping the second gate wiring layer 55 in a plan view. In other words, the two gate pads 37 are disposed on both sides of the connection wiring layer 51 in the X direction in a plan view. The two gate pads 37 are electrically connected to the second gate wiring layer 55.

[0038] (Internal structure of GaN transistor) The configuration of one of the GaN transistors 22 in the cell region 38 of the GaN chip 20A will be described with reference to Figures 5 and 6. Figure 5 schematically shows the planar structure of a portion of the cell region 38. Figure 6 is a cross-sectional view of the GaN chip 20A taken along line F6-F6 in Figure 5, and schematically shows the cross-sectional structure of one GaN transistor 22. To make the drawings easier to understand, hatching has been omitted from some of the components of the GaN transistor 22.

[0039] As shown in Fig. 5, the cell region 38 includes an active region 38A that contributes to the transistor operation of the GaN transistor 22 and an inactive region 38B that does not contribute to the transistor operation. In the example of Fig. 5, the active regions 38A and the inactive regions 38B are arranged alternately. A large number of GaN transistors 22 are provided in each active region 38A. In the example of Fig. 5, four GaN transistors 22 are arranged in each active region 38A.

[0040] The GaN transistor 22 includes a gate electrode 28 , a source electrode 29 , and a drain electrode 30 . The drain electrode 30 is formed in the active region 38A. In one example, in the arrangement direction of the active region 38A and the inactive region 38B, the active region 38A extends over approximately the same range as the drain electrode 30. In the arrangement direction, the inactive region 38B extends over a range where the drain electrode 30 is not present. Therefore, in the arrangement direction, the inactive region 38B is adjacent to the active region 38A.

[0041] In the active region 38A, the source electrode 29, the gate electrode 28, and the drain electrode 30 are arranged adjacent to each other on the electron supply layer 25 in a direction perpendicular to the arrangement direction in a plan view.

[0042] 6, the GaN transistor 22 is provided on the substrate surface 21S side of the substrate 21. A buffer layer 23 is provided on the substrate surface 21S of the substrate 21. The GaN transistor 22 is provided on the buffer layer 23.

[0043] The buffer layer 23 may include one or more nitride semiconductor layers. The buffer layer 23 may be made of any material that can suppress warping of the substrate 21 and cracks in the GaN chip 20A due to, for example, a mismatch in thermal expansion coefficients between the substrate 21 and the electron transit layer 24 (described later). For example, the buffer layer 23 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 23 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0044] In one example, the buffer layer 23 may include a first buffer layer that is an AlN layer formed on the substrate 21, and a second buffer layer that is an AlGaN layer formed on the AlN layer (first buffer layer). The first buffer layer may be an AlN layer having a thickness of, for example, 100 nm or more and 300 nm or less. On the other hand, the second buffer layer may be formed by stacking multiple graded AlGaN layers having a thickness of, for example, 100 nm or more and 300 nm or less. Note that, in order to suppress leakage current in the buffer layer 23, impurities may be introduced into a portion of the buffer layer 23 to make the buffer layer 23 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0045] Next, the cross-sectional structure of one GaN transistor 22 will be described. The GaN transistor 22 includes an electron transit layer 24 , an electron supply layer 25 , a gate layer 27 , a gate electrode 28 , a source electrode 29 , a drain electrode 30 , a first insulating film 31 , and a second insulating film 32 .

[0046] The electron transport layer 24 is formed on the buffer layer 23. The electron transport layer 24 is composed of a nitride semiconductor. The electron transport layer 24 may be, for example, a GaN layer. The electron transport layer 24 has a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress the leakage current in the electron transport layer 24, a part of the electron transport layer 24 may be made semi-insulating except for the surface layer region by introducing impurities. In this case, the impurity is, for example, C, and the peak concentration of the impurity in the electron transport layer 24 may be, for example, 1×10 19 cm -3 or more.

[0047] The electron supply layer 25 is formed on the electron transport layer 24. The electron supply layer 25 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 24, and may be, for example, an AlGaN layer. In this case, since the bandgap increases as the Al composition increases, the electron supply layer 25 which is an AlGaN layer has a larger bandgap than the electron transport layer 24 which is a GaN layer. In one example, the electron supply layer 25 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The electron supply layer 25 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 25 may have a thickness of 8 nm or more.

[0048] The electron transit layer 24 and the electron supply layer 25 are made of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) that makes up the electron transit layer 24 and the nitride semiconductor (e.g., AlGaN) that makes up the electron supply layer 25 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the electron transit layer 24 and the electron supply layer 25 and piezoelectric polarization caused by stress applied to the electron supply layer 25 near the heterojunction interface, the energy level of the conduction band of the electron transit layer 24 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 26 spreads within the electron transit layer 24 near the heterojunction interface between the electron transit layer 24 and the electron supply layer 25 (e.g., within a few nanometers from the interface).

[0049] The gate layer 27 is formed on the electron supply layer 25. More specifically, the gate layer 27 is formed on a portion of the electron supply layer 25. The gate layer 27 is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 27 may be made of any material having a band gap smaller than that of the electron supply layer 25 (e.g., an AlGaN layer). In one example, the gate layer 27 may be a GaN (p-type GaN) layer containing acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and C. The peak concentration of the acceptor-type impurities in the gate layer 27 is 7×10 18 cm -3 More than 1×10 20 cm -3 In one example, the gate layer 27 may be a GaN layer containing at least one of Mg and Zn as an impurity.

[0050] The gate electrode 28 is located above the electron supply layer 25. The gate electrode 28 may be composed of one or more metal layers. In one example, the gate electrode 28 may be composed of a titanium nitride (TiN) layer. In another example, the gate electrode 28 may include a first metal layer composed of titanium (Ti) and a second metal layer composed of TiN provided on the first metal layer. The gate electrode 28 can form a Schottky junction with the gate layer 27.

[0051] The first insulating film 31 may be provided on a portion of the gate layer 27. The first insulating film 31 may be sandwiched between the gate layer 27 and the gate electrode 28. The first insulating film 31 may be made of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), aluminum oxide (AlO), AlN, and aluminum oxynitride (AlON). In one example, the first insulating film 31 may be made of SiN. The first insulating film 31 includes an opening 31A that exposes the gate layer 27.

[0052] Gate electrode 28 is in contact with both gate layer 27 and first insulating film 31. Gate electrode 28 includes a gate contact portion that is in contact with gate layer 27 through opening 31A in first insulating film 31, and a gate field plate portion formed on first insulating film 31. The gate field plate portion is continuous with and formed integrally with the gate contact portion.

[0053] The second insulating film 32 covers the electron supply layer 25, the gate layer 27, the first insulating film 31, and the gate electrode 28. The second insulating film 32 includes a first opening 32A and a second opening 32B that expose the surface of the electron supply layer 25. The first opening 32A and the second opening 32B are formed spaced apart from each other. The gate layer 27 is located between the first opening 32A and the second opening 32B and is spaced apart from each of the first opening 32A and the second opening 32B. More specifically, the gate layer 27 is located closer to the first opening 32A than to the second opening 32B.

[0054] The second insulating film 32 may be, for example, a passivation film and may be made of at least one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the second insulating film 32 may be made of Si3N4. That is, the first insulating film 31 and the second insulating film 32 may be made of the same material. The second insulating film 32 may have a thickness of, for example, 80 nm to 200 nm.

[0055] The source electrode 29 is in contact with the electron supply layer 25 through the first opening 32A in the second insulating film 32. The source electrode 29 is in ohmic contact with the 2DEG 26 directly below the electron supply layer 25 through the first opening 32A. In one example, the source electrode 29 may include a source contact portion 29A filling the first opening 32A and a source field plate portion 29B covering the second insulating film 32. The source field plate portion 29B is continuous with and integrally formed with the source contact portion 29A. The source field plate portion 29B includes an end portion 29C located between the second opening 32B and the gate layer 27 in a plan view. The source field plate portion 29B serves to reduce electric field concentration near the end of the gate electrode 28 and the end of the gate layer 27 when a gate voltage is applied to the gate electrode 28. Although not shown, the source electrode 29 is electrically connected to the substrate 21.

[0056] The drain electrode 30 is in contact with the electron supply layer 25 through the second opening 32B of the second insulating film 32. The drain electrode 30 is in ohmic contact with the 2DEG 26 directly below the electron supply layer 25 through the second opening 32B. Each of the drain electrode 30 and the source electrode 29 can be formed of one or more metal layers (e.g., any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer).

[0057] [Internal structure of a GaN chip] The cross-sectional structures of the GaN chips 20A to 20F will be described with reference to FIGS. 7 and 8. FIG. 7 schematically shows the cross-sectional structure of the nitride semiconductor device 10 taken along line F7-F7 in FIG. 2. FIG. 8 schematically shows the cross-sectional structure of the nitride semiconductor device 10 taken along line F8-F8 in FIG. 2. FIG. 7 schematically shows the cross-sectional structures of the GaN chips 20A and 20B, and FIG. 8 schematically shows the cross-sectional structures of the GaN chips 20A, 20C, and 20E. To facilitate understanding of the drawings, FIGS. 7 and 8 show the GaN transistor 22 in FIG. 5 in a simplified dashed-line frame. The GaN chips 20A to 20F include GaN transistors 22 with the same configuration. The GaN chips 20A to 20F have the same internal structure. Therefore, the internal structure of the GaN chip 20A will be described below, and a detailed description of the internal structures of the GaN chips 20B to 20F will be omitted.

[0058] The GaN chip 20A includes a third insulating film 33 and a wiring layer 34. The GaN chip 20A also includes the source pad 35, drain pad 36, and gate pad 37 described above.

[0059] The third insulating film 33 is an insulating film that covers the source electrode 29 and the drain electrode 30 (not shown in FIGS. 7 and 8, see FIG. 5) of the GaN transistor 22. The third insulating film 33 is an interlayer insulating film and is made of, for example, SiO2.

[0060] The wiring layer 34 electrically connects the gate electrode 28 (not shown in Figures 7 and 8, see Figure 5), source electrode 29, and drain electrode 30 of the GaN transistor 22 to the source pad 35, drain pad 36, and gate pad 37, respectively.

[0061] The wiring layer 34 includes a source wiring portion 34S that electrically connects the source electrode 29 and the source pad 35, a drain wiring portion 34D that electrically connects the drain electrode 30 and the drain pad 36, and a gate wiring portion 34G (see FIG. 8) that electrically connects the gate electrode 28 and the gate pad 37. Each of the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G includes a portion provided on the third insulating film 33.

[0062] The source wiring portion 34S includes a plurality of source contacts (not shown) provided in a portion overlapping the source electrode 29 in a plan view. The plurality of source contacts penetrate the third insulating film 33 in the Z direction and are in contact with the source electrode 29.

[0063] The drain wiring portion 34D includes a plurality of drain contacts (not shown) provided in a portion overlapping the drain electrode 30 in a plan view. The plurality of drain contacts penetrate the third insulating film 33 in the Z direction and are in contact with the drain electrode 30.

[0064] The gate wiring portion 34G includes a plurality of gate contacts (not shown) provided in a portion overlapping the gate electrode 28 in a plan view. The plurality of gate contacts penetrate the third insulating film 33 in the Z direction and are in contact with the gate electrode 28.

[0065] Each of the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G is formed, for example, by a plurality of metal layers. In one example, each of the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G is formed by electrolytic plating. Each of the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G is formed, for example, by a Ti / Cu layer serving as a seed layer and a Cu layer serving as a plating layer.

[0066] The wiring layer 34 includes a fourth insulating film 34A that insulates the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G from one another. The fourth insulating film 34A is provided on the third insulating film 33. In one example, the thickness of the fourth insulating film 34A is equal to the thicknesses of the source wiring portion 34S, the drain wiring portion 34D, and the gate wiring portion 34G. In one example, the thickness of the fourth insulating film 34A is thinner than the thickness of the third insulating film 33. The fourth insulating film 34A is an interlayer insulating film and is made of, for example, SiO2.

[0067] On the wiring layer 34, a source pad 35, a drain pad 36, and a gate pad 37 (see FIG. 8) are provided. The source pad 35 is disposed at a position overlapping the source wiring portion 34S in a plan view. In other words, the source wiring portion 34S is disposed at a position overlapping the source pad 35 in a plan view. The source pad 35 includes a contact portion in contact with the source wiring portion 34S.

[0068] The drain pad 36 is disposed at a position overlapping the drain wiring portion 34D in a plan view. In other words, the drain wiring portion 34D is disposed at a position overlapping the drain pad 36 in a plan view. The drain pad 36 includes a contact portion in contact with the drain wiring portion 34D.

[0069] 8 is disposed at a position overlapping the gate wiring portion 34G in a plan view. In other words, the gate wiring portion 34G is disposed at a position overlapping the gate pad 37 in a plan view. The gate pad 37 includes a contact portion in contact with the gate wiring portion 34G.

[0070] Each of the source pad 35, the drain pad 36, and the gate pad 37 is made up of, for example, multiple metal layers. In one example, each of the source pad 35, the drain pad 36, and the gate pad 37 is provided by electrolytic plating. Each of the source pad 35, the drain pad 36, and the gate pad 37 is made up of, for example, a Ti layer as a seed layer and a Cu layer as a plating layer.

[0071] The GaN chip 20A includes a fifth insulating film 39 that insulates the source pad 35, the drain pad 36, and the gate pad 37 from one another. In one example, the thickness of the fifth insulating film 39 is equal to the thicknesses of the source pad 35, the drain pad 36, and the gate pad 37. In one example, the thickness of the fifth insulating film 39 is equal to or less than the thickness of the third insulating film 33. The fifth insulating film 39 is an interlayer insulating film and is made of, for example, SiO2. The thickness of the fifth insulating film 39 can be changed as desired. In one example, the thickness of the fifth insulating film 39 may be thicker than the thickness of the third insulating film 33.

[0072] 2, 7, and 8, the GaN chip 20A includes posts 40 provided on a source pad 35, a drain pad 36, and a gate pad 37. The posts 40 are exposed from the first sealing resin 60. In one example, the posts 40 are exposed from a sealing surface 60S of the first sealing resin 60.

[0073] The posts 40 include source posts 41, drain posts 42, and gate posts 43. The source posts 41, drain posts 42, and gate posts 43 are arranged spaced apart from one another in a direction perpendicular to the thickness direction (Z direction) of the first sealing resin 60. The first sealing resin 60 is interposed between the source posts 41, drain posts 42, and gate posts 43 in the direction perpendicular to the thickness direction of the first sealing resin 60. Therefore, the source posts 41, drain posts 42, and gate posts 43 are insulated by the first sealing resin 60.

[0074] The source post 41 includes a top surface 41S exposed from the sealing surface 60S. The drain post 42 includes a top surface 42S exposed from the sealing surface 60S. The gate post 43 includes a top surface 43S exposed from the sealing surface 60S. As shown in FIGS. 7 and 8 , the top surfaces 41S of the source post 41, 42S of the drain post 42, 43S of the gate post 43, and the sealing surface 60S are flush with each other. In one example, the top surfaces 41S of the source post 41, 42S of the drain post 42, 43S of the gate post 43, and the sealing surface 60S are ground together, so that the top surfaces 41S of the source post 41, 42S of the drain post 42, 43S of the gate post 43, and the sealing surface 60S are flush with each other. Therefore, the top surface 41S of the source post 41, the top surface 42S of the drain post 42, the top surface 43S of the gate post 43, and the sealing surface 60S each have grinding marks.

[0075] The source post 41 is provided on the source pad 35. The source post 41 is in contact with the source pad 35. The source post 41 is electrically connected to the source electrode 29 (see FIG. 5) via the source pad 35 and the source wiring portion 34S.

[0076] 2, the source post 41 has a strip shape extending in the X direction in a plan view. In the example shown in Fig. 2, the width dimension (size in the Y direction) of the source post 41 is smaller than the width dimension (size in the Y direction) of the source pad 35. The length dimension (size in the X direction) of the source post 41 is smaller than the length dimension (size in the X direction) of the source pad 35.

[0077] A connection wiring layer 51 is provided on the source post 41 as the external wiring layer 50. The width dimension (size in the Y direction) of the connection wiring layer 51 is larger than the width dimension of the source post 41. The length dimension (size in the X direction) of the connection wiring layer 51 is larger than the length dimension of the source post 41. Therefore, in a plan view, the connection wiring layer 51 protrudes from the source post 41 in both the X direction and the Y direction. The portion of the connection wiring layer 51 protruding from the source post 41 in a plan view is provided on the sealing surface 60S.

[0078] 2, the drain post 42 has a strip shape extending in the X direction in a plan view. In the example shown in Fig. 2, the width dimension (size in the Y direction) of the drain post 42 is smaller than the width dimension (size in the Y direction) of the drain pad 36. The length dimension (size in the X direction) of the drain post 42 is smaller than the length dimension (size in the X direction) of the drain pad 36.

[0079] A drain wiring layer 53 is provided on the drain post 42 as the external wiring layer 50. The width dimension (size in the Y direction) of the drain wiring layer 53 is larger than the width dimension of the drain post 42. The length dimension (size in the X direction) of the drain wiring layer 53 is larger than the length dimension of the drain post 42. Therefore, in a plan view, the drain wiring layer 53 protrudes from the drain post 42 in both the X direction and the Y direction. The portion of the drain wiring layer 53 protruding from the drain post 42 in a plan view is provided on the sealing surface 60S.

[0080] As shown in Fig. 8, the gate posts 43 are provided on the gate pads 37. A plurality of gate posts 43 are provided corresponding to the number of gate pads 37. In the example shown in Fig. 8, two gate posts 43 are provided corresponding to the two gate pads 37. Each gate post 43 is electrically connected to the gate electrode 28 (see Fig. 5) via the gate pad 37 and the gate wiring portion 34G.

[0081] 2, gate post 43 has a rectangular shape with its short side in the X direction and its long side in the Y direction in plan view. In the example shown in Fig. 2, the width dimension (size in the X direction) of gate post 43 is smaller than the width dimension (size in the X direction) of gate pad 37. The length dimension (size in the Y direction) of gate post 43 is smaller than the length dimension (size in the Y direction) of gate pad 37.

[0082] A first gate wiring layer 54 is provided on each gate post 43 as an external wiring layer 50. The width dimension of the first gate wiring layer 54 (the dimension in a direction perpendicular to the direction in which the first gate wiring layer 54 extends in a plan view) is larger than the width dimension of the gate post 43. The first gate wiring layer 54 is provided so as to electrically connect two gate posts 43 together.

[0083] Like the GaN chip 20A, the GaN chips 20C and 20E include posts 40. The positional and dimensional relationships between the posts 40 and the external wiring layer 50 of the GaN chips 20C and 20E are the same as those of the GaN chip 20A.

[0084] The GaN chip 20B includes posts 40, similar to the GaN chip 20A. The positional and dimensional relationship between the source post 41 and the source pad 35 of the GaN chip 20B is similar to the positional and dimensional relationship between the source post 41 and the source pad 35 of the GaN chip 20A. The positional and dimensional relationship between the drain post 42 and the drain pad 36 of the GaN chip 20B is similar to the positional and dimensional relationship between the drain post 42 and the drain pad 36 of the GaN chip 20A. The positional and dimensional relationship between the gate post 43 and the gate pad 37 of the GaN chip 20B is similar to the positional and dimensional relationship between the gate post 43 and the gate pad 37 of the GaN chip 20A.

[0085] On the other hand, the positional and dimensional relationship between the GaN chip 20B and the external wiring layer 50 differs from the positional and dimensional relationship between the GaN chip 20A and the external wiring layer 50. More specifically, a connection wiring layer 51 is provided on the drain post 42 of the GaN chip 20B. The width dimension (size in the Y direction) of the connection wiring layer 51 is larger than the width dimension (size in the Y direction) of the drain post 42. The length dimension (size in the X direction) of the connection wiring layer 51 is larger than the length dimension (size in the X direction) of the drain post 42. Therefore, in a planar view, the connection wiring layer 51 protrudes from the drain post 42 in both the X direction and the Y direction. The portion of the connection wiring layer 51 protruding from the drain post 42 in a planar view is provided on the sealing surface 60S.

[0086] A source wiring layer 52 is provided on the source post 41 of the GaN chip 20B. The width dimension (size in the Y direction) of the source wiring layer 52 is larger than the width dimension of the source post 41. The length dimension (size in the X direction) of the source wiring layer 52 is larger than the length dimension of the source post 41. Therefore, in a plan view, the source wiring layer 52 protrudes from the source post 41 in both the X direction and the Y direction. The portion of the source wiring layer 52 protruding from the source post 41 in a plan view is provided on the sealing surface 60S.

[0087] A second gate wiring layer 55 is provided on each gate post 43 of the GaN chip 20B. The width dimension of the second gate wiring layer 55 (the dimension in a direction perpendicular to the direction in which the second gate wiring layer 55 extends in a plan view) is larger than the width dimension of the gate post 43. The second gate wiring layer 55 is provided so as to electrically connect two gate posts 43 together.

[0088] Like the GaN chip 20B, the GaN chips 20D and 20F include posts 40. The positional and dimensional relationships between the posts 40 and the external wiring layer 50 of the GaN chips 20D and 20F are the same as those of the GaN chip 20B.

[0089] Next, the connection between the GaN chip 20A and the GaN chip 20B and the external wiring layer 50 will be described. As shown in FIGS. 2 and 7 , the drain post 42 of the GaN chip 20A is electrically connected to the drain wiring layer 53. Both the source post 41 of the GaN chip 20A and the drain post 42 of the GaN chip 20B are electrically connected to the connection wiring layer 51. The source post 41 of the GaN chip 20B is electrically connected to the source wiring layer 52. The two gate posts 43 of the GaN chip 20A are electrically connected to the first gate wiring layer 54. The two gate posts 43 of the GaN chip 20B are electrically connected to the second gate wiring layer 55.

[0090] In this manner, the source electrode 29 of the GaN chip 20A and the drain electrode 30 of the GaN chip 20B are electrically connected by the connection wiring layer 51. That is, the GaN chip 20B is electrically connected to the GaN chip 20A.

[0091] The GaN chip 20C and the GaN chip 20D are electrically connected to each other. The GaN chip 20E and the GaN chip 20F are electrically connected to each other. The electrical connection between the GaN chip 20C and the GaN chip 20D and the electrical connection between the GaN chip 20E and the GaN chip 20F are both similar to the electrical connection between the GaN chip 20A and the GaN chip 20B.

[0092] The nitride semiconductor device 10 can be said to have a connection wiring layer 51 that electrically connects a source post 41 formed on a source pad 35 of one of two GaN chips adjacent to each other in the first direction (Y direction) and a drain post 42 formed on a drain pad 36 of the other of two GaN chips adjacent to each other in the first direction (Y direction).

[0093] (electromagnetic wave shielding) The nitride semiconductor device 10 includes an electromagnetic wave shield 70. In the first embodiment, the electromagnetic wave shield 70 is provided between GaN chips 20A to 20F that are adjacent to each other in at least one of the X and Y directions. More specifically, the electromagnetic wave shield 70 includes a plurality of (six in the first embodiment) first to sixth electromagnetic wave shields 70A to 70F corresponding to the GaN chips 20A to 20F. The first to sixth electromagnetic wave shields 70A to 70F have the same configuration. Therefore, hereinafter, the configuration of the first electromagnetic wave shield 70A will be described in detail, and detailed descriptions of the second to sixth electromagnetic wave shields 70B to 70F will be omitted.

[0094] As shown in FIG. 7, the first electromagnetic wave shield 70A includes a side shield part 71 provided on each of a plurality of chip side surfaces of the GaN chip 20A, and a back shield part 72 provided on the chip back surface 20R of the GaN chip 20A.

[0095] In one example, the first electromagnetic wave shield 70A is made of a metal layer. More specifically, the side shield part 71 and the back shield part 72 have different configurations. Specifically, the side shield part 71 and the back shield part 72 are formed by different methods. In one example, the side shield part 71 is formed mainly by electrolytic plating. In one example, the back shield part 72 is formed by sputtering. The back shield part 72 may be made of conductive ink. The conductive ink may contain, for example, gold (Au) or silver (Ag). The back shield part 72 may be made of conductive ink applied by inkjet printing.

[0096] The side shield part 71 includes a seed layer 71A provided on the third chip side surface 20PC, which serves as the chip side surface, and a plating layer 71B provided on the seed layer 71A. That is, the metal layer that constitutes the side shield part 71 includes the seed layer 71A and the plating layer 71B. The seed layer 71A is formed, for example, of a laminated structure of a Ti layer and a Cu layer. The plating layer 71B is formed, for example, of a material containing Cu. The metal layer that constitutes the back surface shield part 72 is formed of a sputtered film 72A provided on the substrate back surface 21R of the substrate 21. This sputtered film 72A is formed, for example, of a laminated structure of a Ti film and a Cu film.

[0097] The material forming seed layer 71A can be changed arbitrarily. The material forming plating layer 71B can be changed arbitrarily. The material forming sputtered film 72A can be changed arbitrarily.

[0098] The side shield portion 71 of the first electromagnetic wave shield 70A is provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A. As shown in FIG. 7, the side shield portion 71 is provided over the entire third chip side surface 20PC in the Z direction. The side shield portion 71 is provided over the entire fourth chip side surface 20PD in the Z direction. Although not shown, the side shield portion 71 is provided over the entire first chip side surface 20PA in the Z direction. The side shield portion 71 is provided over the entire second chip side surface 20PB in the Z direction.

[0099] As shown in FIG. 9, the side shield part 71 includes a substrate shield part 71Q that covers the side surface of the substrate 21, and a wiring shield part 71R that covers the side surface of the wiring layer . The substrate shield part 71Q is provided over the entire side surface of the substrate 21 in the Z direction. The substrate shield part 71Q extends in the Z direction. The substrate shield part 71Q is connected to the rear surface shield part 72.

[0100] The wiring shield part 71R is provided over the entire side surface of the wiring layer 34 in the Z direction. The wiring shield part 71R is provided over the entire side surface of the third insulating film 33 in the Z direction. The wiring shield part 71R is provided over the entire side surface of the fifth insulating film 39. The wiring shield part 71R is disposed at a position that does not overlap with the substrate shield part 71Q in a planar view. Specifically, the wiring shield part 71R is disposed more inward of the GaN chip 20A than the substrate shield part 71Q in a planar view.

[0101] The side shield part 71 further includes a step shield part 71S that covers the step part 20PE provided on the third chip side surface 20PC. Thus, the side shield part 71 is provided to cover the step part 20PE. The step part 20PE is provided between the substrate side surface of the substrate 21 on the third chip side surface 20PC and a portion of the GaN chip 20A above the substrate 21. The portion of the GaN chip 20A above the substrate 21 includes the third insulating film 33, the wiring layer 34, and the fifth insulating film 39. In a plan view, the substrate 21 protrudes beyond the third insulating film 33, the wiring layer 34, and the fifth insulating film 39 in the X and Y directions. Therefore, the step shield part 71S covers the portion of the substrate surface 21S of the substrate 21 that protrudes beyond the third insulating film 33, the wiring layer 34, and the fifth insulating film 39 in a plan view. The step shield part 71S is connected to the substrate shield part 71Q and the wiring shield part 71R.

[0102] As shown in FIG. 9, in the GaN chip 20B, similarly to the GaN chip 20A, the side shield portion 71 of the second electromagnetic wave shield 70B is provided so as to cover the step portion 20PE provided on the fourth chip side surface 20PD of the GaN chip 20B.

[0103] The side shield part 71 of the first electromagnetic wave shield 70A includes a protrusion 71P that protrudes upward beyond the third chip side surface 20PC in the Z direction. The protrusion 71P can be considered to be a portion of the side shield part 71 that protrudes from the surface 39S of the fifth insulating film 39 in the Z direction. The protrusion 71P is disposed outward from the chip surface 20S of the GaN chip 20A. In other words, the protrusion 71P is not provided in a position that overlaps the chip surface 20S in a plan view. The protrusion length PA of the protrusion 71P is shorter than the thickness T1 of the substrate 21. The protrusion length PA is shorter than the thickness T2 of the third insulating film 33. The protrusion length PA is shorter than the thickness T3 of the wiring layer 34. The protrusion length PA is shorter than the thickness T4 of the fifth insulating film 39. The protrusion length PA is shorter than the thickness T6 of the side shield part 71. In one example, the protrusion length PA is equal to the thickness T7 of the back surface shield part 72. 9, the thickness T6 of the side shield part 71 can be defined by the distance in the X direction between the third chip side surface 20PC and the surface of the side shield part 71. In the first embodiment, the protrusion 71P is also provided on the side shield parts 71 provided on the first chip side surface 20PA, the second chip side surface 20PB, and the fourth chip side surface 20PD. Also, as shown in FIG. 9, the side shield part 71 of the second electromagnetic wave shield 70B of the GaN chip 20B includes the protrusion 71P, similar to the GaN chip 20A.

[0104] In the protrusion 71P, the plating layer 71B covers the surface (upper surface) of the seed layer 71A. In one example, the surface of the seed layer 71A is flush with the surface 39S of the fifth insulating film 39. That is, the seed layer 71A does not protrude in the Z direction from the surface 39S of the fifth insulating film 39. On the other hand, the plating layer 71B protrudes in the Z direction from the surface 39S of the fifth insulating film 39. Therefore, the protrusion 71P is composed of the plating layer 71B. That is, the protrusion length PA is equal to the thickness of the plating layer 71B of the side shield part 71.

[0105] In one example, the thickness T6 of the side shield part 71 is thinner than the thickness T1 of the substrate 21. In one example, the thickness T6 of the side shield part 71 is thinner than the thickness T2 of the third insulating film 33. In one example, the thickness T6 of the side shield part 71 is thinner than the thickness T3 of the wiring layer 34. In one example, the thickness T6 of the side shield part 71 is thinner than the thickness T4 of the fifth insulating film 39. In one example, the thickness T6 of the side shield part 71 is thinner than the thickness T5 of the external wiring layer 50. In one example, the thickness T6 of the side shield part 71 is 1 μm or more.

[0106] 7, the back surface shield part 72 of the first electromagnetic wave shield 70A is provided over the entire substrate back surface 21R of the substrate 21 of the GaN chip 20A. In other words, the back surface shield part 72 of the first electromagnetic wave shield 70A is provided over the entire chip back surface 20R of the GaN chip 20A. The back surface shield part 72 is connected to the side surface shield part 71. More specifically, the back surface shield part 72 is connected to the side surface shield parts 71 provided on each of the first to fourth chip side surfaces 20PA to 20PD. Therefore, the first electromagnetic wave shield 70A covers the GaN chip 20A from below in the X, Y, and Z directions.

[0107] The rear surface shield part 72 is provided on the substrate rear surface 21R of the substrate 21 and therefore protrudes in the Z direction from the sealed rear surface 60R. In the first embodiment, the rear surface shield part 72 is not in contact with the sealed rear surface 60R. It can be said that the rear surface shield part 72 is provided at a distance from the sealed rear surface 60R.

[0108] 4, the rear surface shield part 72 protrudes from the substrate 21 in both the X direction and the Y direction in plan view. That is, the area of ​​the rear surface shield part 72 is larger than the area of ​​the substrate rear surface 21R of the substrate 21 in plan view.

[0109] In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T1 of the substrate 21. In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T2 of the third insulating film 33. In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T3 of the wiring layer 34. In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T4 of the fifth insulating film 39. In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T5 of the external wiring layer 50. In one example, the thickness T7 of the rear shield part 72 is 1 μm or more. In one example, the thickness T7 of the rear shield part 72 is thinner than the thickness T6 of the side shield part 71.

[0110] The rear surface shield part 72 is provided on the rear surface 21R of the substrate 21 and is therefore electrically connected to the substrate 21. Since the source electrode 29 of the GaN transistor 22 of the GaN chip 20A is electrically connected to the substrate 21, it can be said that the rear surface shield part 72 is electrically connected to the source electrode 29. In this way, the first electromagnetic wave shield 70A is electrically connected to the source electrode 29 of the GaN transistor 22 of the GaN chip 20A.

[0111] 4, each of the GaN chips 20A to 20F is provided with a rear surface shield part 72. The rear surface shield parts 72 of the GaN chips 20A to 20F are arranged spaced apart from each other in a plan view.

[0112] The shortest distances DA between adjacent GaN chips 20A to 20F are equal to each other. The shortest distance DA is, for example, 10 μm or more and 50 μm or less. The shortest distance DB between the GaN chips 20A, 20B and the first sealing side surface 60A in the X direction is smaller than the shortest distance DA. The shortest distance DB is, for example, smaller than ½ of the shortest distance DA. The shortest distance DC between the GaN chips 20E, 20F and the second sealing side surface 60B in the X direction is smaller than the shortest distance DA. The shortest distance DC is, for example, smaller than ½ of the shortest distance DA. In one example, the shortest distance DC is equal to the shortest distance DB. The shortest distance DD between the GaN chips 20A, 20C, 20E and the fourth sealing side surface 60D in the Y direction is smaller than the shortest distance DA. The shortest distance DD is, for example, smaller than ½ of the shortest distance DA. In one example, the shortest distance DD is equal to the shortest distance DB. The shortest distance DE between the GaN chips 20B, 20D, and 20F and the third sealing side surface 60C in the Y direction is smaller than the shortest distance DA. The shortest distance DE is, for example, smaller than 1 / 2 of the shortest distance DA. In one example, the shortest distance DE is equal to the shortest distance DB. It can also be said that the shortest distance DE is equal to the shortest distance DD.

[0113] 2 and 4, in one example, the shortest distance DA is smaller than the width dimension of the first gate wiring layer 54. In one example, the shortest distance DA is smaller than the width dimension of the second gate wiring layer 55. In one example, the shortest distance DA is smaller than the width dimension of the source wiring layer 52. In one example, the shortest distance DA is smaller than the width dimension of the drain wiring layer 53.

[0114] As shown in FIGS. 4 and 9 , in one example, the shortest distance DA is smaller than the thickness (dimension in the Z direction) of the GaN chips 20A-20F. In one example, the shortest distance DA is smaller than the thickness T1 (dimension in the Z direction) of the substrate 21 of the GaN chips 20A-20F. In one example, the shortest distance DA is smaller than the thickness T2 (dimension in the Z direction) of the third insulating film 33. In one example, the shortest distance DA is smaller than the thickness T3 of the wiring layer 34. In one example, the shortest distance DA is smaller than the thickness T4 (dimension in the Z direction) of the fifth insulating film 39. In one example, the shortest distance DA is smaller than the thickness of the source pad 35. In one example, the shortest distance DA is smaller than the thickness of the drain pad 36. In one example, the shortest distance DA is smaller than the thickness of the gate pad 37. In one example, the shortest distance DA is smaller than the width dimension of the source pad 35, the width dimension of the drain pad 36, and the width dimension of the gate pad 37. In one example, the shortest distance DA is smaller than the thickness T5 (dimension in the Z direction) of the external wiring layer 50 shown in FIG. 7 . In one example, the shortest distance DA is smaller than the width dimension of the post 40. In one example, the shortest distance DA is greater than twice the thickness T6 of the side shield part 71 of the first electromagnetic wave shield 70A. In another example, each of the shortest distances DB to DE is greater than the thickness T6 of the side shield part 71.

[0115] Here, the shortest distance DA can be defined as the distance in the X or Y direction between the back surface shield parts 72 of the GaN chips 20A to 20F in plan view. The shortest distance DA can also be defined as the distance in the X or Y direction between the parts of the side surface shield parts 71 of the GaN chips 20A to 20F that cover the side surfaces of the substrate 21 in plan view.

[0116] The shortest distance DB can be defined in plan view by the distance in the X direction between the back surface shield part 72 of the GaN chips 20A, 20B and the first sealing side surface 60A. Also, the shortest distance DB can be defined in plan view by the distance in the X direction between the part of the side surface shield part 71 of the GaN chips 20A, 20B that covers the side surface of the substrate 21 and the first sealing side surface 60A.

[0117] The shortest distance DC can be defined in plan view by the distance in the X direction between the back surface shield part 72 of the GaN chips 20E, 20F and the second sealing side surface 60B. Also, the shortest distance DC can be defined in plan view by the distance in the X direction between the part of the side surface shield part 71 of the GaN chips 20E, 20F that covers the side surface of the substrate 21 and the second sealing side surface 60B.

[0118] The shortest distance DD can be defined as the distance in the Y direction between the back surface shield part 72 of the GaN chips 20A, 20C, and 20E and the fourth sealing side surface 60D in a plan view. Also, the shortest distance DD can be defined as the distance in the Y direction between the part of the side surface shield part 71 of the GaN chips 20A, 20C, and 20E that covers the side surface of the substrate 21 and the fourth sealing side surface 60D in a plan view.

[0119] The shortest distance DE can be defined in plan view by the distance in the Y direction between the back surface shield part 72 of the GaN chips 20B, 20D, and 20F and the third sealing side surface 60C. Also, the shortest distance DE can be defined in plan view by the distance in the Y direction between the part of the side surface shield part 71 of the GaN chips 20B, 20D, and 20F that covers the side surface of the substrate 21 and the third sealing side surface 60C.

[0120] The width of the source pad 35 can be defined by the dimension in a direction perpendicular to the extension direction of the source pad 35 in a plan view. The width of the drain pad 36 can be defined by the dimension in a direction perpendicular to the extension direction of the drain pad 36 in a plan view. The width of the gate pad 37 can be defined by the dimension in a direction perpendicular to the extension direction of the gate pad 37 in a plan view. The width of the first gate wiring layer 54 can be defined by the dimension in a direction perpendicular to the extension direction of the first gate wiring layer 54 in a plan view. The width of the second gate wiring layer 55 can be defined by the dimension in a direction perpendicular to the extension direction of the second gate wiring layer 55 in a plan view. The width of the source wiring layer 52 can be defined by the dimension in a direction perpendicular to the extension direction of the source wiring layer 52 in a plan view. The width of the drain wiring layer 53 can be defined by the dimension in a direction perpendicular to the extension direction of the drain wiring layer 53 in a plan view. The width dimension of the post 40 can be defined as the dimension in a direction perpendicular to the direction in which the post 40 extends in a plan view.

[0121] (1st sealing resin) 2, 7, and 8, the GaN chips 20A to 20F are sealed with a first sealing resin 60. As shown in Fig. 9, the first sealing resin 60 is interposed between the GaN chip 20A and the GaN chip 20B. More specifically, the first sealing resin 60 is interposed between a first electromagnetic wave shield 70A provided on the GaN chip 20A and a second electromagnetic wave shield 70B provided on the GaN chip 20B.

[0122] The first sealing resin 60 includes a wiring sealing layer 61 and a substrate sealing layer 62. The wiring sealing layer 61 and the substrate sealing layer 62 are separated for convenience, and there is no interface between the wiring sealing layer 61 and the substrate sealing layer 62.

[0123] The wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the first electromagnetic wave shield 70A of the GaN chip 20A and the wiring shield portion 71R of the second electromagnetic wave shield 70B of the GaN chip 20B. Although not designated by reference numerals below, the wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the first electromagnetic wave shield 70A and the wiring shield portion 71R of the third electromagnetic wave shield 70C of the GaN chip 20C, and between the wiring shield portion 71R of the third electromagnetic wave shield 70C and the wiring shield portion 71R of the fifth electromagnetic wave shield 70E of the GaN chip 20E. Although not shown, the wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the third electromagnetic wave shield 70C of the GaN chip 20C and the wiring shield portion 71R of the fourth electromagnetic wave shield 70D of the GaN chip 20D, and between the wiring shield portion 71R of the fifth electromagnetic wave shield 70E of the GaN chip 20E and the wiring shield portion 71R of the sixth electromagnetic wave shield 70F of the GaN chip 20F. The wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the second electromagnetic wave shield 70B and the wiring shield portion 71R of the fourth electromagnetic wave shield 70D, and between the wiring shield portion 71R of the fourth electromagnetic wave shield 70D and the wiring shield portion 71R of the sixth electromagnetic wave shield 70F. In this way, the wiring sealing layer 61 is interposed between adjacent wiring shield portions 71R in the X or Y direction of the wiring shield portions 71R of the first to sixth electromagnetic wave shields 70A to 70F, and insulates the wiring shield portions 71R of the first to sixth electromagnetic wave shields 70A to 70F from each other. Also, the first sealing resin 60 can be said to be provided so as to cover each of the wiring shield portions 71R of the first to sixth electromagnetic wave shields 70A to 70F and to be interposed between adjacent wiring shield portions 71R in the X or Y direction.

[0124] 9, the substrate sealing layer 62 is interposed between the substrate shield portion 71Q of the first electromagnetic wave shield 70A of the GaN chip 20A and the substrate shield portion 71Q of the second electromagnetic wave shield 70B of the GaN chip 20B. The substrate sealing layer 62 is interposed between the substrate shield portion 71Q of the first electromagnetic wave shield 70A and the substrate shield portion 71Q of the third electromagnetic wave shield 70C of the GaN chip 20C, and between the substrate shield portion 71Q of the third electromagnetic wave shield 70C and the substrate shield portion 71Q of the fifth electromagnetic wave shield 70E of the GaN chip 20E, as shown in FIG. Although not shown, the substrate sealing layer 62 is interposed between the substrate shield portion 71Q of the third electromagnetic wave shield 70C and the substrate shield portion 71Q of the fourth electromagnetic wave shield 70D of the GaN chip 20D, and between the substrate shield portion 71Q of the fifth electromagnetic wave shield 70E and the substrate shield portion 71Q of the sixth electromagnetic wave shield 70F of the GaN chip 20F. The substrate sealing layer 62 is interposed between the substrate shield portion 71Q of the second electromagnetic wave shield 70B and the substrate shield portion 71Q of the fourth electromagnetic wave shield 70D, and between the substrate shield portion 71Q of the fourth electromagnetic wave shield 70D and the substrate shield portion 71Q of the sixth electromagnetic wave shield 70F. In this way, the board sealing layer 62 is interposed between adjacent board shield portions 71Q in the X direction or Y direction of the board shield portions 71Q of the first to sixth electromagnetic wave shields 70A to 70F, insulating the first to sixth electromagnetic wave shields 70A to 70F from one another. Furthermore, the first sealing resin 60 covers each of the board shield portions 71Q of the first to sixth electromagnetic wave shields 70A to 70F, and is disposed so as to be interposed between adjacent board shield portions 71Q in the X direction or Y direction. Therefore, the sealing back surface 60R is exposed between adjacent electromagnetic wave shields in the X direction or Y direction among the first to sixth electromagnetic wave shields 70A to 70F.

[0125] 9, in GaN chips 20A and 20B adjacent to each other in the Y direction (first direction), the dimension HA in the Y direction (first direction) of the wiring sealing layer 61 is larger than the dimension HB in the Y direction (first direction) of the substrate sealing layer 62. The dimension HB is equal to the shortest distance DA (see FIG. 4) between adjacent substrates 21.

[0126] As shown in FIG. 7 , the Y-direction dimension HC of the wiring encapsulation layer 61 interposed between the fourth encapsulation side surface 60D and the wiring layer 34 of the GaN chip 20A is larger than the Y-direction dimension HD of the substrate encapsulation layer 62 interposed between the fourth encapsulation side surface 60D and the substrate 21 of the GaN chip 20A. The Y-direction dimension HE of the wiring encapsulation layer 61 interposed between the third encapsulation side surface 60C and the wiring layer 34 of the GaN chip 20B is larger than the Y-direction dimension HF of the substrate encapsulation layer 62 interposed between the third encapsulation side surface 60C and the substrate 21 of the GaN chip 20B. Both the dimensions HC and HE are smaller than the dimension HA. The dimension HC is equal to the dimension HE. Both the dimensions HD and HF are smaller than the dimension HB. The dimension HD is equal to the dimension HF. The dimension HD is equal to the shortest distance DD (see FIG. 4 ) between the first electromagnetic wave shield 70A and the fourth encapsulation side surface 60D in the X-direction. The dimension HF is equal to the shortest distance DE (see FIG. 4) between the second electromagnetic wave shield 70B and the third sealing side surface 60C in the X direction.

[0127] Although not shown, the GaN chips 20C and 20D have the same relationship of dimensions HA to HF as the GaN chips 20A and 20B. The GaN chips 20E and 20F have the same relationship of dimensions HA to HF as the GaN chips 20A and 20B.

[0128] Although not shown, in the GaN chips 20A, 20C, and 20E adjacent to each other in the X direction (second direction), the first dimension in the X direction (second direction) of the wiring sealing layer 61 is larger than the second dimension in the X direction (second direction) of the substrate sealing layer 62. The second dimension is smaller than the shortest distance DA (see FIG. 4).

[0129] The third dimension in the X direction of the wiring sealing layer 61 interposed between the first sealing side surface 60A and the wiring shield portion 71R of the first electromagnetic wave shield 70A is larger than the fourth dimension in the X direction of the board sealing layer 62 interposed between the first sealing side surface 60A and the board shield portion 71Q of the first electromagnetic wave shield 70A. The fifth dimension in the X direction of the wiring sealing layer 61 interposed between the second sealing side surface 60B and the wiring shield portion 71R of the fifth electromagnetic wave shield 70E is larger than the sixth dimension in the X direction of the board sealing layer 62 interposed between the second sealing side surface 60B and the board shield portion 71Q of the fifth electromagnetic wave shield 70E. Both the third dimension and the fifth dimension are smaller than the first dimension. The third dimension is equal to the fifth dimension. Both the fourth dimension and the sixth dimension are smaller than the second dimension. The fourth dimension is equal to the sixth dimension. Similarly, the GaN chips 20B, 20D, and 20F have the same relationships of the first to sixth dimensions as the GaN chips 20A, 20C, and 20E. The fourth dimension is smaller than the shortest distance DB in the X direction between the substrate shield portion 71Q of the first electromagnetic wave shield 70A and the first sealing side surface 60A. The sixth dimension is smaller than the shortest distance DC in the X direction between the substrate shield portion 71Q of the third electromagnetic wave shield 70C and the second sealing side surface 60B.

[0130] As shown in FIG. 7, the first sealing resin 60 covers the wiring layer 34 of the GaN chips 20A and 20B. As shown in FIG. 8, the first sealing resin 60 covers the wiring layer 34 of the GaN chips 20A, 20C, and 20E. Although not shown, the first sealing resin 60 also covers the wiring layer 34 of the GaN chips 20D and 20F. In this way, the first sealing resin 60 covers the wiring layer 34 of the GaN chips 20A to 20F. Furthermore, the first sealing resin 60 covers each of the drain pad 36, source pad 35, and gate pad 37 exposed from the wiring layer 34 of the GaN chips 20A to 20F. More specifically, the first sealing resin 60 covers each of the drain pad 36 protruding from the drain post 42 in a plan view, the source pad 35 protruding from the source post 41 in a plan view, and the gate pad 37 protruding from the gate post 43.

[0131] [Circuit configuration of nitride semiconductor devices] Next, an example of the circuit configuration of the nitride semiconductor device 10 will be described. Fig. 10 shows a schematic circuit configuration of the nitride semiconductor device 10. In the description of the circuit configuration of the nitride semiconductor device 10, the external wiring layers 50 will be referred to as the "external wiring layer 50U," the "external wiring layer 50V," and the "external wiring layer 50W" for convenience. The connection wiring layer 51, the drain wiring layer 53, the source wiring layer 52, the first gate wiring layer 54, and the second gate wiring layer 55 of the external wiring layer 50 will also be labeled with "U," "V," and "W" for convenience.

[0132] 10, nitride semiconductor device 10 includes GaN transistors 22 of GaN chips 20A and 20B connected in series, GaN transistors 22 of GaN chips 20C and 20D connected in series, and GaN transistors 22 of GaN chips 20E and 20F connected in series. Nitride semiconductor device 10 also includes external wiring layers 50U corresponding to GaN chips 20A and 20B, external wiring layers 50V corresponding to GaN chips 20C and 20D, and external wiring layers 50W corresponding to GaN chips 20E and 20F.

[0133] The source electrode 29 of the GaN transistor 22 of the GaN chip 20A is electrically connected to the drain electrode 30 of the GaN transistor 22 of the GaN chip 20B. The connection wiring layer 51U is electrically connected to the node between the source electrode 29 of the GaN transistor 22 of the GaN chip 20A and the drain electrode 30 of the GaN transistor 22 of the GaN chip 20B. The drain electrode 30 of the GaN transistor 22 of the GaN chip 20A is electrically connected to the drain wiring layer 53U. The source electrode 29 of the GaN transistor 22 of the GaN chip 20B is electrically connected to the source wiring layer 52U. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20A is electrically connected to the first gate wiring layer 54U. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20B is electrically connected to the second gate wiring layer 55U.

[0134] The source electrode 29 of the GaN transistor 22 of the GaN chip 20C is electrically connected to the drain electrode 30 of the GaN transistor 22 of the GaN chip 20D. The connection wiring layer 51V is electrically connected to the node between the source electrode 29 of the GaN transistor 22 of the GaN chip 20C and the drain electrode 30 of the GaN transistor 22 of the GaN chip 20D. The drain electrode 30 of the GaN transistor 22 of the GaN chip 20C is electrically connected to the drain wiring layer 53V. The source electrode 29 of the GaN transistor 22 of the GaN chip 20D is electrically connected to the source wiring layer 52V. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20C is electrically connected to the first gate wiring layer 54V. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20D is electrically connected to the second gate wiring layer 55V.

[0135] The source electrode 29 of the GaN transistor 22 of the GaN chip 20E is electrically connected to the drain electrode 30 of the GaN transistor 22 of the GaN chip 20F. The connection wiring layer 51W is electrically connected to the node between the source electrode 29 of the GaN transistor 22 of the GaN chip 20E and the drain electrode 30 of the GaN transistor 22 of the GaN chip 20F. The drain electrode 30 of the GaN transistor 22 of the GaN chip 20E is electrically connected to the drain wiring layer 53W. The source electrode 29 of the GaN transistor 22 of the GaN chip 20F is electrically connected to the source wiring layer 52W. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20E is electrically connected to the first gate wiring layer 54W. The gate electrode 28 of the GaN transistor 22 of the GaN chip 20F is electrically connected to the second gate wiring layer 55W.

[0136] On the other hand, the GaN transistors 22 of the GaN chips 20A and 20B, the GaN transistors 22 of the GaN chips 20C and 20D, and the GaN transistors 22 of the GaN chips 20E and 20F are insulated from one another.

[0137] [Overall configuration of semiconductor module] Next, an example of the configuration of a semiconductor module 100 including a nitride semiconductor device 10 will be described. FIG. 11 is a plan view showing a schematic internal configuration of the semiconductor module 100. FIG. 12 is an enlarged view of the nitride semiconductor device 10 of FIG. 11 and its periphery. FIG. 13 is a rear view of the semiconductor module 100. FIG. 14 is a cross-sectional view showing a schematic cross-sectional structure of the semiconductor module 100 taken along line F14-F14 of FIG. 11. Note that a second sealing resin 180, which will be described later, is omitted from FIG. 11 to facilitate understanding of the drawing.

[0138] 11, the semiconductor module 100 includes a support substrate 110, a drive chip 160 electrically connected to the nitride semiconductor device 10, and a control chip 170 electrically connected to the drive chip 160. The nitride semiconductor device 10, the drive chip 160, and the control chip 170 are each disposed on the support substrate 110. The semiconductor module 100 includes a second sealing resin 180 (see FIG. 14) that seals the nitride semiconductor device 10, the drive chip 160, and the control chip 170.

[0139] The support substrate 110 is formed in the shape of a rectangular flat plate with its thickness direction in the Z direction. In one example, the support substrate 110 is formed in a rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction in a plan view. The support substrate 110 has a support substrate front surface 110S and a support substrate back surface 110R facing opposite sides in the Z direction, and first to fourth support substrate side surfaces 110A to 110D connecting the support substrate front surface 110S and the support substrate back surface 110R.

[0140] The support substrate front surface 110S is the surface on which the nitride semiconductor device 10, the drive chip 160, and the control chip 170 are arranged. The support substrate rear surface 110R is the mounting surface for the semiconductor module 100. In other words, the semiconductor module 100 has a surface-mounted package structure. The first support substrate side surface 110A and the second support substrate side surface 110B constitute both end surfaces of the support substrate 110 in the X direction, and the third support substrate side surface 110C and the fourth support substrate side surface 110D constitute both end surfaces of the support substrate 110 in the Y direction.

[0141] The nitride semiconductor device 10, the drive chip 160, and the control chip 170 are arranged spaced apart from each other in the Y direction. In a plan view, the nitride semiconductor device 10 is disposed closer to the fourth support substrate side surface 110D than the drive chip 160 and the control chip 170. In a plan view, the control chip 170 is disposed closer to the third support substrate side surface 110C than the nitride semiconductor device 10 and the drive chip 160. The drive chip 160 is disposed between the nitride semiconductor device 10 and the control chip 170 in the Y direction. In the example of FIG. 11 , the drive chip 160 is disposed closer to the control chip 170 than the nitride semiconductor device 10 in the Y direction. In a plan view, the nitride semiconductor device 10 is disposed so that its longitudinal direction coincides with the longitudinal direction of the support substrate 110 and its lateral direction coincides with the lateral direction of the support substrate 110. As shown in FIG. 14, the nitride semiconductor device 10 is disposed so that the sealing surface 60S faces the support substrate surface 110S.

[0142] 11, the support substrate 110 includes a first connection wiring 121 and a second connection wiring 122 provided on the support substrate 110. Both the first connection wiring 121 and the second connection wiring 122 can be said to be provided on the support substrate surface 110S.

[0143] The first connection wiring 121 electrically connects the driving chip 160 to the nitride semiconductor device 10. The second connection wiring 122 electrically connects the control chip 170 to the driving chip 160. For example, a plurality of first connection wirings 121 and a plurality of second connection wirings 122 are provided.

[0144] 12, the plurality of first connection wirings 121 include gate connection wirings 121A and output connection wirings 121B. The gate connection wirings 121A are wirings for individually and electrically connecting the drive chip 160 to the plurality of first gate wiring layers 54 and the plurality of second gate wiring layers 55 of the nitride semiconductor device 10. A plurality of gate connection wirings 121A (six in this embodiment) are provided in accordance with the total number of the first gate wiring layers 54 and the second gate wiring layers 55. The output connection wirings 121B are wirings for individually and electrically connecting the drive chip 160 to the plurality of connection wiring layers 51 of the nitride semiconductor device 10. A plurality of output connection wirings 121B (three in this embodiment) are provided in accordance with the number of connection wiring layers 51.

[0145] 13, the semiconductor module 100 includes a plurality of (two in this embodiment) drive terminals 141 and 142, a plurality of (three in this embodiment) output terminals 143 to 145, and a plurality of (three in this embodiment) boot terminals 146 to 148. The semiconductor module 100 also includes a plurality of (twelve in this embodiment) control terminals 150. The drive terminals 141 and 142, the output terminals 143 to 145, the boot terminals 146 to 148, and the control terminal 150 are formed on the rear surface 110R of the support substrate.

[0146] The driving terminals 141, 142 are terminals for supplying current to the nitride semiconductor device 10, and are arranged on both sides of the nitride semiconductor device 10 in the Y direction in a plan view. Each of the driving terminals 141, 142 is formed in a strip shape extending in the X direction in a plan view. In one example, the length dimension (size in the X direction) of the driving terminals 141, 142 is greater than the size of the nitride semiconductor device 10 in the X direction.

[0147] The driving terminal 141 is electrically connected to the drain wiring layer 53 of the GaN chips 20A, 20C, and 20E of the nitride semiconductor device 10. The driving terminal 141 is provided on one of both Y-direction end portions of the support substrate rear surface 110R, which end portion is closer to the fourth support substrate side surface 110D.

[0148] The driving terminal 142 is electrically connected to the source wiring layer 52 of the GaN chips 20B, 20D, and 20F of the nitride semiconductor device 10. The driving terminal 142 is disposed between the nitride semiconductor device 10 and the driving chip 160 in the Y direction in a plan view.

[0149] 13, the output terminals 143 to 145 are terminals for outputting current from the nitride semiconductor device 10, and are arranged between the drive terminals 141 and 142 in the Y direction in a plan view. The output terminals 143 to 145 can also be said to be arranged at positions overlapping the nitride semiconductor device 10 in a plan view. The output terminals 143 to 145 are arranged aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0150] The output terminal 143 is an output terminal of the GaN chips 20A, 20B (see FIG. 12), and is arranged at a position overlapping with the connection wiring layer 51 corresponding to the GaN chips 20A, 20B. The output terminal 143 is electrically connected to the connection wiring layer 51 corresponding to the GaN chips 20A, 20B.

[0151] The output terminal 144 is an output terminal of the GaN chips 20C, 20D (see FIG. 12), and is arranged at a position overlapping with the connection wiring layer 51 corresponding to the GaN chips 20C, 20D. The output terminal 144 is electrically connected to the connection wiring layer 51 corresponding to the GaN chips 20C, 20D.

[0152] The output terminal 145 is an output terminal of the GaN chips 20E, 20F (see FIG. 12), and is arranged at a position overlapping with the connection wiring layer 51 corresponding to the GaN chips 20E, 20F. The output terminal 145 is electrically connected to the connection wiring layer 51 corresponding to the GaN chips 20E, 20F.

[0153] The boot terminals 146 to 148 are terminals that are electrically connected to boot diodes BD (see FIG. 15) of a bootstrap circuit provided in the drive chip 160. In a plan view, the boot terminals 146 to 148 are arranged closer to the drive terminal 142 (drive chip 160) than the output terminals 143 to 145. The boot terminals 146 to 148 are arranged aligned with each other in the Y direction and spaced apart from each other in the X direction. When viewed from the Y direction, the boot terminals 146 to 148 are arranged offset from the output terminals 143 to 145.

[0154] The control terminals 150 are terminals electrically connected to the control chip 170. The control terminals 150 are provided at one of both ends in the Y direction of the back surface 110R of the support substrate, which is closer to the third support substrate side surface 110C. In a plan view, the control terminals 150 are arranged closer to the third support substrate side surface 110C than the control chip 170. The control terminals 150 are arranged aligned with each other in the Y direction and spaced apart from each other in the X direction.

[0155] 11 and 12, the semiconductor module 100 includes a drive wiring 123, a control wiring 124, a boot wiring 125, a first terminal wiring 126, and a second terminal wiring 127. Each of the drive wiring 123, the control wiring 124, the boot wiring 125, the first terminal wiring 126, and the second terminal wiring 127 is provided on the support substrate surface 110S.

[0156] The semiconductor module 100 also includes a drive through wiring 131, a control through wiring 132, a boot through wiring 133, a first terminal through wiring 134, a second terminal through wiring 135, and an output through wiring 136. Each of the drive through wiring 131, the control through wiring 132, the boot through wiring 133, the first terminal through wiring 134, the second terminal through wiring 135, and the output through wiring 136 is a wiring that penetrates the support substrate 110 in the Z direction. An example of each of the control through wiring 132, the boot through wiring 133, the first terminal through wiring 134, the second terminal through wiring 135, and the output through wiring 136 is a via.

[0157] The drive wiring 123 is a wiring electrically connected to the nitride semiconductor device 10. The drive wiring 123 includes a first drive wiring 123A and a second drive wiring 123B. The first drive wiring 123A is a wiring for electrically connecting the nitride semiconductor device 10 and the drive terminal 141. A plurality of first drive wirings 123A (three in the first embodiment) are provided. The plurality of first drive wirings 123A are individually and electrically connected to the drain wiring layers 53 of the GaN chips 20A, 20C, and 20E. The plurality of first drive wirings 123A includes portions that overlap with the drive terminal 141 in a plan view.

[0158] The second drive wiring 123B is a wiring for electrically connecting the nitride semiconductor device 10 and the drive terminal 142. A plurality of second drive wirings 123B (three in the first embodiment) are provided. The plurality of second drive wirings 123B are individually and electrically connected to the source wiring layers 52 of the GaN chips 20B, 20D, and 20F. The plurality of second drive wirings 123B includes portions that overlap with the drive terminal 142 in a plan view.

[0159] The driving through wiring 131 is a wiring that electrically connects the driving wiring 123 to the driving terminals 141 and 142. The driving through wiring 131 includes a first driving through wiring 131A and a second driving through wiring 131B.

[0160] The first drive through wiring 131A is a wiring that electrically connects the first drive wiring 123A and the drive terminal 141. A plurality of first drive through wirings 131A (three in the first embodiment) are provided in accordance with the number of first drive wirings 123A. The first drive through wiring 131A is provided at a position that overlaps both the first drive wiring 123A and the drive terminal 141 in a plan view.

[0161] The second drive through wiring 131B is a wiring that electrically connects the second drive wiring 123B and the drive terminal 142. A plurality of second drive through wirings 131B (three in the first embodiment) are provided in accordance with the number of second drive wirings 123B. The second drive through wiring 131B is provided at a position that overlaps both the second drive wiring 123B and the drive terminal 142 in a plan view.

[0162] 11, the control wiring 124 is a wiring electrically connected to the control chip 170, and a plurality of control wirings 124 (12 in this embodiment) are provided. The control wirings 124 are provided, for example, according to the number of control terminals 150. The plurality of control wirings 124 include portions that individually overlap with the plurality of control terminals 150 in a plan view.

[0163] The control through wiring 132 is a wiring that electrically connects the plurality of control wirings 124 and the plurality of control terminals 150 individually. A plurality of control through wirings 132 (12 in the first embodiment) are provided in accordance with the number of control terminals 150. The control through wirings 132 are provided at positions that overlap both the plurality of control terminals 150 and the control wirings 124 that correspond to the plurality of control terminals 150 in a plan view.

[0164] The boot wiring 125 is a wiring for electrically connecting the drive chip 160 and the boot terminals 146 to 148. A plurality of boot wirings 125 (three in the first embodiment) are provided in accordance with the number of the boot terminals 146 to 148.

[0165] 12, the boot through wiring 133 is a wiring that electrically connects the plurality of boot wirings 125 to the boot terminals 146-148 individually. A plurality of boot through wirings 133 (three in the first embodiment) are provided in accordance with the number of boot wirings 125. The boot through wirings 133 are provided at positions that overlap both the boot terminals 146-148 and the boot wirings 125 corresponding to the boot terminals 146-148 in plan view.

[0166] 11, the first terminal wiring 126 is a wiring for electrically connecting the driving chip 160 and the driving terminal 141. The first terminal wiring 126 includes a portion that overlaps with the driving terminal 141 in a plan view.

[0167] 12, the first terminal through wiring 134 is a wiring that electrically connects the first terminal wiring 126 and the driving terminal 141. The first terminal through wiring 134 is provided at a position that overlaps both the first terminal wiring 126 and the driving terminal 141 in a plan view.

[0168] 11, the second terminal wiring 127 is a wiring for electrically connecting the driving chip 160 and the driving terminal 142. The second terminal wiring 127 includes a portion that overlaps with the driving terminal 142 in a plan view.

[0169] 12, the second terminal through wiring 135 is a wiring that electrically connects the second terminal wiring 127 and the driving terminal 142. The second terminal through wiring 135 is provided at a position that overlaps both the second terminal wiring 127 and the driving terminal 142 in a plan view.

[0170] 14, the external wiring layer 50 of the nitride semiconductor device 10 is electrically connected to the first connection wiring 121 and the drive wiring 123 individually by a conductive bonding material SD such as solder paste. Therefore, the nitride semiconductor device 10 is disposed spaced apart from the support substrate surface 110S in the Z direction.

[0171] The output through wiring 136 is wiring that electrically connects the plurality of output connection wirings 121B and the output terminals 143 to 145 individually. A plurality of output through wirings 136 (three in the first embodiment) are provided in accordance with the number of output connection wirings 121B. The output through wirings 136 are provided at positions that overlap both the output terminals 143 to 145 and the output connection wirings 121B corresponding to the output terminals 143 to 145 in plan view.

[0172] The second sealing resin 180 is provided on the support substrate 110. The second sealing resin 180 is formed in the shape of a rectangular plate. Four sealing side surfaces of the second sealing resin 180 are flush with the first to fourth support substrate side surfaces 110A to 110D of the support substrate 110. The second sealing resin 180 is filled in the portion between the nitride semiconductor device 10 and the support substrate surface 110S in the Z direction. This insulates, for example, the external wiring layer 50 of the nitride semiconductor device 10 from the boot wiring 125. Furthermore, for example, the external wiring layer 50 of the nitride semiconductor device 10 is insulated from the first connection wiring 121 and the portion of the drive wiring 123 to which the conductive bonding material SD is not applied.

[0173] [Circuit configuration of semiconductor module] Next, a description will be given of the circuit configuration of the semiconductor module 100. Fig. 15 shows a schematic circuit configuration relating to the GaN chips 20A and 20B of the nitride semiconductor device 10 in the semiconductor module 100. Note that the circuit configuration relating to the GaN chips 20C and 20D and the circuit configuration relating to the GaN chips 20E and 20F in the semiconductor module 100 are similar to the circuit configuration relating to the GaN chips 20A and 20B, and therefore description thereof will be omitted.

[0174] The driver chip 160 includes a driver circuit GD1 that drives the GaN transistor 22 of the GaN chip 20A, a driver circuit GD2 that drives the GaN transistor 22 of the GaN chip 20B, and a boot diode BD and resistor R1 of a bootstrap circuit. The bootstrap circuit includes a boot capacitor BC provided outside the semiconductor module 100.

[0175] The boot capacitor BC is electrically connected to the boot terminal 146 and the output terminal 143. More specifically, a first electrode of the boot capacitor BC is electrically connected to the boot terminal 146, and a second electrode of the boot capacitor BC is electrically connected to the output terminal 143. A cathode of a boot diode BD is electrically connected to the boot terminal 146. An anode of the boot diode BD is electrically connected to a first end of a resistor R1. A second end of the resistor R1 is electrically connected to a power supply terminal (VCC) assigned to one of the plurality of control terminals 150. The drive terminal 141 is electrically connected to a drive power supply DV provided outside the semiconductor module 100. A capacitor C1 is connected in parallel to the drive power supply DV in a conductive path connecting the drive terminal 141 and the positive electrode of the drive power supply DV. The negative electrode of the drive power supply DV and the capacitor C1 are both grounded. The drive terminal 142 is also grounded via a resistor R2. The control terminal 150 (power supply terminal VCC) is electrically connected to a control power supply CV provided outside the semiconductor module 100. A capacitor C2 is connected in parallel to the control power supply CV in the conductive path connecting the control terminal 150 and the positive electrode of the control power supply CV. The negative electrode of the control power supply CV and the capacitor C2 are both grounded.

[0176] The driver circuit GD1 is electrically connected to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20A. The driver circuit GD1 supplies a gate control signal for driving the GaN transistor 22 of the GaN chip 20A to the gate electrode 28. The low-potential side power supply terminal of the driver circuit GD1 is electrically connected to the source electrode 29 of the GaN transistor 22 of the GaN chip 20A. The high-potential side power supply terminal of the driver circuit GD1 is electrically connected to the boot terminal 146 and the cathode of the boot diode BD.

[0177] The driver circuit GD2 is electrically connected to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20B. The driver circuit GD2 supplies a gate control signal for driving the GaN transistor 22 of the GaN chip 20B to the gate electrode 28. The high-potential power supply terminal of the driver circuit GD2 is electrically connected to the second end of the resistor R1 and the control terminal 150 (power supply terminal VCC). In addition, the low-potential power supply terminal of the driver circuit GD2 is grounded.

[0178] A signal is input to the control chip 170 from outside the semiconductor module 100. Based on the input signal, the control chip 170 outputs a signal to the driver circuits GD1, GD2 to generate a gate control signal for the driver circuits GD1, GD2.

[0179] [Method of manufacturing a nitride semiconductor device] Next, an example of a method for manufacturing the nitride semiconductor device 10 will be described with reference to Figs. 16 to 45. Figs. 16 to 45 show exemplary manufacturing steps for the nitride semiconductor device 10. Figs. 16 to 24 show a schematic cross-sectional structure of the GaN transistor 22. Figs. 25 to 44 show schematic cross-sectional structures of the GaN chips 20A and 20B. Fig. 45 shows the planar structure of a portion of a wafer 821, which will be described later. Note that GaN chips 20C to 20F are similar to GaN chips 20A and 20B, and therefore description thereof will be omitted.

[0180] As shown in FIG. 16, the method for manufacturing the nitride semiconductor device 10 includes preparing a wafer 821. The wafer 821 is formed in a flat plate shape with the Z direction as its thickness direction. The wafer 821 has a wafer front surface 821S and a wafer back surface 821R (see FIG. 25) facing opposite sides in the Z direction. The wafer 821 constitutes the substrate 21. In practice, the wafer 821 is formed to a size that allows tens or hundreds of substrates 21 to be formed thereon. The wafer 821 is, for example, a Si wafer.

[0181] Wafer 821 includes, on the wafer surface 821S side, a plurality of chip formation regions 821A (see FIG. 25) in which GaN transistors 22 are formed. An example of a method for manufacturing GaN transistors 22 will be described below with reference to FIGS.

[0182] 16, a buffer layer 823 is formed on a wafer 821, and then an electron transit layer 824 is formed on the buffer layer 823. The buffer layer 823 and the electron transit layer 824 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0183] Although detailed illustration is omitted, in one example, the buffer layer 823 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the wafer 821 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in that order from the side closest to the AlN layer. The electron transit layer 824 formed on the buffer layer 823 may be a GaN layer.

[0184] 17, an electron supply layer 825 made of a nitride semiconductor is formed on the electron transit layer 824, and then a nitride semiconductor layer 827 is formed on the electron supply layer 825. The electron transit layer 824 and the nitride semiconductor layer 827 can be epitaxially grown using the MOCVD method.

[0185] The electron transit layer 824 may be a GaN layer, while the electron supply layer 825 may be an AlGaN layer. Therefore, the nitride semiconductor constituting the electron supply layer 825 has a larger band gap than the electron transit layer 824.

[0186] The nitride semiconductor layer 827 is made of a nitride semiconductor containing acceptor-type impurities. In one example, the nitride semiconductor layer 827 containing acceptor-type impurities can be formed by doping with Mg during growth of the nitride semiconductor layer 827. The nitride semiconductor layer 827 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 825. The nitride semiconductor layer 827 is a semiconductor layer that constitutes the gate layer 27 (see FIG. 6).

[0187] 18 and 19, a first insulating film 831 is formed. As shown in FIG. 18, the first insulating film 831 is formed on the nitride semiconductor layer 827 by, for example, low-pressure chemical vapor deposition (LPCVD). The first insulating film 831 is formed, for example, over the entire upper surface of the nitride semiconductor layer 827. The first insulating film 831 is an insulating film that constitutes the first insulating film 31 (see FIG. 6) and may be formed of, for example, at least one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the first insulating film 831 is formed of Si3N4.

[0188] Next, a resist mask 840 is formed on the first insulating film 831. The resist mask 840 includes an opening 840A that exposes a portion of the upper surface of the first insulating film 831. The opening 840A is formed by selectively removing the resist film using lithography.

[0189] 19, the first insulating film 831 exposed in the opening 840A is removed by etching using the resist mask 840. As a result, the opening 31A is formed in the first insulating film 831. For example, dry etching is used for the etching.

[0190] 20, an electrode layer 828 is formed, connected to the nitride semiconductor layer 827 through the opening 31A. The electrode layer 828 is an electrode layer that constitutes the gate electrode 28, and is, for example, a TiN layer. The electrode layer 828 is formed by, for example, a sputtering method. The electrode layer 828 fills the opening 31A and is formed over the entire upper surface of the first insulating film 831.

[0191] Subsequently, as shown in FIGS. 21 and 22, the nitride semiconductor layer 827, the first insulating film 831, and the electrode layer 828 are etched to form the gate layer 27, the first insulating film 31, and the gate electrode .

[0192] 21, a resist mask 841 is formed on the electrode layer 828. The resist mask 841 is formed on a portion of the upper surface of the electrode layer 828. Next, as shown in FIG. 22, the nitride semiconductor layer 827, the first insulating film 831, and the electrode layer 828 are removed by etching using the resist mask 841. As a result, the gate layer 27 is formed from the nitride semiconductor layer 827, the gate electrode 28 is formed from the electrode layer 828, and the first insulating film 31 is formed from the first insulating film 831. For example, dry etching is used for the etching.

[0193] 23, a second insulating film 832 is formed to cover the electron supply layer 825, the gate layer 27, the first insulating film 31, and the gate electrode 28. The second insulating film 832 is an insulating film that constitutes the second insulating film 32 and is formed of, for example, LPVCD. The second insulating film 832 may be formed of at least one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the second insulating film 832 is formed of Si3N4. That is, the second insulating film 832 is formed of the same material as the first insulating film 831. The second insulating film 832 may be formed of a different material from the first insulating film 831.

[0194] 24, a first opening 32A and a second opening 32B are formed through the second insulating film 832 to expose the electron supply layer 825. The first opening 32A and the second opening 32B are formed so that the gate layer 27 is located between the first opening 32A and the second opening 32B. The gate layer 27 may be located closer to the first opening 32A than the second opening 32B. The first opening 32A and the second opening 32B are formed by, for example, etching.

[0195] Subsequently, as shown in FIG. 24, the source electrode 29 and the drain electrode 30 (both see FIG. 6) are formed so as to be in contact with the electron supply layer 825. In this process, a metal layer 829 is first formed on the second insulating film 832. The metal layer 829 is formed over the entire upper surface of the second insulating film 832. The metal layer 829 fills the first opening 32A and the second opening 32B and is formed to contact the electron supply layer 825 through the first opening 32A and the second opening 32B. In one example, the metal layer 829 may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. Next, the metal layer 829 is selectively removed by lithography and etching. This forms the source electrode 29 and the drain electrode 30 shown in FIG. 6. Through the above processes, the GaN transistor 22 is formed.

[0196] 25, a third insulating film 833 is formed on the second insulating film 832 (see FIG. 24), then a wiring layer 834 is formed on the third insulating film 833, and then a fifth insulating film 839 is formed on the wiring layer 834. Next, the source pad 35, the drain pad 36, and the gate pad 37 (see FIG. 8) are formed on the fifth insulating film 839.

[0197] The third insulating film 833 is an insulating film that constitutes the third insulating film 33, and is formed by, for example, plasma CVD (Plasma Enhanced Chemical Vapor Deposition: PECVD). In one example, the third insulating film 833 is formed of SiO2. The third insulating film 833 is formed over the entire surface of the second insulating film 832.

[0198] Next, a fourth insulating film 834A is formed on the third insulating film 833. The fourth insulating film 834A is an insulating film that constitutes the fourth insulating film 34A and is formed, for example, by PECVD. In one example, the fourth insulating film 834A is formed of either SiN or SiO2. Next, a plurality of source wiring portions 34S, drain wiring portions 34D, and gate wiring portions 34G are provided on the fourth insulating film 834A. More specifically, the fourth insulating film 834A is selectively removed, for example, by etching, to form grooves for forming the source wiring portions 34S, drain wiring portions 34D, and gate wiring portions 34G. Then, the source wiring portions 34S, drain wiring portions 34D, and gate wiring portions 34G are formed so as to fill the respective grooves, for example, by electrolytic plating. In this manner, the wiring layer 834 is formed.

[0199] Next, a fifth insulating film 839 is formed on the wiring layer 834 by, for example, PECVD. The fifth insulating film 839 is formed, for example, over the entire upper surface of the wiring layer 834. In one example, the fifth insulating film 839 is formed of either SiN or SiO2. Next, the fifth insulating film 839 is selectively removed by, for example, etching, to form grooves for forming the source pad 35, the drain pad 36, and the gate pad 37. Then, the source pad 35, the drain pad 36, and the gate pad 37 are formed so as to fill each groove by, for example, electrolytic plating.

[0200] Next, as shown in FIG. 26, portions between adjacent GaN transistors 22 above the wafer 821 are removed by, for example, etching. As a result, a fifth insulating film 39 is formed from a fifth insulating film 839, a fourth insulating film 34A is formed from a fourth insulating film 834A, thereby forming an interconnect layer 34 from an interconnect layer 834, and a third insulating film 33 from a third insulating film 833. In addition, a second insulating film 32 is formed from a second insulating film 832 shown in FIG. 24, an electron supply layer 25 (see FIG. 6) is formed from an electron supply layer 825, an electron transit layer 24 (see FIG. 6) is formed from an electron transit layer 824, and a buffer layer 23 (see FIG. 6) is formed from a buffer layer 823. In this way, a plurality of chip formation regions 821A in which GaN transistors 22 are formed are formed on the wafer 821. Through the above steps, a wafer 821 including a plurality of chip formation regions 821A in which GaN transistors 22 are formed is prepared on the wafer surface 821S side of the wafer 821.

[0201] As shown in FIGS. 27 to 29, the method for manufacturing the nitride semiconductor device 10 includes forming a groove 821B between adjacent chip formation regions 821A. 27, a dry film resist 842 is formed on the fifth insulating film 39, the source pad 35, the drain pad 36, and the gate pad 37. The dry film resist 842 also covers the side surfaces of the fifth insulating film 39, the side surfaces of the fourth insulating film 34A of the wiring layer 34, and the side surfaces of the third insulating film 33. The dry film resist 842 has an opening 842A formed therein that exposes the wafer 821. The opening 842A exposes a portion of the wafer 821 between adjacent chip formation regions 821A.

[0202] Next, as shown in FIG. 28, a portion of the wafer 821 in the thickness direction exposed from the opening 842A is removed by dry etching using a dry film resist 842. As a result, a groove 821B is formed in the wafer 821. This groove 821B is formed between adjacent chip formation regions 821A of the wafer 821 in a plan view. The groove 821B is formed so that its width dimension TB is smaller than the distance TA between the wiring layers 34 of adjacent chip formation regions 821A. In other words, forming the groove 821B between adjacent chip formation regions 821A means forming a groove 821B with a width dimension TB smaller than the distance TA between the wiring layers 34 of adjacent chip formation regions 821A. Thereafter, as shown in FIG. 29, the dry film resist 842 is removed.

[0203] 30 to 34, the method for manufacturing the nitride semiconductor device 10 includes forming the side shield portions 71 of the first to sixth electromagnetic wave shields 70A to 70D. The method for manufacturing the nitride semiconductor device 10 also includes forming posts 40 on the wafer surface 821S side. The posts 40 are formed on the source pad 35, drain pad 36, and gate pad 37 (see FIG. 8) of each GaN transistor 22 on the wafer surface 821S side.

[0204] 30, a seed layer 900 is formed on each of the chip formation region 821A, the exposed portion of the wafer surface 821S, and the inner surface of the groove 821B. The seed layer 900 is, for example, a Ti / Cu layer. The seed layer 900 constitutes part of the seed layer 71A of the side shield part 71 (see FIG. 7) and the post 40. The seed layer 900 is an example of a metal layer formed on the side and bottom surfaces of the groove 821B.

[0205] 31, a dry film resist 843 is formed on the portion of the seed layer 900 that covers the chip surfaces 20S of the GaN chips 20A and 20B. The dry film resist 843 has openings 843A that open between adjacent chip formation regions 821A, including the grooves 821B.

[0206] Next, a plating layer 910 is formed on the seed layer 900 exposed from the dry film resist 843. The plating layer 910 is formed, for example, by electrolytic plating using the exposed seed layer 900 as a conductive path. The plating layer 910 is made of, for example, a material containing Cu. In one example, the plating layer 910 is a Cu layer. Then, the dry film resist 843 is removed. The plating layer 910 forms the plating layer 71B of the side shield part 71. The plating layer 910 is an example of a metal layer formed on the side and bottom surfaces of the groove 821B.

[0207] Next, as shown in FIG. 32, a dry film resist 844 is formed on the seed layer 900. The dry film resist 844 is formed so as to fill the gap between adjacent chip formation regions 821A, including the grooves 821B. In the example of FIG. 32, the dry film resist 844 has an opening 844A that partially exposes a region of the seed layer 900 corresponding to the drain pad 36 of the GaN chip 20A and an opening 844B that partially exposes a region of the seed layer 900 corresponding to the source pad 35 of the GaN chip 20B. Although not shown, the dry film resist 843 has openings that partially expose regions of the seed layer 900 corresponding to the gate pads 37 of the GaN chips 20A and 20B. The dry film resist 843 also has an opening that partially exposes a region of the seed layer 900 corresponding to the source pad 35 of the GaN chip 20A and an opening that partially exposes a region of the seed layer 900 corresponding to the drain pad 36 of the GaN chip 20B.

[0208] 33, a plating layer 40B is formed to fill the openings 844A and 844B of the dry film resist 844. The plating layer 40B is formed by, for example, electrolytic plating using the seed layer 900 as a conductive path. The plating layer 40B is, for example, a Cu layer. Next, as shown in FIG. 34, the dry film resist 844 is removed.

[0209] 35, the portion of the seed layer 900 exposed from the plating layer 40B is removed. Through the above steps, a post 40 is formed in each chip formation region 821A. The post 40 is composed of the seed layer 40A, which is the portion of the seed layer 900 (see FIG. 34) covered with the plating layer 40B, and the plating layer 40B on the seed layer 40A. Furthermore, the portion of the seed layer 900 that constitutes the side shield part 71 is separated from the post 40. Here, as shown in FIG. 35, the portion that constitutes the side shield part 71 connects the side shield parts 71 of the first to sixth electromagnetic wave shields 70A to 70F within the groove 821B.

[0210] 35, a source post 41 is formed on the source pad 35 of the GaN chip 20A, and a drain post 42 is formed on the drain pad 36 of the GaN chip 20B. In other words, forming the post 40 includes forming the source post 41 on the source pad 35 of one of two adjacent chip formation regions 821A, and forming the drain post 42 on the drain pad 36 of the other.

[0211] As shown in FIGS. 36 and 37, the method for manufacturing the nitride semiconductor device 10 includes forming, on the wafer 821, a resin layer 860 that fills the grooves 821B and from which the top surfaces of the posts 40 are exposed.

[0212] As shown in FIG. 36, the resin layer 860 is formed so as to fill the grooves 821B and the spaces between adjacent chip formation regions 821A and to cover the posts 40. In the example of FIG. 36, the resin layer 860 covers both the upper surfaces 41S of the source posts 41 and the upper surfaces 42S of the drain posts 42. The resin layer 860 is formed by transfer molding or compression molding. The resin layer 860 is, for example, a black epoxy resin. The resin layer 860 is a layer that constitutes the first sealing resin 60. Here, the portion of the resin layer 860 that fills the grooves 821B corresponds to the substrate sealing layer 62 (see FIG. 7), and the portion that fills the spaces between adjacent chip formation regions 821A corresponds to the wiring sealing layer 61 (see FIG. 7).

[0213] Next, as shown in Fig. 37, both the resin layer 860 and the posts 40 are ground to expose the posts 40 from an upper surface 860S of the resin layer 860. As a result, the thicknesses of the resin layer 860 and the posts 40 in Fig. 37 are thinner than the thicknesses of the resin layer 860 and the posts 40 in Fig. 36. In addition, the upper surface 860S of the resin layer 860 corresponds to the sealing surface 60S of the first sealing resin 60 (see Fig. 7).

[0214] 37, the upper surface 860S of the resin layer 860 is flush with the upper surface 41S of the source post 41 of the GaN chip 20A and the upper surface 42S of the drain post 42 of the GaN chip 20B. Although not shown, the upper surface 860S of the resin layer 860 is flush with the upper surface 42S of the drain post 42 of the GaN chip 20A and the upper surface 43S of the gate post 43, and the upper surface 41S of the source post 41 of the GaN chip 20B and the upper surface 43S of the gate post 43. In this way, the upper surface 860S of the resin layer 860 is flush with the upper surfaces of the posts 40.

[0215] In this way, forming a resin layer 860 on the wafer 821 with the upper surfaces of the posts 40 exposed includes forming the resin layer 860 so that it fills the grooves 821B and the spaces between adjacent chip formation regions 821A and covers the posts 40, and exposing the posts 40 from the upper surface 860S of the resin layer 860 by grinding both the upper surface 860S of the resin layer 860 and the upper surfaces of the posts 40.

[0216] As shown in FIGS. 38 to 41, the method for manufacturing the nitride semiconductor device 10 includes forming an external wiring layer 50. As shown in FIGS. 38, a seed layer 50A is formed on an upper surface 860S of the resin layer 860 and the upper surfaces of the posts 40. The seed layer 50A is, for example, a Ti layer.

[0217] Next, as shown in Fig. 39, a dry film resist 845 is formed on the seed layer 50A. In the example of Fig. 39, the dry film resist 845 has openings 845A that expose the seed layer 50A in the portions where the connection wiring layer 51 (see Fig. 7) will be formed. Although not shown, the dry film resist 845 has openings that expose the seed layer 50A in the portions where the drain wiring layer 53, the source wiring layer 52, the first gate wiring layer 54, and the second gate wiring layer 55 (see Figs. 7 and 8) will be formed.

[0218] 40, a plating layer 50B is formed to fill the openings 845A of the dry film resist 845. The plating layer 50B is formed, for example, by electrolytic plating using the seed layer 50A as a conductive path. The plating layer 50B is, for example, a Cu layer. Next, the dry film resist 845 is removed.

[0219] 41, the portion of the seed layer 50A exposed from the plating layer 50B is removed. In the example of FIG. 41, a connection wiring layer 51 is formed. In this manner, the method for manufacturing the nitride semiconductor device 10 includes forming, on the upper surface 860S of the resin layer 860, the connection wiring layer 51 that electrically connects the source post 41 and the drain post 42 to each other. Through the above steps, the external wiring layer 50 is formed.

[0220] 42, the method for manufacturing the nitride semiconductor device 10 includes forming the substrate 21. The method for manufacturing the nitride semiconductor device 10 also includes forming the side shield portions 71 of the first to sixth electromagnetic wave shields 70A to 70F.

[0221] In this step, wafer 821 is ground from wafer back surface 821R to expose resin layer 860, seed layer 71A (900), and plating layer 71B (910) in groove 821B. This electrically separates wafer 821 for each chip formation region 821A to form substrate 21 on which GaN transistors 22 are formed, and side shield parts 71 including seed layer 71A and plating layer 71B are also formed.

[0222] In the example of FIG. 42, the portion of the resin layer 860 that fills the groove 821B (substrate sealing layer 62) is also partially ground in the thickness direction. As a result, the wafer 821 is divided into each chip forming region 821A. As a result, the substrates 21 are formed, and the seed layer 71A and plating layer 71B provided on the side surfaces of the grooves 821B are exposed, thereby separating the side shield parts 71. That is, the side shield parts 71 are formed for each chip forming region 821A. In this case, the wafer back surface 821R constitutes the substrate back surface 21R of the substrate 21. Since the resin layer 860 is interposed between adjacent substrates 21, the substrates 21 are insulated for each chip forming region 821A. Furthermore, both the back surface 860R of the resin layer 860 and the wafer back surface 821R (substrate back surface 21R of the substrate 21) have grinding marks. Furthermore, the back surface 860R of the resin layer 860 and the wafer back surface 821R (substrate back surface 21R of the substrate 21) are flush with each other. Therefore, the substrate back surface 21R of the substrate 21 is exposed from the back surface 860R of the resin layer 860. Furthermore, the back surface of the side shield part 71 is flush with the back surface 860R of the resin layer 860 and the substrate back surface 21R of the substrate 21. Therefore, the back surface of the side shield part 71 is exposed from the back surface 860R of the resin layer 860. In other words, the seed layer 71A and the plating layer 71B are exposed from the back surface 860R of the resin layer 860.

[0223] As shown in FIG. 43, the method for manufacturing the nitride semiconductor device 10 includes forming the rear surface shield portions 72 of the first to sixth electromagnetic wave shields 70A to 70F. In one example, a back-side metal layer is formed on the wafer back surface 821R (substrate back surface 21R of the substrate 21) after the wafer back surface 821R has been ground. The back-side metal layer is formed by sputtering on the substrate back surface 21R of the substrate 21 and the back surface of the side shield part 71. In other words, the back-side metal layer is a sputtered film 72A. Therefore, the back surface shield part 72 is formed of the sputtered film 72A. This sputtered film 72A is, for example, a Cu film. In this way, the back surface shield part 72 is connected to the side shield part 71.

[0224] As shown in Fig. 44, the method for manufacturing the nitride semiconductor device 10 includes forming a plating layer 50C on the surface of the external wiring layer 50. The plating layer 50C is formed by, for example, electroless plating. In the example of Fig. 44, the plating layer 50C is formed on the upper surface and side surfaces of the connection wiring layer 51. As an example, the plating layer 50C may be a layered structure of nickel (Ni), palladium (Pd), and Au, or a layered structure of Ni / Au.

[0225] 45, the manufacturing method for the nitride semiconductor device 10 includes cutting the resin layer 860 to separate the nitride semiconductor device 10 into individual pieces so as to include a plurality (six in the example of FIG. 45) of chip formation regions 821A in which the source posts 41 and the drain posts 42 are electrically connected by the connection wiring layer 51. The separation of the nitride semiconductor device 10 is performed after the formation of the connection wiring layer 51 (after the step of FIG. 44).

[0226] As shown in Fig. 45, a plurality of nitride semiconductor devices 10 are formed on a wafer 821. In one example, a dicing blade is used to cut the resin layer 860 along cutting lines CL shown in Fig. 45. This results in individual nitride semiconductor devices 10 including the GaN chips 20A to 20F (see Fig. 2). Through the above steps, the nitride semiconductor devices 10 are manufactured.

[0227] [Operation of the first embodiment] The operation of the nitride semiconductor device 10 of the first embodiment will be described. The closer the multiple chip formation regions 821A are located to each other in the wafer 821, the smaller the variation in the characteristics (gate threshold voltage, drain-source current) of the GaN transistors 22 in the chip formation regions 821A. In the method for manufacturing the nitride semiconductor device 10 in the first embodiment, the GaN chips 20A-20F are formed by adjacent chip formation regions 821A in the wafer 821. This makes it possible to reduce the variation in the characteristics of the GaN transistors 22 in the GaN chips 20A-20F of the nitride semiconductor device 10.

[0228] On the other hand, since the GaN chips 20A to 20F are located close to each other, electromagnetic waves generated in each of the GaN chips 20A to 20F may affect adjacent GaN chips among the GaN chips 20A to 20F.

[0229] In this regard, in the first embodiment, an electromagnetic wave shield 70 is provided between adjacent GaN chips among the GaN chips 20A to 20F. As a result, electromagnetic waves generated toward adjacent GaN chips among the GaN chips 20A to 20F are blocked by the electromagnetic wave shield 70. Therefore, it is possible to prevent electromagnetic waves generated in each of the GaN chips 20A to 20F from affecting adjacent GaN chips among the GaN chips 20A to 20F.

[0230] [Effects of the first embodiment] The nitride semiconductor device 10 and the semiconductor module 100 of the first embodiment provide the following advantages.

[0231] (1-1) The nitride semiconductor device 10 includes a first sealing resin 60, and a GaN chip 20A and a GaN chip 20B that are spaced apart from each other in the Y direction within the first sealing resin 60. An electromagnetic wave shield 70 is provided in the first sealing resin 60 between the GaN chip 20A and the GaN chip 20B in the Y direction.

[0232] This configuration can suppress both the electromagnetic waves generated in the GaN chip 20A from affecting the GaN chip 20B and the electromagnetic waves generated in the GaN chip 20B from affecting the GaN chip 20A. Therefore, the influence of the electromagnetic waves on the nitride semiconductor device 10 can be suppressed.

[0233] (1-2) Each of the GaN chip 20A and the second GaN chip 20B includes first to fourth chip side surfaces 20PA to 20PD. The first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A include a third chip side surface 20PC as a first opposing surface facing the GaN chip 20B in the Y direction. The first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20B include a fourth chip side surface 20PD as a second opposing surface facing the GaN chip 20A in the Y direction. The electromagnetic wave shield 70 includes a first electromagnetic wave shield 70A including a side shield portion 71 provided on the third chip side surface 20PC of the GaN chip 20A as the first opposing surface, and a second electromagnetic wave shield 70B including a side shield portion 71 provided on the fourth chip side surface 20PD of the GaN chip 20B as the second opposing surface.

[0234] According to this configuration, the side shield portion 71 of the first electromagnetic wave shield 70A can prevent electromagnetic waves from the GaN chip 20A from affecting the GaN chip 20B. Also, the side shield portion 71 of the second electromagnetic wave shield 70B can prevent electromagnetic waves from the GaN chip 20B from affecting the GaN chip 20A.

[0235] (1-3) Each of the GaN chip 20A and the GaN chip 20B includes first to fourth chip side surfaces 20PA to 20PD. The first electromagnetic wave shield 70A includes a side shield portion 71 provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A. The second electromagnetic wave shield 70B includes a side shield portion 71 provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20B.

[0236] According to this configuration, the side shield portion 71 of the first electromagnetic wave shield 70A can prevent electromagnetic waves generated from the GaN chip 20A from propagating to the periphery of the GaN chip 20A in a planar view. The side shield portion 71 of the second electromagnetic wave shield 70B can prevent electromagnetic waves generated from the GaN chip 20B from propagating to the periphery of the GaN chip 20B in a planar view.

[0237] (1-4) The side shield portion 71 of the first electromagnetic wave shield 70A is provided over the entire first to fourth chip side surfaces 20PA-20PD of the GaN chip 20A in the Z direction. The side shield portion 71 of the second electromagnetic wave shield 70B is provided over the entire first to fourth chip side surfaces 20PA-20PD of the GaN chip 20B in the Z direction. This configuration can enhance the effect of (1-3) above.

[0238] (1-5) The side shield portion 71 of the first electromagnetic wave shield 70A includes a protrusion 71P that protrudes upward in the Z direction beyond the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20A. The side shield portion 71 of the second electromagnetic wave shield 70B includes a protrusion 71P that protrudes upward in the Z direction beyond the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20B. This configuration can further enhance the effect of (1-3) above.

[0239] (1-6) The protrusion 71P of the first electromagnetic wave shield 70A is disposed outward from the chip surface 20S of the GaN chip 20A. The protrusion 71P of the second electromagnetic wave shield 70B is disposed outward from the chip surface 20S of the GaN chip 20B. The source pad 35, the drain pad 36, and the gate pad 37 are exposed on the chip surfaces 20S of the GaN chips 20A and 20B.

[0240] With this configuration, a distance can be secured between the first electromagnetic wave shield 70A and the source pad 35, drain pad 36, and gate pad 37 of the GaN chip 20A, thereby enabling favorable insulation between the first electromagnetic wave shield 70A and the source pad 35, drain pad 36, and gate pad 37 of the GaN chip 20A. A distance can be secured between the second electromagnetic wave shield 70B and the source pad 35, drain pad 36, and gate pad 37 of the GaN chip 20B, thereby enabling favorable insulation between the second electromagnetic wave shield 70B and the source pad 35, drain pad 36, and gate pad 37 of the GaN chip 20B.

[0241] (1-7) The side shield portion 71 of the first electromagnetic wave shield 70A is made of a metal layer. The side shield portion 71 of the second electromagnetic wave shield 70B is made of a metal layer.

[0242] With this configuration, both the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B can be made thinner than when both are made of, for example, metal plates. Therefore, even if the distance between the GaN chip 20A and the GaN chip 20B is small, both the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B can be disposed between the GaN chip 20A and the GaN chip 20B.

[0243] (1-8) The thickness of each of the side shield portions 71 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B is 1 μm or more. This configuration can prevent a decrease in the effectiveness of the side shield portion 71 of the first electromagnetic wave shield 70A in blocking electromagnetic waves generated from the GaN chip 20A. It can also prevent a decrease in the effectiveness of the side shield portion 71 of the second electromagnetic wave shield 70B in blocking electromagnetic waves generated from the GaN chip 20B.

[0244] (1-9) Each of the GaN chip 20A and the GaN chip 20B includes a substrate 21 having a chip front surface 20S, a chip back surface 20R opposite the chip front surface 20S, a substrate front surface 21S, and a substrate back surface 21R opposite the substrate front surface 21S and constituting the chip back surface 20R. The first electromagnetic wave shield 70A includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20A. The second electromagnetic wave shield 70B includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20B.

[0245] According to this configuration, the rear surface shield portion 72 of the first electromagnetic wave shield 70A can prevent electromagnetic waves generated from the GaN chip 20A from propagating to the outside of the GaN chip 20A via the rear surface 21R of the substrate 21. The rear surface shield portion 72 of the second electromagnetic wave shield 70B can prevent electromagnetic waves generated from the GaN chip 20B from propagating to the outside of the GaN chip 20B via the rear surface 21R of the substrate 21.

[0246] (1-10) The rear surface shield portion 72 of the first electromagnetic wave shield 70A is provided over the entire substrate rear surface 21R of the substrate 21 of the GaN chip 20A. The rear surface shield portion 72 of the second electromagnetic wave shield 70B is provided over the entire substrate rear surface 21R of the substrate 21 of the GaN chip 20B. This configuration can enhance the effect of (1-9) above.

[0247] (1-11) The area of ​​the rear surface shield portion 72 of the first electromagnetic wave shield 70A is larger than the area of ​​the substrate rear surface 21R of the substrate 21 of the GaN chip 20A. The area of ​​the rear surface shield portion 72 of the second electromagnetic wave shield 70B is larger than the area of ​​the substrate rear surface 21R of the substrate 21 of the GaN chip 20B. This configuration can further enhance the effect of (1-9) above.

[0248] (1-12) The rear shield portion 72 of the first electromagnetic wave shield 70A is connected to the side shield portion 71. The rear shield portion 72 of the second electromagnetic wave shield 70B is connected to the side shield portion 71.

[0249] According to this configuration, first electromagnetic wave shield 70A can prevent electromagnetic waves generated from GaN chip 20A from propagating through first to fourth chip side surfaces 20PA-20PD and substrate back surface 21R of substrate 21. Therefore, electromagnetic waves from GaN chip 20A are less likely to propagate outside GaN chip 20A. Second electromagnetic wave shield 70B can prevent electromagnetic waves generated from GaN chip 20B from propagating through first to fourth chip side surfaces 20PA-20PD and substrate back surface 21R of substrate 21. Therefore, electromagnetic waves from GaN chip 20B are less likely to propagate outside GaN chip 20B.

[0250] (1-13) Each of the GaN chip 20A and the GaN chip 20B is provided with a GaN transistor 22. A rear shield part 72 provided on the substrate rear surface 21R of the substrate 21 of the GaN chip 20A is electrically connected to the source of the GaN transistor 22 of the GaN chip 20A. A rear shield part 72 provided on the substrate rear surface 21R of the substrate 21 of the GaN chip 20B is electrically connected to the source of the GaN transistor 22 of the GaN chip 20B.

[0251] According to this configuration, the first electromagnetic wave shield 70A can enhance the effect of suppressing the propagation of electromagnetic waves generated from the GaN chip 20A outside the GaN chip 20A. The second electromagnetic wave shield 70B can enhance the effect of suppressing the propagation of electromagnetic waves generated from the GaN chip 20B outside the GaN chip 20B.

[0252] (1-14) The thickness T7 of the rear surface shield portion 72 of each of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B is 1 μm or more. This configuration can suppress a decrease in the effectiveness of the back shield portion 72 of the first electromagnetic wave shield 70A in blocking electromagnetic waves generated from the GaN chip 20A. It can also suppress a decrease in the effectiveness of the back shield portion 72 of the second electromagnetic wave shield 70B in blocking electromagnetic waves generated from the GaN chip 20B.

[0253] (1-15) The shortest distance between the GaN chip 20A and the GaN chip 20B is smaller than both the thickness of the GaN chip 20A and the thickness of the GaN chip 20B. This configuration can reduce the size of the nitride semiconductor device 10 in plan view. On the other hand, although there is concern about the influence of electromagnetic waves from the GaN chips 20A, 20B when the GaN chips 20A, 20B are close to each other, the electromagnetic wave shield 70 provided between the GaN chips 20A, 20B can suppress the influence of electromagnetic waves from the GaN chips 20A, 20B.

[0254] (1-16) The shortest distance between the GaN chip 20A and the GaN chip 20B is smaller than the thickness of the substrate 21 of the GaN chips 20A and 20B. According to this configuration, the same effect as in (1-15) above can be obtained.

[0255] (1-17) The shortest distance between the GaN chip 20A and the GaN chip 20B is smaller than the thickness of the wiring layer 34 of the GaN chips 20A and 20B. According to this configuration, the same effect as in (1-15) above can be obtained.

[0256] (1-18) The shortest distance between the GaN chip 20A and the GaN chip 20B is smaller than the width of the posts 40 of the GaN chips 20A and 20B. This configuration provides the same effect as in (1-15) above.

[0257] (1-19) The shortest distance between the GaN chip 20A and the GaN chip 20B is greater than twice the thickness of the side shield portion 71 of the first electromagnetic wave shield 70A and the thickness of the side shield portion 71 of the second electromagnetic wave shield 70B.

[0258] According to this configuration, the side shield portion 71 of the first electromagnetic wave shield 70A and the side shield portion 71 of the second electromagnetic wave shield 70B provided between the GaN chip 20A and the GaN chip 20B can be arranged apart from each other. This allows the side shield portions 71 to be provided individually for the GaN chips 20A and 20B. Therefore, it is possible to prevent electromagnetic waves from the GaN chip 20A from propagating from the first to fourth chip side surfaces 20PA to 20PD to the outside of the GaN chip 20A. It is also possible to prevent electromagnetic waves from the GaN chip 20B from propagating from the first to fourth chip side surfaces 20PA to 20PD to the outside of the GaN chip 20B.

[0259] (1-20) The shortest distance between the GaN chip 20A and the GaN chip 20B is smaller than the width of the source pad 35, the width of the drain pad 36, and the width of the gate pad 37 of the GaN chips 20A and 20B. This configuration provides the same effect as in (1-15) above.

[0260] (1-21) The shortest distance between the GaN chip 20A and the GaN chip 20B is 10 μm or more and 50 μm or less. This configuration provides the same effect as in (1-15) above.

[0261] (1-22) The posts 40 include a source post 41 formed on the source pad 35 of the GaN chip 20B and a drain post 42 formed on the drain pad 36 of the GaN chip 20A. The nitride semiconductor device 10 includes a connection wiring layer 51. The connection wiring layer 51 is provided on the sealing surface 60S of the first sealing resin 60, and electrically connects the source post 41 and the drain post 42 to each other.

[0262] According to this configuration, the electrical connection configuration between the source post 41 and the drain post 42 using the connection wiring layer 51 can make the connection configuration thinner in the Z direction, compared to an electrical connection configuration between the source post 41 and the drain post 42 using wires, clips, etc. Therefore, compared to an electrical connection configuration between the source post 41 and the drain post 42 using wires, clips, etc., the height of the nitride semiconductor device 10 can be reduced.

[0263] (1-23) Each of the substrate rear surfaces 21R of the plurality of substrates 21 is exposed from the sealing rear surface 60R of the first sealing resin 60. According to this configuration, heat from the GaN transistor 22 is easily dissipated from the substrate 21 to the outside of the nitride semiconductor device 10 via the substrate back surface 21R. This improves the heat dissipation performance of the nitride semiconductor device 10. In addition, by providing the back surface shield part 72 on the substrate back surface 21R, the heat dissipation performance of the nitride semiconductor device 10 can be further improved.

[0264] (1-24) The substrate rear surface 21R and the sealing rear surface 60R have grinding marks. According to this configuration, the rear surface shield part 72 provided on the substrate rear surface 21R and the sealing rear surface 60R fits into the grinding marks, thereby improving the adhesion between the substrate rear surface 21R, the sealing rear surface 60R, and the rear surface shield part 72.

[0265] (1-25) The top surface 41S of the source post 41, the top surface 42S of the drain post 42, and the sealing surface 60S are flush with each other. This configuration makes it easier to form the connection wiring layer 51 that electrically connects the source post 41 and the drain post 42 on the sealing surface 60S.

[0266] (1-26) Each GaN transistor 22 includes a drain electrode 30, a source electrode 29, and a gate electrode 28, and a wiring layer 34 provided on the substrate 21 and electrically connecting the drain electrode 30, the source electrode 29, and the gate electrode 28 to a drain pad 36, a source pad 35, and a gate pad 37, respectively. A first sealing resin 60 covers the multiple wiring layers 34 and is provided so as to be interposed between the wiring layers 34 of each of the two GaN chips 20A, 20B adjacent to each other in the first direction (Y direction).

[0267] According to this configuration, the first sealing resin 60 interposed between the wiring layers 34 of the GaN chips 20A, 20B can improve the insulation performance of the GaN transistors 22 of the GaN chips 20A, 20B.

[0268] (1-27) The semiconductor module 100 includes a first connection wiring 121 provided on a support substrate 110 and electrically connecting the drive chip 160 and the nitride semiconductor device 10, and a second connection wiring 122 provided on the support substrate 110 and electrically connecting the control chip 170 and the drive chip 160.

[0269] According to this configuration, the nitride semiconductor device 10 and the driver chip 160 are electrically connected, and the control chip 170 and the driver chip 160 are electrically connected, inside the semiconductor module 100. Therefore, the conductive path between the nitride semiconductor device 10 and the driver chip 160 can be made shorter than when the nitride semiconductor device 10 and the driver chip 160 are electrically connected outside the semiconductor module 100. Furthermore, the conductive path between the driver chip 160 and the control chip 170 can be made shorter than when the driver chip 160 and the control chip 170 are electrically connected outside the semiconductor module 100.

[0270] (1-28) An electromagnetic wave shield 70 is provided between the nitride semiconductor device 10 and the driver chip 160. According to this configuration, the influence of electromagnetic waves generated from the nitride semiconductor device 10 on the driver chip 160 can be suppressed.

[0271] (1-29) A method for manufacturing nitride semiconductor device 10 includes preparing a wafer 821 having a wafer front surface 821S and a wafer back surface 821R opposite to wafer front surface 821S, and including a plurality of chip formation regions 821A in which GaN transistors 22 are formed on the side of wafer front surface 821S; forming grooves 821B between adjacent chip formation regions 821A; forming a metal layer on the side and bottom of grooves 821B; forming resin layer 860 to fill grooves 821B and cover wafer 821; and grinding wafer back surface 821R so that both resin layer 860 and the metal layer are exposed.

[0272] According to this configuration, the metal layer covering the side surfaces of adjacent chip formation regions 821A can be easily separated for each chip formation region 821A. Also, the wafer 821 can be easily separated for each chip formation region 821A.

[0273] (1-30) The method further includes forming a backside metal layer on the wafer backside 821R after the wafer backside 821R has been ground. This configuration allows the back surface side metal layer to be easily connected to the side shield part 71. Therefore, a chip in which the back surface side metal layer is connected to the side shield part 71 can be easily manufactured.

[0274] (1-31) The substrate 21 of the GaN chips 20A to 20F is formed of a common wafer 821. The GaN chips 20A to 20F are formed in adjacent chip formation regions 821A of the wafer 821.

[0275] According to this configuration, the GaN chips 20A to 20F can be arranged close to each other during the manufacture of the nitride semiconductor device 10. This makes it possible to reduce variations in the electrical characteristics of the GaN chips 20A to 20F and to reduce the size of the nitride semiconductor device 10.

[0276] Second Embodiment 46 to 49, a nitride semiconductor device 10 according to the second embodiment will be described. The nitride semiconductor device 10 according to the second embodiment differs from the nitride semiconductor device 10 according to the first embodiment mainly in that a driving chip 80 is added. Below, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0277] FIG. 46 schematically shows the planar structure of the nitride semiconductor device 10 of the second embodiment. In FIG. 46, part of the internal structure of the nitride semiconductor device 10 is indicated by a dashed line. FIG. 47 schematically shows the cross-sectional structure of the nitride semiconductor device 10 taken along line F47-F47 in FIG. 46. FIG. 48 shows an enlarged view of the cross-sectional structure of the nitride semiconductor device 10 of FIG. 47, including a driver chip 80 (described later) and its surrounding area. FIG. 49 schematically shows the backside structure of the nitride semiconductor device 10 of FIG. 46.

[0278] [Configuration of nitride semiconductor device] 46, the nitride semiconductor device 10 includes GaN chips 20A to 20D and a driver chip 80. The nitride semiconductor device 10 includes a first sealing resin 60 that seals the GaN chips 20A to 20D and the driver chip 80.

[0279] The configuration of the GaN chips 20A to 20D is the same as that of the first embodiment. The GaN chips 20A and 20B and the GaN chips 20C and 20D are arranged spaced apart from each other in the Y direction. The GaN chips 20A and 20C are arranged side by side in the X direction. The GaN chips 20B and 20D are arranged side by side in the X direction. The GaN chip 20A is arranged in a position facing the GaN chip 20B in the Y direction. The GaN chip 20C is arranged in a position facing the GaN chip 20D in the Y direction. Here, the GaN chip 20A is an example of a "first GaN chip," the GaN chip 20B is an example of a "second GaN chip," the GaN chip 20C is an example of a "third GaN chip," and the GaN chip 20D is an example of a "fourth GaN chip."

[0280] Each of the GaN chips 20A to 20D of the second embodiment differs from the GaN chips 20A to 20F of the first embodiment (see FIG. 2) mainly in the gate post 43. The gate post 43 of the second embodiment electrically connects two gate pads 37 spaced apart in the X direction. The gate posts 43 of the GaN chips 20A to 20D are arranged closer to the third sealing side surface 60C in the Y direction than the drain posts 42 of the GaN chips 20A to 20D. Each gate post 43 is generally U-shaped in plan view and opens toward the third sealing side surface 60C.

[0281] The gate posts 43 of the GaN chips 20B and 20D have a different shape in plan view from the gate posts 43 of the GaN chips 20A and 20B. More specifically, a first end of the gate post 43 of the GaN chip 20B, which is an end closer to the GaN chip 20D, is provided so as to avoid a source wiring layer 52, which will be described later, in plan view. In one example, the Y-direction dimension of the first end of the gate post 43 of the GaN chip 20B is smaller than the Y-direction dimension of a second end of the gate post 43 of the GaN chip 20B that is opposite the first end in the X-direction. Therefore, the first end of the gate post 43 is in partial contact with the gate pad 37 closer to the GaN chip 20D.

[0282] A first end portion of gate post 43 of GaN chip 20D, which is an end portion closer to GaN chip 20B, is provided so as to avoid source wiring layer 52, which will be described later, in a plan view. In one example, the dimension in the Y direction of first end portion of gate post 43 of GaN chip 20D is smaller than the dimension in the Y direction of second end portion of gate post 43 of GaN chip 20D, which is opposite to the first end portion in the X direction. Therefore, first end portion of gate post 43 is in partial contact with gate pad 37 closer to GaN chip 20B.

[0283] The nitride semiconductor device 10 includes an external wiring layer 50. The external wiring layer 50 is provided so as to be exposed from a sealing surface 60S of the first sealing resin 60. The external wiring layer 50 is a wiring layer that electrically connects the GaN chips 20A to 20D.

[0284] The external wiring layer 50 includes connection wiring layers 51A and 51B, a source wiring layer 52, a drain wiring layer 53, first gate wiring layers 54A and 54B, and second gate wiring layers 55A and 55B. The connection wiring layers 51A, 51B are disposed in the center of the first sealing resin 60 in the Y direction in plan view. The connection wiring layers 51A, 51B are arranged aligned with each other in the Y direction and spaced apart from each other in the X direction. Each of the connection wiring layers 51A, 51B has a rectangular shape in plan view. The connection wiring layers 51A, 51B have the same size and shape.

[0285] The connection wiring layer 51A connects the source post 41 of the GaN chip 20A and the drain post 42 of the GaN chip 20B. This electrically connects the source electrode 29 (see FIG. 6) of the GaN transistor 22 of the GaN chip 20A and the drain electrode 30 (see FIG. 6) of the GaN transistor 22 of the GaN chip 20B. The connection wiring layer 51A is in contact with the entire upper surface 41S of the source post 41 of the GaN chip 20A. The connection wiring layer 51A is in contact with the entire upper surface 42S of the drain post 42 of the GaN chip 20B. In one example, the X-direction dimension of the connection wiring layer 51A is larger than the X-direction dimension of the upper surface 41S of the source post 41 (upper surface 42S of the drain post 42) and smaller than the X-direction dimension of the source wiring portion 34S (drain wiring portion 34D).

[0286] The connection wiring layer 51B connects the source post 41 of the GaN chip 20C and the drain post 42 of the GaN chip 20D. This electrically connects the source electrode 29 of the GaN transistor 22 of the GaN chip 20C and the drain electrode 30 of the GaN transistor 22 of the GaN chip 20D. The connection wiring layer 51B is in contact with the entire upper surface 41S of the source post 41 of the GaN chip 20C. The connection wiring layer 51B is in contact with the entire upper surface 42S of the drain post 42 of the GaN chip 20D. In one example, the X-direction dimension of the connection wiring layer 51B is larger than the X-direction dimension of the upper surface 41S of the source post 41 (upper surface 42S of the drain post 42) and smaller than the X-direction dimension of the source wiring portion 34S (drain wiring portion 34D).

[0287] The drain wiring layer 53 is disposed at an end of the first sealing resin 60 closer to the fourth sealing side surface 60D in the Y direction. The drain wiring layer 53 has a strip shape extending in the X direction in a plan view. The drain wiring layer 53 connects the drain post 42 of the GaN chip 20A to the drain post 42 of the GaN chip 20C. This electrically connects the drain electrode 30 of the GaN transistor 22 of the GaN chip 20A to the drain electrode 30 of the GaN transistor 22 of the GaN chip 20C. The drain wiring layer 53 is in contact with, for example, the entire upper surface 42S of the drain post 42 of the GaN chip 20A and the entire upper surface 42S of the drain post 42 of the GaN chip 20C.

[0288] The source wiring layer 52 is disposed at an end of the first sealing resin 60 closer to the third sealing side surface 60C in the Y direction. The source wiring layer 52 has a strip shape extending in the X direction in a plan view. The source wiring layer 52 connects the source post 41 of the GaN chip 20B to the source post 41 of the GaN chip 20D. This electrically connects the source electrode 29 of the GaN transistor 22 of the GaN chip 20B to the source electrode 29 of the GaN transistor 22 of the GaN chip 20D. The source wiring layer 52 contacts, for example, the entire top surface 41S of the source post 41 of the GaN chip 20B and the entire top surface 41S of the source post 41 of the GaN chip 20D. The size and shape of the source wiring layer 52 may be the same as, for example, the drain wiring layer 53. The source wiring layer 52 is disposed so as to overlap, in a plan view, both the gate pad 37 of the GaN chip 20B closer to the GaN chip 20D and the gate pad 37 of the GaN chip 20D closer to the GaN chip 20B. These two gate pads 37 include portions that protrude in the Y direction closer to the fourth sealing side surface 60D than the source wiring layer 52 in plan view.

[0289] The first gate wiring layer 54A is disposed between the drain wiring layer 53 and the connection wiring layer 51A in the Y direction. The first gate wiring layer 54A is disposed at a position overlapping the gate post 43 of the GaN chip 20A in a planar view. The first gate wiring layer 54A is in contact with the gate post 43 of the GaN chip 20A. This electrically connects the first gate wiring layer 54A to the gate electrode 28 of the GaN chip 20A. The first gate wiring layer 54A has a strip shape extending in the X direction in a planar view. For example, the X direction dimension of the first gate wiring layer 54A is larger than the X direction dimension of the connection wiring layer 51A. For example, the Y direction dimension of the first gate wiring layer 54A is larger than the Y direction dimension of a portion of the gate post 43 that overlaps with the first gate wiring layer 54A in a planar view.

[0290] The first gate wiring layer 54B is disposed between the drain wiring layer 53 and the connection wiring layer 51B in the Y direction. The first gate wiring layer 54B is disposed at a position overlapping the gate post 43 of the GaN chip 20C in a plan view. The first gate wiring layer 54B is in contact with the gate post 43 of the GaN chip 20C. This electrically connects the first gate wiring layer 54B to the gate electrode 28 of the GaN chip 20C. The first gate wiring layer 54B has a strip shape extending in the X direction in a plan view. For example, the X direction dimension of the first gate wiring layer 54B is larger than the X direction dimension of the connection wiring layer 51B. For example, the Y direction dimension of the first gate wiring layer 54B is larger than the Y direction dimension of the portion of the gate post 43 that overlaps with the first gate wiring layer 54B in a plan view. The size and shape of the first gate wiring layer 54B are, for example, the same as those of the first gate wiring layer 54A.

[0291] The second gate wiring layer 55A is disposed between the source wiring layer 52 and the connection wiring layer 51A in the Y direction. The second gate wiring layer 55A is disposed at a position overlapping the gate post 43 of the GaN chip 20B in a plan view. The second gate wiring layer 55A contacts the gate post 43 of the GaN chip 20B. This electrically connects the second gate wiring layer 55A to the gate electrode 28 of the GaN chip 20B. The second gate wiring layer 55A has a strip shape extending in the X direction in a plan view. For example, the X direction dimension of the second gate wiring layer 55A is larger than the X direction dimension of the connection wiring layer 51A. For example, the Y direction dimension of the second gate wiring layer 55A is larger than the Y direction dimension of the portion of the gate post 43 that overlaps with the second gate wiring layer 55A in a plan view. The size and shape of the second gate wiring layer 55A are the same as, for example, the first gate wiring layer 54A.

[0292] The second gate wiring layer 55B is disposed between the source wiring layer 52 and the connection wiring layer 51B in the Y direction. The second gate wiring layer 55B is disposed at a position overlapping the gate post 43 of the GaN chip 20D in a planar view. The second gate wiring layer 55B contacts the gate post 43 of the GaN chip 20D. This electrically connects the second gate wiring layer 55B to the gate electrode 28 of the GaN chip 20D. The second gate wiring layer 55B has a strip shape extending in the X direction in a planar view. For example, the X direction dimension of the second gate wiring layer 55B is larger than the X direction dimension of the connection wiring layer 51B. For example, the Y direction dimension of the second gate wiring layer 55B is larger than the Y direction dimension of the portion of the gate post 43 that overlaps with the second gate wiring layer 55B in a planar view. The size and shape of the second gate wiring layer 55B are, for example, the same as those of the second gate wiring layer 55A.

[0293] As shown in FIG. 46, the driver chip 80 is disposed between the GaN chip 20A and the GaN chip 20B in the Y direction and between the GaN chip 20C and the GaN chip 20D in the Y direction. The driver chip 80 is configured to drive the GaN transistors 22 (see FIG. 6) of the GaN chips 20A to 20D. The dimension of the driver chip 80 in the X direction is larger than the dimension of each of the GaN chips 20A to 20D in the X direction. The driver chip 80 is disposed so as to face both of the GaN chips 20A and 20C arranged in the X direction in the Y direction. The driver chip 80 is disposed so as to face both of the GaN chips 20B and 20D arranged in the X direction in the Y direction. The connection wiring layers 51A and 51B are disposed so as to straddle the driver chip 80 in a plan view.

[0294] The driver chip 80 has a rectangular shape with its longer sides oriented in the X direction and its shorter sides oriented in the Y direction in plan view. The driver chip 80 includes a chip front surface 80S, a chip back surface 80R opposite to the chip front surface 80S, and first to fourth chip side surfaces 80A to 80D connecting the chip front surface 80S and the chip back surface 80R.

[0295] The first chip side surface 80A and the second chip side surface 80B constitute both end surfaces of the driver chip 80 in the X direction. The first chip side surface 80A constitutes the side surface of the driver chip 80 closer to the first sealing side surface 60A of the first sealing resin 60. The second chip side surface 80B constitutes the side surface of the driver chip 80 closer to the second sealing side surface 60B of the first sealing resin 60. The third chip side surface 80C and the fourth chip side surface 80D constitute both end surfaces of the driver chip 80 in the Y direction. The third chip side surface 80C constitutes the side surface of the driver chip 80 closer to the GaN chips 20B and 20D. The fourth chip side surface 80D constitutes the side surface of the driver chip 80 closer to the GaN chips 20A and 20C. The third chip side surface 80C faces the GaN chips 20B and 20D. Therefore, the third chip side surface 80C is an example of a "sixth chip-facing surface." The fourth chip side surface 80D faces the GaN chips 20A and 20C. Therefore, the fourth chip side surface 80D is an example of a "fifth chip-facing surface."

[0296] The driver chip 80 includes a plurality of gate pads 81A to 81D, a source pad 82, a plurality of boot pads 83A and 83B, and a plurality of input pads 84A to 84E, 85A, and 85B. These pads 81A to 81D, 82, 83A, 83B, 84A to 84E, 85A, and 85B are exposed from the sealing surface 60S of the first sealing resin 60.

[0297] A plurality of gate pads 81A to 81D are provided corresponding to the GaN chips 20A to 20D. The gate pads 81B and 81D are disposed between the connection wiring layer 51A and the connection wiring layer 51B in the X direction.

[0298] In a plan view, the gate pads 81A and 81B are arranged at ends of the drive chip 80 closer to the GaN chips 20A and 20C in the Y direction. The gate pads 81A and 81B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The gate pad 81A is arranged adjacent to the GaN chip 20A in the Y direction. The gate pad 81A is arranged closer to the first sealing side surface 60A with respect to the connection wiring layer 51A and adjacent to the connection wiring layer 51A in the X direction. The gate pad 81B is arranged adjacent to the GaN chip 20C in the Y direction. The gate pad 81B is arranged closer to the first sealing side surface 60A with respect to the connection wiring layer 51B and adjacent to the connection wiring layer 51B in the X direction.

[0299] The gate pad 81A is a pad for electrical connection to the first gate wiring layer 54A. It can also be said that the gate pad 81A is a pad for electrical connection to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20A. It can also be said that the gate pad 81A is a pad for outputting a gate signal to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20A. The gate pad 81B is a pad for electrical connection to the first gate wiring layer 54B. It can also be said that the gate pad 81B is a pad for electrical connection to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20C. It can also be said that the gate pad 81B is a pad for outputting a gate signal to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20C.

[0300] In a plan view, the gate pads 81C and 81D are arranged at the end of the drive chip 80 closer to the GaN chips 20C and 20D in the Y direction. The gate pads 81C and 81D are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The gate pad 81C is arranged adjacent to the GaN chip 20B in the Y direction. The gate pad 81C is arranged closer to the first sealing side surface 60A with respect to the connection wiring layer 51A and adjacent to the connection wiring layer 51A in the X direction. Therefore, it can also be said that the gate pads 81A and 81C are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The gate pad 81D is arranged adjacent to the GaN chip 20D in the Y direction. The gate pad 81D is arranged closer to the first sealing side surface 60A with respect to the connection wiring layer 51B and adjacent to the connection wiring layer 51B in the X direction. Therefore, it can be said that the gate pads 81B and 81D are arranged at the same position in the X direction and spaced apart from each other in the Y direction.

[0301] The gate pad 81C is a pad for electrical connection to the second gate wiring layer 55A. It can also be said that the gate pad 81C is a pad for electrical connection to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20B. It can also be said that the gate pad 81C is a pad for outputting a gate signal to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20B. The gate pad 81D is a pad for electrical connection to the second gate wiring layer 55B. It can also be said that the gate pad 81D is a pad for electrical connection to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20D. It can also be said that the gate pad 81D is a pad for outputting a gate signal to the gate electrode 28 of the GaN transistor 22 of the GaN chip 20D.

[0302] In a plan view, the source pad 82 is arranged at an end of the drive chip 80 closer to the GaN chips 20B and 20D in the Y direction. The source pad 82 is arranged between the connection wiring layer 51A and the connection wiring layer 51B in the X direction. The source pad 82 is arranged at a position adjacent to the connection wiring layer 51A in the X direction. The source pad 82 is a pad for electrical connection to the source wiring layer 52. It can also be said that the source pad 82 is a pad for electrical connection to the source electrodes 29 of the GaN transistors 22 of the GaN chips 20B and 20D.

[0303] The boot pads 83A and 83B are arranged between the connection wiring layer 51A and the connection wiring layer 51B in the X direction. The boot pads 83A and 83B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In a plan view, the boot pad 83A is arranged at an end of the drive chip 80 closer to the GaN chips 20A and 20C in the Y direction. In a plan view, the boot pad 83B is arranged at an end of the drive chip 80 closer to the GaN chips 20B and 20D in the Y direction. The boot pad 83B is arranged at a position adjacent to the source pad 82 in the X direction. The boot pads 83A and 83B are electrically connected to an input pad 84E within the drive chip 80. An external capacitor is connected to the boot pads 83A and 83B.

[0304] The input pads 84A to 84E are distributed and arranged at both ends in the X direction of the driver chip 80. The input pads 84A to 84C are arranged at the end of the driver chip 80 closer to the first sealing side surface 60A. The input pads 84D and 84E are arranged at the end of the driver chip 80 closer to the second sealing side surface 60B.

[0305] Input pads 84A to 84C are arranged at the same position in the X direction and spaced apart from each other in the Y direction. Input pad 84A is arranged in a position adjacent to GaN chip 20A in the Y direction on drive chip 80 in a plan view. Input pad 84B is arranged in a position adjacent to GaN chip 20B in the Y direction on drive chip 80 in a plan view. Input pad 84C is arranged between input pad 84A and input pad 84B in the Y direction. For example, input pad 84C is arranged in a position adjacent to input pad 84B in the Y direction. For example, input pads 84A to 84C are pads to which control signals are input.

[0306] The input pads 84D and 84E are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The input pad 84D is arranged in a position adjacent to the GaN chip 20D in the Y direction on the drive chip 80 in a plan view. The input pad 84E is arranged in a position closer to the GaN chip 20C on the drive chip 80 in the Y direction. In one example, the input pad 84D is a pad for electrical connection to the drain wiring layer 53. The input pad 84D can also be said to be a pad for electrical connection to the drain electrodes 30 of the GaN transistors 22 of the GaN chips 20A and 20C. The input pad 84D is electrically connected to, for example, a regulator circuit (not shown) or a step-down converter (not shown) on the drive chip 80. In one example, the input pad 84E is a pad for connecting an external capacitor to the regulator circuit or the step-down converter.

[0307] The input pads 85A and 85B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The input pad 85A is arranged in a position adjacent to the GaN chip 20C in the Y direction on the drive chip 80 in a plan view. The input pad 85A is arranged in a position adjacent to the gate pad 81B in the X direction. The input pad 85B is arranged in a position adjacent to the GaN chip 20D in the Y direction on the drive chip 80 in a plan view. The input pad 85B is arranged in a position adjacent to the gate pad 81D in the X direction. In one example, the input pad 85A is a pad electrically connected to the source electrode 29 of the GaN transistor 22 of the GaN chip 20A. In one example, the input pad 85B is a pad electrically connected to the source electrode 29 of the GaN transistor 22 of the GaN chip 20C.

[0308] As shown in FIGS. 47 and 48, the driver chip 80 includes a driver substrate 91, a driver circuit 92, a third insulating film 93, a wiring layer 94, and a fifth insulating film 95. The drive substrate 91 can be formed of Si, SiC, GaN, sapphire, or other substrate materials, similar to the GaN chips 20A to 20D. The drive substrate 91 may be a semiconductor substrate. In one example, the drive substrate 91 may be a Si substrate. The drive substrate 91 may be made of the same material as the substrate 21. The thickness of the drive substrate 91 may be, for example, not less than 200 μm and not more than 1500 μm. The thickness of the drive substrate 91 may be equal to the thickness of the substrate 21. In the second embodiment, the drive substrate 91 has the same configuration as the substrate 21 of the GaN chips 20A to 20D.

[0309] The drive circuit 92 is provided between the drive substrate 91 and the third insulating film 93. A part of the drive circuit 92 may be provided on at least one of the drive substrate 91 and the third insulating film 93. The drive circuit 92 includes a gate driver circuit that drives the GaN transistors 22 of the GaN chips 20A to 20D. The drive circuit 92 (gate driver circuit) may be configured to drive the GaN chips 20A to 20D individually. In one example, the drive circuit 92 may include a buffer layer 23, an electron transit layer 24, and an electron supply layer 25 (see FIG. 6 ), similar to the GaN transistors 22.

[0310] The third insulating film 93 is an interlayer insulating film, similar to the third insulating film 33 of the GaN chips 20A to 20D, and is made of, for example, SiO2. In one example, the third insulating film 93 is made of the same material as the third insulating film 33 of the GaN chips 20A to 20D. In one example, the thickness of the third insulating film 93 is equal to the thickness of the third insulating film 33. In the second embodiment, the third insulating film 93 has the same configuration as the third insulating film 33 of the GaN chips 20A to 20D.

[0311] The wiring layer 94 electrically connects the drive circuit 92 to the gate pads 81A-81D, the source pad 82, the boot pads 83A and 83B, the input pads 84A-84E, and the input pads 85A and 85B (see FIG. 46). Although not shown, the wiring layer 94 includes a plurality of wiring sections that electrically connect the drive circuit 92 to the gate pads 81A-81D, the source pad 82, the boot pads 83A and 83B, the input pads 84A-84E, and the input pads 85A and 85B. Each wiring section is provided on the third insulating film 93. Each wiring section is made up of, for example, a plurality of metal layers. In one example, each wiring section is made up of a Ti layer as a seed layer and a Cu layer as a plating layer.

[0312] The wiring layer 94 includes a fourth insulating film that covers the plurality of wiring portions and insulates them from each other. In one example, the thickness of the fourth insulating film is equal to the thickness of the plurality of wiring portions. The thickness of the fourth insulating film is thinner than the thickness of the third insulating film 93. In one example, the thickness of the fourth insulating film is equal to the thickness of the fourth insulating film 34A (see FIG. 7) of the GaN chips 20A to 20D. The fourth insulating film is an interlayer insulating film and is made of, for example, SiO2. In one example, the fourth insulating film is made of the same material as the fourth insulating film 34A of the GaN chips 20A to 20D. In the second embodiment, the fourth insulating film has the same configuration as the fourth insulating film 34A of the GaN chips 20A to 20D.

[0313] A plurality of gate intermediate pads, a source intermediate pad, a plurality of boot intermediate pads, and a plurality of input intermediate pads (all not shown) are provided on the wiring layer 94. These intermediate pads are individually provided on the plurality of wiring portions. As a result, these intermediate pads are individually electrically connected to the plurality of wiring portions. Each of the plurality of gate intermediate pads, the source intermediate pads, the plurality of boot intermediate pads, and the plurality of input intermediate pads is composed of, for example, a plurality of metal layers. In one example, each of these intermediate pads is composed of a Ti layer as a seed layer and a Cu layer as a plating layer.

[0314] The driver chip 80 includes a fifth insulating film 95 that insulates the plurality of gate intermediate pads, the source intermediate pad, the plurality of boot intermediate pads, and the plurality of input intermediate pads from one another. In one example, the thickness of the fifth insulating film 95 is equal to the thickness of the above-mentioned intermediate pads. The thickness of the fifth insulating film 95 is equal to or less than the thickness of the third insulating film 93. The thickness of the fifth insulating film 95 is equal to the thickness of the fifth insulating film 39 of the GaN chips 20A to 20D. The fifth insulating film 95 is an interlayer insulating film and is made of, for example, SiO2. In one example, the fifth insulating film 95 is made of the same material as the fifth insulating film 39 of the GaN chips 20A to 20D.

[0315] The driver chip 80 includes posts (not shown) provided on a plurality of gate intermediate pads, a plurality of source intermediate pads, a plurality of boot intermediate pads, and a plurality of input intermediate pads. The posts are exposed from the sealing surface 60S of the first sealing resin 60.

[0316] The posts include a plurality of gate posts, a source post, a plurality of boot posts, and a plurality of input posts. A first sealing resin 60 is interposed between these posts. Therefore, these posts are insulated by the first sealing resin 60.

[0317] A plurality of gate posts are provided on the plurality of gate intermediate pads in correspondence with each other. The plurality of gate posts are individually electrically connected to the plurality of gate intermediate pads. A source post is provided on the source intermediate pads in correspondence with each other. The source post is electrically connected to the source intermediate pads. A plurality of input posts are provided on the plurality of input intermediate pads in correspondence with each other. The plurality of input posts are individually electrically connected to the plurality of input intermediate pads. A plurality of boot posts are provided on the plurality of boot intermediate pads in correspondence with each other. The plurality of boot posts are individually electrically connected to the plurality of boot intermediate pads.

[0318] The gate pads 81A to 81D are provided on the gate posts in correspondence with each other. The gate pads 81A to 81D are electrically connected to the gate posts individually. Therefore, the gate pads 81A to 81D are electrically connected to the drive circuit 92 via the corresponding gate posts, gate intermediate pads, and corresponding wiring portions.

[0319] The source pad 82 is provided on the source post. The source pad 82 is electrically connected to the source post. Therefore, the source pad 82 is electrically connected to the drive circuit 92 via the source post, the source intermediate pad, and the corresponding wiring portion.

[0320] The boot pads 83A and 83B are provided on a plurality of boot posts corresponding to each other. The boot pads 83A and 83B are individually electrically connected to the plurality of boot posts. Therefore, the boot pads 83A and 83B are electrically connected to the drive circuit 92 via the corresponding boot posts, boot intermediate pads, and corresponding wiring portions.

[0321] The input pads 84A-84E, 85A, and 85B are provided on a plurality of input posts corresponding to each other. The input pads 84A-84E, 85A, and 85B are individually and electrically connected to the plurality of input posts. Therefore, the input pads 84A-84E, 85A, and 85B are electrically connected to the drive circuit 92 via the corresponding input posts, input intermediate pads, and corresponding wiring portions.

[0322] (electromagnetic wave shielding) As shown in Figures 46 to 49, each of the GaN chips 20A to 20D of the second embodiment is provided with first to fourth electromagnetic wave shields 70A to 70D, similar to the first embodiment. The first to fourth electromagnetic wave shields 70A to 70D are arranged spaced apart from each other, similar to the first embodiment. Furthermore, the first to fourth electromagnetic wave shields 70A to 70D have the same configuration as the first embodiment. The first to fourth electromagnetic wave shields 70A to 70D have the same configuration as the first embodiment.

[0323] The first electromagnetic wave shield 70A is provided on the GaN chip 20A. Of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A, the third chip side surface 20PC faces the drive chip 80 in the Y direction. Therefore, the third chip side surface 20PC of the GaN chip 20A is an example of a "first chip-facing surface." The side shield portion 71 of the first electromagnetic wave shield 70A is provided on the third chip side surface 20PC. In the second embodiment, the side shield portion 71 of the first electromagnetic wave shield 70A is provided on the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A, as in the first embodiment. The back surface shield portion 72 of the first electromagnetic wave shield 70A is provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20A, as in the first embodiment.

[0324] The second electromagnetic wave shield 70B is provided on the GaN chip 20B. Of the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20B, the fourth chip side surface 20PD faces the drive chip 80 in the Y direction. Therefore, the fourth chip side surface 20PD of the GaN chip 20B is an example of a "second chip-facing surface." A side shield portion 71 of the second electromagnetic wave shield 70B is provided on the fourth chip side surface 20PD. In the second embodiment, the side shield portion 71 of the second electromagnetic wave shield 70B is provided on the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20B, as in the first embodiment. A back surface shield portion 72 of the second electromagnetic wave shield 70B is provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20B, as in the first embodiment. Therefore, the second electromagnetic wave shield 70B is disposed at the same position as the first electromagnetic wave shield 70A in the X direction. The second electromagnetic wave shield 70B is disposed apart from the first electromagnetic wave shield 70A in the Y direction via the driver chip 80.

[0325] The third electromagnetic wave shield 70C is provided on the GaN chip 20C. Of the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20C, the third chip side surface 20PC faces the drive chip 80 in the Y direction. Therefore, the third chip side surface 20PC of the GaN chip 20C is an example of a "third chip-facing surface." The side shield portion 71 of the third electromagnetic wave shield 70C is provided on the third chip side surface 20PC. In the second embodiment, the side shield portion 71 of the third electromagnetic wave shield 70C is provided on the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20C, as in the first embodiment. The back surface shield portion 72 of the third electromagnetic wave shield 70C is provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20C, as in the first embodiment. Therefore, the third electromagnetic wave shield 70C is disposed adjacent to the first electromagnetic wave shield 70A in the X direction.

[0326] The fourth electromagnetic wave shield 70D is provided on the GaN chip 20D. Of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20D, the fourth chip side surface 20PD faces the drive chip 80 in the Y direction. Therefore, the fourth chip side surface 20PD of the GaN chip 20D is an example of a "fourth chip-facing surface." The side shield portion 71 of the fourth electromagnetic wave shield 70D is provided on the fourth chip side surface 20PD. In the second embodiment, the side shield portion 71 of the fourth electromagnetic wave shield 70D is provided on the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20D, as in the first embodiment. The back surface shield portion 72 of the fourth electromagnetic wave shield 70D is provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20D, as in the first embodiment. Therefore, the fourth electromagnetic wave shield 70D is disposed adjacent to the second electromagnetic wave shield 70B in the X direction.

[0327] 46 to 49, in the second embodiment, the nitride semiconductor device 10 includes an electromagnetic wave shield 70P provided on the drive chip 80. The electromagnetic wave shield 70P has the same configuration as, for example, the first to fourth electromagnetic wave shields 70A to 70D. Therefore, like the first to fourth electromagnetic wave shields 70A to 70D, the electromagnetic wave shield 70P includes a side shield part 71 and a back shield part 72.

[0328] The side shield part 71 of the electromagnetic wave shield 70P is provided on each of the first to fourth chip side surfaces 80A to 80D of the driver chip 80. As shown in FIGS. 47 and 48, the side shield part 71 is provided over the entire third chip side surface 80C in the Z direction. The side shield part 71 is provided over the entire fourth chip side surface 80D in the Z direction. Although not shown, the side shield part 71 is provided over the entire first chip side surface 80A in the Z direction. The side shield part 71 is provided over the entire second chip side surface 80B in the Z direction.

[0329] As shown in FIG. 48, the side shield portion 71 of the electromagnetic wave shield 70P includes a substrate shield portion 71Q that covers the side surface of the drive substrate 91, and a wiring shield portion 71R that covers the side surface of the wiring layer 94.

[0330] The substrate shield part 71Q is provided over the entire side surface of the drive substrate 91 in the Z direction. The substrate shield part 71Q extends in the Z direction. The substrate shield part 71Q is connected to the rear surface shield part 72.

[0331] The wiring shield part 71R is provided over the entire side surface of the wiring layer 94 in the Z direction. The wiring shield part 71R is provided over the entire side surface of the third insulating film 93 in the Z direction. The wiring shield part 71R is provided over the entire side surface of the fifth insulating film 95. The wiring shield part 71R is disposed at a position that does not overlap with the substrate shield part 71Q in a planar view. Specifically, the wiring shield part 71R is disposed inward of the substrate shield part 71Q in a planar view.

[0332] The side shield portion 71 of the electromagnetic wave shield 70P further includes a stepped shield portion 71S that covers a stepped portion 80E provided on the third chip side surface 80C. Thus, the side shield portion 71 is provided to cover the stepped portion 80E. The stepped portion 80E is provided on the third chip side surface 80C between the substrate side surface of the driving substrate 91 and a portion of the driving chip 80 above the driving substrate 91. The portion of the driving chip 80 above the driving substrate 91 includes a third insulating film 93, a wiring layer 94, and a fifth insulating film 95. In a plan view, the driving substrate 91 protrudes in the X and Y directions beyond the third insulating film 93, the wiring layer 94, and the fifth insulating film 95. Therefore, the stepped shield portion 71S covers the portion of the substrate surface 91S of the driving substrate 91 that protrudes beyond the third insulating film 93, the wiring layer 94, and the fifth insulating film 95 in a plan view. The stepped shield portion 71S is connected to the substrate shield portion 71Q and the wiring shield portion 71R. The stepped shield portion 71S of the electromagnetic wave shield 70P is provided so as to cover the stepped portion 80E provided on the fourth chip side surface 80D. Although not shown, the stepped shield portion 71S of the electromagnetic wave shield 70P is provided so as to cover both the stepped portion 80E provided on the first chip side surface 80A and the stepped portion 80E provided on the second chip side surface 80B.

[0333] The side shield portion 71 of the electromagnetic wave shield 70P includes a protrusion 71P that protrudes upward in the Z direction beyond the third chip side surface 80C. The configuration of the protrusion 71P may be the same as the configuration of the protrusion 71P in the first embodiment (see FIG. 9).

[0334] 49, the back surface shield part 72 of the electromagnetic wave shield 70P is provided over the entire chip back surface 80R of the driver chip 80. The back surface shield part 72 is connected to the side surface shield part 71. More specifically, the back surface shield part 72 is connected to the side surface shield part 71 provided on each of the first to fourth chip side surfaces 80A to 80D. Therefore, the electromagnetic wave shield 70P covers the driver chip 80 from below in the X, Y, and Z directions.

[0335] 48, the rear surface shield part 72 is exposed from the sealing rear surface 60R of the first sealing resin 60. In addition, the rear surface shield part 72 is provided on the substrate rear surface 91R and therefore protrudes in the Z direction from the sealing rear surface 60R. In the second embodiment, the rear surface shield part 72 is not in contact with the sealing rear surface 60R. It can be said that the rear surface shield part 72 is provided at a distance from the sealing rear surface 60R.

[0336] 49, the rear surface shield part 72 protrudes from the drive substrate 91 in both the X and Y directions in plan view. That is, the area of ​​the rear surface shield part 72 is larger than the area of ​​the substrate rear surface 21R of the substrate 21 in plan view.

[0337] The back surface shield portion 72 of the electromagnetic wave shield 70P is provided at a distance from the back surface shield portions 72 of the first to fourth electromagnetic wave shields 70A to 70D. The back surface shield portion 72 of the electromagnetic wave shield 70P is disposed between the back surface shield portions 72 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B in the Y direction and between the back surface shield portions 72 of the third electromagnetic wave shield 70C and the fourth electromagnetic wave shield 70D in the Y direction. The area of ​​the back surface shield portion 72 of the electromagnetic wave shield 70P in a plan view is larger than the area of ​​the back surface shield portions 72 of each of the first to fourth electromagnetic wave shields 70A to 70D in a plan view.

[0338] The shortest distance D1 between the GaN chips 20A and 20C and the shortest distance D2 between the GaN chips 20B and 20D are equal to each other. The shortest distances D1 and D2 are, for example, 10 μm or more and 50 μm or less. The shortest distance D3 between the GaN chips 20A and 20B and the first sealing side surface 60A in the X direction is smaller than the shortest distances D1 and D2. The shortest distance D4 between the GaN chips 20C and 20D and the second sealing side surface 60B in the X direction is smaller than the shortest distances D1 and D2. In one example, the shortest distance D3 is equal to the shortest distance D4. The shortest distance D5 between the GaN chips 20A and 20C and the fourth sealing side surface 60D in the Y direction is smaller than the shortest distances D1 and D2. The shortest distance D6 between the GaN chips 20B and 20D and the third sealing side surface 60C in the Y direction is smaller than the shortest distances D1 and D2. In one example, the shortest distance D5 is equal to the shortest distance D6.

[0339] The shortest distance D7 between the GaN chips 20A, 20C and the driver chip 80 is equal to the shortest distance D8 between the GaN chips 20B, 20D and the driver chip 80. The shortest distances D7, D8 are, for example, 10 μm or more and 50 μm or less. In one example, the shortest distances D7, D8 are greater than the shortest distances D1, D2.

[0340] The shortest distance D9 between the driver chip 80 and the first sealing side surface 60A in the X direction is smaller than the shortest distances D7 and D8. In one example, the shortest distance D9 is smaller than half of the shortest distances D7 and D8. The shortest distance D10 between the driver chip 80 and the second sealing side surface 60B in the X direction is smaller than the shortest distances D7 and D8. In one example, the shortest distance D10 is smaller than half of the shortest distances D7 and D8. In one example, the shortest distance D10 is equal to the shortest distance D9. In one example, the shortest distances D9 and D10 are equal to the shortest distances D3 and D4.

[0341] In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the GaN chips 20A to 20D. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the driver chip 80. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the substrate 21 of the GaN chips 20A to 20D. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the driver substrate 91 of the driver chip 80. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the external wiring layer 50. In one example, the shortest distances D7 and D8 are smaller than the width dimension of the first gate wiring layers 54A and 54B. In one example, the shortest distances D7 and D8 are smaller than the width dimension of the second gate wiring layers 55A and 55B. In one example, the shortest distances D7 and D8 are smaller than the width dimension of the source wiring layer 52. In one example, the shortest distances D7 and D8 are smaller than the width of the drain wiring layer 53. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the wiring layer 34 of the GaN chips 20A to 20D. In one example, the shortest distances D7 and D8 are smaller than the thickness (dimension in the Z direction) of the wiring layer 94 of the driver chip 80. In one example, the shortest distances D7 and D8 are smaller than the thickness of the source pad 35. In one example, the shortest distances D7 and D8 are smaller than the thickness of the drain pad 36. In one example, the shortest distances D7 and D8 are smaller than the thickness of the gate pad 37. In one example, the shortest distances D7 and D8 are smaller than the width of the post 40. In one example, the shortest distances D7 and D8 are greater than twice the thickness T5 of the side shield portion 71 of the first electromagnetic wave shield 70A. In one example, the shortest distances D7 and D8 are greater than twice the thickness T6 of the side shield portion 71 of the electromagnetic wave shield 70P. In addition, in one example, the shortest distances D1 and D2 are equal to the shortest distance DA (see FIG. 4) in the first embodiment.

[0342] Here, the shortest distance D1 can be defined as the minimum value of the distance in the X direction between the side shield part 71 provided on the GaN chip 20A and the side shield part 71 provided on the GaN chip 20C. The shortest distance D2 can be defined as the distance in the X direction between the side shield part 71 provided on the GaN chip 20B and the side shield part 71 provided on the GaN chip 20D.

[0343] The shortest distance D3 can be defined as the minimum distance in the X direction between the side shield part 71 provided on the GaN chips 20A and 20B and the first sealing side surface 60A in plan view. The shortest distance D4 can be defined as the minimum distance in the X direction between the side shield part 71 provided on the GaN chips 20C and 20D and the second sealing side surface 60B in plan view.

[0344] The shortest distance D5 can be defined as the minimum distance in the Y direction between the side shield part 71 provided on the GaN chips 20A and 20C and the fourth sealing side surface 60D in a plan view. The shortest distance D6 can be defined as the minimum distance in the Y direction between the side shield part 71 provided on the GaN chips 20B and 20D and the third sealing side surface 60C in a plan view.

[0345] The shortest distance D7 can be defined as the minimum value of the distance in the Y direction between the back surface shield part 72 provided on the GaN chips 20A and 20C and the back surface shield part 72 provided on the drive chip 80 in a plan view. The shortest distance D8 can be defined as the minimum value of the distance in the Y direction between the back surface shield part 72 provided on the GaN chips 20B and 20D and the back surface shield part 72 provided on the drive chip 80 in a plan view.

[0346] The shortest distance D9 can be defined as the minimum distance in the X direction between the side shield part 71 provided on the driver chip 80 and the first sealing side surface 60A in a plan view. The shortest distance D10 can be defined as the minimum distance in the X direction between the side shield part 71 provided on the driver chip 80 and the second sealing side surface 60B in a plan view.

[0347] (1st sealing resin) As shown in FIGS. 46 to 49, first sealing resin 60 seals GaN chips 20A to 20D and driver chip 80. As shown in FIG. 47, first sealing resin 60 is interposed between GaN chip 20C and driver chip 80, and between GaN chip 20D and driver chip 80. More specifically, first sealing resin 60 is interposed in the Y direction between third electromagnetic wave shield 70C provided on GaN chip 20C and electromagnetic wave shield 70P provided on driver chip 80. First sealing resin 60 is interposed in the Y direction between fourth electromagnetic wave shield 70D provided on GaN chip 20D and electromagnetic wave shield 70P provided on driver chip 80.

[0348] 48, similarly to the first embodiment, the first sealing resin 60 includes a wiring sealing layer 61 and a substrate sealing layer 62. The wiring sealing layer 61 and the substrate sealing layer 62 are separated for convenience, and there is no interface between the wiring sealing layer 61 and the substrate sealing layer 62.

[0349] The wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the third electromagnetic wave shield 70C provided on the GaN chip 20C and the wiring shield portion 71R of the electromagnetic wave shield 70P provided on the drive chip 80. The wiring encapsulation layer 61 is interposed between the wiring shield portion 71R provided on the electromagnetic wave shield 70P and the wiring shield portion 71R provided on the fourth electromagnetic wave shield 70D of the GaN chip 20D. Although not shown, the wiring encapsulation layer 61 is interposed between the wiring shield portion 71R of the first electromagnetic wave shield 70A provided on the GaN chip 20A and the wiring shield portion 71R of the electromagnetic wave shield 70P, and between the wiring shield portion 71R of the second electromagnetic wave shield 70B provided on the GaN chip 20B and the wiring shield portion 71R of the electromagnetic wave shield 70P. Furthermore, the wiring sealing layer 61 is interposed between the wiring shield portion 71R of the first electromagnetic wave shield 70A and the wiring shield portion 71R of the third electromagnetic wave shield 70C in the X direction, and between the wiring shield portion 71R of the second electromagnetic wave shield 70B and the wiring shield portion 71R of the fourth electromagnetic wave shield 70D in the X direction.

[0350] The substrate sealing layer 62 is interposed in the Y direction between the substrate shield portion 71Q of the third electromagnetic wave shield 70C provided on the GaN chip 20C and the substrate shield portion 71Q of the electromagnetic wave shield 70P provided on the drive chip 80. The substrate sealing layer 62 is interposed in the Y direction between the substrate shield portion 71Q of the fourth electromagnetic wave shield 70D provided on the GaN chip 20D and the substrate shield portion 71Q of the electromagnetic wave shield 70P. Although not shown, the substrate sealing layer 62 is interposed in the Y direction between the substrate shield portion 71Q of the first electromagnetic wave shield 70A provided on the GaN chip 20A and the substrate shield portion 71Q of the electromagnetic wave shield 70P. The substrate sealing layer 62 is interposed in the Y direction between the substrate shield portion 71Q of the second electromagnetic wave shield 70B provided on the GaN chip 20B and the substrate shield portion 71Q of the electromagnetic wave shield 70P. Furthermore, the board sealing layer 62 is interposed between the board shield portion 71Q of the first electromagnetic wave shield 70A and the board shield portion 71Q of the third electromagnetic wave shield 70C in the X direction, and between the board shield portion 71Q of the second electromagnetic wave shield 70B and the board shield portion 71Q of the fourth electromagnetic wave shield 70D in the X direction. In this way, the board sealing layer 62 is interposed between adjacent board shield portions 71Q in the X direction or the Y direction in the board shield portions 71Q of each of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P, and insulates the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P from each other. Furthermore, the first sealing resin 60 covers each of the board shield portions 71Q of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P, and is disposed so as to be interposed between adjacent board shield portions 71Q in the X direction or Y direction. Therefore, the sealing back surface 60R is exposed between adjacent electromagnetic wave shields in the X direction or Y direction among the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P.

[0351] 48, in the GaN chip 20C and the driver chip 80 adjacent to each other in the Y direction (first direction), the dimension HA in the Y direction (first direction) of the wiring sealing layer 61 is larger than the dimension HB in the Y direction (first direction) of the substrate sealing layer 62. The dimension HB is smaller than the shortest distance D1 (see FIG. 49). Note that the dimension HA in the Y direction of the wiring sealing layer 61 in the GaN chip 20D and the driver chip 80, the dimension HA in the Y direction of the wiring sealing layer 61 in the GaN chip 20A and the driver chip 80, and the dimension HA in the Y direction of the wiring sealing layer 61 in the GaN chip 20B and the driver chip 80 are each equal to the dimension HA in the Y direction of the wiring sealing layer 61 in the GaN chip 20A and the driver chip 80.

[0352] [Method of manufacturing a nitride semiconductor device] Next, an example of a method for manufacturing the nitride semiconductor device 10 of the second embodiment will be described. The method for manufacturing the nitride semiconductor device 10 of the second embodiment differs from the method for manufacturing the nitride semiconductor device 10 of the first embodiment mainly in that a manufacturing process for the driver chip 80 is added. The manufacturing process for the driver chip 80 will be described below.

[0353] In the step of preparing a wafer 821 in the method for manufacturing the nitride semiconductor device 10 (FIGS. 16 to 24), the wafer 821 constitutes the driving substrates 91 of the plurality of driving chips 80. In the step of preparing the wafer 821, the GaN transistors 22 are formed and the driving circuits 92 are also formed. That is, the wafer 821 includes a plurality of chip formation regions 821A (see FIG. 26) in which the GaN transistors 22 are formed and a plurality of chip formation regions (not shown) in which the driving circuits 92 are formed. Furthermore, a third insulating film 833 (see FIG. 25) of the wafer 821 constitutes the third insulating film 93 of the driving chip 80. That is, the third insulating film 833 includes the third insulating film 33 of the GaN chips 20A to 20D and the third insulating film 93 of the driving chip 80. Furthermore, a wiring layer 834 (see FIG. 25) of the wafer 821 constitutes the wiring layer 94 of the driving chip 80. That is, the wiring layer 834 includes the wiring layer 34 of the GaN chips 20A to 20D and the wiring layer 94 of the driver chip 80. Furthermore, the fifth insulating film 839 (see FIG. 25) of the wafer 821 constitutes the fifth insulating film 95 of the driver chip 80. That is, the fifth insulating film 839 includes the fifth insulating film 39 of the GaN chips 20A to 20D and the fifth insulating film 95 of the driver chip 80.

[0354] In the process of preparing this wafer 821, the portions between adjacent GaN transistors 22 and drive circuits 92 above wafer 821 are removed, for example, by etching. That is, in wafer 821, the portions between GaN transistors 22 corresponding to GaN chips 20A and 20C and drive circuits 92, and the portions between GaN transistors 22 corresponding to GaN chips 20B and 20D and drive circuits 92 are removed. In addition, in wafer 821, the portions between GaN transistor 22 corresponding to GaN chip 20A and GaN transistor 22 corresponding to GaN chip 20C, and the portions between GaN transistor 22 corresponding to GaN chip 20B and GaN transistor 22 corresponding to GaN chip 20D are removed. In this way, the third insulating film 33 of GaN chips 20A to 20D and the third insulating film 93 of drive chip 80 are formed in a common process. The wiring layer 34 of GaN chips 20A to 20D and the wiring layer 94 of drive chip 80 are formed in a common process. The fifth insulating film 39 of the GaN chips 20A to 20D and the fifth insulating film 95 of the driver chip 80 are formed in a common process.

[0355] In the method for manufacturing the nitride semiconductor device 10, after forming the grooves 821B (see FIGS. 27 to 29) between adjacent chip formation regions 821A, the side shield portions 71 of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are formed. In other words, the side shield portions 71 of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are formed in a common process.

[0356] In the method for manufacturing the nitride semiconductor device 10, after forming the posts, the resin layer 860, and the external wiring layer 50, the wafer back surface 821R of the wafer 821 is ground to expose the resin layer 860 in the grooves 821B. This forms the substrate 21 of the GaN chips 20A to 20D and the drive substrate 91 of the drive chip 80. Then, the first to fourth electromagnetic wave shields 70A to 70D and the side shield portions 71 of the electromagnetic wave shield 70P are separated from each other. In this way, the substrate 21 of the GaN chips 20A to 20D and the drive substrate 91 of the drive chip 80 are formed from the same wafer 821.

[0357] Thereafter, the back surface shield portions 72 of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are formed. That is, the back surface shield portions 72 of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are formed in a common process. Thereafter, as in the first embodiment, a plating layer 50C is formed on the surface of the external wiring layer 50, and the resulting product is singulated to manufacture the nitride semiconductor device 10.

[0358] [Effects of the second embodiment] According to the nitride semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) Nitride semiconductor device 10 includes GaN chips 20A to 20D sealed with first sealing resin 60, and a driver chip 80 sealed with first sealing resin 60 and configured to drive GaN chips 20A to 20D. GaN chip 20A and GaN chip 20B are spaced apart in the Y direction (first direction). GaN chip 20C and GaN chip 20D are spaced apart in the Y direction. Driver chip 80 is located between GaN chips 20A, 20C and GaN chips 20B, 20D in the Y direction (first direction).

[0359] According to this configuration, the conductive path between the GaN chips 20A to 20D and the driver chip 80 can be made shorter than in a configuration in which the driver chip is disposed outside the nitride semiconductor device.

[0360] (2-2) Between the GaN chips 20A, 20C and the driving chip 80, and between the GaN chips 20B, 20D and the driving chip 80, electromagnetic wave shields 70 are provided. According to this configuration, the electromagnetic wave shield 70 can prevent electromagnetic waves from the GaN chips 20A and 20C from affecting the driver chip 80. The electromagnetic wave shield 70 can also prevent electromagnetic waves from the GaN chips 20B and 20D from affecting the driver chip 80.

[0361] (2-3) Each of the GaN chips 20A to 20D includes first to fourth chip side surfaces 20PA to 20PD. The first electromagnetic wave shield 70A includes a side shield portion 71 provided on a third chip side surface 20PC of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A, which serves as a first chip-facing surface that faces the driving chip 80 in the Y direction. The second electromagnetic wave shield 70B includes a side shield portion 71 provided on a fourth chip side surface 20PD of the GaN chip 20B, which serves as a second chip-facing surface that faces the driving chip 80 in the Y direction, of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20B. The third electromagnetic wave shield 70C includes a side shield portion 71 provided on a third chip side surface 20PC of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20C, which serves as a third chip-facing surface that faces the driving chip 80 in the Y direction. The fourth electromagnetic wave shield 70D includes a side shield portion 71 provided on the fourth chip side surface 20PD as a fourth chip facing surface that faces the driver chip 80 in the Y direction among the first to fourth chip side surfaces 20PA-20PD of the GaN chip 20D.

[0362] With this configuration, the side shield portion 71 of the first electromagnetic wave shield 70A can prevent electromagnetic waves from the GaN chip 20A from affecting the drive chip 80. Furthermore, the side shield portion 71 of the second electromagnetic wave shield 70B can prevent electromagnetic waves from the GaN chip 20B from affecting the drive chip 80. Furthermore, the side shield portion 71 of the third electromagnetic wave shield 70C can prevent electromagnetic waves from the GaN chip 20C from affecting the drive chip 80. Furthermore, the side shield portion 71 of the fourth electromagnetic wave shield 70D can prevent electromagnetic waves from the GaN chip 20D from affecting the drive chip 80.

[0363] (2-4) The driver chip 80 includes first to fourth chip side surfaces 80A to 80D. The fourth chip side surface 80D, which serves as a fifth chip-facing surface, faces the GaN chips 20A and 20C in the Y direction. The third chip side surface 80C, which serves as a sixth chip-facing surface, faces the GaN chips 20B and 20D in the Y direction. The electromagnetic wave shield 70P includes side shield portions 71 provided on the third chip side surface 80C and the fourth chip side surface 80D.

[0364] According to this configuration, side shield portion 71 of electromagnetic wave shield 70P can prevent electromagnetic waves generated from drive chip 80 from affecting GaN chips 20A to 20D.

[0365] (2-5) The side shield portions 71 of the first electromagnetic wave shield 70A are provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20A. The side shield portions 71 of the second electromagnetic wave shield 70B are provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20B. The side shield portions 71 of the third electromagnetic wave shield 70C are provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20C. The side shield portions 71 of the fourth electromagnetic wave shield 70D are provided on each of the first to fourth chip side surfaces 20PA to 20PD of the GaN chip 20D.

[0366] According to this configuration, the side shield portion 71 of the first electromagnetic wave shield 70A can prevent electromagnetic waves generated from the GaN chip 20A from propagating to the periphery of the GaN chip 20A in a planar view. The side shield portion 71 of the second electromagnetic wave shield 70B can prevent electromagnetic waves generated from the GaN chip 20B from propagating to the periphery of the GaN chip 20B in a planar view. The side shield portion 71 of the third electromagnetic wave shield 70C can prevent electromagnetic waves generated from the GaN chip 20C from propagating to the periphery of the GaN chip 20C in a planar view. The side shield portion 71 of the fourth electromagnetic wave shield 70D can prevent electromagnetic waves generated from the GaN chip 20D from propagating to the periphery of the GaN chip 20D in a planar view.

[0367] (2-6) The electromagnetic wave shield 70P includes side shield portions 71 provided on the first to fourth chip side surfaces 80A to 80D of the driver chip 80, respectively. According to this configuration, the side shield portions 71 of the electromagnetic wave shield 70P can prevent electromagnetic waves generated from the driver chip 80 from propagating to the periphery of the driver chip 80 in plan view.

[0368] (2-7) The first electromagnetic wave shield 70A includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20A. The second electromagnetic wave shield 70B includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20B. The third electromagnetic wave shield 70C includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20C. The fourth electromagnetic wave shield 70D includes a back surface shield part 72 provided on the substrate back surface 21R of the substrate 21 of the GaN chip 20D.

[0369] With this configuration, the rear surface shield portion 72 of the first electromagnetic wave shield 70A can prevent electromagnetic waves generated from the GaN chip 20A from propagating to the outside of the GaN chip 20A via the rear surface 21R of the substrate 21. The rear surface shield portion 72 of the second electromagnetic wave shield 70B can prevent electromagnetic waves generated from the GaN chip 20B from propagating to the outside of the GaN chip 20B via the rear surface 21R of the substrate 21. The rear surface shield portion 72 of the third electromagnetic wave shield 70C can prevent electromagnetic waves generated from the GaN chip 20C from propagating to the outside of the GaN chip 20C via the rear surface 21R of the substrate 21. The rear surface shield portion 72 of the fourth electromagnetic wave shield 70D can prevent electromagnetic waves generated from the GaN chip 20D from propagating to the outside of the GaN chip 20D via the rear surface 21R of the substrate 21.

[0370] (2-8) The side shield portion 71 and the back shield portion 72 of the first electromagnetic wave shield 70A are connected to each other. The side shield portion 71 and the back shield portion 72 of the second electromagnetic wave shield 70B are connected to each other. The side shield portion 71 and the back shield portion 72 of the third electromagnetic wave shield 70C are connected to each other. The side shield portion 71 and the back shield portion 72 of the fourth electromagnetic wave shield 70D are connected to each other.

[0371] According to this configuration, the first electromagnetic wave shield 70A can prevent electromagnetic waves generated from the GaN chip 20A from propagating through the first to fourth chip side surfaces 20PA-20PD and the back surface 21R of the substrate 21. This makes it difficult for electromagnetic waves from the GaN chip 20A to propagate outside the GaN chip 20A. The second electromagnetic wave shield 70B can prevent electromagnetic waves generated from the GaN chip 20B from propagating through the first to fourth chip side surfaces 20PA-20PD and the back surface 21R of the substrate 21. This makes it difficult for electromagnetic waves from the GaN chip 20B to propagate outside the GaN chip 20B. The third electromagnetic wave shield 70C can prevent electromagnetic waves generated from the GaN chip 20C from propagating through the first to fourth chip side surfaces 20PA-20PD and the back surface 21R of the substrate 21. This makes it difficult for electromagnetic waves from the GaN chip 20C to propagate outside the GaN chip 20C. The fourth electromagnetic wave shield 70D can prevent electromagnetic waves generated from the GaN chip 20D from propagating through the first to fourth chip side surfaces 20PA to 20PD and the substrate back surface 21R of the substrate 21. Therefore, the electromagnetic waves from the GaN chip 20D are less likely to propagate outside the GaN chip 20D.

[0372] (2-9) The drive chip 80 includes a drive substrate 91 having a chip front surface 80S, a chip back surface 80R opposite the chip front surface 80S, a substrate front surface 91S, and a substrate back surface 91R opposite the substrate front surface 91S and constituting the chip back surface 80R. The electromagnetic wave shield 70P includes a back surface shield portion 72 provided on the substrate back surface 91R of the drive substrate 91.

[0373] According to this configuration, the rear shield portion 72 of the electromagnetic wave shield 70P can prevent electromagnetic waves generated from the driver chip 80 from propagating to the outside of the driver chip 80 via the substrate rear surface 91R of the driver substrate 91.

[0374] (2-10) The side shield portion 71 and the back shield portion 72 of the electromagnetic wave shield 70P provided on the driver chip 80 are connected to each other. According to this configuration, the electromagnetic wave shield 70P can prevent electromagnetic waves generated from the driver chip 80 from propagating through the first to fourth chip side surfaces 80A to 80D and the substrate back surface 91R of the driver substrate 91. Therefore, the electromagnetic waves from the driver chip 80 are less likely to propagate outside the driver chip 80.

[0375] (2-11) The rear surface shield portion 72 of the electromagnetic wave shield 70P provided on the driver chip 80 is exposed from the sealing rear surface 60R of the first sealing resin 60. According to this configuration, heat generated from the driver chip 80 is dissipated to the outside of the nitride semiconductor device 10 via the rear surface shield portion 72 of the electromagnetic wave shield 70P. Therefore, the heat dissipation performance of the driver chip 80 can be improved.

[0376] (2-12) The nitride semiconductor device 10 includes a first connection wiring layer 51A that electrically connects the drain of the GaN chip 20A to the source of the GaN chip 20B, and a second connection wiring layer 51B that electrically connects the drain of the GaN chip 20C to the source of the GaN chip 20D. Both the first connection wiring layer 51A and the second connection wiring layer 51B extend in the Y direction across the driver chip 80.

[0377] This configuration can shorten the conductive path between the drain of the GaN chip 20A and the source of the GaN chip 20B, and can shorten the conductive path between the drain of the GaN chip 20C and the source of the GaN chip 20D.

[0378] (2-13) The substrate 21 of the GaN chips 20A to 20D and the drive substrate 91 of the drive chip 80 are formed using the same wafer 821. According to this configuration, it is possible to reduce the distance between adjacent chips among the GaN chips 20A to 20D and the driver chip 80, compared to when the GaN chips 20A to 20D and the driver chip 80 are formed on separate wafers, thereby enabling the nitride semiconductor device 10 to be miniaturized.

[0379] <Example of change> The above-described embodiments can be modified as follows: The following modifications can be combined with each other as long as no technical contradiction occurs.

[0380] [Example of electromagnetic shield modification] In the first embodiment, the configuration of the side shield portions 71 of the first to sixth electromagnetic wave shields 70A to 70F can be modified as desired. FIGS. 50 to 55 show nitride semiconductor devices 10 according to first to fifth modifications. FIG. 50 schematically shows a partial cross-sectional structure of the nitride semiconductor device 10 according to the first modification. FIG. 51 schematically shows a partial cross-sectional structure of the nitride semiconductor device 10 according to the second modification. FIG. 52 schematically shows a partial cross-sectional structure of the nitride semiconductor device 10 according to the third modification. FIG. 53 schematically shows a partial cross-sectional structure of the nitride semiconductor device 10 according to the fourth modification. FIGS. 50 to 53 schematically show cross-sectional structures of the GaN chip 20A and the GaN chip 20B cut along the YZ plane. FIG. 54 schematically shows the back surface structure of the nitride semiconductor device 10 according to the fifth modification. FIG. 55 schematically shows the back surface structure of the nitride semiconductor device 10 according to the sixth modification. The first to sixth modified examples may be combined with each other to the extent that no technical contradiction occurs.

[0381] As shown in FIG. 50 , in the nitride semiconductor device 10 of the first modified example, the side shield portion 71 of the first electromagnetic wave shield 70A is provided between the GaN chip 20A and the GaN chip 20B in the Y direction, but is not provided between the GaN chip 20A and the fourth sealing side surface 60D in the Y direction. The side shield portion 71 of the second electromagnetic wave shield 70B is provided between the GaN chip 20A and the GaN chip 20B in the Y direction, but is not provided between the GaN chip 20B and the third sealing side surface 60C in the Y direction. In this manner, the side shield portions 71 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B may be provided only between the GaN chip 20A and the GaN chip 20B in the Y direction. Note that the third to sixth electromagnetic wave shields 70C to 70F may also be modified in a similar manner.

[0382] 51 , in the nitride semiconductor device 10 of the second modified example, the back surface shield portion 72 may be omitted from the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B. In the nitride semiconductor device 10 of the second modified example, the side surface shield portions 71 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B are exposed from the encapsulation back surface 60R. Note that the third to sixth electromagnetic wave shields 70C to 70F may also be modified in a similar manner.

[0383] 52, in the nitride semiconductor device 10 of the third modified example, the side shield parts 71 may be omitted from the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B. In the nitride semiconductor device 10 of the third modified example, the back surface shield part 72 includes a part that protrudes from the substrate 21 in a plan view. The size of the back surface shield part 72 in a plan view can be changed arbitrarily. For example, the area of ​​the back surface shield part 72 in a plan view may be equal to or smaller than the area of ​​the back surface 21R of the substrate 21. The third to sixth electromagnetic wave shields 70C to 70F may also be changed in a similar manner.

[0384] 53, in the nitride semiconductor device 10 of the fourth modified example, the side shield part 71 and the back shield part 72 in the first electromagnetic wave shield 70A may be separated. The side shield part 71 and the back shield part 72 in the second electromagnetic wave shield 70B may be separated. Note that the third to sixth electromagnetic wave shields 70C to 70F may also be modified in the same way.

[0385] As shown in FIG. 54 , in the nitride semiconductor device 10 of the fifth modified example, the back surface shield portion 72 of the first electromagnetic wave shield 70A and the back surface shield portion 72 of the second electromagnetic wave shield 70B may be integrated. The back surface shield portion 72 of the third electromagnetic wave shield 70C and the back surface shield portion 72 of the fourth electromagnetic wave shield 70D may be integrated. The back surface shield portion 72 of the fifth electromagnetic wave shield 70E and the back surface shield portion 72 of the sixth electromagnetic wave shield 70F may be integrated. The back surface shield portions 72 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B, the back surface shield portions 72 of the third electromagnetic wave shield 70C and the fourth electromagnetic wave shield 70D, and the back surface shield portions 72 of the fifth electromagnetic wave shield 70E and the sixth electromagnetic wave shield 70F are arranged apart from one another. The first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B are electrically connected to one another via the back surface shield portion 72. The third electromagnetic wave shield 70C and the fourth electromagnetic wave shield 70D are electrically connected to each other via a rear surface shield portion 72. The fifth electromagnetic wave shield 70E and the sixth electromagnetic wave shield 70F are electrically connected to each other via a rear surface shield portion 72.

[0386] 55, in the nitride semiconductor device 10 of the sixth modified example, the back surface shield portions 72 of the first to sixth electromagnetic wave shields 70A to 70F may be integrated, so that the first to sixth electromagnetic wave shields 70A to 70F are electrically connected to one another.

[0387] The first to sixth modified examples shown in FIGS. 50 to 55 may also be applied to the first to fourth electromagnetic wave shields 70A to 70D of the second embodiment. When the first modified example is applied to the second embodiment, the side shield portions 71 of the first electromagnetic wave shield 70A are provided between the GaN chip 20A and the GaN chip 20B in the X direction and between the GaN chip 20A and the drive chip 80 in the Y direction, but are not provided between the GaN chip 20A and the fourth sealing side surface 60D in the Y direction or between the GaN chip 20A and the first sealing side surface 60A in the X direction. The side shield portions 71 of the second electromagnetic wave shield 70B are provided between the GaN chip 20A and the GaN chip 20B in the X direction and between the GaN chip 20B and the drive chip 80 in the Y direction, but are not provided between the GaN chip 20B and the fourth sealing side surface 60D in the Y direction or between the GaN chip 20B and the second sealing side surface 60B in the X direction. The side shield portions 71 of the third electromagnetic wave shield 70C are provided between the GaN chip 20C and the GaN chip 20D in the X direction and between the GaN chip 20C and the drive chip 80 in the Y direction, but are not provided between the GaN chip 20C and the third sealing side surface 60C in the Y direction or between the GaN chip 20C and the first sealing side surface 60A in the X direction. The side shield portions 71 of the fourth electromagnetic wave shield 70D are provided between the GaN chip 20C and the GaN chip 20D in the X direction and between the GaN chip 20D and the drive chip 80 in the Y direction, but are not provided between the GaN chip 20D and the third sealing side surface 60C in the Y direction or between the GaN chip 20D and the second sealing side surface 60B in the X direction.

[0388] When the fifth modified example is applied to the second embodiment, the back surface shield portions 72 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B are integrated. The back surface shield portions 72 of the third electromagnetic wave shield 70C and the fourth electromagnetic wave shield 70D are integrated. The back surface shield portion 72 of the electromagnetic wave shield 70P provided on the drive chip 80 is disposed apart from the back surface shield portions 72 of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B and the back surface shield portions 72 of the third electromagnetic wave shield 70C and the fourth electromagnetic wave shield 70D.

[0389] When the sixth modified example is applied to the second embodiment, the rear surface shield portions 72 of the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are integrated together, so that the first to fourth electromagnetic wave shields 70A to 70D and the electromagnetic wave shield 70P are electrically connected to each other.

[0390] 50 to 53 can also be applied to the electromagnetic wave shield 70P provided in the drive chip 80 of the second embodiment. When the first modification example is applied to the electromagnetic wave shield 70P, at least one of the portion facing the first sealing side surface 60A and the portion facing the second sealing side surface 60B of the side shield part 71 of the electromagnetic wave shield 70P is omitted.

[0391] In the first embodiment, the protrusion 71P may be omitted from the side shield portion 71 of at least one of the first to sixth electromagnetic wave shields 70A to 70F. In the second embodiment, the protrusion 71P may be omitted from the side shield portion 71 of at least one of the first to fourth electromagnetic wave shields 70A to 70D.

[0392] In the first embodiment, at least one of the side shield portions 71 of the first to sixth electromagnetic wave shields 70A to 70F may be configured to cover part, rather than the entire Z-direction, of the first to fourth chip side surfaces 20PA to 20PD of the corresponding GaN chip among the GaN chips 20A to 20F. Note that the side shield portions 71 of the first to fourth electromagnetic wave shields 70A to 70D in the second embodiment can also be modified in a similar manner.

[0393] In each embodiment, the protruding portion 71P of the side shield part 71 may be provided so as to overlap the chip surface 20S in plan view. In each embodiment, the side shield part 71 may be made of a metal plate instead of a metal layer.

[0394] [Modifications of Nitride Semiconductor Devices] The number of GaN chips in the nitride semiconductor device 10 can be changed arbitrarily. In one example, as shown in FIG. 57, the nitride semiconductor device 10 may include two GaN chips. For convenience, the two GaN chips are referred to as "GaN chip 20A" and "GaN chip 20B." The GaN chip 20A and the GaN chip 20B are arranged adjacent to each other in the Y direction (first direction).

[0395] As shown in FIGS. 56 to 58, the configuration of the GaN chips 20A, 20B of this modified example is the same as the configuration of the GaN chips 20A, 20B of the first embodiment (see FIG. 2). As in the first embodiment, the GaN chip 20A is provided with a first electromagnetic wave shield 70A, and the GaN chip 20B is provided with a second electromagnetic wave shield 70B. The configurations of the first electromagnetic wave shield 70A and the second electromagnetic wave shield 70B are the same as in the first embodiment. Therefore, it can be said that an electromagnetic wave shield is provided between the GaN chip 20A and the GaN chip 20B.

[0396] As shown in FIGS. 56 and 57, the first sealing resin 60 is formed in a rectangular shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view. As shown in FIG. 58, the substrate back surface 21R of the substrate 21 of the GaN chip 20A is covered by the back surface shield portion 72 of the first electromagnetic wave shield 70A. The substrate back surface 21R of the substrate 21 of the GaN chip 20B is covered by the back surface shield portion 72 of the second electromagnetic wave shield 70B. The substrate back surfaces 21R of the substrate 21 of the GaN chip 20A and the substrate back surfaces 21R of the substrate 21 of the GaN chip 20B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. Therefore, the back surface shield portion 72 of the first electromagnetic wave shield 70A and the back surface shield portion 72 of the second electromagnetic wave shield 70B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. In one example, the substrate back surface 21R of the substrate 21 of the GaN chip 20A, the substrate back surface 21R of the substrate 21 of the GaN chip 20B, and the sealing back surface 60R are flush with one another. In one example, the substrate back surface 21R of the substrate 21 of the GaN chip 20A, the substrate back surface 21R of the substrate 21 of the GaN chip 20B, and the sealing back surface 60R are ground, so that the substrate back surface 21R of the substrate 21 of the GaN chip 20A, the substrate back surface 21R of the substrate 21 of the GaN chip 20B, and the sealing back surface 60R are flush with one another. Therefore, the substrate back surface 21R of the substrate 21 of the GaN chip 20A, the substrate back surface 21R of the substrate 21 of the GaN chip 20B, and the sealing back surface 60R have grinding marks. Both the back surface shield portion 72 of the first electromagnetic wave shield 70A and the back surface shield portion 72 of the second electromagnetic wave shield 70B protrude in the Z direction from the sealing back surface 60R.

[0397] The nitride semiconductor device 10 may include four GaN chips. In this case, the four GaN chips may be configured such that two pairs of GaN chips adjacent to each other in the Y direction (first direction) are arranged spaced apart from each other in the X direction (second direction). The nitride semiconductor device 10 may also include eight or more GaN chips.

[0398] As another example, in the first embodiment, the nitride semiconductor device 10 may include one GaN chip 20. FIGS.

[0399] The nitride semiconductor device 10 includes one GaN chip 20, an electromagnetic wave shield 70Q provided on the GaN chip 20, and a first sealing resin 60 that at least partially seals the GaN chip 20 and the electromagnetic wave shield 70Q.

[0400] As shown in Figures 59 and 60, the configuration of the GaN chip 20 is the same as the configuration of the GaN chip 20A of the first embodiment. As shown in Figures 59 to 61, the configuration of the electromagnetic wave shield 70Q is the same as the configuration of the first electromagnetic wave shield 70A of the first embodiment. The rear surface shield part 72 of the electromagnetic wave shield 70Q is exposed from the first sealing resin 60. The rear surface shield part 72 is provided over most of the sealing rear surface 60R.

[0401] In each embodiment, the substrate back surface 21R of the substrate 21 of at least one of the GaN chips 20A to 20F (20A to 20D) of the nitride semiconductor device 10 does not have to be flush with the sealing back surface 60R of the first sealing resin 60. Also, in the second embodiment, the substrate back surface 91R of the drive substrate 91 of the drive chip 80 does not have to be flush with the sealing back surface 60R of the first sealing resin 60.

[0402] In each embodiment, the substrate back surface 21R of the substrate 21 of at least one of the GaN chips 20A to 20F (GaN chips 20A to 20D in the second embodiment) of the nitride semiconductor device 10 does not have to be exposed from the first sealing resin 60. That is, the first sealing resin 60 may be configured to cover the substrate back surface 21R of the substrate 21 of at least one of the GaN chips 20A to 20F (GaN chips 20A to 20D in the second embodiment). In this case, in the first embodiment, the back surface shield part 72 of the first to sixth electromagnetic wave shields 70A to 70F is provided in a region of the sealing back surface 60R of the first sealing resin 60 that corresponds to the substrate back surface 21R of the substrate 21 of the GaN chips 20A to 20F. That is, the back surface shield part 72 may be provided apart from the substrate 21 of the GaN chips 20A to 20F. In the second embodiment, the rear surface shield parts 72 of the first to fourth electromagnetic wave shields 70A to 70D are provided in regions of the sealing rear surface 60R of the first sealing resin 60 that correspond to the substrate rear surface 21R of the substrate 21 of the GaN chips 20A to 20D. In other words, the rear surface shield parts 72 may be provided apart from the substrate 21 of the GaN chips 20A to 20D.

[0403] Furthermore, in the second embodiment, the substrate back surface 91R of the driving substrate 91 of the driving chip 80 does not have to be exposed from the first sealing resin 60. In other words, the first sealing resin 60 may be configured to cover the substrate back surface 91R of the driving substrate 91. In this case, the back surface shield portion 72 of the electromagnetic wave shield 70P is provided in a region of the sealing back surface 60R of the first sealing resin 60 that corresponds to the substrate back surface 91R of the driving substrate 91. In other words, the back surface shield portion 72 may be provided at a distance from the driving substrate 91.

[0404] In the method for manufacturing the nitride semiconductor device 10 of each embodiment, at least one of the substrate back surface 21R of the substrate 21 of the GaN chips 20A to 20F (GaN chips 20A to 20D in the second embodiment) and the sealing back surface 60R of the first sealing resin 60 may not have grinding marks. In the second embodiment, the substrate back surface 91R of the drive substrate 91 of the drive chip 80 may not have grinding marks.

[0405] In each embodiment, the top surfaces 41S of the source posts 41, the top surfaces 42S of the drain posts 42, and the sealing surface 60S of the first sealing resin 60 in the posts 40 do not have to be flush with each other. In one example, the top surfaces 41S of the source posts 41 and the top surfaces 42S of the drain posts 42 may protrude from the sealing surface 60S.

[0406] In each embodiment, the dimension HA of the wiring sealing layer 61 in the first sealing resin 60 may be equal to the dimension HB of the substrate sealing layer 62. Also, the dimension HA of the wiring sealing layer 61 may be smaller than the dimension HB of the substrate sealing layer 62.

[0407] In each embodiment, the configuration of the gate layer 27 can be changed as desired. In one example, as shown in FIG. 62, the gate layer 27 includes a gate layer main body 27A, a source extension 27B extending from the gate layer main body 27A toward a source contact portion 29A of the source electrode 29 (see FIG. 6), and a drain extension 27C extending from the gate layer main body 27A toward the drain electrode 30 (see FIG. 6). The gate layer main body 27A includes an upper surface 27S of the gate layer 27. A lower surface 27R of the gate layer 27 is formed by the lower surface of the gate layer main body 27A, the lower surface of the source extension 27B, and the lower surface of the drain extension 27C. Therefore, the lower surface 27R of the gate layer 27 has a larger area than the upper surface 27S.

[0408] The gate layer main body 27A is located between the source extension 27B and the drain extension 27C, and is provided integrally with the source extension 27B and the drain extension 27C. The gate layer main body 27A corresponds to a relatively thick portion of the gate layer 27.

[0409] Both the source extension portion 27B and the drain extension portion 27C are thinner than the gate layer main body portion 27A. Both the source extension portion 27B and the drain extension portion 27C may have a thickness equal to or less than half the thickness of the gate layer main body portion 27A. The drain extension portion 27C may extend further outward from the gate layer main body portion 27A than the source extension portion 27B in a planar view. That is, the drain extension portion 27C may have a larger dimension in the X direction than the source extension portion 27B. The source extension portion 27B may have a dimension in the X direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the drain extension portion 27C may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.6 μm or less.

[0410] 62, one of the source extension portion 27B and the drain extension portion 27C may be omitted from the gate layer 27. When the gate layer 27 includes one of the source extension portion 27B and the drain extension portion 27C, local electric field concentration in the gate layer 27 can be suppressed.

[0411] In each embodiment, the number of gate pads 37 of the nitride semiconductor device 10 can be changed as desired. In one example, the nitride semiconductor device 10 may include one gate pad 37.

[0412] In the first embodiment, the source post 41 of the GaN chip 20A and the drain post 42 of the GaN chip 20B may be electrically connected by, for example, a wire or a clip. The source post 41 of the GaN chip 20C and the drain post 42 of the GaN chip 20D may be electrically connected by, for example, a wire or a clip. The source post 41 of the GaN chip 20E and the drain post 42 of the GaN chip 20F may be electrically connected by, for example, a wire or a clip. The connection structure of the posts 40 of the GaN chips 20A to 20D of the second embodiment can also be modified in a similar manner.

[0413] [Modification of the manufacturing method of the semiconductor device] Before forming the connection wiring layer 51, the resin layer 860 may be cut to include the plurality of chip formation regions 821A, thereby dividing the nitride semiconductor device 10 into individual pieces.

[0414] The resin layer 860 may be formed by transfer molding or compression molding so that the upper surfaces of the posts 40 are exposed from the resin layer 860. In this case, the step of grinding both the upper surfaces 860S of the resin layer 860 and the upper surfaces of the posts 40 is omitted.

[0415] [Example of semiconductor module change] The driving chip 160 may be provided with an electromagnetic wave shield 70. In this case, the driving chip 160 includes a chip front surface, a chip back surface opposite the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface. The electromagnetic wave shield 70 includes, for example, a side shield portion 71 provided on one of the chip side surfaces facing the nitride semiconductor device 10. In one example, the electromagnetic wave shield 70 includes a side shield portion 71 provided on each of the plurality of chip side surfaces. In another example, the electromagnetic wave shield 70 includes a back shield portion 72 provided on the chip back surface. The electromagnetic wave shield 70 provided on the driving chip 160 may have a configuration in which the side shield portion 71 and the back shield portion 72 are connected to each other.

[0416] The control chip 170 may be provided with an electromagnetic wave shield 70. In this case, the control chip 170 includes a chip front surface, a chip back surface opposite the chip front surface, and multiple chip side surfaces connecting the chip front surface and the chip back surface. The electromagnetic wave shield 70 includes, for example, a side shield portion 71 provided on the chip side surface facing the drive chip 160 among the multiple chip side surfaces. In one example, the electromagnetic wave shield 70 includes a side shield portion 71 provided on each of the multiple chip side surfaces. In another example, the electromagnetic wave shield 70 includes a back shield portion 72 provided on the chip back surface. The electromagnetic wave shield 70 provided on the drive chip 160 may have a configuration in which the side shield portion 71 and the back shield portion 72 are connected to each other.

[0417] The nitride semiconductor device 10 and the driver chip 160 may be electrically connected to each other outside the semiconductor module 100 . The driving chip 160 and the control chip 170 may be electrically connected to each other outside the semiconductor module 100 .

[0418] The control chip 170 may be omitted from the semiconductor module 100. In this case, instead of the second connection wiring 122 and the control wiring 124, third connection wiring is provided on the support substrate 110, which electrically connects the drive chip 160 and the plurality of control terminals 150 individually.

[0419] The boot terminals 146 to 148 may be omitted from the semiconductor module 100. In this case, the boot wiring 125 may also be omitted. The second sealing resin 180 may be omitted from the semiconductor module 100.

[0420] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be placed directly on the second element in contact with the second element, while in other embodiments, the first element may be placed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0421] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0422] <Additional Notes> The technical ideas that can be understood from the above-described embodiments and modifications are described below. The reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0423] [Appendix 1] a first sealing resin (60); a first GaN chip (20A) and a second GaN chip (20B) provided in the first sealing resin (60) and spaced apart from each other in a first direction (Y) perpendicular to a thickness direction (Z) of the first sealing resin (60); Including, An electromagnetic wave shield (70 / 70A, 70B) is provided in the first sealing resin (60) between the first GaN chip (20A) and the second GaN chip (20B) in the first direction (Y). Nitride semiconductor device (10).

[0424] [Appendix 2] each of the first GaN chip (20A) and the second GaN chip (20B) includes a plurality of chip side surfaces (20PA to 20PD); the plurality of chip side surfaces (20PA to 20PD) of the first GaN chip (20A) include a first opposing surface (20PC) that faces the second GaN chip (20B) in the first direction (Y), the plurality of chip side surfaces (20PA to 20PD) of the second GaN chip (20B) include a second opposing surface (20PD) that faces the first GaN chip (20A) in the first direction (Y), The electromagnetic wave shield (70 / 70A, 70B) is a first electromagnetic wave shield (70A) including a side shield portion (71) provided on the first opposing surface (20PC); a second electromagnetic wave shield (70B) including a side shield portion (71) provided on the second opposing surface (20PD); Contains 2. The nitride semiconductor device according to claim 1.

[0425] [Appendix 3] each of the first GaN chip (20A) and the second GaN chip (20B) includes a plurality of chip side surfaces (20PA to 20PD); The electromagnetic wave shield (70 / 70A, 70B) includes a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD). 2. The nitride semiconductor device according to claim 1.

[0426] [Appendix 4] The side shield part (71) is provided over the entire chip side surface (20PA to 20PD) in the thickness direction (Z). 4. The nitride semiconductor device according to claim 2 or 3.

[0427] [Appendix 5] The side shield part (71) includes a protruding part (71P) protruding above the chip side surface (20PA to 20PD) in the thickness direction (Z). 5. The nitride semiconductor device according to any one of claims 2 to 4.

[0428] [Appendix 6] The protrusion (71P) is disposed outward from the chip surface (20S). 6. The nitride semiconductor device according to claim 5.

[0429] [Appendix 7] The side shield portion (71) is made of a metal layer. 7. The nitride semiconductor device according to any one of claims 2 to 6.

[0430] [Appendix 8] The metal layer is a seed layer (71A) provided on the chip side surface (20PA to 20PD); a plating layer (71B) provided on the seed layer (71A); Contains 8. The nitride semiconductor device according to claim 7.

[0431] [Appendix 9] The side shield portion (71) is made of a metal layer, The metal layer is a seed layer (71A) provided on the chip side surface (20PA to 20PD); a plating layer (71B) provided on the seed layer (71A); Including, the side shield part (71) includes a protruding part (71P) protruding above the chip side surface (20PA to 20PD) in the thickness direction (Z), The plating layer (71B) on the protruding portion (71P) covers the surface of the seed layer (71A). 5. The nitride semiconductor device according to any one of claims 2 to 4.

[0432] [Appendix 10] The plating layer (71B) is made of a material containing Cu. 10. The nitride semiconductor device according to claim 8 or 9.

[0433] [Appendix 11] The seed layer (71A) has a laminated structure of a Ti layer and a Cu layer. 11. The nitride semiconductor device according to any one of claims 8 to 10.

[0434] [Appendix 12] The thickness (T6) of the side shield part (71) is 1 μm or more. 12. The nitride semiconductor device according to any one of claims 2 to 11.

[0435] [Appendix 13] Each of the first GaN chip (20A) and the second GaN chip (20B) Chip surface (20S) and a chip back surface (20R) opposite to the chip front surface (20S); a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S) and constituting the chip back surface (20R); Including, The electromagnetic wave shield (70 / 70A, 70B) includes a rear surface shield portion (72) provided on the substrate rear surface (21R) of the substrate (21) of each of the first GaN chip (20A) and the second GaN chip (20B). 7. The nitride semiconductor device according to any one of claims 2 to 6.

[0436] [Appendix 14] The rear surface shield part (72) is provided over the entire rear surface (21R) of the substrate. 14. The nitride semiconductor device according to claim 13.

[0437] [Appendix 15] The area of ​​the rear shield part (72) is larger than the area of ​​the rear surface (21R) of the substrate. 15. The nitride semiconductor device according to claim 14.

[0438] [Appendix 16] The rear shield part (72) is connected to the side shield part (71). 16. The nitride semiconductor device according to any one of claims 13 to 15.

[0439] [Appendix 17] The rear surface shield part (72) provided on the substrate rear surface (21R) of the substrate (21) of the first GaN chip (20A) and the rear surface shield part (72) provided on the substrate rear surface (21R) of the substrate (21) of the second GaN chip (20B) are spaced apart from each other in the first direction (X). 17. The nitride semiconductor device according to any one of claims 13 to 16.

[0440] [Appendix 18] Each of the first GaN chip (20A) and the second GaN chip (20B) is provided with a GaN transistor (22), the rear surface shield portion (72) provided on the substrate rear surface (21R) of the substrate (21) of the first GaN chip (20A) is electrically connected to the source of the GaN transistor (22) of the first GaN chip (20A); The rear surface shield portion (72) provided on the rear surface (21R) of the substrate (21) of the second GaN chip (20B) is electrically connected to the source of the GaN transistor (22) of the second GaN chip (20B). 18. The nitride semiconductor device according to any one of claims 13 to 17.

[0441] [Appendix 19] The rear shield part (72) is made of a metal layer. 19. The nitride semiconductor device according to any one of claims 13 to 18.

[0442] [Appendix 20] The metal layer is formed of a sputtered film (72A) provided on the rear surface (21R) of the substrate. 20. The nitride semiconductor device according to claim 19.

[0443] [Appendix 21] The sputtered film (72A) is composed of a laminated structure of a Ti film and a Cu film. 21. The nitride semiconductor device according to claim 20.

[0444] [Appendix 22] The first sealing resin (60) has a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S), The rear shield portion (72) is exposed from the sealing rear surface (60R). 22. The nitride semiconductor device according to any one of claims 13 to 21.

[0445] [Appendix 23] The rear shield portion (72) protrudes from the sealing rear surface (60R) in the thickness direction (Z). 23. The nitride semiconductor device according to claim 22.

[0446] [Appendix 24] The thickness of the rear shield part (72) is 1 μm or more. 24. The nitride semiconductor device according to any one of claims 13 to 23.

[0447] [Appendix 25] Each of the first GaN chip (20A) and the second GaN chip (20B) Chip surface (20S) and a chip back surface (20R) opposite to the chip front surface (20S); a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S) and constituting the chip back surface (20R); a GaN transistor (22) provided on the substrate surface (21S); a wiring layer (34) provided on the GaN transistor (22) and electrically connected to the GaN transistor (22); Contains 13. The nitride semiconductor device according to any one of claims 1 to 12.

[0448] [Appendix 26] The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is smaller than both the thickness of the first GaN chip (20A) and the thickness of the second GaN chip (20B). 26. The nitride semiconductor device according to claim 25.

[0449] [Appendix 27] The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is smaller than the thickness (T1) of the substrate (21). 26. The nitride semiconductor device according to claim 25.

[0450] [Appendix 28] The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is smaller than the thickness (T3) of the wiring layer (34). 26. The nitride semiconductor device according to claim 25.

[0451] [Appendix 29] each of the first GaN chip (20A) and the second GaN chip (20B) includes a plurality of chip side surfaces (20PA to 20PD); the electromagnetic wave shield (70 / 70A, 70B) includes a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD), The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is greater than twice the thickness (T6) of the side shield part (71). 26. The nitride semiconductor device according to claim 25.

[0452] [Appendix 30] a post (40) provided on a source pad (35), a drain pad (36), and a gate pad (37) of each of the GaN transistors (22) and exposed from the first sealing resin (60); The post (40) includes a predetermined width; The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is smaller than the width dimension of the post (40). 26. The nitride semiconductor device according to claim 25.

[0453] [Appendix 31] a source pad (35), a drain pad (36), and a gate pad (37) electrically connected to each of the GaN transistors (22) include a predetermined width; The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is smaller than the width dimension of the source pad (35), the width dimension of the drain pad (36), and the width dimension of the gate pad (37). 26. The nitride semiconductor device according to claim 25.

[0454] [Appendix 32] The shortest distance (DA) between the first GaN chip (20A) and the second GaN chip (20B) is 10 μm or more and 50 μm or less. 32. The nitride semiconductor device according to any one of claims 1 to 31.

[0455] [Appendix 33] a step portion (20PE) is provided between the substrate (21) and the wiring layer (34); A distance (TA) between the wiring layer (34) of the first GaN chip (20A) and the wiring layer (34) of the second GaN chip (20B) is greater than a distance (TB) between the substrate (21) of the first GaN chip (20A) and the substrate (21) of the second GaN chip (20B). 32. The nitride semiconductor device according to any one of claims 25 to 31.

[0456] [Appendix 34] The electromagnetic wave shield (70 / 70A, 70B) is provided so as to cover the step portion (20PE). 34. The nitride semiconductor device according to claim 33.

[0457] [Appendix 35] a post (40) provided on a source pad (35), a drain pad (36), and a gate pad (37) electrically connected to each of the GaN transistors (22), the post (40) being exposed from the first sealing resin (60); The post (40) a source post (41) formed on the source pad (35) of the second GaN chip (20B); a drain post (42) formed on the drain pad (36) of the first GaN chip (20A); Including, the first sealing resin (60) includes a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S), A connection wiring layer (51) is provided on the sealing surface (60S) and electrically connects the source post (41) and the drain post (42) to each other. 26. The nitride semiconductor device according to claim 25.

[0458] [Appendix 36] The top surface (41S) of the source post (41), the top surface (42S) of the drain post (42), and the sealing surface (60S) are flush with each other. 36. The nitride semiconductor device according to claim 35.

[0459] [Appendix 37] a first sealing resin (60) having a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S); a first GaN chip (20A) and a second GaN chip (20B) provided in the first sealing resin (60) and spaced apart from each other in a first direction (Y) perpendicular to a thickness direction (Z) of the first sealing resin (60); Including, Each of the first GaN chip (20A) and the second GaN chip (20B) a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S); a GaN transistor (22) provided on the substrate surface (21S); Including, An electromagnetic wave shield (70 / 70A, 70B) is provided on the rear surface (21R) of the substrate of each of the first GaN chip (20A) and the second GaN chip (20B). Nitride semiconductor device (10).

[0460] [Appendix 38] a driving chip (80) that drives the first GaN chip (20A) and the second GaN chip (20B); The first sealing resin (60) seals the first GaN chip (20A), the second GaN chip (20B), and the driver chip (80). 38. The nitride semiconductor device according to any one of claims 1 to 37.

[0461] [Appendix 39] The electromagnetic wave shields (70 / 70A, 70B, 70P) are arranged between the first GaN chip (20A) and the drive chip (80) and between the second GaN chip (20B) and the drive chip (80). 39. The nitride semiconductor device according to claim 38.

[0462] [Appendix 40] The driving chip (80) Chip surface (80S) and a chip back surface (80R) opposite to the chip front surface (80S); a drive substrate (91) having a substrate surface (91S) and a substrate back surface (91R) opposite to the substrate surface (91S) and constituting the chip back surface (80R); The electromagnetic wave shield (70 / 70P) includes a rear shield portion (72) provided on the rear surface (91R) of the drive substrate (91). 39. The nitride semiconductor device according to claim 39.

[0463] [Appendix 41] a third GaN chip (20C) and a fourth GaN chip (20D) sealed with the first sealing resin (60); a driver chip (80) that is sealed with the first sealing resin (60) and drives the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D); Including, The first GaN chip (20A) and the second GaN chip (20B) are arranged side by side in the first direction (Y), the third GaN chip (20C) and the fourth GaN chip (20D) are arranged side by side in the first direction (Y), The drive chip (80) is disposed between the first GaN chip (20A) and the second GaN chip (20B) in the first direction (Y) and between the third GaN chip (20C) and the fourth GaN chip (20D) in the first direction (Y). 38. The nitride semiconductor device according to any one of claims 1 to 37.

[0464] [Appendix 42] Electromagnetic wave shields (70 / 70A to 70D, 70P) are provided between the first GaN chip (20A) and the third GaN chip (20C) and the drive chip (80), and between the second GaN chip (20B) and the fourth GaN chip (20D) and the drive chip (80). 42. The nitride semiconductor device according to claim 41.

[0465] [Appendix 43] a third GaN chip (20C) and a fourth GaN chip (20D) sealed with the first sealing resin (60); a driver chip (80) that is sealed with the first sealing resin (60) and drives the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D); Including, The first GaN chip (20A) and the second GaN chip (20B) are arranged side by side in the first direction (Y), the third GaN chip (20C) and the fourth GaN chip (20D) are arranged side by side in the first direction (Y), the drive chip (80) is disposed between the first GaN chip (20A) and the second GaN chip (20B) in the first direction (Y) and between the third GaN chip (20C) and the fourth GaN chip (20B) in the first direction (Y); each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) includes a plurality of chip side surfaces (20PA to 20PD); the plurality of chip side surfaces (20PA to 20PD) of the first GaN chip (20A) include a first chip opposing surface (20PC) that faces the driver chip (80) in the first direction (Y), the plurality of chip side surfaces (20PA to 20PD) of the second GaN chip (20B) include a second chip facing surface (20PD) facing the driver chip (80) in the first direction (Y), the plurality of chip side surfaces (20PA to 20PD) of the third GaN chip (20C) include a third chip facing surface (20PC) facing the driver chip (80) in the first direction (Y), the plurality of chip side surfaces (20PA to 20PD) of the fourth GaN chip (20D) include a fourth chip facing surface (20PD) facing the driver chip (80) in the first direction (Y), The electromagnetic wave shield (70 / 70A to 70D) is a first electromagnetic wave shield (70A) including a side shield portion (71) provided on the first chip facing surface (20PC); a second electromagnetic wave shield (70B) including a side shield portion (71) provided on the second chip-facing surface (20PD); a third electromagnetic wave shield (70C) including a side shield portion (71) provided on the third chip-opposing surface (20PC); a fourth electromagnetic wave shield (70D) including a side shield portion (71) provided on the fourth chip-facing surface (20PD); Contains 2. The nitride semiconductor device according to claim 1.

[0466] [Appendix 44] The driving chip (80) includes a plurality of chip side surfaces (80A to 80D), The plurality of chip side surfaces (80A to 80D) of the driver chip (80) are a fifth chip-facing surface (80D) facing the first GaN chip (20A) and the third GaN chip (20C) in the first direction (Y); a sixth chip-facing surface (80C) facing the second GaN chip (20B) and the fourth GaN chip (20D) in the first direction (Y); Including, The electromagnetic wave shield (70 / 70P) includes side shield portions (71) provided on the fifth chip-facing surface (80D) and the sixth chip-facing surface (80C). 44. The nitride semiconductor device according to claim 43.

[0467] [Appendix 45] each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) includes a plurality of chip side surfaces (20PA to 20PD); The electromagnetic wave shield (70 / 70A to 70D) is a first electromagnetic wave shield (70A) including a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD) of the first GaN chip (20A); a second electromagnetic wave shield (70B) including a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD) of the second GaN chip (20B); a third electromagnetic wave shield (70C) including a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD) of the third GaN chip (20C); a fourth electromagnetic wave shield (70D) including a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD) of the fourth GaN chip (20D); Contains 43. The nitride semiconductor device according to claim 42.

[0468] [Appendix 46] The driving chip (80) includes a plurality of chip side surfaces (80A to 80D), The electromagnetic wave shield (70 / 70P) includes a side shield portion (71) provided on each of the plurality of chip side surfaces (80A to 80D) of the driver chip (80). 46. ​​The nitride semiconductor device according to claim 42 or 45.

[0469] [Appendix 47] Each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) is Chip surface (20S) and a chip back surface (20R) opposite to the chip front surface (20S); a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S) and constituting the chip back surface (20R); Including, the first electromagnetic wave shield (70A) includes a rear surface shield portion (72) provided on the substrate rear surface (21R) of the substrate (21) of the first GaN chip (20A), the second electromagnetic wave shield (70B) includes a rear surface shield portion (72) provided on the substrate rear surface (21R) of the substrate (21) of the second GaN chip (20B), the third electromagnetic wave shield (70C) includes a rear surface shield portion (72) provided on the substrate rear surface (21R) of the substrate (21) of the third GaN chip (20C), The fourth electromagnetic wave shield (70D) includes a rear surface shield portion (72) provided on the rear surface (21R) of the substrate (21) of the fourth GaN chip (20D). 44. The nitride semiconductor device according to claim 43.

[0470] [Appendix 48] The rear surface shield portion (72) of the first electromagnetic wave shield (70A), the rear surface shield portion (72) of the second electromagnetic wave shield (70B), the rear surface shield portion (72) of the third electromagnetic wave shield (70C), and the rear surface shield portion (72) of the fourth electromagnetic wave shield (70D) are arranged apart from one another. 48. The nitride semiconductor device according to claim 47.

[0471] [Appendix 49] the side shield portion (71) and the back shield portion (72) of the first electromagnetic wave shield (70A) are connected to each other, the side shield portion (71) and the back shield portion (72) of the second electromagnetic wave shield (70B) are connected to each other, the side shield portion (71) and the rear shield portion (72) of the third electromagnetic wave shield (70C) are connected to each other, The side shield portion (71) and the rear shield portion (72) of the fourth electromagnetic wave shield (70D) are connected to each other. 49. The nitride semiconductor device according to claim 47 or 48.

[0472] [Appendix 50] The driving chip (80) Chip surface (80S) and a chip back surface (80R) opposite to the chip front surface (80S); a drive substrate (91) having a substrate surface (91S) and a substrate back surface (91R) opposite to the substrate surface (91S) and constituting the chip back surface (80R); Including, The electromagnetic wave shield (70 / 70P) includes a rear shield portion (72) provided on the rear surface (91R) of the drive substrate (91). 47. The nitride semiconductor device according to claim 46.

[0473] [Appendix 51] The side shield portion (71) and the back shield portion (72) of the electromagnetic wave shield (70P) provided on the drive chip (80) are connected to each other. 51. The nitride semiconductor device according to claim 50.

[0474] [Appendix 52] the first sealing resin (60) includes a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S), The back surface shield portion (72) of the electromagnetic wave shield (70P) provided on the drive chip (80) is exposed from the sealing back surface (60R). 52. The nitride semiconductor device according to claim 50 or 51.

[0475] [Appendix 53] the first GaN chip (20A) is disposed at a position facing the second GaN chip (20B) in the first direction (Y), The third GaN chip (20C) is disposed at a position facing the fourth GaN chip (20D) in the first direction (Y). 53. The nitride semiconductor device according to any one of claims 41 to 52.

[0476] [Appendix 54] each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) includes a GaN transistor (22); a first connection wiring layer (51A) that electrically connects the drain of the GaN transistor (22) of the first GaN chip (20A) and the source of the GaN transistor (22) of the second GaN chip; a second connection wiring layer (51B) that electrically connects the drain of the GaN transistor (22) of the third GaN chip (20C) and the source of the GaN transistor (22) of the fourth GaN chip (20D); Including, Both the first connection wiring layer (51A) and the second connection wiring layer (51B) extend in the first direction (Y) across the driver chip (80). 54. The nitride semiconductor device according to claim 53.

[0477] [Appendix 55] The driving chip (80) includes a plurality of pads (81A to 81D, 82, 83A, 84A to 84E, 85A, 85B), Some of the pads (81A to 81D, 82, 83A, 84A to 84E, 85A, 85B) are disposed between the first connection wiring layer (51A) and the second connection wiring layer (51B). 55. The nitride semiconductor device according to claim 54.

[0478] [Appendix 56] the first sealing resin (60) includes a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S), The first connection wiring layer (51A), the second connection wiring layer (51B), and the plurality of pads (81A to 81D, 82, 83A, 84A to 84E, 85A, 85B) are exposed from the sealing surface (60S). 56. The nitride semiconductor device according to claim 55.

[0479] [Appendix 57] each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) includes a GaN transistor (22); the drain of the GaN transistor (22) of the first GaN chip (20A) and the drain of the GaN transistor (22) of the third GaN chip (20C) are electrically connected; the source of the GaN transistor (22) of the second GaN chip (20B) and the source of the GaN transistor (22) of the fourth GaN chip (20D) are electrically connected; the source of the GaN transistor (22) of the first GaN chip (20A) is electrically connected to the drain of the GaN transistor (22) of the second GaN chip (20B); The source of the GaN transistor (22) of the third GaN chip (20C) is electrically connected to the drain of the GaN transistor (22) of the fourth GaN chip (20D). 54. The nitride semiconductor device according to any one of claims 41 to 53.

[0480] [Appendix 58] a drain wiring layer (53) that electrically connects the drain of the GaN transistor (22) of the first GaN chip (20A) and the drain of the GaN transistor (22) of the third GaN chip (20C); a source wiring layer (52) that electrically connects the source of the GaN transistor (22) of the second GaN chip (20B) and the source of the GaN transistor (22) of the fourth GaN chip (20D); Including, The drain wiring layer (53) and the source wiring layer (52) are disposed at positions different from the driver chip (80) in the first direction (Y). 58. The nitride semiconductor device according to claim 57.

[0481] [Appendix 59] the first sealing resin (60) includes a sealing surface (60S) and a sealing back surface (60R) opposite to the sealing surface (60S), Both the drain wiring layer (53) and the source wiring layer (52) are exposed from the sealing surface (60S). 59. The nitride semiconductor device according to claim 58.

[0482] [Appendix 60] Each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D) is Chip surface (20S) and a chip back surface (20R) opposite to the chip front surface (20S); a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S) and constituting the chip back surface (20R); Including, The driving chip (80) Chip surface (80S) and a chip back surface (80R) opposite to the chip front surface (80S); a drive substrate (91) having a substrate surface (91S) and a substrate back surface (91R) opposite to the substrate surface (91S) and constituting the chip back surface (80R); Including, The drive substrate (91) has the same configuration as the substrate (21) of each of the first GaN chip (20A), the second GaN chip (20B), the third GaN chip (20C), and the fourth GaN chip (20D). 47. The nitride semiconductor device according to any one of notes 41 to 46.

[0483] [Appendix 61] a first sealing resin (60); a GaN chip (20) provided in the first sealing resin (60); Including, The GaN chip (20) includes a plurality of chip side surfaces (20PA to 20PD), An electromagnetic wave shield (70) is provided on at least one of the chip side surfaces (20PA to 20PD). Nitride semiconductor device (10).

[0484] [Appendix 62] The electromagnetic wave shield (70) includes a side shield portion (71) provided on each of the plurality of chip side surfaces (20PA to 20PD). 62. The nitride semiconductor device according to claim 61.

[0485] [Appendix 63] The GaN chip (20) Chip surface (20S) and a chip back surface (20R) opposite to the chip front surface (20S); a substrate (21) having a substrate surface (21S) and a substrate back surface (21R) opposite to the substrate surface (21S) and constituting the chip back surface (20R); Including, The electromagnetic wave shield (70) includes a rear shield portion (72) provided on the rear surface (21R) of the substrate (21). 63. The nitride semiconductor device according to claim 61 or 62.

[0486] [Appendix 64] a support substrate (110); A nitride semiconductor device (10) according to any one of Supplementary Notes 1 to 37, disposed on the support substrate (110); a driver chip (160) disposed on the support substrate (110) and driving the nitride semiconductor device (10); a control chip (170) disposed on the support substrate (110) and electrically connected to the drive chip (160); a second sealing resin (180) that seals the nitride semiconductor device (10), the drive chip (160), and the control chip (170); A semiconductor module (100).

[0487] [Appendix 65] An electromagnetic wave shield (70 / 70B, 70D) is provided between the nitride semiconductor device (10) and the driver chip (160). 65. The semiconductor module of claim 64.

[0488] [Appendix 66] An electromagnetic wave shield (70) is provided between the driving chip (160) and the control chip (170). 66. The semiconductor module of claim 64 or 65.

[0489] [Appendix 67] a first connection wiring (121) provided on the support substrate (110) and electrically connecting the drive chip (160) and the nitride semiconductor device (10); a second connection wiring (122) provided on the support substrate (110) and electrically connecting the control chip (170) and the drive chip (160); Equipped with 67. The semiconductor module according to any one of claims 64 to 66.

[0490] [Appendix 68] The support substrate (110) has a support substrate front surface (110S) and a support substrate back surface (110R) facing the opposite side to the support substrate front surface (110S), drive terminals (141, 142) and a control terminal (150) provided on the rear surface (110R) of the support substrate; a driving wiring (123) provided on the surface (110S) of the support substrate and electrically connected to the nitride semiconductor device (10); a control wiring (124) provided on the surface (110S) of the support substrate and electrically connected to the control chip (170); a drive through wiring (131) that penetrates the support substrate (110) in the thickness direction (Z) of the support substrate (110) and electrically connects the drive terminals (141, 142) and the drive wiring (123); a control through-wire (132) that penetrates the support substrate (110) in the thickness direction (Z) of the support substrate (110) and electrically connects the control terminal (150) and the control wire (124); Equipped with 68. The semiconductor module of claim 67.

[0491] [Appendix 69] Boot terminals (146-148) provided on the rear surface (110R) of the support substrate; a boot wiring (125) provided on the surface (110S) of the support substrate and electrically connected to the driver chip (160); a boot through wiring (133) that penetrates the support substrate (110) in the thickness direction (Z) of the support substrate (110) and electrically connects the boot terminals (146-148) and the boot wiring (125); Equipped with 69. The semiconductor module of claim 68.

[0492] [Appendix 70] Preparing a wafer (821) having a wafer front surface (821S) and a wafer back surface (821R) opposite to the wafer front surface (821S), the wafer (821) including a plurality of chip formation regions (821A) on the wafer front surface (821S) side in which GaN transistors (22) are formed; forming a groove (821B) between adjacent chip forming regions (821A); forming metal layers (900, 910) on the side and bottom surfaces of the groove (821B); forming a resin layer (860) so as to fill the groove (821B) and cover the wafer (821); grinding the rear surface of the wafer so that the resin layer and the metal layers on the side surfaces of the grooves are exposed; A method for manufacturing a nitride semiconductor device (10), comprising:

[0493] [Appendix 71] Forming the metal layer (900, 910) includes forming the metal layer (900, 910) by electrolytic plating. 71. A method for manufacturing a nitride semiconductor device according to claim 70.

[0494] [Appendix 72] forming the metal layers (900, 910) forming a seed layer (900) on the wafer surface (821S) and the side and bottom surfaces of the grooves (821B); forming a plating layer (910) on portions of the seed layer (900) corresponding to the side and bottom surfaces of the groove (821B) by electrolytic plating; Contains 72. A method for manufacturing a nitride semiconductor device according to claim 71.

[0495] [Appendix 73] forming posts (40) on the wafer surface (821S); removing portions of the seed layer (900) exposed from both the posts (40) and the plating layer (910); Contains 73. A method for manufacturing a nitride semiconductor device according to claim 72.

[0496] [Appendix 74] The method further includes forming a sputtered film (72A) by sputtering on the wafer rear surface (821R) after the wafer rear surface (821R) has been ground. 74. A method for manufacturing a nitride semiconductor device according to any one of claims 70 to 73.

[0497] [Appendix 75] The sputtered film (72A) is formed so as to connect to the metal layers (71A, 71B) exposed from the rear surface (21R) of the wafer. 75. A method for manufacturing a nitride semiconductor device according to claim 74.

[0498] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0499] 10...Nitride semiconductor device 20, 20A~20F...GaN chip 20PA~20PD...1st to 4th chip sides 20PE...Stepped part 20S: Chip surface 20R...Chip backside 21... Circuit board 21S…Substrate surface 21R...Back side of board 22...GaN transistor 23...Buffer layer 24...Electron transit layer 25…electron supply layer 26...Two-dimensional electron gas (2DEG) 27...Gate layer 27A...Gate layer main body 27B…Source extension part 27C...Drain extension 27S…Top surface 27R…Bottom surface 28...Gate electrode 29...Source electrode 30...Drain electrode 31...First insulating film 31A…Opening 32...Second insulating film 32A…1st opening 32B…Second opening 33...Third insulating film 34...Wiring layer 34A...Fourth insulating film 34S...Source wiring section 34D...Drain wiring section 34G...Gate wiring section 35...Sauce pad 36...Drain pad 37...Gate pad 38...Cell area 38A…Active area 38B...Inactive area 39...5th insulating film 39S…Surface 40...Post 40A...seed layer 40B...plated layer 41...Sauce post 41S…Top surface 42...Drain post 42S…Top surface 43...Gate post 43S…Top surface 50, 50U, 50V, 50W...external wiring layer 50A…seed layer 50B, 50C...plated layer 51, 51A, 51B, 51U, 51V, 51W...Connection wiring layer 52, 52U, 52V, 52W...Source wiring layer 53, 53U, 53V, 53W...Drain wiring layer 54, 54A, 54B, 54U, 54V, 54W...First gate wiring layer 55, 55A, 55B, 55U, 55V, 55W...Second gate wiring layer 60...First sealing resin 60S…Sealing surface 60R…Sealing back side 60A~60D...1st~4th sealing side 61...Wiring sealing layer 62...Substrate sealing layer 70, 70P, 70Q...Electromagnetic wave shield 70A~70F...1st to 6th electromagnetic wave shields 71...Side shield part 71A...Seed layer 71B...plated layer 71P…Protrusion 71Q...Board shield section 71R...Wiring shield section 71S...Step shield section 72...Back shield 72A...Sputtered film 80...Drive chip 80S: Chip surface 80R...Chip backside 80A~80D...Chip side 80E...Stepped section 81A~81D...Gate pad 82...Sauce Pad 83A, 83B...Boot pad 84A~84E, 85A, 85B...Input pads 91...Drive board 91S...Substrate surface 91R...Back of the board 92...Drive circuit 93...Third insulating film 94...Wiring layer 95...5th insulating film 96...Step 100...Semiconductor module 110...Support substrate 110S…Support substrate surface 110R…Back side of support board 110A~110D...1st~4th support board side 121...First connection wiring 121A...Gate connection wiring 121B...Output connection wiring 122...Second connection wiring 123...Drive wiring 123A...First drive wiring 123B...Second drive wiring 124...Control wiring 125...Boot wiring 126…Wiring for first terminal 127…Wiring for second terminal 131...Drive through wiring 131A...First drive through wiring 131B...Second drive through wiring 132...Control through wiring 133...Boot through wiring 134...Through wiring for first terminal 135...Through wiring for second terminal 136...Output through wiring 141, 142...Drive terminals 143~145...Output terminals 146~148...Boot terminals 150...Control terminal 160...Drive chip 170...Control chip 180…Second sealing resin 821...wafer 821A: Chip formation area 821B…Groove 821S...wafer surface 821R...Wafer backside 823...Buffer layer 824...Electron transit layer 825…electron supply layer 827...Nitride semiconductor layer 828...Electrode layer 829…Metal layer 831...First insulating film 832...Second insulating film 833...Third insulating film 834...Wiring layer 834A...Fourth insulating film 839...5th insulating film 840...Resist mask 840A…Opening 841...Resist mask 842...Dry film resist 842A…Opening 843...Dry film resist 843A…Opening 844...Dry film resist 844A, 844B…Opening 845...Dry film resist 845A…Opening 860...Resin layer 900…Seed layer 910...plated layer BC: Boot capacitor BD: Boot diode C1, C2...capacitors CV: Control power supply DV: Drive power supply GD1, GD2...Driver circuit SD: Conductive adhesive R1: Resistor DA~DE...shortest distance D1~D10…Shortest distance T1: Thickness of the board T2: Thickness of the third insulating film T3: Thickness of the wiring layer T4: Thickness of the fifth insulating film T5: Thickness of the outer wiring layer T6: Thickness of side shield T7: Thickness of rear shield TA: distance between wiring layers TB... Groove width dimension CL…cutting line

Claims

1. a first sealing resin; a first GaN chip and a second GaN chip provided in the first sealing resin and spaced apart from each other in a first direction perpendicular to a thickness direction of the first sealing resin; Including, An electromagnetic wave shield is provided in the first sealing resin between the first GaN chip and the second GaN chip in the first direction. Nitride semiconductor devices.

2. each of the first GaN chip and the second GaN chip includes a plurality of chip side surfaces; the plurality of chip side surfaces of the first GaN chip include a first opposing surface that faces the second GaN chip in the first direction; the plurality of chip side surfaces of the second GaN chip include a second opposing surface that faces the first GaN chip in the first direction; The electromagnetic wave shield is a first electromagnetic wave shield including a side shield portion provided on the first opposing surface; a second electromagnetic wave shield including a side shield portion provided on the second opposing surface; Contains The nitride semiconductor device according to claim 1 .

3. each of the first GaN chip and the second GaN chip includes a plurality of chip side surfaces; The electromagnetic wave shield includes a side shield portion provided on each of the plurality of chip side surfaces. The nitride semiconductor device according to claim 1 .

4. The side shield portion is provided over the entire side surface of the chip in the thickness direction. The nitride semiconductor device according to claim 2 .

5. The side shield part includes a protruding part that protrudes above the chip side surface in the thickness direction. The nitride semiconductor device according to claim 2 .

6. The protrusion is disposed outward from the chip surface. The nitride semiconductor device according to claim 5 .

7. The side shield portion is made of a metal layer. The nitride semiconductor device according to claim 2 .

8. The metal layer is a seed layer provided on a side surface of the chip; a plating layer provided on the seed layer; Contains The nitride semiconductor device according to claim 7 .

9. the side shield portion is made of a metal layer, The metal layer is a seed layer provided on a side surface of the chip; a plating layer provided on the seed layer; Including, the side shield part includes a protruding part that protrudes above the chip side surface in the thickness direction, The plating layer in the protruding portion covers the surface of the seed layer. The nitride semiconductor device according to claim 2 .

10. Each of the first GaN chip and the second GaN chip comprises: a chip surface; a chip back surface opposite to the chip front surface; a substrate having a substrate surface and a substrate back surface opposite to the substrate surface and constituting the chip back surface; Including, The electromagnetic wave shield includes a rear surface shield portion provided on the rear surface of the substrate of each of the first GaN chip and the second GaN chip. The nitride semiconductor device according to claim 2 .

11. The rear shield part is connected to the side shield part. The nitride semiconductor device according to claim 10.

12. Each of the first GaN chip and the second GaN chip comprises: a chip surface; a chip back surface opposite to the chip front surface; a substrate having a substrate surface and a substrate back surface opposite to the substrate surface and constituting the chip back surface; a GaN transistor provided on the surface of the substrate; a wiring layer provided on the GaN transistor and electrically connected to the GaN transistor; Contains The nitride semiconductor device according to claim 1 .

13. The shortest distance between the first GaN chip and the second GaN chip is smaller than the thickness of the substrate. The nitride semiconductor device according to claim 12 .

14. The shortest distance between the first GaN chip and the second GaN chip is 10 μm or more and 50 μm or less. The nitride semiconductor device according to claim 1 .

15. a driving chip for driving the first GaN chip and the second GaN chip; The first sealing resin seals the first GaN chip, the second GaN chip, and the driver chip. The nitride semiconductor device according to claim 1 .

16. The electromagnetic wave shield is disposed between the first GaN chip and the driving chip and between the second GaN chip and the driving chip. The nitride semiconductor device according to claim 15.

17. The driving chip includes: a chip surface; a chip back surface opposite to the chip front surface; a drive substrate having a substrate surface and a substrate back surface opposite to the substrate surface and constituting the chip back surface; The electromagnetic wave shield includes a rear shield portion provided on the rear surface of the drive substrate. The nitride semiconductor device according to claim 16.

18. A support substrate; The nitride semiconductor device according to claim 1 , which is disposed on the support substrate; a driver chip disposed on the support substrate and configured to drive the nitride semiconductor device; a control chip disposed on the support substrate and electrically connected to the drive chip; a second sealing resin that seals the nitride semiconductor device, the drive chip, and the control chip; 12. A semiconductor module comprising:

19. preparing a wafer having a wafer front surface and a wafer back surface opposite to the wafer front surface, the wafer including a plurality of chip formation regions on the wafer front surface side, each having a GaN transistor formed therein; forming a groove between adjacent chip forming regions; forming a metal layer on the side and bottom surfaces of the groove; forming a resin layer to fill the groove and cover the wafer; grinding the back surface of the wafer so that both the resin layer and the metal layer are exposed; A method for manufacturing a nitride semiconductor device, comprising:

20. and forming a backside metal layer on the backside of the wafer after the backside of the wafer has been ground. The method for manufacturing a nitride semiconductor device according to claim 19.

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