Semiconductor device

Abstract

To provide a semiconductor device having excellent electric characteristics without reducing the opening ratio even in a minute pixel circuit.SOLUTION: A semiconductor device includes an oxide semiconductor layer with a pattern, a gate electrode facing the oxide semiconductor layer, a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, a first insulating layer provided over the gate electrode and having a first opening provided overlapping with a pattern end part of the oxide semiconductor layer in a plan view, and a first electrode provided over the first insulating layer and inside the first opening, and in contact with the oxide semiconductor layer so as to cover the pattern end part of the oxide semiconductor layer at a bottom part of the first opening.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Recently, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and a very low off-current than transistors using amorphous silicon for the channel.

[0003] In recent years, pixel sizes of display devices have been reduced. Along with this reduction in pixel size, reductions in wiring width and transistor size have been considered. However, there are limits to these reductions, and the aperture ratio is reduced due to the arrangement of metal layers and semiconductor layers that constitute pixel circuits. Therefore, development is underway to use transistors in pixel circuits that use oxide semiconductor layers as channels, which can provide sufficient characteristics for driving pixel circuits even with small transistor sizes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146819 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-159315 Summary of the Invention [Problem to be solved by the invention]

[0005] To reduce the pixel size without reducing the aperture ratio, it is necessary to devise a layout for the pixel circuit and a structure for the transistors in the pixel circuit. On the other hand, the transistors in the pixel circuit are required to have good initial characteristics and reliability in stress tests.

[0006] An object of one embodiment of the present invention is to realize a semiconductor device that has good electrical characteristics without reducing the aperture ratio even when the pixel circuit is minute. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer having a pattern, a gate electrode facing the oxide semiconductor layer, a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, a first insulating layer provided above the gate electrode and having a first opening that overlaps with an end portion of the pattern of the oxide semiconductor layer in a planar view, and a first electrode provided above the first insulating layer and inside the first opening, and in contact with the oxide semiconductor layer at the bottom of the first opening so as to cover the end portion of the pattern of the oxide semiconductor layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 2] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 4] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 5] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 6] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 7] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 8] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 9] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 10] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 11] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 12] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 13] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 14] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. [Figure 15] 1 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention; [Figure 16] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 17] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 18] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, configurations similar to those described above with respect to the previous drawings are designated by the same reference numeral followed by an alphabet, and detailed description may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the following description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, although the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer as an example of a display device, the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] [1. First embodiment] [1-1. Configuration of display device 10] The configuration of a display device 10 according to one embodiment of the present invention will be described with reference to Figs. 1 to 15. Fig. 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. Fig. 2 is a plan view showing an overview of a display device according to one embodiment of the present invention. Figs. 3 to 13 are plan views explaining the layout of each layer in a display device according to one embodiment of the present invention. Fig. 14 is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention. Fig. 15 is a plan view showing the structure of a semiconductor device according to one embodiment of the present invention. The cross-sectional view of Fig. 1 is a cross-sectional view for explaining the layer structure of display device 10, and may not strictly match the plan view of Fig. 2.

[0015] As shown in FIG. 1, the display device 10 is provided above a substrate SUB. The display device 10 includes a transistor Tr1, a transistor Tr2 (Tr2-1, Tr2-2), wiring W (W1, W2), a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr1 is a semiconductor device included in a pixel circuit of the display device 10. The transistor Tr2 is a semiconductor device included in a peripheral circuit. As will be described in detail later, the peripheral circuit is a circuit that drives the pixel circuit. In the following description, the term "semiconductor device" may include only the configuration of the transistor Tr1, or may include the configurations of both the transistors Tr1 and Tr2.

[0016] [1-2. Configuration of transistor Tr1] The transistor Tr1 has an oxide semiconductor layer OS (OS1, OS2), a gate insulating layer GI1, a gate electrode GL1, a connection electrode ZM, a connection electrode WM, and a wiring XM. The gate electrode GL1 faces the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided closer to the substrate SUB than the gate electrode GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is reversed may also be used.

[0017] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is an oxide semiconductor layer in a region overlapping with the gate electrode GL1 in a planar view. The oxide semiconductor layer OS1 functions as a semiconductor layer and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode GL1. In other words, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are layers formed from the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is an oxide semiconductor layer whose resistance is reduced by implanting impurities into a layer having the same physical properties as the oxide semiconductor layer OS1.

[0018] An insulating layer IL2 is provided above the gate electrode GL1. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via a connection electrode WM provided inside an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. The opening WCON overlaps with the pattern of the oxide semiconductor layer OS in a planar view. In this embodiment, the opening WCON is located inside the pattern of the oxide semiconductor layer OS in a planar view (see FIG. 2). The connection electrode WM is in contact with the oxide semiconductor layer OS at the bottom of the opening WCON. The wiring W1 and the connection electrode WM are metal layers and are in the same layer. A data signal related to the gradation of the pixel is transmitted to the wiring W1. An insulating layer IL3 is provided above the insulating layer IL2 and the wiring W1. In other words, the wiring W1 is provided between the insulating layer IL2 and the insulating layer IL3. Similarly, the insulating layer IL2 is provided between the insulating layer IL3 and the oxide semiconductor layer OS. The connection electrode ZM and the wiring XM are above the insulating layer IL3 and in contact with the upper surface of the insulating layer IL3. In other words, the insulating layer IL3 is in contact with the lower surfaces of the connection electrodes ZM and the wiring XM below the connection electrodes ZM and the wiring XM.

[0019] The connection electrode ZM is connected to the oxide semiconductor layer OS2 through an opening ZCON provided in the insulating layers IL3 and IL2 and the gate insulating layer GI1. The connection electrode ZM is in contact with the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The wiring XM is connected to the wiring W1 through an opening XCON provided in the insulating layer IL3. The connection electrodes WM, ZM and wiring XM are metal layers. As described above, the gate electrode GL1, the connection electrode ZM and the wiring XM are provided above the oxide semiconductor layer OS. The connection structure between the oxide semiconductor layer OS2 and the connection electrode ZM in the opening ZCON will be described in detail later.

[0020] The connection electrode ZM may be referred to as the "first electrode." The wiring W1 and the connection electrode WM may be referred to as the "second electrode." The wiring XM is provided in the same layer as the connection electrode ZM, but is separated from the connection electrode ZM. The material of the connection electrode ZM is the same as the material of the wiring XM.

[0021] The insulating layer IL3 may be referred to as the "first insulating layer." The insulating layer IL1 may be referred to as the "second insulating layer." The insulating layer IL2 may be referred to as the "third insulating layer." The opening ZCON may be referred to as the "first opening." The opening WCON may be referred to as the "second opening."

[0022] An insulating layer IL4 is provided above the connection electrode ZM. The insulating layer IL4 reduces steps formed by structures provided below the insulating layer IL4. The insulating layer IL4 is sometimes called a planarizing film. A pixel electrode PTCO is provided above the insulating layer IL4. The pixel electrode PTCO is connected to the connection electrode ZM through an opening PCON provided in the insulating layer IL4. The region where the connection electrode ZM and the pixel electrode PTCO contact is called a contact region CON2. In a plan view, the contact region CON2 overlaps with the gate electrode GL1. The pixel electrode PTCO is a transparent conductive layer.

[0023] An insulating layer IL5 is provided above the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided above the insulating layer IL5. That is, the pixel electrode PTCO faces the common electrode CTCO via the insulating layer IL5. The common electrode CTCO is connected to the common auxiliary electrode CMTL at an opening PCON. As will be described in detail later, the common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The electrical resistance of the common auxiliary electrode CMTL is lower than the electrical resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. A spacer SP is provided above the common electrode CTCO.

[0024] Spacers SP are provided for some of the pixels. For example, spacers SP may be provided for any one of blue, red, and green pixels. However, spacers SP may also be provided for all pixels. The height of the spacers SP is half the height of the cell gap. Spacers are also provided on the opposing substrate, and the spacers on the opposing substrate and the spacers SP overlap in a planar view.

[0025] A light-shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as the light-shielding layer LS. However, the light-shielding layer LS may be formed of only the light-shielding layer LS1 or only the light-shielding layer LS2. In plan view, the light-shielding layer LS is provided in a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap. That is, in plan view, the light-shielding layer LS is provided in a region where the light-shielding layer LS overlaps with the oxide semiconductor layer OS1. The light-shielding layer LS prevents light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the oxide semiconductor layer OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate electrode GL1 may be connected in a peripheral region of the pixel circuit.

[0026] The insulating layer IL1 and the gate insulating layer GI2 are provided between the light-shielding layer LS and the oxide semiconductor layer OS. In the present embodiment, the configuration in which the oxide semiconductor layer OS is in contact with the insulating layer IL1 has been illustrated, but this configuration is not limiting. For example, a metal oxide layer may be provided between the oxide semiconductor layer OS and the insulating layer IL1. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer. In this case, the metal oxide layer may be provided in the same region as the insulating layer IL1, or may be processed into the same pattern as the oxide semiconductor layer OS.

[0027] [1-3. Configuration of transistor Tr2] The transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2.

[0028] Each of the p-type transistor Tr2-1 and the n-type transistor Tr2-2 has a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S (S1 to S3). The gate electrode GL2 faces the semiconductor layer S. The gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate transistor in which the gate electrode GL2 is provided closer to the substrate SUB than the semiconductor layer S is exemplified, but a top-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed may also be used.

[0029] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor layer in a region that overlaps with the gate electrode GL2 in a planar view. The semiconductor layer S1 functions as a channel of the transistors Tr2-1 and Tr2-2. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer with higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers that invade toward the semiconductor layer S1.

[0030] An insulating layer IL1 and a gate insulating layer GI1 are provided above the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 simply functions as an interlayer film. A wiring W2 is provided above these insulating layers. The wiring W2 is connected to the semiconductor layer S2 through an opening provided in the insulating layer IL1 and the gate insulating layer GI1. An insulating layer IL2 is provided above the wiring W2. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the wiring W2 through an opening provided in the insulating layer IL2. An insulating layer IL3 is provided above the wiring W1. A wiring XM is provided above the insulating layer IL3. The wiring XM is connected to the wiring W1 through an opening provided in the insulating layer IL3.

[0031] The gate electrode GL2 and the light-shielding layer LS2 are in the same layer. The wiring W2 and the gate electrode GL1 are in the same layer. The term "in the same layer" means that a single layer is patterned to form multiple components.

[0032] [1-4. Planar layout of the display device 10] The planar layout of the pixels of the display device 10 will be described with reference to Figures 2 to 13. The pixel electrode PTCO, the common auxiliary electrode CMTL, the common electrode CTCO, and the spacer SP are omitted in Figure 2. The planar layouts of the pixel electrode PTCO, the common auxiliary electrode CMTL, and the common electrode CTCO are shown in Figures 11 to 13, respectively.

[0033] As shown in FIGS. 2 and 3, the light-shielding layer LS extends in the D1 direction. The shape of the light-shielding layer LS differs depending on the pixel. In this embodiment, a protrusion PJT protruding in the D2 direction is provided from a part of the light-shielding layer LS extending in the D1 direction. As shown in FIG. 5, the light-shielding layer LS is provided in a region including a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap in a plan view. The gate electrode GL1 can also be called a "gate line."

[0034] 2, 4, and 5, the oxide semiconductor layer OS extends in the D2 direction. The gate electrode GL1 extends in the D1 direction so as to intersect with the oxide semiconductor layer OS. The pattern of the gate electrode GL1 is provided inside the pattern of the light-shielding layer LS. In other words, the oxide semiconductor layer OS is formed in an elongated shape (a shape having a long side) intersecting with the gate electrode GL1.

[0035] 2, 6, and 7, the opening WCON is provided near the upper end of the pattern of the oxide semiconductor layer OS in a region overlapping with the wiring W1 (W1-1, W1-2). A main portion of the pattern of the oxide semiconductor layer OS extends in the D2 direction between adjacent wirings W1 (W1-1, W1-2). The remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion toward the region of the opening WCON in a direction oblique to the D1 and D2 directions.

[0036] 2 and 7, multiple wirings W1 extend in the D2 direction. When it is necessary to distinguish adjacent wirings W1 from one another, the adjacent wirings W1 are referred to as wirings W1-1 and W1-2. In this case, it can be said that the main portion of the oxide semiconductor layer OS extends in the D2 direction between the wirings W1-1 and W1-2 and intersects with the gate electrode GL1. In other words, the oxide semiconductor layer OS is provided elongated in the D2 direction and is connected to the wiring W1-1 at one longitudinal end of the oxide semiconductor layer OS.

[0037] As shown in FIGS. 2, 8, and 9, the opening ZCON is provided near the lower end of the pattern of the oxide semiconductor layer OS. The opening ZCON is provided in a region overlapping with the lower end of the pattern of the oxide semiconductor layer OS but not overlapping with the gate electrode GL1. The opening ZCON is provided in a region overlapping with the connection electrode ZM. The connection electrode ZM overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between the wiring W1-1 and the wiring W1-2. The connection electrode ZM contacts the oxide semiconductor layer OS at the opening ZCON that does not overlap with the gate electrode GL1.

[0038] The oxide semiconductor layer OS overlaps a portion of the opening ZCON. Similarly, the connection electrode ZM overlaps a portion of the opening ZCON. Inside the pattern of the opening ZCON, in the region where the oxide semiconductor layer OS and the connection electrode ZM overlap, the oxide semiconductor layer OS and the connection electrode ZM are in contact with each other. As will be described in detail later, inside the pattern of the opening ZCON, in the region where neither the oxide semiconductor layer OS nor the connection electrode ZM overlaps, an insulating layer IL1 provided below the oxide semiconductor layer OS and an insulating layer IL4 provided above the connection electrode ZM are in contact with each other.

[0039] In other words, the oxide semiconductor layer OS is connected to the connection electrode ZM at the other longitudinal end of the oxide semiconductor layer OS. The connection electrode ZM is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS. In the D1 direction, the width of the connection electrode ZM is smaller than the width of the oxide semiconductor layer OS.

[0040] 2, 7, and 8, the oxide semiconductor layer OS is in contact with the wiring W1 on the opposite side of the gate electrode GL1 from the opening ZCON. The opening ZCON partially overlaps with the light-shielding layer LS.

[0041] As shown in FIGS. 2, 10, and 11, the opening PCON is provided near the upper end of the pattern of the connection electrode ZM. The opening PCON is provided in a region overlapping with the pattern of the gate electrode GL1 and the pattern of the connection electrode ZM. The opening PCON is provided in a region overlapping with the pixel electrode PTCO. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZM between the wiring W1-1 and the wiring W1-2. Therefore, the pixel electrode PTCO contacts the connection electrode ZM at the opening PCON that overlaps with the gate electrode GL1.

[0042] The pixel electrode PTCO extends into the light-transmitting region described below. In other words, the pixel electrode PTCO is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS and the wiring W1-1. In the D1 direction, the width of the pixel electrode PTCO in the portion where the opening PCON is provided is larger than the width of the oxide semiconductor layer OS.

[0043] 11, the connection electrode ZM is formed in an elongated shape extending along the wiring W1-1. In the direction D1, the width of the opening PCON constituting the contact region CON2 is greater than the width of the connection electrode ZM. In plan view, the entire connection electrode ZM overlaps with the pixel electrode PTCO.

[0044] As shown in FIG. 11, the pixel electrodes PTCO are arranged in the D2 direction. Of the pixels adjacent to each other in the D2 direction, one pixel may be referred to as the "first pixel" and the other pixel may be referred to as the "second pixel." For example, the first pixel is the pixel corresponding to the upper pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction in FIG. 11, and the second pixel is the pixel corresponding to the lower pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction. In this case, a pixel signal is supplied to the first pixel and the second pixel from the wiring W1-1.

[0045] The pixel electrodes PTCO are arranged in the direction D1. The pixel adjacent to the first pixel in the direction D1 is called the "third pixel," and the pixel adjacent to the second pixel in the direction D1 is called the "fourth pixel." The third pixel and the fourth pixel are adjacent to each other in the direction D2. A pixel signal is supplied to the third pixel and the fourth pixel from the wiring W1-2 adjacent to the wiring W1-1.

[0046] As described above, each of the first, second, third, and fourth pixels includes a transistor Tr1 (pixel transistor), a connection electrode ZM, and a pixel electrode PTCO.

[0047] As described above, the transistor Tr1 includes an oxide semiconductor layer OS, a gate electrode GL1 facing the oxide semiconductor layer OS, and a gate insulating layer GI1 between the oxide semiconductor layer OS and the gate electrode GL1. The connection electrode ZM overlaps the gate electrode GL1 and the oxide semiconductor layer OS in a plan view, but is in contact with the oxide semiconductor layer OS through an opening ZCON that does not overlap with the gate electrode GL1. The pixel electrode PTCO overlaps the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZM in a plan view, and is connected to the connection electrode ZM through an opening PCON that overlaps with the gate electrode GL1.

[0048] 11 overlaps with the oxide semiconductor layer OS of the first pixel and the oxide semiconductor layer OS of the second pixel provided below the first pixel in a plan view. In addition, the pixel electrode PTCO of the first pixel also overlaps with the oxide semiconductor layer OS of the fourth pixel in a plan view.

[0049] As shown in FIG. 12, the common auxiliary electrode CMTL is provided in a lattice pattern so as to surround the periphery of the pixel region. In other words, the common auxiliary electrode CMTL is provided in common to a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided so as to expose the pixel electrode PTCO. The pattern of the opening OP is provided inside the pattern of the pixel electrode PTCO. The area where the opening OP is provided corresponds to the display area. In other words, the opening ZCON is included in the display area. The display area means an area where a user can see light from the pixels. For example, an area that is light-shielded by a metal layer and from which a user cannot see light is not included in the display area. In other words, the above-mentioned display area may be called a "light-transmitting area (or opening area)".

[0050] As shown in Fig. 13, the common electrode CTCO is provided in common to a plurality of pixels. A slit SL is provided in a region corresponding to the opening OP. The slit SL has a curved shape (a vertically long S-shape). The tip of the slit SL has a shape in which the width perpendicular to the extension direction of the tip becomes smaller. With reference to Figs. 1 and 13, the common electrode CTCO has a slit SL at a position opposite to the pixel electrode PTCO.

[0051] [1-5. Connection structure between oxide semiconductor layer OS and connection electrode ZM] The connection structure between the oxide semiconductor layer OS and the connection electrode ZM in the opening ZCON will be described using Figures 14 and 15. In Figure 14, for convenience of explanation, the light-shielding layer LS is shown as a single layer. The transistor Tr1 in Figure 14 is the same as the transistor Tr1 in Figure 1. Therefore, explanations that overlap with those in Figure 1 will be omitted. The lower part of Figure 14 shows the overall structure of the transistor Tr1, and the upper part of Figure 14 shows a partially enlarged view of the region of the transistor Tr1 shown in the lower part, surrounded by a dotted square line.

[0052] As shown in FIG. 15, in the direction opposite to the D2 direction (D2' direction), the connection electrode ZM extends beyond the pattern end of the oxide semiconductor layer OS. Furthermore, in the D2' direction, the opening ZCON extends beyond the pattern end of the oxide semiconductor layer OS and the pattern end of the connection electrode ZM. In other words, the pattern end of the oxide semiconductor layer OS and the pattern end of the connection electrode ZM in the D2' direction overlap with the opening ZCON in plan view. Therefore, as shown in FIG. 14, in the D2' direction, the connection electrode ZM extends beyond the pattern end of the oxide semiconductor layer OS and is in contact with the insulating layer IL1 outside the pattern of the oxide semiconductor layer OS. In other words, the connection electrode ZM is in contact with the top surface and side surface of the oxide semiconductor layer OS at the pattern end of the oxide semiconductor layer OS in the D2' direction. In other words, the connection electrode ZM covers the pattern end of the oxide semiconductor layer OS at the bottom of the opening ZCON. The pattern end of the connection electrode ZM in the D2' direction is present at the bottom of the opening ZCON, and the insulating layer IL1 is exposed from the connection electrode ZM at the bottom of the opening ZCON.

[0053] The insulating layer IL1 provided below the oxide semiconductor layer OS is thinned by etching the oxide semiconductor layer OS and the connection electrode ZM. Therefore, when the insulating layer IL1 overlapping the opening ZCON is divided into an OS region overlapping the oxide semiconductor layer OS, a ZM region overlapping the connection electrode ZM but not the oxide semiconductor layer OS, and an NO region overlapping neither the oxide semiconductor layer OS nor the connection electrode ZM in a plan view, the thickness of the insulating layer IL1 in these regions is different. Specifically, the thickness of the insulating layer IL1 in the ZM region is smaller than the thickness of the insulating layer IL1 in the OS region. Similarly, the thickness of the insulating layer IL1 in the NO region is smaller than the thickness of the insulating layer IL1 in the ZM region. With the above-described configuration, the insulating layer IL1 and the insulating layer IL4 are in contact at the bottom of the opening ZCON, improving adhesion between the insulating layer IL1 and the insulating layer IL4.

[0054] In other words, in plan view, the thickness of the insulating layer IL1 in the ZM region that overlaps with the connection electrode ZM but does not overlap with the oxide semiconductor layer OS in the opening ZCON is smaller than the thickness of the insulating layer IL1 in the OS region that overlaps with the oxide semiconductor layer OS in the opening ZCON. Similarly, in plan view, the thickness of the insulating layer IL1 in the NO region that does not overlap with either the oxide semiconductor layer OS or the connection electrode ZM in the opening ZCON is smaller than the thickness of the insulating layer IL1 in the ZM region that overlaps with the connection electrode ZM but does not overlap with the oxide semiconductor layer OS in the opening ZCON.

[0055] As described above, in a cross-sectional view, the insulating layer IL1 inside the opening ZCON has a stepped shape. A step portion ST1 is formed between the ZM region and the OS region. A step portion ST2 is formed between the NO region and the ZM region. The step portion ST1 may be referred to as a "first step portion." The step portion ST2 may be referred to as a "second step portion." The step portion ST1 is formed near the pattern end of the oxide semiconductor layer OS in a planar view. The step portion ST2 is formed near the pattern end of the connection electrode ZM in a planar view. The connection electrode ZM covers the step portion ST1. A portion of the insulating layer IL1 is exposed from the connection electrode ZM at the step portion ST2.

[0056] 15, in plan view, the connection electrode ZM is located inside the pattern of the light-shielding layer LS. In other words, as shown in Fig. 14, the pattern end of the light-shielding layer LS is located in the direction D2' from the pattern end of the connection electrode ZM.

[0057] Conventionally, measures have been taken to prevent a decrease in pixel aperture ratio due to pixel size reduction in order to realize high-definition display devices. For example, a configuration has been adopted in which a light-transmitting oxide semiconductor layer is used as a semiconductor layer that functions as a channel, and a transparent conductive layer such as ITO (Indium Tin Oxide) is used as a connection electrode connected to the oxide semiconductor layer.

[0058] On the other hand, in the process of realizing an embodiment of the present invention, it was found that when ITO is used as the connecting electrode, the initial characteristics of the transistor Tr1 may deteriorate. Specifically, in the transistor Tr1 according to this embodiment, a transistor in which the connecting electrode ZM is replaced from a metal layer to ITO may experience a phenomenon in which the initial characteristics vary greatly. More specifically, in an N-type transistor in which ITO is used as the connecting electrode and an oxide semiconductor layer is used as the semiconductor layer, the threshold voltage in the Id-Vg characteristics tends to shift in the negative direction.

[0059] The cause of the above phenomenon is thought to be moisture permeation through ITO. In other words, when an organic resin is used as the insulating layer IL4, moisture contained in the insulating layer IL4 permeates the connecting electrode ZM (ITO) and reaches the oxide semiconductor layer OS, causing oxygen vacancies in the oxide semiconductor layer OS, resulting in the above phenomenon. This problem was newly recognized in the process of arriving at the present invention, and was not a problem that had been recognized previously.

[0060] Fig. 19 is a cross-sectional view showing the structure of a semiconductor device according to a comparative example. As shown in Fig. 19, in the conventional configuration (comparative example), the occurrence of the above-mentioned phenomenon can be suppressed by providing a connection electrode ZM' made of a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO (transparent conductive layer). However, there is a problem in that the aperture ratio is reduced because the metal layer used as the connection electrode ZM' blocks light.

[0061] Furthermore, when forming the opening ZCON, taking into consideration the offset amount relative to the pattern of the gate electrode GL1 (the distance from the gate electrode GL1 taking into account misalignment when forming the pattern of the opening ZCON) and the processing size of the opening ZCON, it is difficult to provide the opening ZCON inside the pattern of the light-shielding layer LS in a planar view. Therefore, at least a portion of the opening ZCON ends up being formed outside the pattern of the light-shielding layer LS in a planar view. For example, if a portion of the opening ZCON is formed outside the pattern of the light-shielding layer LS in a planar view, and an attempt is made to form the connection electrode ZM' so that the pattern of the connection electrode ZM' is located inside the pattern of the light-shielding layer LS, the upper surface of the oxide semiconductor layer OS provided below the connection electrode ZM' will be exposed from the connection electrode ZM' and come into contact with the insulating layer IL4.

[0062] If the oxide semiconductor layer OS comes into contact with the insulating layer IL4, moisture contained in the insulating layer IL4 will reach the oxide semiconductor layer OS, forming oxygen vacancies in the oxide semiconductor layer OS and shifting the threshold voltage of the transistor in the negative direction. Furthermore, to reliably prevent the oxide semiconductor layer OS from coming into contact with the insulating layer IL4, it is necessary to ensure that the oxide semiconductor layer OS is not exposed by the connection electrodes ZM'. Therefore, the pattern of the connection electrodes ZM' must be larger than the pattern of the openings ZCON. This poses a problem of further expanding the light-shielded area.

[0063] As described above, in the configuration of the transistor according to the comparative example, it was necessary to prevent the upper surface of the oxide semiconductor layer OS from being exposed from the connection electrode ZM′ at the bottom of the opening ZCON, which resulted in the problem that the connection electrode ZM′ was formed in a region that did not overlap with the light-shielding layer LS in a plan view, widening the light-shielded region.

[0064] On the other hand, in the transistor Tr1 according to this embodiment, the pattern end of the oxide semiconductor layer OS is formed in the region overlapping with the opening ZCON in plan view, and the upper surface of the oxide semiconductor layer OS and the pattern end of the oxide semiconductor layer OS are covered with the connection electrode ZM, thereby suppressing the above problem. Furthermore, the pattern of the connection electrode ZM overlaps with the pattern of the light-shielding layer LS in plan view, thereby suppressing light blocking by the connection electrode ZM. In this case, the connection electrode ZM is provided so as to cover the pattern end of the oxide semiconductor layer OS, thereby suppressing moisture from reaching the oxide semiconductor layer OS.

[0065] In this embodiment, the width of the oxide semiconductor layer OS is larger than the width of the opening ZCON in the D1 direction in plan view. That is, one side of the pattern of the oxide semiconductor layer OS overlaps with the opening ZCON in plan view. However, the present invention is not limited to the above configuration. For example, the width of the oxide semiconductor layer OS may be smaller than the width of the opening ZCON in the D1 direction in plan view. That is, three sides of the pattern of the oxide semiconductor layer OS may overlap with the opening ZCON in plan view.

[0066] [1-6. Materials of each component of the display device 10] The substrate SUB can be a rigid substrate that is light-transmitting and not flexible, such as a glass substrate, a quartz substrate, or a sapphire substrate. On the other hand, if the substrate SUB needs to be flexible, a flexible substrate that contains resin and has flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate SUB. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0067] Common metal materials can be used for the gate electrodes GL1 and GL2, the wirings W1 and W2, the connecting electrodes ZM and WM, the light-shielding layer LS, and the common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), and silver (Ag), or alloys or compounds thereof, can be used for the electrodes. The above materials can be used as single layers or as multilayers for the electrodes.

[0068] For example, a laminated structure of Ti / Al / Ti is used as the gate electrode GL1. In this embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the above-mentioned laminated structure is a forward tapered shape.

[0069] The gate insulating layers GI1, GI2 and the insulating layers IL1 to IL5 can be made of a general insulating material. For example, the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL3, IL5 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x) or other inorganic insulating layers can be used. As these insulating layers, insulating layers with few defects can be used. As the insulating layer IL4, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. As the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL3, IL5, the above organic insulating materials may be used. As the members of the above insulating layers, etc., the above materials may be used in a single layer or in a laminated layer.

[0070] As an example of the insulating layer, a 100 nm thick SiO x The insulating layer IL1 is made of SiO 2 having a total thickness of 300 nm to 700 nm. x / SiN x / SiO x The gate insulating layer GI2 is made of SiO 2 with a total thickness of 60 to 150 nm. x / SiN x The insulating layer IL2 is made of SiO 2 with a total thickness of 300 nm to 500 nm. x / SiN x / SiO x The insulating layer IL3 is made of SiO 2 having a total thickness of 200 nm to 500 nm. x (single layer), SiN x The insulating layer IL4 is an organic layer having a thickness of 2 μm to 4 μm. The insulating layer IL5 is a SiN layer having a thickness of 50 nm to 150 nm. x (single layer) is used.

[0071] The above SiO x N y and AlO x N y is a silicon and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0072] The oxide semiconductor layer OS can be formed using a metal oxide having semiconductor properties.

[0073] The oxide semiconductor layer OS can be formed by sputtering, the details of which will be described later. The composition of the oxide semiconductor layer OS formed by sputtering depends on the composition of the sputtering target. In this case, the composition of the metal elements in the oxide semiconductor layer OS can be determined based on the composition of the metal elements in the sputtering target.

[0074] As described above, the pixel electrode PTCO and the common electrode CTCO are formed of a transparent conductive layer. The transparent conductive layer may be formed of ITO or a mixture of indium oxide and zinc oxide (IZO). However, other materials may also be used for the transparent conductive layer.

[0075] As described above, when a metal oxide layer is provided between the oxide semiconductor layer OS and the insulating layer IL1, a metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0076] As described above, the transistor Tr1 according to this embodiment makes it possible to realize a semiconductor device having good electrical characteristics without reducing the aperture ratio.

[0077] [2. Second Embodiment] The overall configuration of the display device described in the first embodiment will be described with reference to FIGS.

[0078] [2-1. Overview of the display device 20] FIG. 16 is a plan view showing an overview of a display device according to one embodiment of the present invention. As shown in FIG. 16, the display device 20 includes an array substrate 300, a seal portion 400, a counter substrate 500, a flexible printed circuit board 600 (FPC 600), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the seal portion 400. A plurality of pixel circuits 310 are arranged in a matrix in a liquid crystal region 22 surrounded by the seal portion 400. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 410 (described later) in a planar view. The liquid crystal region 22 is an area that contributes to display. The liquid crystal region 22 may also be referred to as a "display region." The above-mentioned transistor Tr1 is provided in the liquid crystal region 22 (display region).

[0079] The sealing region 24, in which the sealing portion 400 is provided, is the region surrounding the liquid crystal region 22. The FPC 600 is provided in the terminal region 26. The terminal region 26 is the region where the array substrate 300 is exposed from the counter substrate 500, and is provided outside the sealing region 24. Note that the outside of the sealing region 24 means the outside of the region where the sealing portion 400 is provided and the region surrounded by the sealing portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies signals to drive each pixel circuit 310. The sealing region 24 or the region combining the sealing region 24 and the terminal region 26 is the region surrounding the liquid crystal region 22 (display region). These regions may be referred to as the "frame region." The above-mentioned transistor Tr2 is provided in the frame region.

[0080] [2-2. Circuit configuration of display device 20] Fig. 17 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. As shown in Fig. 17, a source driver circuit 320 is provided adjacent to the liquid crystal region 22 in which the pixel circuits 310 are arranged in the direction D1 (column direction), and a gate driver circuit 330 is provided adjacent to the liquid crystal region 22 in the direction D2 (row direction). The source driver circuit 320 and the gate driver circuit 330 are provided in the sealing region 24. However, the region in which the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 310 are provided.

[0081] Source wiring 321 extends from the source driver circuit 320 in the D1 direction and is connected to a plurality of pixel circuits 310 arranged in the D1 direction. Gate wiring 331 extends from the gate driver circuit 330 in the D2 direction and is connected to a plurality of pixel circuits 310 arranged in the D2 direction.

[0082] A terminal portion 333 is provided in the terminal region 26. The terminal portion 333 and the source driver circuit 320 are connected by a connection wiring 341. Similarly, the terminal portion 333 and the gate driver circuit 330 are connected by a connection wiring 341. When the FPC 600 is connected to the terminal portion 333, the external device to which the FPC 600 is connected is connected to the display device 20, and each pixel circuit 310 provided in the display device 20 is driven by a signal from the external device.

[0083] The transistor Tr1 shown in the first embodiment is used in the pixel circuit 310. The transistor Tr2 shown in the first embodiment is applied to transistors included in the source driver circuit 320 and the gate driver circuit 330.

[0084] 2-3. Pixel circuit 310 of display device 20 FIG. 18 is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. As shown in FIG. 18, the pixel circuit 310 includes elements such as a transistor 800, a storage capacitor 890, and a liquid crystal element 410. One electrode of the storage capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to a gate wiring 331. The first source electrode 830 is connected to a source wiring 321. The first drain electrode 840 is connected to the storage capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first embodiment is applied to the transistor 800 shown in FIG. 18. In this embodiment, for convenience of explanation, 830 is referred to as a source electrode and 840 as a drain electrode, but the source and drain functions of these electrodes may be interchanged.

[0085] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions based on the semiconductor device of each embodiment, such combinations are included in the scope of the present invention as long as they include the gist of the present invention.

[0086] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0087] 10: display device, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel circuit, 320: source driver circuit, 321: source wiring, 330: gate driver circuit, 331: gate wiring, 333: terminal section, 341: connection wiring, 400: sealing section, 410: liquid crystal element, 500: opposing substrate, 600: flexible printed circuit board (FPC), 700: IC chip, 800: transistor, 810: first gate electrode, 830: first source electrode, 840: first drain electrode, 890: storage capacitor, CMTL: common auxiliary electrode, CON2: contact region, CTCO: common electrode, GI1, GI2: gate insulating layer, GL1, GL2: gate electrode, IGO: oxide semiconductor, IL1 to IL5: insulating layer, LS: Light-shielding layer, OP: Opening, OS: Oxide semiconductor layer, PCON: Opening, PJT: Protrusion, PTCO: Pixel electrode, S: Semiconductor layer, SL: Slit, SP: Spacer, ST1, ST2: Step, SUB: Substrate, Tr1, Tr2: Transistor, W1, W2, XM: Wiring, WCON, XCON, ZCON: Opening, WM, ZM, ZTCO: Connection electrode

Claims

1. a patterned oxide semiconductor layer; a gate electrode facing the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided above the gate electrode and having a first opening that overlaps with a pattern end of the oxide semiconductor layer in a plan view; a first electrode provided above the first insulating layer and inside the first opening, the first electrode being in contact with the oxide semiconductor layer at the bottom of the first opening so as to cover an end of a pattern of the oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first electrode is made of a metal.

3. The semiconductor device according to claim 1 , wherein the first electrode is in contact with an upper surface and a side surface of the oxide semiconductor layer at an end portion of a pattern of the oxide semiconductor layer.

4. a light-shielding layer provided below the oxide semiconductor layer, The semiconductor device according to claim 1 , wherein the first electrode is located inside a pattern of the light-shielding layer in a plan view.

5. a light-shielding layer provided below the oxide semiconductor layer; a second insulating layer provided between the light-shielding layer and the oxide semiconductor layer, The semiconductor device according to claim 3 , wherein the first electrode is in contact with the second insulating layer outside the pattern of the oxide semiconductor layer in a plan view.

6. In a plan view, the second insulating layer has a first step portion near an end of a pattern of the oxide semiconductor layer, The semiconductor device according to claim 5 , wherein the first electrode covers the first step portion.

7. In a plan view, a pattern end of the first electrode overlaps with the first opening, In a plan view, the second insulating layer has a second step portion near an end of a pattern of the first electrode, The semiconductor device according to claim 6 , wherein said second insulating layer is exposed from said first electrode at said second step portion.

8. a third insulating layer provided between the first insulating layer and the oxide semiconductor layer, the third insulating layer having the first opening and a second opening located inside the pattern of the oxide semiconductor layer in a plan view; The semiconductor device according to claim 1 , further comprising: a second electrode provided between said third insulating layer and said first insulating layer and inside said second opening.

9. The semiconductor device according to claim 8 , wherein the second electrode is a metal.

10. 6. The semiconductor device according to claim 5, wherein a thickness of the second insulating layer located in a region in the first opening that overlaps with the first electrode but does not overlap with the oxide semiconductor layer in a plan view is smaller than a thickness of the second insulating layer located in a region in the first opening that overlaps with the oxide semiconductor layer in a plan view.

11. 11. The semiconductor device according to claim 10, wherein a thickness of the second insulating layer located in a region in the first opening that does not overlap with either the oxide semiconductor layer or the first electrode in a planar view is smaller than a thickness of the second insulating layer located in a region in the first opening that does not overlap with the oxide semiconductor layer but overlaps with the first electrode in a planar view.

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