Scanning drive method for high-quality image, and cholesteric liquid crystal display device using the same

Abstract

To provide a display device including a display panel.SOLUTION: A display panel includes a first substrate, a second substrate, a cholesteric liquid crystal (ChLC) layer, and a drive circuit section. A plurality of first electrodes formed on the first substrate extends in a first direction. A plurality of second electrodes formed on the second substrate extends in a second direction different from the first direction. The ChLC layer is formed between the first substrate and the second substrate. The drive circuit section applies a plurality of alternating current (AC) voltage pulses to pixel circuits at intersections of the first electrodes and the second electrodes. The drive circuit section is further configured to perform a full-screen reset procedure on the display panel, followed by a pulse-width modulation (PWM) scan procedure to control cholesteric molecules in the pixel circuits to enter a focal conic state.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63 / 654,247, filed May 31, 2024, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to a display device, and more particularly to a scan driving method for high-quality images and a cholesteric liquid crystal display device using the same. [Background technology]

[0003] The display screen of a cholesteric liquid crystal (ChLC) display device can be reset by controlling the ChLC molecules of the ChLC display device to enter a planar state (e.g., a bright state) during the reset stage of a PWM (pulse width modulation) scanning method. However, increasing the scanning time can decrease the reflectivity of the ChLC molecules in both the dark state (e.g., the focal conic state) and the bright state (e.g., the planar state), thereby limiting the effectiveness of increasing the scanning time in the PWM scanning method to improve screen contrast.

[0004] Therefore, in order to solve the above problems, a scan driving method for high quality images and a cholesteric liquid crystal display device using the same are needed. Summary of the Invention

[0005] In one aspect of the present disclosure, a display device is provided that includes a display panel. The display panel includes a first substrate, a second substrate, a cholesteric liquid crystal (ChLC) layer, and a drive circuit section. A plurality of first electrodes formed on the first substrate extend in a first direction. A plurality of second electrodes formed on the second substrate extend in a second direction different from the first direction. The ChLC layer is formed between the first substrate and the second substrate. The drive circuit section applies a plurality of alternating current (AC) voltage pulses to pixel circuits at intersections of the first electrodes and the second electrodes. The drive circuit section is further configured to perform a full-screen reset procedure on the display panel, followed by a pulse-width modulation (PWM) scan procedure to control cholesteric molecules in the pixel circuits to enter a focal conic state.

[0006] In another aspect of the present disclosure, there is provided a scan driving method for use with a cholesteric liquid crystal display device, the method including the steps of performing a full screen reset procedure on the cholesteric liquid crystal display device to control cholesteric molecules in pixel circuits of the cholesteric liquid crystal display device to enter a focal conic state, and performing a pulse width modulation (PWM) scan procedure on the cholesteric liquid crystal display device following the full screen reset procedure to render an image on the cholesteric liquid crystal display device.

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present disclosure. [Figure 2A] FIG. 2A is a diagram of a display device according to the embodiment of FIG. [Figure 2B] FIG. 2B is a cross-sectional view of the display panel of FIG. 2A. [Figure 3] FIG. 3 shows the state transitions of the ChLC molecules during the reset stage of the PWM scanning procedure. [Figure 4] FIG. 4 shows reflectance versus voltage (RV) curves for rendering a dark screen and a bright screen. [Figure 5] FIG. 5 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments. [Figure 6] FIG. 6 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments. [Figure 7] FIG. 7 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments. [Figure 8] FIG. 8 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments. [Figure 9] FIG. 9 is a flowchart of a method for driving a cholesteric liquid crystal display according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of operations, components, and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, a first operation performed before or after a second operation in the description can include an embodiment in which the first and second operations are performed together, and can also include an embodiment in which an additional operation may be performed between the first and second operations. For example, in the following description, a reference to a second operation or a first operation of a second operation can include an embodiment in which the first and second operations are formed in direct contact with each other, and can also include an embodiment in which an additional operation may be formed between the first and second operations such that the first and second operations are not in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various described embodiments and / or configurations.

[0010] Time-relative terms such as "prior to," "before," "posterior to," and "after" may be used herein to facilitate the description to describe the relationship of one action or feature to another, as shown in the figures. Such time-relative terms are intended to encompass different sequences of actions depicted in the figures. Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to facilitate the description to describe the relationship of one element or feature to another, as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly. Relative terms of connection, such as "connect," "connected," "connection," "couple," "coupled," and "in communication," may be used herein for ease of description to describe an operational connection, coupling, or link between two elements or features. Relative terms of connection are intended to encompass different connections, couplings, or links of devices or components. Devices or components may be connected, coupled, or linked to each other directly or indirectly, for example, through another set of components. Devices or components may be connected, coupled, or linked to each other by wire and / or wirelessly.

[0011] As used herein, the singular terms "a," "an," and "the" can include plural referents unless the context clearly dictates otherwise. For example, a reference to a device can include a plurality of devices unless the context clearly dictates otherwise. The terms "comprises" and "including" can indicate the presence of stated features, integers, steps, operations, elements, and / or components, but cannot exclude the presence of one or more combinations of features, integers, steps, operations, elements, and / or components. The term "and / or" can include any and all combinations of one or more listed items.

[0012] Furthermore, amounts, ratios, and other numerical values ​​may be presented herein in a range format. It will be understood that such range format is used for convenience and brevity and includes the numerical values ​​explicitly stated as the limits of the range, but should also be understood flexibly to include all individual numerical values ​​or subranges subsumed within that range, as if each numerical value and subrange were expressly stated.

[0013] The nature and use of the embodiments are described in detail below. It should be understood, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to embody and use the present disclosure without limiting the scope of the disclosure.

[0014] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present disclosure.

[0015] In some embodiments, the electronic device 1 may be an e-book, an e-paper, an electronic whiteboard, a temperature display board, etc., but the present disclosure is not limited thereto. As shown in FIG. 1 , the electronic device 1 may include a processing unit 10 and a display device 20. The processing unit 10 may be a central processing unit (CPU), a digital signal processor (DSP), an image signal processor (ISP), a microprocessor, a microcontroller unit (MCU), or any other equivalent circuit, but the present disclosure is not limited thereto. The display device 20 may be a cholesteric liquid crystal display (ChLCD) device.

[0016] In some embodiments, the display device 20 may include a driver circuit 21 and a display panel 22. The display panel 22 may be a ChLCD panel including multiple ChLC layers for red, green, and blue pixel arrays. The driver circuit 21 may also include a dynamic drive scheme (DDS) driver circuit 211 and a pulse-width modulation (PWM) driver circuit 212. In some embodiments, one of the DDS driver circuit 211 and the PWM driver circuit 212 is used to drive the display panel 22. In other words, the display panel 22 may be driven in either a DDS drive mode or a PWM drive mode depending on the drive mode selected by the driver circuit 21.

[0017] In some embodiments, the DDS drive mode exhibits certain characteristics, such as a faster scanning speed and high image contrast for the display effect. However, the color scale effect is not ideal because the reflectance is significantly reduced when displaying colors in a dark state, typically about 4.5%. Furthermore, the gray scale depth of the DDS drive mode is relatively limited, typically ranging from 4 to 8 levels. The PWM drive mode has certain characteristics, such as a slow scanning speed and low image contrast for the display effect. However, the color scale display effect is better in the PWM drive mode because the reflection is reduced when displaying colors in a dark state, typically about 6% reflectance. Furthermore, the PWM drive mode provides a relatively high gray scale color depth, typically divided into 16 levels.

[0018] Figure 2A is a diagram of a display device according to the embodiment of Figure 1. Figure 2B is a cross-sectional view of the display panel of Figure 2A.

[0019] In some embodiments, the display panel 22 may include multiple display units 22B, 22G, and 22R, a scan electrode driver circuit 221, and a data electrode driver circuit 222, as shown in FIG. 2A. Furthermore, the display units 22B, 22G, and 22R may be stacked to form a display panel, with the display units 22B, 22G, and 22R being the top, middle, and bottom display units, respectively, as shown in FIG. 2B. The display units 22B, 22G, and 22R may include pixels that display blue, green, and red, respectively, enabling the display panel 22 to render a screen 30 (e.g., a color display screen). The display unit 22B may include scan electrodes BSE1-BSEN (e.g., N electrodes along the Y axis) and data electrodes BDE1-BDEM (e.g., M electrodes along the X axis). The scan electrodes and data electrodes in the display units 22G and 22R are similarly arranged.

[0020] In some embodiments, the scan electrodes BSE1 to BSEN can be called common (COM) electrodes, and the data electrodes BDE1 to BDEM can be called segment (SEG) electrodes. Furthermore, as shown in FIG. 2A, the scan electrodes BSE1 to BSEN and the data electrodes BDE1 to BDEM intersect with each other in a top view of the display panel 22.

[0021] In some embodiments, a pixel circuit (e.g., a ChLC pixel circuit not explicitly shown in FIG. 2A ) is disposed at each intersection between scan electrodes BSE1-BSEN and data electrodes BDE1-BDEM of display unit 22B. This arrangement enables the pixel circuits of display unit 22B to form a blue pixel array with a resolution of M*N. For example, the pixel circuit (e.g., for blue) located at the intersection between scan electrode BSE1 and data electrode BDE1 of display unit 22B may be assigned coordinate B(1,1), while the pixel circuit located at the intersection between scan electrode BSEN and data electrode BDEj of display unit 22B may be assigned coordinate B(N,j), and so on.

[0022] Similarly, the display unit 22G may include scan electrodes GSE1-GSEN (e.g., N electrodes along the Y axis) and data electrodes GDE1-GDEM (e.g., M electrodes along the X axis). The coordinates of each pixel circuit located at the intersection between the scan electrodes GSE1-GSEN and the data electrodes GDE1-GDEM of the display unit 22G can be assigned in the same manner as those of the display unit 22B.

[0023] Similarly, the display unit 22R may include electrodes RSE1-RSEN (e.g., N electrodes along the Y axis) and data electrodes RDE1-RDEM (e.g., M electrodes along the X axis). Coordinates of each pixel circuit located at the intersection between the scan electrodes RSE1-RSEN and the data electrodes RDE1-RDEM of the display unit 22R can be assigned in the same manner as those of the display unit 22B.

[0024] In addition, the scan electrodes BSE1-BSEN, GSE1-GSEN, and RSE1-RSEN of the display units 22B, 22G, and 22R may be electrically connected to the scan electrode drive circuit 221. In some embodiments, when the first row of the display panel 22 is to be activated, the scan electrode drive circuit 221 may apply a voltage pulse to the scan electrodes BSE1, GSE1, and RSE1 (e.g., a common electrode) to activate them simultaneously. In other words, the scan electrodes of the same row number may be activated simultaneously by the scan electrode drive circuit 221. In some embodiments, the scan electrode drive circuit 221 and the data electrode drive circuit 222 can be collectively regarded as a drive circuit section.

[0025] In some embodiments, the scan electrode drive circuit 221 can activate one or more rows (i.e., scan electrodes) of the display panel 22. For example, when two adjacent rows (e.g., rows n and (n+1)) of the display panel 22 are to be activated simultaneously, the scan electrode drive circuit 221 may simultaneously apply a first drive voltage to the scan electrodes BSEn, GSEn, and RSEn of the nth row, and simultaneously apply a second drive voltage to the scan electrodes BSE(n+1), GSE(n+1), and RSE(n+1) of the n+1th row. It should be noted that the current stages of rows n and (n+1) can be different, so that the first drive voltage is different from the second drive voltage.

[0026] Referring to FIG. 2B , in some embodiments, display units 22B, 22G, and 22R may be stacked in this order on a surface (e.g., surface 250) facing incident light. Display unit 22B may include a ChLC layer 230B, substrates 231B and 232B, layers 241B and 242B, and an encapsulant 233B. For example, ChLC layer 230B may be sealed between opposing substrates 231B and 232B by encapsulant 233B applied to the edges of substrates 231B and 232B. Furthermore, the average refractive index n and helical pitch p of ChLC layer 230B are determined so that the wavelength λ is approximately 480 nm, for example. The average refractive index n can be adjusted by selecting the liquid crystal material and the chiral material, and the helical pitch p can be adjusted by adjusting the content of the chiral material. Therefore, ChLC layer 230B can selectively reflect blue light in a planar state. The layers 241B and 242B may refer to regions where the scan electrodes BSE1-BSEN and data electrodes BDE1-BDEM of the display unit 22B, which are electrically connected to the scan electrode drive circuit 221 and the data electrode drive circuit 222, respectively, are arranged. In the focal conic state, the liquid crystal molecules of the ChLC layer 230B are randomly rotated by the electrodes (e.g., layers 241B and 242B) to form a helical structure, and the helical axes of the helical structure are randomly oriented. As a result, the ChLC layer 230B loses selectivity for reflection wavelengths, and transmits most of the incident light. The transmitted light is absorbed by the light-absorbing layer 240, resulting in a dark (black) display. The light-absorbing layer 240 may be provided on the bottom surface of the display unit 22R. The display units 22G and 22R have a similar configuration to the display unit 22B, and therefore details will not be repeated here.

[0027] Figure 3 shows the state transition of ChLC molecules during the reset stage of the PWM scanning procedure, and Figure 4 shows the reflectance versus voltage (RV) curves for rendering a dark screen and a bright screen.

[0028] For simplicity, display unit 22B is shown in Figure 3. In some embodiments, the full-screen reset stage includes a first reset stage and a second reset stage arranged in sequence. During the first reset stage, V HT One or more first alternating current (AC) voltage pulses with a voltage amplitude (e.g., a very high AC voltage difference between activated scan electrodes and data electrodes, e.g., 40 V or more) are applied to the ChLC layer 230B, 230G, or 230R, causing the ChLC molecules 30 in the ChLC layer 230B, 230G, or 230R to enter a homeotropic state. Therefore, incident light passes through the ChLC molecules 30 and is absorbed by the light-absorbing layer 240 at the bottom of the display panel 22, thereby rendering a black screen. During a second reset stage following the first reset stage, one or more second AC voltage pulses with a voltage amplitude of VFC are applied to the ChLC layer 230B, 230G, or 230R, causing the ChLC molecules 30 in the ChLC layer 230B, 230G, or 230R to enter a focal conic state (e.g., a dark state) without entering a planar state (e.g., a bright state). Furthermore, the cycle of the first AC voltage pulse can be different from the cycle of the second AC voltage pulse, and the overall duration of the first AC voltage pulse in the first reset stage can be different from the duration of the second AC voltage pulse in the second reset stage.

[0029] Specifically, after a second AC voltage pulse (e.g., VFC) is applied to the ChLC layer 230B, 230G, or 230R, the ChLC molecules 30 of the ChLC layer 230B, 230G, or 230R are reset to a focal conic state as an initial state before writing pixel data to each pixel circuit in a selection stage of the PWM scanning procedure, thereby improving the contrast and National Television System Committee (NTSC) color space of the display screen rendered on the display panel 22.

[0030] Embodiment 1 FIG. 5 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments.

[0031] In some embodiments, the full screen reset stage can include a first reset stage (e.g., Reset (HT)) and a second reset stage (e.g., Reset (FC)). During the first reset stage, V HT Two first AC voltage pulses with a voltage amplitude of 1 V are first applied to all pixel circuits of display units 22B, 22G, and 22R, thereby controlling all ChLC molecules in ChLC layer 230B, 230G, or 230R to enter a homeotropic (HT) state. In some embodiments, the duration T1 of the first AC voltage pulses (e.g., from time t0 to t1) can be 10 ms to 300 ms. In some embodiments, the duration T1 of the first AC voltage pulses can be 10 ms to 490 ms. Thereafter, during a relaxation time (e.g., duration T2 from time t1 to t2), no voltage is applied to the pixel circuits of display units 22B, 22G, and 22R, and during the relaxation time, all ChLC molecules in ChLC layers 230B, 230G, and 230R transition from the homeotropic state to a planar state (e.g., a bright state), thereby allowing a user to perceive a white screen. In some embodiments, the duration of the relaxation time T2 can be between 10 ms and 300 ms. In some embodiments, the duration of the relaxation time T2 can be between 10 ms and 490 ms. Following the relaxation time, a second reset phase is performed. During the second reset phase, V FC Two second AC voltage pulses with voltage amplitudes of 10 ms to 300 ms are applied to the pixel circuits of display units 22B, 22G, and 22R, thereby controlling the ChLC molecules in ChLC layer 230B, 230G, or 230R to enter a focal conic (FC) state (e.g., a dark state), allowing the user to perceive a black screen. In some embodiments, the duration T3 of the second AC voltage pulses (e.g., times t2 to t3) can be 10 ms to 300 ms. In some embodiments, the duration T3 of the second AC voltage pulses can be 10 ms to 490 ms.

[0032] Thereafter, during a selection stage of the PWM scanning procedure (e.g., duration T4 from time t3 to t4), the scan electrodes of display units 22B, 22G, and 22R are sequentially activated, and a respective selection AC voltage pulse is applied to each pixel circuit of the activated scan electrodes, thereby reducing the V bright and V dark A grayscale pixel value is written to each pixel circuit that is halfway between

[0033] For example, the amplitude of the selected AC voltage pulse is V SEL_B ~ and V SEL_D A voltage amplitude V SEL_B is used, the pixel value of the particular pixel circuit will be approximately 255 (i.e., a bright pixel). SEL_D When V is used, the pixel value of the particular pixel circuit will be approximately 0 (i.e., a dark pixel). SEL_B ~V SEL_D When a voltage amplitude of 0 is used, the pixel value of a particular pixel circuit will be between 0 and 255 (i.e., a grayscale pixel). It should be noted that a PWM scanning procedure is performed to sequentially activate each scan electrode in each display unit 22B, 22G, 22R. During the selection stage of the pixel circuits of the activated scan electrodes, the user can perceive the display screen being sequentially rendered on the display panel 22.

[0034] Following the selection stage, a deselection stage (e.g., duration T5 from time t4 to t5) is performed, in which a low voltage swing V NONSEL A plurality of AC voltage pulses with .times. ...

[0035] Embodiment 2 FIG. 6 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments.

[0036] The waveform diagram shown in FIG. 6 is similar to the waveform diagram shown in FIG. 5, except that there is no relaxation time between the first reset stage (e.g., duration T11 from time t0 to t1) and the second reset stage (e.g., duration T12 from time t1 to t2) in the full-screen reset stage. More specifically, the first reset stage (e.g., duration T11) is immediately followed by the second reset stage (e.g., duration T12). Because there is no relaxation time following the first reset stage to allow the ChLC molecules in all pixel circuits of display units 22B, 22G, and 22R to transition from a homeotropic state to a planar state (e.g., a bright state), the user does not perceive a white screen. Instead, the ChLC molecules in all pixel circuits transition directly from the homeotropic state to a focal conic state (e.g., a dark state), thereby perceiving a black screen. In some embodiments, durations T11 and T12 are 10 ms to 300 ms. In some embodiments, durations T11 and T12 are between 10 ms and 490 ms. The selected stage (e.g., duration T13 from time t2 to t3) and the non-selected stage (e.g., duration T14 from time t3 to t4) in the PWM scanning procedure shown in Figure 6 are similar to those shown in Figure 5, and therefore the details are repeated here.

[0037] Embodiment 3 FIG. 7 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments.

[0038] The waveform diagram shown in FIG. 7 is similar to that shown in FIG. 6, except that the voltage applied to the pixel circuits during the second reset stage of FIG. 7 (e.g., duration T22 from time t1 to t2) gradually increases. More specifically, the first reset stage (e.g., duration T21 from time t0 to time t1) is immediately followed by the second reset stage (e.g., duration T22), and the user does not perceive a white screen because there is no relaxation time following the first reset stage to allow the ChLC molecules in all pixel circuits of display units 22B, 22G, and 22R to transition from a homeotropic state to a planar state (e.g., a bright state). At the end of the first reset stage, the AC voltage is -V HT When this occurs, the voltages applied to all pixel circuits of display units 22B, 22G, and 22R gradually increase to 0V. In addition, the duration T22 of the second reset stage may be different from the duration T21 of the first reset stage. In some embodiments, the durations T21 and T22 are between 10 ms and 300 ms. In some embodiments, the durations T21 and T22 are between 10 ms and 490 ms.

[0039] Specifically, when the voltage applied to all pixel circuits of display units 22B, 22G, and 22R gradually increases to 0V, the ChLC molecules of all pixel circuits transition directly from the homeotropic state to the focal conic state (e.g., dark state), thereby allowing the user to perceive a black screen. The selection stage (e.g., duration T23 from time t2 to t3) and the non-selection stage (e.g., duration T24 from time t3 to t4) during the PWM scanning procedure shown in Figure 7 are similar to those shown in Figure 5, and therefore the details are repeated here.

[0040] Embodiment 4 FIG. 8 is a waveform diagram illustrating AC voltage pulse signals applied to pixel circuits during a full screen reset stage and PWM scanning procedure according to some embodiments.

[0041] The waveform diagram shown in FIG. 8 is similar to that shown in FIG. 7, except that the voltage applied to the pixel circuits during the second reset stage of FIG. 8 (e.g., duration T32 from time t1 to time t2) gradually decreases. More specifically, the first reset stage (e.g., duration T31 from time t0 to t1) is immediately followed by the second reset stage (e.g., duration T32), and there is no relaxation time following the first reset stage (e.g., duration T31) to allow the ChLC molecules in all pixel circuits of display units 22B, 22G, and 22R to transition from a homeotropic state to a planar state (e.g., a bright state), so the user does not perceive a white screen. At the end of the first reset stage (e.g., duration T31), the AC voltage V HT When this occurs, the voltages applied to all pixel circuits of display units 22B, 22G, and 22R gradually decrease to 0V. Furthermore, the duration of the second reset stage (e.g., duration T32) can be different from the duration of the first reset stage (e.g., duration T31). In some embodiments, durations T31 and T32 are between 10 ms and 300 ms. In some embodiments, durations T31 and T32 are between 10 ms and 490 ms.

[0042] Specifically, when the voltage applied to all pixel circuits of display units 22B, 22G, and 22R gradually decreases to 0V, the ChLC molecules of all pixel circuits transition directly from the homeotropic state to the focal conic state (e.g., dark state), thereby allowing the user to perceive a black screen. The selection stage (e.g., duration T33 from time t2 to t3) and the non-selection stage (e.g., duration T34 from time t3 to t4) during the PWM scanning procedure shown in Figure 8 are similar to those shown in Figure 5, and therefore the details are repeated here.

[0043] In consideration of the above, compared to the technique in which ChLC molecules are reset to a planar state by the reset step, by using the technique of applying different reset AC voltages in different reset steps as described in the first to fourth embodiments, it is possible to improve the contrast and NTSC color space of the display image rendered by the ChLC display device (e.g., improving the contrast from 7 to 10 and the NTSC color space from 23% to 32%) while maintaining the reflectance of the ChLC display device (e.g., about 29%). Furthermore, the user does not perceive any residual image while the ChLC display device is performing a full-screen reset operation, thereby improving the user experience.

[0044] FIG. 9 is a flowchart of a method for driving a cholesteric liquid crystal display according to some embodiments. See FIGS. 2 and 9. The order in which the steps of method 900 are shown in FIG. 9 is for illustration only, and the operations of method 900 can be performed in an order different from that shown in FIG. 9. It should be understood that additional operations may be performed before, during, and / or after method 900 shown in FIG. 9, and some other processes may only be briefly described herein. Method 900 may include steps 910-920.

[0045] Step 910: A full screen reset procedure is performed on the cholesteric liquid crystal display device to control cholesteric molecules in pixel circuits of the cholesteric liquid crystal display device to enter a focal conic state. In some embodiments, the full screen reset procedure includes a first reset stage and a second reset stage. In some embodiments, a relaxation time follows immediately after the first reset stage, and the second reset stage follows immediately after the relaxation time, as shown in FIG. 5. In some embodiments, the second reset stage follows immediately after the first reset stage, as shown in FIGS. 6, 7, and 8.

[0046] Step 920: To render an image on the cholesteric liquid crystal display device, a pulse width modulation (PWM) scanning procedure followed by a full screen reset procedure is performed on the cholesteric liquid crystal display device. In some embodiments, the PWM scanning procedure can refer to the embodiments of FIGS. 5 to 8 and includes a select stage and a deselect stage. The select stage may include a voltage pulse with a specific voltage amplitude to control the pixel value of each pixel circuit. During the deselect stage, a low voltage amplitude (e.g., V shown in FIGS. 5 to 8) is applied. NONSEL ) are applied to the pixel circuits of the activated scan electrodes. It should be noted that the state of the ChLC molecules in the pixel circuits does not change during the deselection stage.

[0047] While the present disclosure has been described with reference to specific embodiments, it is apparent that many alternatives, modifications, and variations may be apparent to those skilled in the art. For example, various components of the embodiments may be exchanged, added, or substituted in other embodiments. Also, not all elements in the figures are necessary for the operation of the disclosed embodiments. For example, one skilled in the art of the disclosed embodiments could make and use the teachings of the present disclosure by simply using the elements of the independent claims. Accordingly, the embodiments of the present disclosure described herein are intended to be illustrative, not limiting. Various changes can be made without departing from the spirit and scope of the present disclosure.

[0048] Although numerous features and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the invention, the present disclosure is illustrative only, and changes may be made in details, particularly in matters of shape, size, and arrangement of parts, within the scope of the principles of the invention to the fullest extent indicated by the broad and general meaning of the terms in which the appended claims are expressed.

Claims

1. A display panel is provided, the display panel comprising: a first substrate on which a plurality of first electrodes extending in a first direction are formed; a second substrate on which a plurality of second electrodes extending in a second direction different from the first direction are formed; a cholesteric liquid crystal layer formed between the first substrate and the second substrate; a drive circuit section configured to apply a plurality of alternating current (AC) voltage pulses to a pixel circuit at an intersection between the first electrode and the second electrode; Equipped with the drive circuit section is further configured to perform a full-screen reset procedure on the display panel, followed by a pulse-width modulation (PWM) scanning procedure to control cholesteric molecules in the pixel circuits to enter a focal conic state. Display device.

2. the full-screen reset procedure includes a first reset stage and a second reset stage arranged in sequence; the cholesteric molecules of the pixel circuit enter a homeotropic state during the first reset stage and enter the focal conic state during the second reset stage. The display device according to claim 1 .

3. a plurality of first AC voltage pulses with a first voltage amplitude are applied to the pixel circuit during the first reset stage; a plurality of second AC voltage pulses with a second voltage amplitude are applied to the pixel circuit during the second reset stage; the first voltage amplitude is greater than the second voltage amplitude; The display device according to claim 2 .

4. 4. The display device of claim 3, wherein the first duration of the first reset stage and the second duration of the second reset stage are between 10 ms and 490 ms.

5. the full screen reset procedure further includes a relaxation time between the first reset stage and the second reset stage; the cholesteric molecules of the cholesteric liquid crystal layer enter a planar state during the relaxation time.

5. A display device according to claim 4.

6. 6. The display device of claim 5, wherein the differential voltage sensed by the cholesteric molecules of the pixel circuit during the relaxation time is about 0 V, and the relaxation time is between 10 ms and 490 ms.

7. a plurality of first AC voltage pulses with a first voltage amplitude are applied to the pixel circuit during the first reset stage; a differential voltage sensed by the cholesteric molecules of the pixel circuit at the end of the first reset phase is equal to a negative first voltage with the first voltage amplitude; the drive circuit section gradually increases the differential voltage sensed by the cholesteric molecules of the pixel circuit from the negative first voltage to 0 V during the second reset stage; The display device according to claim 2 .

8. a plurality of first AC voltage pulses with a first voltage amplitude are applied to the pixel circuit during the first reset stage; a differential voltage sensed by the cholesteric molecules of the cholesteric liquid crystal layer at the end of the first reset phase is equal to a positive first voltage with the first voltage amplitude; the drive circuit section gradually reduces the differential voltage sensed by the cholesteric molecules of the pixel circuit from the positive first voltage to 0 V during the second reset stage. The display device according to claim 2 .

9. 1. A scan drive method for use in a cholesteric liquid crystal display device, comprising: performing a full screen reset procedure on the cholesteric liquid crystal display device to control cholesteric molecules in pixel circuits of the cholesteric liquid crystal display device to enter a focal conic state; performing a full screen reset procedure followed by a pulse width modulation (PWM) scanning procedure on the cholesteric liquid crystal display device to render an image on the cholesteric liquid crystal display device; A method comprising:

10. The full screen reset procedure includes a first reset stage and a second reset stage arranged in sequence, and the method includes: controlling the cholesteric molecules of the cholesteric liquid crystal display device to enter a homeotropic state during the first reset stage and to enter the focal conic state during the second reset stage; applying a plurality of first alternating current (AC) voltage pulses with a first voltage amplitude to the pixel circuit during the first reset phase; applying a plurality of second AC voltage pulses with a second voltage amplitude to the pixel circuit during the second reset stage; Further comprising: the first voltage amplitude is higher than the second voltage amplitude; 10. The method of claim 9.

11. 11. The method of claim 10, wherein the first duration of the first reset stage and the second duration of the second reset stage are between 10 ms and 490 ms.

12. The full screen reset procedure further includes a relaxation time between the first reset stage and the second reset stage, and the method further comprises: and controlling the cholesteric molecules of the pixel circuits of the cholesteric liquid crystal display device to enter a planar state during the relaxation time. The method of claim 11.

13. 13. The method of claim 12, wherein the differential voltage sensed by the cholesteric molecules of the pixel circuit during the relaxation time is about 0V, and the relaxation time is between 10 ms and 490 ms.

14. applying a plurality of first AC voltage pulses with a first voltage amplitude to the pixel circuit during the first reset stage; gradually increasing a differential voltage sensed by the cholesteric molecules of the pixel circuit during the second reset stage from a negative first voltage to 0V; Further comprising: a differential voltage sensed by the cholesteric molecules of the pixel circuit at the end of the first reset phase is equal to a negative first voltage with the first voltage amplitude; The method of claim 10.

15. applying a plurality of first AC voltage pulses with a first voltage amplitude to the pixel circuit during the first reset stage; gradually decreasing a differential voltage sensed by the cholesteric molecules of the pixel circuit during the second reset stage from a positive first voltage to 0V; Further comprising: a differential voltage sensed by the cholesteric molecules of the pixel circuit at the end of the first reset phase is equal to a positive first voltage with the first voltage amplitude; The method of claim 10.

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