Manufacturing method for capacitor element

Abstract

To provide a material with excellent ferroelectricity.SOLUTION: A metal oxide film includes a first layer and a second layer. The first layer contains a first oxygen and hafnium. The second layer contains a second oxygen and zirconium. Hafnium and zirconium are bonded together through the first oxygen. The second oxygen is bonded to zirconium.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a metal oxide, a capacitor using a metal oxide, and a manufacturing method thereof. Another embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) processed from semiconductor wafers and formed into chips, and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials and oxide semiconductors are known as semiconductor thin films applicable to transistors.

[0007] Furthermore, as shown in Non-Patent Document 1, research and development of memory arrays using ferroelectrics is being actively conducted. Furthermore, for the next generation of ferroelectric memories, research on hafnium oxide is also being actively conducted, including research on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), and research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-patent document 2] Zhen Fan,et al,“Ferroelectric HfO2-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-patent document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2”,VLSI 2020 [Non-patent document 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 Summary of the Invention [Problem to be solved by the invention]

[0009] As shown in Non-Patent Documents 1 to 4, various research and development efforts are being conducted on ferroelectrics. For example, Non-Patent Document 1 reports that, as shown in FIG. 5A, in the case of "orthorhombic phase ferroelectric," the sign of polarization (P) changes depending on the movement of oxygen atoms. Furthermore, Non-Patent Document 2 reports that, as shown in FIG. 5B, the magnitude of polarization and the dielectric constant (ε r ) has been reported to change.

[0010] In addition, in Non-Patent Document 3, as shown in FIG. 6, the rewrite endurance, which is one of the reliability tests for ferroelectrics, is 10 9 Furthermore, Non-Patent Document 4 reports the diffraction intensity, polarization, and crystal structure of HfO2, as shown in Figures 7A, 7B, and 7C.

[0011] As mentioned above, various research and development efforts are being conducted on ferroelectrics. However, there is still much room for improvement in the properties of ferroelectrics, and improvements in properties such as reliability are required.

[0012] Therefore, an object of one embodiment of the present invention is to provide a material having good ferroelectricity. Another object of one embodiment of the present invention is to provide a capacitor including a material that can have ferroelectricity. Another object of one embodiment of the present invention is to provide the capacitor with good productivity. Another object of one embodiment of the present invention is to provide a semiconductor device including the capacitor and a transistor. Another object of one embodiment of the present invention is to provide the semiconductor device that can be miniaturized or highly integrated.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0014] One aspect of the present invention is a metal oxide film having a first layer and a second layer, the first layer having a first oxygen and hafnium, the second layer having a second oxygen and zirconium, the hafnium and zirconium being bonded to each other via the first oxygen, and the second oxygen being bonded to the zirconium.

[0015] Another embodiment of the present invention is a metal oxide film having a plurality of first layers and a plurality of second layers, wherein the first layers have a first oxygen and hafnium, and the second layers have a second oxygen and zirconium, wherein the hafnium contained in one of the plurality of first layers and the zirconium contained in one of the plurality of second layers are bonded to each other via the first oxygen contained in one of the plurality of first layers, and the zirconium contained in one of the plurality of second layers and the hafnium contained in another of the plurality of first layers are bonded to each other via the second oxygen contained in one of the plurality of second layers.

[0016] Another embodiment of the present invention is a semiconductor device including a capacitor and a transistor electrically connected to the capacitor, wherein the capacitor includes a first conductor, a second conductor, and a metal oxide film. The metal oxide film is provided between the first conductor and the second conductor. The metal oxide film includes a first layer and a second layer. The first layer includes first oxygen and hafnium. The second layer includes second oxygen and zirconium. The hafnium and zirconium are bonded to each other through the first oxygen. The second oxygen is bonded to the zirconium.

[0017] In the above, the transistor preferably has silicon in a channel formation region.

[0018] In the above, the transistor preferably includes an oxide semiconductor in a channel formation region.

[0019] In the above, the concentration of at least one of hydrogen and carbon contained in the metal oxide film is 5×10 20 atoms / cm 3 It is preferable that:

[0020] In the above, the concentration of at least one of hydrogen and carbon contained in the metal oxide film is 1×10 20 atoms / cm 3 It is preferable that:

[0021] In the above, the metal oxide film may contain chlorine.

[0022] Another embodiment of the present invention is a method for forming a metal oxide film, which includes a first step of introducing a first oxidizing gas, a second step of introducing a first precursor, a third step of introducing a second oxidizing gas, and a fourth step of introducing a second precursor, wherein the first precursor is HfCl4 and the second precursor is ZrCl4, and the first to fourth steps are repeated multiple times.

[0023] In the above, the first oxidizing gas and the second oxidizing gas are preferably either or both of H2O and O3, respectively.

[0024] In the above, it is preferable that there is a fifth step of introducing a purge gas between the first step and the second step, between the second step and the third step, between the third step and the fourth step, and between the fourth step and the first step, and that the purge gas is N2.

[0025] In the above, it is preferable that one or more of the first to fourth steps are performed using an ALD apparatus. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a material having good ferroelectricity can be provided. According to another embodiment of the present invention, a capacitor including a material that can have ferroelectricity can be provided. According to another embodiment of the present invention, the capacitor can be provided with good productivity. According to another embodiment of the present invention, a semiconductor device including the capacitor and a transistor can be provided. According to another embodiment of the present invention, the semiconductor device can be miniaturized or highly integrated.

[0027] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0028] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a capacitor according to one embodiment of the present invention. [Figure 2] FIG. 2 is a model diagram illustrating the crystal structure of hafnium oxide according to one embodiment of the present invention. [Figure 3] FIG. 3 is a diagram showing a film formation sequence of a metal oxide film according to one embodiment of the present invention. [Figure 4] Fig. 4A is a cross-sectional view of a metal oxide film manufacturing apparatus according to one embodiment of the present invention, and Fig. 4B is a model diagram of the crystal structure of HfZrOx. [Figure 5] FIG. 5A is a diagram for explaining the polarization of a ferroelectric material, as disclosed in Non-Patent Document 1, and FIG. 5B is a diagram for explaining the magnitude of polarization and the change in dielectric constant depending on the composition of Hf and Zr, as disclosed in Non-Patent Document 2. [Figure 6] FIG. 6 is a diagram for explaining the rewrite endurance of a ferroelectric material, as disclosed in Non-Patent Document 3. [Figure 7] 7A to 7C are diagrams for explaining the diffraction intensity, polarization, and crystal structure of HfO2, as disclosed in Non-Patent Document 4. [Figure 8] 8A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 9] 9A and 9B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 10] Figure 10A is a diagram explaining the classification of IGZO crystal structures, Figure 10B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 10C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 11] 11A and 11B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A and 12B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A and 13B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17]17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 26B to 26D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 27B to 27D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 28B to 28D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 29] 29A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 29B to 29D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 30 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 32] FIG. 32 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 33] FIG. 33 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 34] Fig. 34A is a plan view of a semiconductor device according to one embodiment of the present invention, and Fig. 34B and Fig. 34C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 35 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 36] FIG. 36 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 37] FIG. 37 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 38] FIG. 38 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 39] 39A and 39B are cross-sectional views illustrating the structure of a memory device according to one embodiment of the present invention. [Figure 40] 40A to 40C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 41] 41A and 41B are block diagrams illustrating a configuration example of a memory device according to one embodiment of the present invention, and perspective views illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 42] Fig. 42A is a circuit diagram showing an example of the configuration of a memory cell, Fig. 42B is a graph showing an example of the hysteresis characteristics of a ferroelectric layer, and Fig. 42C is a timing chart showing an example of a method of driving a memory cell. [Figure 43] 43A to 43E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 44] 44A to 44H are diagrams showing electronic devices according to one embodiment of the present invention. [Figure 45] Figure 45A is an optical microscope photograph showing the appearance of the sample, Figure 45B is a cross-sectional schematic diagram of the sample, and Figure 45C is a diagram showing the input voltage waveform. [Figure 46] 46A to 46F are diagrams for explaining a method for obtaining PE characteristics using a triangular wave. [Figure 47] 47A and 47B show the results of PE and GIXD measurements, respectively. [Figure 48] FIG. 48 shows the results of the SIMS analysis. [Figure 49] FIG. 49 shows the results of the SIMS analysis. [Figure 50] FIG. 50 shows the results of the SIMS analysis. [Figure 51] FIG. 51 shows the results of the SIMS analysis. [Figure 52] 52A and 52B are diagrams showing the measurement results of fatigue characteristics. [Figure 53] Fig. 53A is a graph showing PE characteristics, and Fig. 53B is a graph showing the measurement results of fatigue characteristics. [Figure 54] FIG. 54 is a diagram showing PE characteristics for each voltage amplitude of a triangular wave. [Figure 55] Figure 55A is a schematic top view of the sample, and Figure 55B is a schematic cross-sectional view of the sample. [Figure 56]FIG. 56 is a diagram illustrating the results of electron holography analysis. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0030] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may unintentionally be thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbol may be assigned.

[0031] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0032] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0033] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0034] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0036] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0037] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0038] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0039] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0040] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0041] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0042] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor, or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0043] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0044] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0045] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0047] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0048] (Embodiment 1) In this embodiment, a method for manufacturing a capacitor according to one embodiment of the present invention will be described with reference to FIGS. 1A to 1C.

[0049] As shown in FIG. 1A, a conductor 110 is formed on a substrate (not shown). The conductor 110 can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. By forming the conductor 110 using the ALD method, it may be possible to relatively easily form a conductive film with good flatness. For example, a titanium nitride film may be formed using a thermal ALD method. The conductor 110 may also be appropriately patterned using a lithography method or the like.

[0050] 1B, the insulator 130 is formed on the conductor 110. The insulator 130 can be formed by sputtering, CVD, ALD, or the like. For example, by forming the insulator 130 by the ALD method, the insulator 130 can be formed on the conductor 110 with good coverage. This can prevent leakage current from occurring between the upper electrode and the lower electrode of the capacitor element 100.

[0051] It is preferable that the insulator 130 is made of a material that can have ferroelectricity, such as hafnium oxide, zirconium oxide, or HfZrO. x(x is a real number greater than 0), hafnium oxide to which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added, and zirconium oxide to which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added. Furthermore, examples of materials that may have ferroelectricity include PbTiO x Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound containing multiple materials selected from the materials listed above may be used. Alternatively, the insulator 130 may have a layered structure made of multiple materials selected from the materials listed above.

[0052] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material that can exhibit ferroelectricity because it can be processed into a thin film of a few nanometers and still retain ferroelectricity. Here, the film thickness of the insulator 130 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). By thinning the insulator 130, the capacitor element 100 can be combined with a miniaturized transistor 200, which will be described later, to form a semiconductor device.

[0053] Here, the crystal structure of hafnium oxide, one of the materials that can be used for the insulator 130, will be described with reference to FIG. 2. FIG. 2 is a model diagram illustrating the crystal structure of hafnium oxide (HfO2 in this embodiment). Hafnium oxide is known to have a variety of crystal structures, such as cubic (space group: Fm-3m), tetragonal (space group: P42 / nmc), orthorhombic (space group: Pbc22), and monoclinic (space group: P21 / c) crystal structures shown in FIG. 2. Furthermore, as shown in FIG. 2, each of the above crystal structures can undergo a phase change. For example, by doping hafnium oxide with zirconium to form a composite material, the crystal structure of monoclinic hafnium oxide can be changed to an orthorhombic crystal structure.

[0054] When the above-mentioned composite material is formed by alternately depositing hafnium oxide and zirconium oxide in a 1:1 ratio using the ALD method, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. The amorphous structure can then be converted to an orthorhombic crystal structure by subjecting the composite material to a heat treatment or the like. Note that the orthorhombic crystal structure may change to a monoclinic crystal structure. To impart ferroelectricity to the above-mentioned composite material, an orthorhombic crystal structure is preferable to a monoclinic crystal structure.

[0055] The crystal structure of the insulator 130 is not particularly limited. The crystal structure of the insulator 130 may be one or more selected from the group consisting of a cubic system, a tetragonal system, an orthorhombic system, and a monoclinic system. In particular, the insulator 130 preferably has an orthorhombic crystal structure because it exhibits ferroelectricity. Alternatively, the crystal structure of the insulator 130 may be an amorphous structure. Alternatively, the insulator 130 may have a composite structure having an amorphous structure and a crystalline structure.

[0056] The insulator 130 is a material containing hafnium oxide and zirconium oxide (HfZrO xWhen using a film made of a material other than a silicon dioxide, it is preferable to form the film using a thermal ALD method.

[0057] Furthermore, when forming the insulator 130 using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also referred to as Hydro Carbon, HC) as a precursor. If the insulator 130 contains either or both of hydrogen and carbon, crystallization of the insulator 130 may be hindered. For this reason, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the insulator 130. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0058] Furthermore, when forming the insulator 130 using a thermal ALD method, the oxidizing agent can be H2O or O3. Note that using O3 as the oxidizing agent for the thermal ALD method is more preferable than using H2O because it can reduce the hydrogen concentration in the film. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0059] 1C, the conductor 120 is formed on the insulator 130. Here, the conductor 120 is disposed apart from the conductor 110 via the insulator 130. The conductor 120 may have a layered structure of a conductor 120a provided on and in contact with the insulator 130 and a conductor 120b provided on and in contact with the conductor 120a.

[0060] The conductor 120a may be formed by an ALD method, a CVD method, or the like. For example, a titanium nitride film may be formed by a thermal ALD method. Here, the conductor 120a is preferably formed by a method in which the substrate is heated, as in the thermal ALD method. For example, the substrate temperature may be set to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher. Alternatively, the substrate temperature may be set to 500°C or lower, preferably 450°C or lower. For example, the substrate temperature may be set to about 400°C.

[0061] By forming the conductor 120a within the temperature range described above, it is possible to impart ferroelectricity to the insulator 130 without performing a high-temperature baking process (e.g., a baking process at a heat treatment temperature of 400°C or higher or 500°C or higher) after forming the conductor 120a.

[0062] Furthermore, by depositing the conductor 120a using the ALD method, which causes relatively little damage to the base, as described above, excessive destruction of the crystalline structure of the insulator 130 can be suppressed, thereby enhancing the ferroelectricity of the insulator 130.

[0063] For example, when the conductor 120a is formed by a sputtering method or the like, there is a possibility that damage may occur in the underlayer, in this case the insulator 130. For example, when a material containing hafnium oxide and zirconium oxide (HfZrO x When the conductor 120a is formed by sputtering, the HfZrO x Damage occurs to HfZrO x Therefore, it is preferable to form the conductor 120a by the ALD method, which causes relatively little damage to the underlying layer.

[0064] In addition, after forming the conductor 120a by sputtering, a heat treatment is performed to form HfZrO x It can also repair damage to the crystal structure of the material.

[0065] where HfZrO x Dangling bonds in (e.g., O * ) and HfZrO x The hydrogen contained in the x In some cases, damage to the crystal structure of HfZrO cannot be repaired. x The dangling bonds in the conductive layer 120a are formed by damage caused when the conductive layer 120a is formed by sputtering, for example.

[0066] Therefore, the insulator 130, here HfZrO x For example, the insulator 130 may contain hydrogen at a concentration of 5×10 20 atoms / cm 3 Less than 1×10 is preferred 20 atoms / cm 3 The following is more preferred:

[0067] As described above, in order to reduce the hydrogen concentration in the insulator 130, it is preferable to use a material that does not contain hydrocarbons as a precursor. This may result in the insulator 130 being a film that does not contain hydrocarbons as a main component or that contains an extremely small amount of hydrocarbons. For example, the concentration of carbon that constitutes the hydrocarbons contained in the insulator 130 is preferably 5×10 20 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 The result is as follows.

[0068] Furthermore, when a material that does not contain hydrocarbons is used as a precursor to form the insulator 130, the insulator 130 may be a film that does not contain carbon as a main component or has an extremely low carbon content. For example, the carbon concentration in the insulator 130 is preferably 5×10 20 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 The result is as follows.

[0069] It is preferable to use a material containing very little of at least one of hydrogen, hydrocarbon, and carbon for the insulator 130, but it is particularly important to reduce the hydrocarbon and carbon contents. Hydrocarbons and carbon are heavier molecules or atoms than hydrogen, and therefore are difficult to remove in subsequent processes. Therefore, it is preferable to thoroughly eliminate hydrocarbons and carbon when forming the insulator 130.

[0070] As described above, by using a material for the insulator 130 that does not contain at least one of hydrogen, hydrocarbons, and carbon, or that has an extremely low content of at least one of hydrogen, hydrocarbons, and carbon, it is possible to improve the crystallinity of the insulator 130 and create a structure with high ferroelectricity.

[0071] As described above, by thoroughly removing impurities in the film of the insulator 130, here, at least one of hydrogen, hydrocarbon, and carbon, a film having high-purity intrinsic ferroelectricity, here, a high-purity intrinsic capacitor element, can be formed. Note that the manufacturing process of a capacitor element having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor described in the embodiment described later are highly compatible. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0072] As described above, in one embodiment of the present invention, for example, a ferroelectric material is formed as the insulator 130 by thermal ALD using a hydrocarbon-free precursor (typically a chlorine-based precursor) and an oxidizing agent (typically O). Then, the conductor 120a is formed by thermal ALD (typically at 400°C or higher). This allows the crystallinity or ferroelectricity of the insulator 130 to be improved without annealing after the formation of the conductor 120a, in other words, by utilizing the temperature during the formation of the conductor 120a. Note that improving the crystallinity or ferroelectricity of the insulator 130 by utilizing the temperature during the formation of the conductor 120a without annealing after the formation of the conductor 120a is sometimes referred to as self-annealing.

[0073] Note that the conductor 120b may be formed by a sputtering method, an ALD method, a CVD method, or the like. For example, tungsten may be formed by a metal CVD method.

[0074] In the above manner, the capacitor element 100 having the insulator 130 between the conductor 110 and the conductor 120 shown in FIG. 1C can be manufactured. As described above, the capacitor element 100 according to the present embodiment can enhance the ferroelectricity of the insulator 130 without performing a high-temperature baking process after the formation of the conductor 120a. Thereby, the process of manufacturing the ferroelectric capacitor can be reduced, so that the productivity of the ferroelectric capacitor and the semiconductor device including the same can be improved.

[0075] <Film formation by ALD method> Hereinafter, with reference to FIGS. 3 and 4, a method for forming the insulator 130 by the ALD method and a film forming apparatus used for the film formation will be described.

[0076] The ALD method utilizes the self-control property of atoms and can deposit atoms one by one, so that extremely thin film formation is possible, film formation on a structure with a high aspect ratio is possible, film formation with few defects such as pinholes is possible, film formation with excellent coverage is possible, and film formation at low temperature is possible, and the like.

[0077] In the ALD method, a first source gas (also called a precursor) and a second source gas (also called an oxidizing gas) are alternately introduced into the reaction chamber, and film formation is achieved by repeating this process. When introducing the precursor or oxidizing gas, N2, Ar, or other carrier / purge gases can be introduced into the reaction chamber along with the precursor or oxidizing gas. The use of a carrier / purge gas prevents the precursor or oxidizing gas from adsorbing to the inside of the piping and valves, allowing the precursor or oxidizing gas to be introduced into the reaction chamber (also called a carrier gas). Furthermore, the carrier / purge gas allows the precursor or oxidizing gas remaining in the reaction chamber to be quickly exhausted (also called a purge gas). Because of its dual role of introduction (carrier) and exhaust (purge), it is sometimes called a carrier / purge gas. Furthermore, the use of a carrier / purge gas improves the uniformity of the resulting film, making it preferable.

[0078] 3 shows a film formation sequence of a film of a material that can have ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method. In the following, an example is shown in which a ferroelectric layer containing hafnium oxide and zirconium oxide is formed as the insulator 130.

[0079] The precursor 401 may be a precursor containing hafnium and one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen. The precursor 402 may be a precursor containing zirconium and one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen. In this section, HfCl4 is used as the precursor 401 containing hafnium, and ZrCl4 is used as the precursor 402 containing zirconium.

[0080] Precursors 401 and 402 are formed by heating and gasifying liquid or solid raw materials. Precursor 401 is formed from a solid HfCl4 raw material, and precursor 402 is formed from a solid ZrCl4 raw material. Precursors 401 and 402 preferably have reduced impurities, and these solid raw materials also preferably have reduced impurities. Examples of such impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, and Zn. In the solid HfCl4 raw material and the solid ZrCl4 raw material, the above impurities are preferably less than 1000 wppb. Here, wppb is a unit that represents the concentration of an impurity converted into mass in parts per billion.

[0081] The oxidizing gas 403 may be O2, O3, N2O, or NO 2、 One or more gases selected from H2O and H2O2 can be used. In this example, a gas containing H2O is used as the oxidizing gas 403. In addition, one or more gases selected from N2, He, Ar, Kr, and Xe can be used as the carrier / purge gas 404. In this example, N2 is used as the carrier / purge gas 404.

[0082] First, an oxidizing gas 403 is introduced into the reaction chamber (step S01). Next, the introduction of the oxidizing gas 403 is stopped, leaving only the carrier purge gas 404, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S02). Next, a precursor 401 and a carrier purge gas 404 are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S03). In this way, the precursor 401 is adsorbed onto the surface to be formed. Next, the introduction of the precursor 401 is stopped, leaving only the carrier purge gas 404, and the precursor 401 remaining in the reaction chamber is purged (step S04). Next, the oxidizing gas 403 is introduced into the reaction chamber. By introducing the oxidizing gas 403, the precursor 401 is oxidized to form hafnium oxide (step S05). Next, the introduction of the oxidizing gas 403 is stopped, and only the carrier purge gas 404 is used to purge the oxidizing gas 403 remaining in the reaction chamber (step S06).

[0083] Next, precursor 402 and carrier purge gas 404 are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S07). In this way, precursor 402 is adsorbed onto the oxygen layer of the hafnium oxide. Next, the introduction of precursor 402 is stopped, and only carrier purge gas 404 is used to purge the precursor 402 remaining in the reaction chamber (step S08). Next, returning to step S01, oxidizing gas 403 is introduced into the reaction chamber. By introducing oxidizing gas 403, precursor 402 is oxidized, and zirconium oxide is formed on the hafnium oxide.

[0084] The above-described steps S01 to S08 constitute one cycle, which is repeated until the desired film thickness is achieved. Note that steps S01 to S08 may be performed at a temperature in the range of 250° C. to 450° C., preferably 350° C. to 400° C.

[0085] As described above, by forming the insulator 130 using the ALD method, a layered crystalline structure can be formed, in which a hafnium layer, an oxygen layer, a zirconium layer, and an oxygen layer are alternately formed. Furthermore, as described above, by forming the insulator 130 using a precursor with reduced impurities, it is possible to prevent impurities from being mixed in during film formation and interfering with the formation of the layered crystalline structure. By forming the insulator 130 into a layered crystalline structure with high crystallinity, the insulator 130 can be made to have high ferroelectricity.

[0086] However, the insulator 130 does not necessarily exhibit ferroelectricity immediately after being formed. As described above, the insulator 130 may exhibit ferroelectricity not immediately after being formed, but after the conductor 120 is formed on the insulator 130.

[0087] Next, a manufacturing apparatus used for film formation by the ALD method will be described with reference to Fig. 4A. Fig. 4A is a schematic diagram of a manufacturing apparatus 900 used for film formation by the ALD method.

[0088] 4A, the manufacturing apparatus 900 includes a reaction chamber 901, a gas inlet 903, a reaction chamber inlet 904, an exhaust port 905, a wafer stage 907, and a shaft 908. In FIG. 4A, a wafer 950 is placed on the wafer stage 907.

[0089] A heater system for heating the precursor 401, precursor 402, oxidizing gas 403, and carrier / purge gas 404 may be disposed inside the reaction chamber 901. The wafer stage 907 may also be provided with a heater system for heating the wafer 950. The wafer stage 907 may also be provided with a rotation mechanism for horizontally rotating the stage about an axis 908. Although not shown, a gas supply system is disposed before the gas inlet 903, which introduces the precursor 401, precursor 402, oxidizing gas 403, and carrier / purge gas 404 into the gas inlet 903 at appropriate timing and at appropriate flow rates for appropriate periods of time. Although not shown, an exhaust system including a vacuum pump is disposed beyond the exhaust port 905.

[0090] The manufacturing apparatus 900 shown in Figure 4A is an ALD apparatus known as a cross-flow type. The flows of precursor 401, precursor 402, oxidizing gas 403, and carrier / purge gas 404 in the cross-flow type are described below. Precursor 401, precursor 402, oxidizing gas 403, and carrier / purge gas 404 flow from gas inlet 903 to reaction chamber 901 via reaction chamber inlet 904, reach wafer 950, and are exhausted through exhaust port 905. The arrows in Figure 4A schematically indicate the direction of gas flow.

[0091] As described above, in step S05 of introducing oxidizing gas 403 into reaction chamber 901 shown in FIG. 3, precursor 401 adsorbed on wafer 950 is oxidized by oxidizing gas 403 to form hafnium oxide. Due to the cross-flow structure of manufacturing apparatus 900, oxidizing gas 403 comes into contact with heated reaction chamber components for a long time before reaching wafer 950. For this reason, when O3 is used as oxidizing gas 403, for example, the oxidizing gas 403 reacts with a high-temperature solid surface before reaching wafer 950, decomposing the oxidizing gas 403 and reducing its oxidizing power. Therefore, the deposition rate of hafnium oxide depends on the distance that oxidizing gas 403 reaches wafer 950 from reaction chamber inlet 904. When wafer stage 907 rotates horizontally around axis 908, the periphery of wafer 950 reaches oxidizing gas 403 first, resulting in a hafnium oxide film with a thicker film thickness at the periphery and a thinner film thickness at the center.

[0092] Therefore, it is necessary to set the heating temperature of the reaction chamber to an appropriate temperature to prevent the oxidizing power from decreasing due to the decomposition of the oxidizing gas 403. Note that although the oxidation of the precursor 401 has been described above as an example, the same applies to the oxidation of the precursor 402.

[0093] As a result, a ferroelectric layer with excellent in-plane thickness uniformity can be formed. The in-plane thickness uniformity is preferably ±1.5% or less, and more preferably ±1.0% or less. If the maximum in-plane thickness minus the minimum in-plane thickness is defined as RANGE, and the in-plane thickness uniformity is defined as ±PNU (Percent Non-Uniformity) (%), then the in-plane thickness uniformity can be calculated as ±PNU (%) = (RANGE × 100) / (2 × average in-plane thickness).

[0094] Furthermore, as described above, a highly uniform oxygen layer can be formed by the oxidizing gas 403, which allows the formation of a highly ordered layered crystal structure. By forming the insulator 130 into a highly ordered layered crystal structure in this way, the insulator 130 can have high ferroelectricity.

[0095] By using the above method, it is possible to form the insulator 130 made of a material that can have ferroelectricity. By forming the capacitor 100 using such an insulator 130, it is possible to make the capacitor 100 a ferroelectric capacitor.

[0096] Next, a metal oxide according to one embodiment of the present invention, here HfZrO x The crystal structure model will be explained with reference to FIG. 4B.

[0097] Figure 4B shows HfZrO x , where Hf 0.5 Zr 0.5 4B is a model diagram of the crystal structure of HfO2. The directions of the a-axis, b-axis, and c-axis are also shown in Figure 4B. Figure 4B shows the orthorhombic structure (P CA 21) The structure is one in which Zr is arranged in layers. The orthorhombic structure cell of HfO2 was optimized using first-principles calculations.

[0098] 4B, it can be seen that hafnium and zirconium are bonded to each other via oxygen. This can be achieved by alternately depositing hafnium and zirconium films using the ALD method, as shown in the film formation sequence of FIG.

[0099] In other words, the metal oxide of one embodiment of the present invention can be formed into a crystal structure as shown in FIG. 4B by using the film formation sequence shown in FIG. 3 and the manufacturing apparatus shown in FIG. 4A.

[0100] According to one embodiment of the present invention, a capacitor including a material that can have ferroelectricity can be provided. Alternatively, according to one embodiment of the present invention, the capacitor can be provided with high productivity. Alternatively, according to one embodiment of the present invention, a capacitor that can be miniaturized or highly integrated can be provided.

[0101] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0102] (Embodiment 2) 8A to 25D, an example of a semiconductor device including a transistor 200 and a capacitor 100 according to one embodiment of the present invention and a manufacturing method thereof will be described. Here, the description of the capacitor 100 in Embodiment 1 can be referred to for the capacitor 100 used in the semiconductor device.

[0103] <Configuration example of semiconductor device> 8A to 8D are a top view and a cross-sectional view of a semiconductor device including a transistor 200 and a capacitor 100. FIG. 8A is a top view of the semiconductor device. FIGS. 8B to 8D are cross-sectional views of the semiconductor device. FIG. 8B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 8A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 8C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 8A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 8D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 8A. Note that some elements are omitted from the top view of FIG. 8A for clarity.

[0104] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over an insulator 275 provided in the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and an insulator 285 over the insulator 283 and the insulator 274. The insulators 212, 214, 216, 275, 280, 282, 283, 285, and 274 function as interlayer films. Additionally, insulator 283 contacts a portion of the top surface of insulator 214 , the side surface of insulator 216 , the side surface of insulator 222 , the side surface of insulator 275 , the side surface of insulator 280 , and the side surface and top surface of insulator 282 .

[0105] Here, the transistor 200 has a semiconductor layer, a first gate, a second gate, a source, and a drain. One of the source and the drain of the transistor 200 is above the semiconductor layer and in contact with one of the electrodes of the capacitor 100. Note that an insulator 271 (insulators 271a and 271b) is provided on and in contact with the source and the drain of the transistor 200. Note that the insulators 271a and 271b may be collectively referred to as the insulator 271.

[0106] The capacitor 100 is provided in an opening that reaches one of the source and drain of the transistor 200 and is formed in the insulators 271, 275, 280, 282, 283, and 285. The capacitor 100 includes a conductor 110 that contacts the top surface of one of the source and drain of the transistor 200 in the opening, an insulator 130 that is disposed on the conductor 110 and the insulator 285, and a conductor 120 (conductors 120a and 120b) that is disposed on the insulator 130. Here, the conductor 110 is preferably disposed along the side and bottom surfaces of the opening.

[0107] It is also preferable that an insulator 245 be provided between the conductor 110 and the insulator 280. It is also preferable that the insulator 245 has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). It is also preferable that the insulator 245 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulator 245 has lower permeability to one or both of oxygen and hydrogen than the insulator 280.

[0108] [Transistor 200] As shown in FIGS. 8A to 8D, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 and / or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 271b on the oxide 271b. The oxide 230b includes a conductor 242b on the oxide 230b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 254 and overlapping with a portion of the oxide 230b, and an insulator 275 arranged on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. 8B and 8C , insulator 252 contacts the upper surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and upper surface of oxide 230b, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the lower surface of insulator 250. Furthermore, the upper surface of conductor 260 is disposed so as to be at approximately the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the upper surface of insulator 280. Furthermore, insulator 282 contacts at least a portion of the upper surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0109] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0110] Openings are provided in the insulator 280 and the insulator 275, reaching the oxide 230b. The insulator 252, the insulator 250, the insulator 254, and the conductor 260 are disposed in the openings. In addition, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are disposed between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0111] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0112] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0113] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 252, 250, and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 242a functions as either a source or a drain, and the conductor 242b functions as the other. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0114] FIG. 9A shows an enlarged view of the vicinity of the channel formation region in FIG. 8B. When oxygen is supplied to the oxide 230b, a channel formation region is formed in the region between the conductor 242a and the conductor 242b. Therefore, as shown in FIG. 9A, the oxide 230b includes a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is located in the region between the conductor 242a and the conductor 242b. The region 230ba overlaps with the conductor 242a, and the region 230bb overlaps with the conductor 242b.

[0115] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a lower carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0116] Furthermore, the regions 230ba and 230bb, which function as source and drain regions, have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces resistance. That is, the regions 230ba and 230bb are n-type regions with a higher carrier concentration and lower resistance than the region 230bc.

[0117] Here, the carrier concentration of the region 230bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0118] The carrier concentration in an oxide can be measured using a phase shift method in electron holography analysis, scanning capacitance microscopy (SCM), scanning spreading resistance microscopy (SSRM), or the like. In this specification, a material with a relatively high carrier concentration may be referred to as a material with high electrical conductivity or a material with low resistivity. On the other hand, a material with a relatively low carrier concentration may be referred to as a material with low electrical conductivity or a material with high resistivity.

[0119] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, whose carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0120] 9A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0121] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0122] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0123] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0124] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0125] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0126] In this way, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0127] Furthermore, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Because the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0128] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0129] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0130] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0131] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0132] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface will cause variations in the characteristics of a semiconductor device having the transistor.

[0133] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0134] Therefore, in this embodiment, in a state where the conductors 242a and 242b are provided on the oxide 230b, microwave processing is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 230bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0135] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 230bc. The V of the region 230bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen (H) is removed from the region 230bc, and oxygen vacancies (V O ) can be compensated with oxygen. In other words, in the region 230bc, "V O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen vacancies and V O H can be reduced to lower the carrier concentration.

[0136] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 271 and 280 that are provided to cover the oxide 230b and the conductor 242. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0137] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 252 or after forming the insulating film that becomes the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 252 or the insulator 250 in this manner, oxygen can be efficiently injected into the region 230bc. Furthermore, by arranging the insulator 252 so that it is in contact with the side surface of the conductor 242 and the surface of the region 230bc, it is possible to prevent more oxygen than necessary from being injected into the region 230bc, and to prevent oxidation of the side surface of the conductor 242. Furthermore, it is possible to prevent oxidation of the side surface of the conductor 242 during the formation of the insulating film that becomes the insulator 250.

[0138] The oxygen implanted into the region 230bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 230bc may take one or more of the above forms, and oxygen radicals are particularly preferred. This also improves the film quality of the insulators 252 and 250, thereby improving the reliability of the transistor 200.

[0139] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, thereby maintaining n-type conductivity. In this case, the oxide semiconductor has a structure in which an i-type region (region 230bc) ​​is sandwiched between n-type regions (regions 230ba and 230bb). This structure is sometimes called an n-in junction. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate plane.

[0140] 8C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0141] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulators 252, 250, 254, and conductor 260.

[0142] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0143] The oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0144] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0145] Specifically, when the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0146] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, an atomic ratio of In:M:Zn=1:1:2 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0147] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0148] 8C and other figures, providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230 may result in indium being unevenly distributed in the oxide 230 at and near the interface between the oxide 230 and the insulator 252. This results in the surface area of ​​the oxide 230 having an atomic ratio similar to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 230, particularly the oxide 230b, can improve the field-effect mobility of the transistor 200.

[0149] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0150] At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, 283, and 285 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0151] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0152] For the insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a high hydrogen barrier property, for the insulators 212, 275, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function, for the insulators 214, 271, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 285 toward the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like toward the substrate through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like toward an upper side of the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0153] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured that have excellent characteristics.

[0154] Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but may have a polycrystalline structure in some areas. The insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0155] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited by, for example, sputtering. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore can reduce the hydrogen concentration in the insulators 212, 214, 271, 275, 282, 283, and 285. Note that the deposition method is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0156] It may also be preferable to reduce the resistivity of the insulators 212, 275, and 283. For example, it may be preferable to reduce the resistivity of the insulators 212, 275, and 283 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212, the insulator 275, and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 110 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 275, and the insulator 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0157] Furthermore, the insulators 216, 274, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as the insulators 216, 274, 280, and 285 as appropriate.

[0158] The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Also, a part of the conductor 205 may be embedded in the insulator 214.

[0159] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0160] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0161] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0162] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0163] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0164] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0165] As shown in FIG. 8A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 8C, the conductor 205 preferably extends to areas outside the channel width direction ends of the oxide 230a and the oxide 230b. That is, outside the side surfaces of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0166] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0167] 8C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0168] Note that although the transistor 200 illustrates a structure in which the conductor 205 has a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0169] Insulator 222 and insulator 224 function as gate insulators.

[0170] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0171] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 and the oxygen contained in the oxide 230.

[0172] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0173] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 222 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0174] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like, as appropriate.

[0175] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0176] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0177] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0178] The conductor 242a and the conductor 242b are provided in contact with the top surface of the oxide 230b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0179] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0180] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0181] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By forming the conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction can be increased, as shown in Fig. 8D. This increases the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0182] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film at least against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. The insulator 271 may be made of, for example, aluminum oxide or magnesium oxide.

[0183] The insulator 275 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. The insulator 275 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 275 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0184] By providing the insulators 271 and 275 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. That is, it is possible to prevent the oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase the resistivity and reduce the on-current.

[0185] The insulator 252 functions as part of the gate insulator. A barrier insulating film against oxygen is preferably used as the insulator 252. Any of the insulators that can be used for the insulator 282 described above may be used as the insulator 252. An insulator containing an oxide of one or both of aluminum and hafnium may be used as the insulator 252. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0186] As shown in FIG. 8C, the insulator 252 is provided in contact with the upper surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the upper surface of the insulator 222. In other words, the regions of the oxide 230a, the oxide 230b, and the insulator 224 that overlap with the conductor 260 are covered with the insulator 252 in the cross section in the channel width direction. This allows the insulator 252, which has a barrier property against oxygen, to block oxygen from being released from the oxide 230a and the oxide 230b when heat treatment or the like is performed. Therefore, oxygen vacancies (V O ) can be reduced. O ), and V O H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0187] Conversely, even if the insulators 280 and 250 contain excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxides 230a and 230b. Therefore, the regions 230ba and 230bb can be prevented from being excessively oxidized via the region 230bc, which can cause a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0188] 8B, the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280. This reduces the oxidation of the side surface of the conductor 242 and the formation of an oxide film on the side surface. This reduces the decrease in the on-state current or the field-effect mobility of the transistor 200.

[0189] Furthermore, the insulator 252, together with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 252 be thin. The thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 252 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 252 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 252 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0190] To form the insulator 252 into a thin film as described above, it is preferable to use the ALD method. ALD methods include the thermal ALD method, in which the reaction between a precursor and a reactant is carried out using only thermal energy, and the plasma enhanced ALD method, in which a plasma excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0191] The ALD method utilizes the self-regulating property of atoms to deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 252 can be formed with good coverage on the side surfaces of openings formed in the insulator 280 or the like, and with the thin film thickness as described above.

[0192] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0193] The insulator 250 functions as part of the gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the insulator 252. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.

[0194] As with insulator 224, insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less, and more preferably 0.5 nm or more and 15.0 nm or less. In this case, insulator 250 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0195] 8A to 8D, the insulator 250 is shown as a single layer, but the present invention is not limited to this and may have a laminated structure of two or more layers. For example, as shown in Fig. 9B, the insulator 250 may have a two-layer laminated structure of an insulator 250a and an insulator 250b on the insulator 250a.

[0196] As shown in FIG. 9B , when the insulator 250 has a two-layer stacked structure, it is preferable that the lower insulator 250a be formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b be formed using an insulator that suppresses oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b contains at least oxygen and hafnium. The thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 250b only needs to have a region with the above-described thickness in at least a portion.

[0197] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a stacked structure of the insulators 250a and 250b, a thermally stable stacked structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 250 to be increased.

[0198] The insulator 254 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 254. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230b. The insulator 254 may be any of the insulators that can be used for the insulator 283 described above. For example, silicon nitride formed by the PEALD method may be used as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0199] Furthermore, the insulator 254 may also have a barrier property against oxygen, which can prevent oxygen contained in the insulator 250 from diffusing into the conductor 260.

[0200] Furthermore, the insulator 254, together with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 254 be thin. The thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 254 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 254 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 254 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0201] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 8B and 8C, the top surface of the conductor 260 is generally flush with the top surface of the insulator 250. Although the conductor 260 is shown in FIGS. 8B and 8C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0202] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0203] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0204] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0205] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0206] 8C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0207] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are to be provided. The top surface of the insulator 280 may be flattened.

[0208] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0209] The insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 280. For example, the insulator 280 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0210] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 in contact with the insulator 280 in the region between the insulators 212 and 283 and having a function of capturing impurities such as hydrogen, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0211] The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is disposed on the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method can be used as the insulator 283. By forming the insulator 283 by a sputtering method, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride formed by a PEALD method or a CVD method may be stacked on silicon nitride formed by a sputtering method.

[0212] [Capacitor element 100] The capacitor 100 includes a conductor 110 that is disposed in an opening formed in the insulators 271, 275, 280, 282, 283, and 285 and that is in contact with the top surface of the conductor 242b, an insulator 130 on the conductor 110 and the insulator 283, and a conductor 120 on the insulator 130. The conductor 120 has a layered structure of a conductor 120a on the insulator 130 and a conductor 120b on the conductor 120a. At least a portion of the conductor 110, the insulator 130, and the conductor 120 is disposed in the opening formed in the insulators 271, 275, 280, 282, 283, and 285.

[0213] The conductor 110 functions as the lower electrode of the capacitor 100, the conductor 120 functions as the upper electrode of the capacitor 100, and the insulator 130 functions as the dielectric of the capacitor 100. The capacitor 100 is configured such that the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 271, 275, 280, 282, 283, and 285, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100. Increasing the capacitance per unit area of ​​the capacitor 100 in this manner can promote miniaturization or high integration of semiconductor devices.

[0214] The shape of the openings formed in the insulators 271, 275, 280, 282, 283, and 285 when viewed from above may be rectangular, polygonal, other than rectangular, polygonal with rounded corners, or circular, including elliptical. Here, it is preferable that the area over which the openings overlap the transistor 200 is large when viewed from above. For example, as shown in FIG. 8A , it is preferable to provide the capacitor 100 so that it fits within the area of ​​the conductor 242b when viewed from above. In this case, the length of the conductor 110 in the channel width direction is smaller than the length of the conductor 242b in the channel width direction. This configuration can reduce the area occupied by a semiconductor device including the capacitor 100 and the transistor 200. However, the configuration is not limited to this, and the length of the conductor 110 in the channel width direction may be larger than the length of the conductor 242b in the channel width direction.

[0215] The conductor 110 is arranged along openings formed in the insulators 271, 275, 280, 282, 283, and 285. Here, it is preferable that the side and bottom surfaces of the openings are joined by curved surfaces. With this configuration, the conductor 110 can be formed into a film with good coverage in the openings.

[0216] Furthermore, it is preferable that the height of a portion of the upper surface of the conductor 110 roughly coincides with the height of the upper surface of the insulator 285. Furthermore, the upper surface of the conductor 242b contacts the lower surface of the conductor 110. The conductor 110 is preferably formed using an ALD method or a CVD method, and any conductor that can be used for the conductor 205 may be used. For example, titanium nitride formed using a thermal ALD method may be used as the conductor 110.

[0217] The insulator 130 is arranged to cover the conductor 110, the insulator 245, and a portion of the insulator 285. Here, the height of the upper surface of the region of the insulator 285 that overlaps with the insulator 130 may be higher than the upper surface of the region that does not overlap with the insulator 130. The insulator 130 is preferably formed by an ALD method, a CVD method, or the like. The insulator 130 is preferably made of a material that can have ferroelectricity.

[0218] Materials that can have ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO x (x is a real number greater than 0), hafnium oxide to which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added, and zirconium oxide to which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added. Furthermore, examples of materials that may have ferroelectricity include PbTiO x Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 130 can have a layered structure made of a plurality of materials selected from the materials listed above. Incidentally, hafnium oxide, zirconium oxide, HfZrO x and materials in which the element J1 is added to hafnium oxide, the crystal structure (characteristics) of which may change not only depending on the film formation conditions but also on various processes, etc., and therefore in this specification and the like, materials that exhibit ferroelectricity are not only called ferroelectrics but also called materials that may have ferroelectricity.

[0219] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can be processed into a thin film of a few nanometers and still retain ferroelectricity. The film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By forming a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a miniaturized transistor 200 to form a semiconductor device. In this specification and the like, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.

[0220] Ferroelectric materials are insulators that exhibit polarization when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses such a material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a ferroelectric random access memory (FeRAM) or a ferroelectric memory. For example, a ferroelectric memory can have a transistor and a ferroelectric capacitor, with one of the source and drain of the transistor electrically connected to one terminal of the ferroelectric capacitor. Therefore, the semiconductor device having the capacitance element 100 and the transistor 200 shown in this embodiment can function as a ferroelectric memory.

[0221] The insulator 130 may have a laminated structure of the above-mentioned material that may have ferroelectricity and a material with high dielectric strength. Materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide or resin with vacancies, etc. By using a laminate of such insulators with high dielectric strength, the dielectric strength may be improved and the leakage current of the capacitor element 100 may be suppressed.

[0222] The conductor 120 is arranged so as to fill the openings formed in the insulators 271, 275, 280, 282, 283, and 285. Here, it is preferable that the conductor 120 has a region that overlaps with the insulator 285 via the insulator 130. With this configuration, the conductor 120 can be insulated from the conductor 110 via the insulator 130. Furthermore, the portion of the conductor 120 above the insulator 283 may be routed and formed into a wiring shape.

[0223] As shown in FIG. 8B, the conductor 120 preferably includes a conductor 120a and a conductor 120b on the conductor 120a. In this case, the conductor 120a may be a thin conductive film with good coverage provided on the insulator 130. The conductor 120b may be disposed so as to fill the opening above the conductor 120a. The conductor 120a is preferably formed by an ALD method, a CVD method, or the like, and may be a conductor that can be used for the conductor 205. For example, titanium nitride formed by an ALD method may be used as the conductor 120a. The conductor 120b is preferably formed by an ALD method, a CVD method, a sputtering method, or the like, and may be a conductor that can be used for the conductor 205. Tungsten formed by a sputtering method may be used as the conductor 120b. However, the conductor 120 is not limited to a two-layer structure and may also be a single-layer structure or a stacked structure of three or more layers.

[0224] A conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 120. The conductor is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0225] Furthermore, it is preferable that insulator 245 be disposed in contact with the side surfaces of openings formed in insulators 271, 275, 280, 282, 283, and 285. Conductor 110 is provided in contact with the inner side surface of insulator 245, insulator 130 is provided in contact with the inner side surface of conductor 110, and conductor 120 is provided in contact with the inner side surface of insulator 130.

[0226] The insulator 245 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 245 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 245 is provided in contact with the insulators 283, 282, 275, and 271, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 or the insulator 285 from mixing into the oxide 230 through the conductor 110. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 245 can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 110.

[0227] When the insulator 245 has a layered structure as shown in FIG. 8B, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen. For example, the first insulator may be made of aluminum oxide deposited by the ALD method, and the second insulator may be made of silicon nitride deposited by the PEALD method. This configuration can suppress oxidation of the conductor 110 and further reduce hydrogen contamination of the conductor 110.

[0228] Although the insulator 245 has a structure in which a first insulator and a second insulator are stacked, the present invention is not limited to this. For example, the insulator 245 may have a single layer or a stacked structure of three or more layers.

[0229] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0230] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0231] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0232] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0233] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0234] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0235] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0236] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0237] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0238] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0239] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0240] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0241] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0242] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0243] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0244] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0245] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 10A. Fig. 10A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0246] As shown in FIG. 10A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0247] The structure within the bold frame in Figure 10A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0248] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 10B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 10B may be simply referred to as the XRD spectrum in this specification. The composition of the CAAC-IGZO film shown in Figure 10B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 10B is 500 nm.

[0249] In Figure 10B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [au]. As shown in Figure 10B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 10B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0250] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 10C. Figure 10C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 10C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0251] As shown in Figure 10C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0252] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 10A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0253] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0254] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0255] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0256] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0257] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0258] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0259] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0260] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0261] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by impurities or defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors enables greater flexibility in the manufacturing process.

[0262] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0263] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0264] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0265] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0266] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0267] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0268] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0269] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0270] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0271] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0272] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0273] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0274] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0275] The channel formation region of the transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0276] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0277] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0278] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0279] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0280] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0281] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0282] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0283] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0284] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0285] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0286] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0287] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0288] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0289] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device illustrated in FIGS. 8A to 8D, which is one embodiment of the present invention, will be described with reference to FIGS. 14A to 25D.

[0290] A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in A of each figure. Note that some elements are omitted from the top view in A of each figure for clarity.

[0291] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0292] There are three types of sputtering methods: RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0293] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD: Metal CVD) and metal-organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.

[0294] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0295] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0296] CVD and ALD differ from sputtering, which deposits particles emitted from a target. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, offers excellent step coverage and thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0297] Furthermore, the CVD method allows for the deposition of a film with any desired composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows for the deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0298] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors or by controlling the number of cycles of each precursor.

[0299] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 14A to 14D). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0300] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, particle generation due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0301] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0302] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 14A to 14D). The insulator 214 is preferably deposited by sputtering. By using the sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0303] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm.2 Over 1.86W / cm 2 The following is true. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and implanted by adjusting the RF power used when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be implanted. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0304] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high ability to capture and fix hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0305] Next, the insulator 216 is deposited on the insulator 214. The insulator 216 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0306] In this embodiment, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0307] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between deposition steps.

[0308] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 214 that functions as an etching stopper film when the insulator 216 is etched to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0309] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0310] After the openings are formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0311] In this embodiment, titanium nitride is deposited as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0312] Next, a conductive film to be the conductor 205b is formed. As the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0313] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 14A to 14D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0314] Next, the insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 15A to 15D). The insulator 222 may contain one or both of aluminum and hafnium oxides. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water can prevent hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0315] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0316] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0317] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0318] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0319] Next, an insulating film 224A is formed on the insulator 222 (see FIGS. 15A to 15D). The insulating film 224A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed as the insulating film 224A by sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0320] Next, oxide films 230A and 230B are sequentially formed on insulating film 224A (see FIGS. 15A to 15D). Preferably, oxide films 230A and 230B are successively formed without being exposed to the atmosphere. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0321] The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230A and the oxide film 230B are preferably formed by an ALD method, since a film of uniform thickness can be formed even in a trench or an opening with a large aspect ratio. The PEALD method is also preferable, since the oxide film 230A and the oxide film 230B can be formed at a lower temperature than in a thermal ALD method. In this embodiment, the oxide film 230A and the oxide film 230B are formed by a sputtering method.

[0322] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0323] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0324] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0325] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1, or an oxide target with an atomic ratio of In:Ga:Zn=1:1:2. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratios.

[0326] It is preferable to form the insulating film 224A, the oxide film 230A, and the oxide film 230B by sputtering without exposing them to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This reduces the amount of hydrogen that gets mixed into the insulating film 224A, the oxide film 230A, and the oxide film 230B between film formation steps.

[0327] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A and the oxide film 230B do not become polycrystallized, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0328] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, it is possible to prevent moisture and other contaminants from being absorbed into the oxide film 230A and the oxide film 230B as much as possible.

[0329] In this embodiment, the heat treatment is performed at 400°C for 1 hour with a nitrogen gas to oxygen gas flow ratio of 4 slm:1 slm. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230A and the oxide film 230B. Reducing the impurities in the film can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230A and the oxide film 230B, reducing the in-plane variation of the crystalline regions in the oxide film 230A and the oxide film 230B. This reduces the in-plane variation of the electrical characteristics of the transistor 200.

[0330] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222. In other words, the hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B decrease.

[0331] In particular, the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide film 230A and the oxide film 230B function as a channel formation region of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide film 230A, and the oxide film 230B in which the hydrogen concentrations are reduced is preferable because it has good reliability.

[0332] Next, a conductive film 242A is formed on the oxide film 230B (see FIGS. 15A to 15D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0333] Next, an insulating film 271A is formed on the conductive film 242A (see FIGS. 15A to 15D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed by sputtering aluminum oxide or silicon nitride.

[0334] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 271A, the film that will become the hard mask may also be formed continuously without exposure to the atmosphere.

[0335] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into island shapes using lithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 16A to 16D). The insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so that at least a portion of each overlaps the conductor 205. This processing can be performed using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. The insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different conditions.

[0336] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. A conductor, semiconductor, or insulator can then be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0337] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B is used as the hard mask.

[0338] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 16B to 16D. As a result, the conductors 242a and 242b shown in FIGS. 8B and 8D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-current of the transistor 200.

[0339] 16B to 16D, the cross sections of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface. For example, the angle between the inclined side surface and the substrate surface (hereinafter, sometimes referred to as the taper angle) is preferably less than 90°. The insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. By tapering the cross sections in this way, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0340] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be configured to be approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors 200.

[0341] Furthermore, by-products generated in the etching process may form layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B. In this case, the layer-like by-products are formed between the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layer-like by-products formed in contact with the upper surface of the insulator 222.

[0342] Next, the insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 17A to 17D). Here, the insulator 275 is preferably in close contact with the top surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 is preferably an insulating film that has the function of suppressing oxygen permeation. For example, the insulator 275 may be formed by depositing an aluminum oxide film by a sputtering method and then depositing a silicon nitride film thereon by a PEALD method. By forming the insulator 275 in such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, may be improved.

[0343] In this way, the oxide 230a, the oxide 230b, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have the function of suppressing oxygen diffusion. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280, etc., into the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B in a later process.

[0344] Next, an insulating film to be the insulator 280 is formed on the insulator 275. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed by sputtering. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed consecutively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0345] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 17A to 17D). Alternatively, a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed on the silicon nitride until it reaches the insulator 280.

[0346] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b are formed (see FIGS. 18A to 18D).

[0347] 18B and 18C, the side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may have a tapered shape. Also, the taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. Furthermore, although not shown in FIGS. 18A to 18C, the upper part of the oxide 230b may be removed when the opening is formed.

[0348] Furthermore, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0349] Here, impurities may adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, etc., or may diffuse into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those originating from components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0350] In particular, impurities such as aluminum or silicon inhibit the formation of a CAAC-OS oxide 230b. Therefore, it is preferable to reduce or eliminate impurity elements such as aluminum or silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms in and around the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0351] Note that the region of the metal oxide where the CAAC-OS transformation is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b be reduced or eliminated.

[0352] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom edge of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom edge of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0353] A cleaning process is performed to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process. Cleaning methods include wet cleaning using a cleaning solution (also known as wet etching), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0354] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0355] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution of ammonia water diluted with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other properties of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0356] For ultrasonic cleaning, it is preferable to use a frequency of 200 kHz or more, and more preferably a frequency of 900 kHz or more, which can reduce damage to the oxide 230b and the like.

[0357] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0358] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0359] A heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a heat treatment in a nitrogen atmosphere may be performed consecutively without exposure to the air.

[0360] Next, the insulating film 252A is formed (see FIGS. 19A to 19D). The insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 252A is preferably formed using an ALD method. As described above, the insulating film 252A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIGS. 19B and 19C, the insulating film 252A needs to be formed with good coverage on the bottom and side surfaces of the opening formed in the insulator 280, etc. In particular, it is preferable that the insulating film 252A be formed with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed with good coverage over the opening.

[0361] When the insulating film 252A is formed by the ALD method, ozone (O), oxygen (O), water (H2O), etc. can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidizing agent, it is possible to reduce hydrogen diffusing into the oxide 230b.

[0362] In this embodiment, the insulating film 252A is formed of aluminum oxide by thermal ALD.

[0363] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere (see FIGS. 19A to 19D). Here, microwave treatment refers to treatment using, for example, a device with a power source that generates high-density plasma using microwaves. In this specification and elsewhere, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0364] In Figures 19B to 19D, dotted lines indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device may be 300 MHz to 300 GHz, preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. High-density plasma can be generated by using high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves to the microwave processing device may be 1000 W to 10,000 W, preferably 2000 W to 5,000 W. The microwave processing device may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side can efficiently guide oxygen ions generated by high-density plasma into the oxide 230b.

[0365] The microwave treatment is preferably carried out under reduced pressure, with the pressure being 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature is 750°C or less, preferably 500°C or less, for example, about 400°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. For example, the heat treatment may be carried out at a temperature of 100°C to 750°C, preferably 300°C to 500°C.

[0366] Furthermore, for example, the microwave treatment may be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) may be greater than 0% and less than or equal to 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) may be greater than 0% and less than or equal to 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) may be greater than 10% and less than or equal to 40%. Even more preferably, the oxygen flow ratio (O2 / (O2+Ar)) may be greater than 10% and less than or equal to 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the region 230bc can be reduced. Furthermore, by preventing excessive oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the regions 230ba and 230bb can be prevented.

[0367] As shown in Figures 19B to 19D, microwave processing is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. In other words, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 9A. The action of plasma, microwaves, etc., can increase the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H→H+V O" reaction occurs, and V contained in region 230bc O Therefore, oxygen vacancies and V in the region 230bc can be reduced. O By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be lowered.

[0368] 9A, conductors 242a and 242b are provided on regions 230ba and 230bb. Here, conductor 242 preferably functions as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when microwave processing is performed in an oxygen-containing atmosphere. Therefore, conductor 242 preferably has the function of blocking electromagnetic waves of 300 MHz or higher and 300 GHz or lower, for example, 2.4 GHz or higher and 2.5 GHz or lower.

[0369] 19B to 19D, the conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions 230ba and 230bb. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0370] Furthermore, insulators 252 having oxygen barrier properties are provided in contact with the side surfaces of conductors 242a and 242b, which makes it possible to prevent oxide films from being formed on the side surfaces of conductors 242a and 242b due to microwave processing.

[0371] In this manner, oxygen vacancies and V OBy removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, maintaining the n-type conductivity. This prevents fluctuations in the electrical characteristics of the transistor 200 and prevents the electrical characteristics of the transistor 200 from varying across the substrate.

[0372] In microwave processing, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interaction between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere may produce an effect equivalent to oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, this thermal energy may be transferred to the hydrogen in the oxide 230b, which may activate and release the hydrogen from the oxide 230b.

[0373] Next, the insulating film 250A is formed (see FIGS. 20A to 20D). Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately after the formation of the insulating film 250A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0374] The insulating film 250A can be formed by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will become the insulator 250 facing the oxide 230b via the thin insulator 252 in a later process, it is preferable that the hydrogen concentration be reduced in this way.

[0375] In this embodiment, the insulating film 250A is formed by depositing silicon oxynitride by the PECVD method.

[0376] Furthermore, when the insulator 250 has a two-layer stacked structure as shown in FIG. 9B , an insulating film that becomes the insulator 250b can be formed after the insulating film 250A is formed. The insulating film that becomes the insulator 250b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that becomes the insulator 250b is preferably formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. The insulating film that becomes the insulator 250b can be formed using the same material as the insulator 222. For example, the insulating film that becomes the insulator 250b can be formed using hafnium oxide by a thermal ALD method.

[0377] Microwave treatment may be performed after the insulating film 250A is formed (see FIGS. 20A to 20D). The microwave treatment may be performed under the same conditions as those performed after the insulating film 252A is formed. Alternatively, the microwave treatment may be performed after the insulating film 250A is formed, without performing the microwave treatment after the insulating film 252A is formed. Alternatively, when an insulating film that will become the insulator 250b is provided as described above, the microwave treatment may be performed after the film is formed. The microwave treatment may be performed under the same conditions as those performed after the insulating film 252A is formed. Alternatively, the microwave treatment may be performed after the insulating film that will become the insulator 250b is formed, without performing the microwave treatment after the insulating film 252A or the insulating film 250A is formed.

[0378] Furthermore, after the formation of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be repeatedly performed multiple times while maintaining a reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0379] Furthermore, by performing microwave processing to modify the film quality of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 252 in a post-process such as film formation of the conductive film that will become the conductor 260, or in a post-treatment such as heat treatment.

[0380] Next, the insulating film 254A is formed (see FIGS. 21A to 21D). The insulating film 254A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 254A is preferably formed by ALD, as with the insulating film 252A. By forming the insulating film by ALD, the insulating film 254A can be formed with a thin film thickness and good coverage. In this embodiment, silicon nitride is formed as the insulating film 254A by PEALD.

[0381] Next, a conductive film that will become the conductor 260a and a conductive film that will become the conductor 260b are formed in this order. The conductive film that will become the conductor 260a and the conductive film that will become the conductor 260b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 260a using the ALD method, and a tungsten film is formed as the conductive film that will become the conductor 260b using the CVD method.

[0382] Next, the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulators 252, 250, 254, and the conductor 260 (the conductors 260a and 260b) (see FIGS. 22A to 22D). As a result, the insulator 252 is disposed so as to cover the opening that reaches the oxide 230b. The conductor 260 is disposed so as to fill the opening via the insulators 252 and 250.

[0383] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0384] Next, the insulator 282 is formed over the insulator 252, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 22A to 22D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentration in the insulator 282 can be reduced.

[0385] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 282. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0386] Alternatively, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0387] Next, an etching mask is formed on the insulator 282 by lithography, and a part of the insulator 282, a part of the insulator 280, a part of the insulator 275, a part of the insulator 222, and a part of the insulator 216 are processed until the top surface of the insulator 214 is exposed (see FIGS. 23A to 23D). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0388] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 600°C or lower. The heat treatment temperature is preferably lower than the heat treatment temperature performed after the formation of the oxide film 230B. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, some of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250, etc.

[0389] Furthermore, by performing this heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by processing the insulators 282, 280, 275, 222, and 216. The hydrogen bonded to the oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

[0390] Furthermore, in the region of the oxide 230 overlapping with the conductor 260, an insulator 252 is provided in contact with the top surface and side surface of the oxide 230. The insulator 252 has a barrier property against oxygen, and can reduce the diffusion of an excessive amount of oxygen into the oxide 230. This allows oxygen to be supplied to the region 230bc and its vicinity without excessive oxygen being supplied. This prevents the side surface of the conductor 242 from being oxidized by excess oxygen, and reduces oxygen vacancies and V formed in the region 230bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0391] On the other hand, when the transistors 200 are highly integrated, the volume of the insulator 280 for each transistor 200 may become excessively small. In this case, the amount of oxygen diffusing into the oxide 230 during the heat treatment is significantly reduced. If the oxide 230 is heated while being in contact with an oxide insulator (such as the insulator 250) that does not contain sufficient oxygen, oxygen constituting the oxide 230 may be released. However, in the transistor 200 described in this embodiment, the insulator 252 is provided in contact with the top and side surfaces of the oxide 230 in a region of the oxide 230 that overlaps with the conductor 260. The insulator 252 has a barrier property against oxygen, and therefore can reduce release of oxygen from the oxide 230 during the heat treatment. This reduces oxygen vacancies and V formed in the region 230bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0392] As described above, in the semiconductor device according to this embodiment, a transistor having good electrical characteristics and good reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. Therefore, a semiconductor device in which variations in the electrical characteristics of the transistor 200 within the substrate surface are suppressed can be provided.

[0393] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 24A to 24D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas. The insulator 283 may also have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and another silicon nitride film may be formed on the silicon nitride by an ALD method. The insulator 283 and the insulator 214, which have high barrier properties, surround the transistor 200, thereby preventing moisture and hydrogen from entering from the outside.

[0394] Next, the insulator 274 is formed over the insulator 283. The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 274 by a CVD method.

[0395] Next, the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby planarizing the upper surface of the insulator 274 (see FIGS. 24A to 24D). The CMP process may remove a portion of the upper surface of the insulator 283.

[0396] Next, the insulator 285 is formed on the insulator 274 and the insulator 283 (see Figures 25A to 25D). The insulator 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 285 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0397] In this embodiment, a silicon oxide film is formed as the insulator 285 by a sputtering method.

[0398] Next, an opening 290 is formed in the insulators 271b, 275, 280, 282, 283, and 285, reaching the conductor 242b (see FIGS. 25A to 25D). The opening 290 may be formed using lithography. Because the opening 290 has a large aspect ratio, anisotropic etching, such as dry etching, is preferable. For example, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, or SiCl4 gas may be used alone or in combination of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, or hydrogen gas may be added to the above gases as appropriate. These etching gases can be switched appropriately depending on the object to be etched (insulator 271b, insulator 275, insulator 280, insulator 282, insulator 283, and insulator 285).

[0399] 25A, the shape of opening 290 is circular when viewed from above, but is not limited to this. For example, opening 290 may have a substantially circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above.

[0400] Here, it is preferable that the side and bottom surfaces of the opening 290 are joined by curved surfaces. With this configuration, the conductor 110 can be formed in the opening 290 with good coverage.

[0401] Next, an insulating film that will become the insulator 245 is formed. At this time, the insulating film is formed so as to be in contact with at least the side surface of the opening 290. For example, the insulating film may be formed along the side surface and bottom surface of the opening 290. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 245, it is preferable to use an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen, or oxygen. For example, it is preferable to form a film of aluminum oxide using the ALD method, and then form a film of silicon nitride thereon using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0402] Next, the insulating film is anisotropically etched to form an insulator 245 in contact with the side surface of the opening 290 (see FIGS. 25A to 25D). At this stage, at least a portion of the insulating film is removed, exposing at least a portion of the upper surface of the conductor 242b. At this time, as shown in FIG. 25B, a portion of the upper surface of the conductor 242b may be removed. The anisotropic etching may be performed, for example, by dry etching. By configuring the side wall of the opening 290 in this manner, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 110 to be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductor 110.

[0403] Next, a conductive film 110A is formed to cover the insulator 285 and the opening 290 (see FIGS. 26A to 26D). At this time, the conductive film 110A is preferably formed in contact with the side and bottom surfaces of the opening 290, which have a large aspect ratio. For this reason, the conductive film 110A is preferably formed using a film formation method with good coverage, such as the ALD method or the CVD method. For example, a titanium nitride film may be formed using the ALD method.

[0404] Next, a filler 135 is formed on the conductive film 110A (see FIGS. 26A to 26D). The filler 135 only needs to be able to fill the opening 290 to the extent that the CMP process performed in the subsequent step can be performed. Therefore, a cavity or the like may be formed in the opening 290. The filler 135 may be made of an insulator or a conductor. For example, the filler 135 may be made of silicon oxide by APCVD.

[0405] Next, a CMP process is performed to remove the layers above the insulator 285, thereby forming the conductor 110 (see FIGS. 27A to 27D). Here, it is preferable that the insulator 285 functions as a stopper for the CMP process of the conductive film 110A. Note that the CMP process may remove a part of the insulator 285.

[0406] Next, an etching process is performed to remove the filler 135 inside the opening 290 (see FIGS. 28A to 28D). Either wet etching or dry etching may be used for the etching process, but wet etching may be used more easily to remove the filler 135 inside the opening 290. When wet etching is used, a hydrofluoric acid-based solution or the like may be used as an etchant.

[0407] Next, an insulating film 130A is formed on the conductor 110 and the insulator 285 (see FIGS. 29A to 29D). The insulating film 130A is preferably formed in contact with the conductor 110 provided inside the opening 290 with a large aspect ratio. For this reason, the insulating film 130A is preferably formed using a film formation method with good coverage, such as the ALD method or the CVD method. The insulating film 130A is preferably made of a material that can have the above-mentioned ferroelectric properties. For example, HfZrO x (x is a real number greater than 0) can be deposited.

[0408] Furthermore, by forming the insulating film 130A using a film formation method such as ALD and covering the conductor 110 with good coverage, it is possible to prevent the upper electrode and the lower electrode of the capacitor element 100 from short-circuiting.

[0409] Next, the conductive film 120A is formed on the insulating film 130A (see FIGS. 29A to 29D). Preferably, at least the conductive film 120A is formed in contact with the insulating film 130A provided inside the opening 290 with a large aspect ratio. For this reason, the conductive film 120A is preferably formed using a film formation method with good embedding properties, such as the ALD method or the CVD method; for example, a titanium nitride film may be formed using the thermal ALD method.

[0410] Here, the conductive film 120A is preferably formed by a method in which the substrate is heated, such as thermal ALD. For example, the substrate temperature may be set to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher. Alternatively, the substrate temperature may be set to 500°C or lower, preferably 450°C or lower. For example, the substrate temperature may be set to about 400°C.

[0411] By forming the conductive film 120A within the above temperature range, the ferroelectricity of the insulator 130 can be enhanced without performing a high-temperature bake treatment after forming the capacitor element 100. This makes it possible to easily fabricate a ferroelectric capacitor and improve the productivity of semiconductor devices.

[0412] Next, a conductive film 120B is formed on the conductive film 120A (see FIGS. 29A to 29D). The conductive film 120B is preferably formed so as to fill the opening 290. For this reason, the conductive film 120B is preferably formed using a film formation method with good filling properties, such as an ALD method or a CVD method, and for example, tungsten may be formed using a metal CVD method.

[0413] By forming the conductive film 120A and the conductive film 120B in this manner, the upper electrode of the capacitor 100 can be provided with good embedding properties in the opening 290, and therefore the capacitance of the capacitor 100 can be increased.

[0414] Next, the conductive film 120A, the conductive film 120B, and the insulating film 130A are processed by lithography to form the conductor 120a, the conductor 120b, and the insulator 130 (see FIGS. 8A to 8D). Note that the insulating film 130A may be left as the insulating film 130A without being processed into the insulator 130. Alternatively, the conductor 120 may be formed so that the portion above the insulator 285 functions as a wiring, or a conductor that functions as a wiring may be formed in a layer above the conductor 120. Furthermore, the above-described lithography may cause the height of the top surface of the region of the insulator 285 that overlaps with the insulator 130 to be higher than the top surface of the region that does not overlap with the insulator 130.

[0415] Through the above steps, a semiconductor device including the transistor 200 and the capacitor 100 shown in FIGS. 8A to 8D can be manufactured.

[0416] As shown in FIGS. 14A to 25D, the transistor 200 and the capacitor 100 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0417] As described above, by thoroughly removing impurities, here at least one of hydrogen, hydrocarbon, and carbon, from the film of the insulator 130, a film having high-purity intrinsic ferroelectricity, here a high-purity intrinsic capacitor element, can be formed. The capacitor element having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor have very high compatibility in their manufacturing processes. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0418] <Microwave processing equipment> A microwave processing apparatus that can be used in the method for manufacturing the semiconductor device will be described below.

[0419] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0420] 30 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, chambers 2706a, 2706b, 2706c, and 2706d.

[0421] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c and 2706d.

[0422] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0423] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3 x 10 -5Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0424] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0425] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0426] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gases entering from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. In order to keep the leak rate below the above-mentioned values, measures must be taken to prevent both external and internal leaks.

[0427] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0428] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit little impurity-containing gases, are used as components constituting the manufacturing apparatus 2700. Furthermore, the aforementioned metals that emit little impurity-containing gases may be coated on alloys containing iron, chromium, nickel, and the like. Alloys containing iron, chromium, nickel, and the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gases.

[0429] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0430] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide or the like to suppress gas emissions.

[0431] The adsorbed matter present in the transfer chamber 2704 and each chamber is adsorbed to the inner walls and other surfaces, and therefore does not affect the pressure in the transfer chamber 2704 or each chamber. However, it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at temperatures between 100°C and 450°C. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by evacuation alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. It is preferable to use a noble gas as the inert gas.

[0432] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbed substances from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be adjusted to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0433] Next, chamber 2706b and chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0434] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave processing on an object to be processed. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0435] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also provided outside chamber 2706b and chamber 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0436] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is delivered to chambers 2706b and 2706c via a gas pipe 2806 that passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 evacuates gases and other gases from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0437] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0438] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because it allows water to be efficiently pumped out.

[0439] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0440] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0441] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0442] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0443] At this time, the ions and radicals generated by the high-density plasma 2810 can modify the film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used as the high-frequency power supply 2816. By applying a bias to the substrate side, ions in the high-density plasma 2810 can be efficiently delivered to the depths of openings in the film or the like on the substrate 2811.

[0444] For example, oxygen radical treatment using high density plasma 2810 can be performed in chamber 2706b or chamber 2706c by introducing oxygen from gas supply source 2801.

[0445] Next, chamber 2706a and chamber 2706d will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0446] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. Chamber 2706a and chamber 2706d differ only in the type of electromagnetic waves. Since the other configurations are largely common, they will be described together below.

[0447] Chamber 2706a and chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Also, outside chamber 2706a and chamber 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0448] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has a function of heating the substrate 2824.

[0449] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0450] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0451] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0452] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0453] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0454] The microwave processing apparatus that can be used in this embodiment is not limited to the above. A microwave processing apparatus 2900 shown in Fig. 33 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also has a substrate holder 2902 that holds multiple substrates 2811 (2811_1 to 2811_n, n is an integer of 2 or more) inside the quartz tube 2901. The microwave processing apparatus 2900 may also have a heating means 2903 outside the quartz tube 2901.

[0455] Microwaves generated by a high-frequency generator 2803 are irradiated onto a substrate placed in a quartz tube 2901 via a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818, allowing adjustment of the pressure inside the quartz tube 2901. A gas supply source 2801 is connected to a gas pipe 2806 via a valve 2802, allowing a desired gas to be introduced into the quartz tube 2901. A heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Alternatively, the microwave treatment can be performed after the substrate 2811 is heated. Alternatively, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0456] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because multiple processing substrates can be uniformly processed during microwave processing or heat treatment, reducing variations between processing substrates. For example, placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because it prevents the processing substrate from being directly exposed to microwaves.

[0457] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0458] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 11A to 13B. FIG.

[0459] Each figure A shows a top view of the semiconductor device. Each figure B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in each figure A. In the top view of each figure A, some elements are omitted for clarity.

[0460] In the semiconductor device shown in each of Figures A and B, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can also be used as the constituent materials of the semiconductor device.

[0461] <Semiconductor Device Modification 1> 11A and 11B is a modified example of the semiconductor device shown in Figures 8A to 8D. The semiconductor device shown in Figures 11A and 11B differs from the semiconductor device shown in Figures 8A to 8D in that a conductor 240 and a conductor 246 are provided. Here, the conductor 240 functions as a plug electrically connected to one of the source and drain of the transistor 200, and the conductor 246 functions as a wiring connected to the plug.

[0462] Conductor 240 is provided so as to fill the openings formed in insulators 271, 275, 280, 282, 283, and 285. The lower surface of conductor 240 contacts the upper surface of conductor 242a. Conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Conductor 240 may also have a layered structure including a thin first conductor provided along the side and bottom surfaces of the opening and a second conductor on the first conductor.

[0463] When the conductor 240 has a layered structure, the first conductor disposed near the insulator 285 and the insulator 280 is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240. The second conductor may be made of the above-mentioned conductive material mainly composed of tungsten, copper, or aluminum.

[0464] 11B shows a configuration in which the first conductor and the second conductor are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers.

[0465] The conductor 246 may be disposed in contact with the upper surface of the conductor 240. The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 246 may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. As shown in FIG. 11B, the upper surface of the region of the insulator 285 that overlaps with the conductor 246 may be higher than the upper surface of the region that does not overlap with the conductor 246. The conductor 246 may be formed so as to be embedded in an opening provided in the insulator.

[0466] It is also preferable that an insulator 241 functioning as a barrier insulating film be provided between the conductor 240 and the insulator 280. It is preferable that the insulator 245 be arranged in contact with the side surfaces of the openings formed in the insulators 271, 275, 280, 282, 283, and 285. It is preferable that the insulator 241 have a structure similar to that of the insulator 245 described above.

[0467] In this modification, an insulator 286 is provided to cover the conductor 246 and the insulator 285. The insulator 286 may be formed using the insulating material that can be used for the insulator 285.

[0468] In this modified example, the capacitance element 100 is formed after the conductor 240 and the conductor 246 are formed. Therefore, unlike the semiconductor device shown in FIGS. 8A to 8D, part of the lower surface of the insulator 130 and part of the side surface of the insulator 245 contact the insulator 286. In other words, the opening into which the capacitance element 100 is embedded is deeper in accordance with the thickness of the insulator 286. This allows the capacitance of the capacitance element 100 to be increased without increasing the area occupied by the semiconductor device.

[0469] <Modification 2 of Semiconductor Device> 12A and 12B is a modified example of the semiconductor device shown in FIGS. 8A to 8D. Similar to the semiconductor device shown in FIGS. 13A and 13B, the semiconductor device shown in FIGS. 12A and 12B has an insulator 241a, a conductor 240a, and a conductor 246a on a conductor 242a. Furthermore, an insulator 241b, a conductor 240b, and a conductor 246b are provided on a conductor 120. Here, the conductor 240b functions as a plug electrically connected to one of the terminals of the capacitor 100, and the conductor 246b functions as a wiring connected to the plug.

[0470] The insulators 241a and 241b can be made of the same conductive material as the above-described insulator 241. The conductors 240a and 240b can be made of the same conductive material as the above-described conductor 240. The conductors 246a and 246b can be made of the same conductive material as the above-described conductor 246.

[0471] 12A and 12B differs from the semiconductor device shown in Figures 13A and 13B in that the conductors 240a and 240b are formed after the formation of the capacitive element 100. Therefore, the lower surfaces of the conductors 246a and 246b contact the upper surface of the insulator 285 formed to cover the conductor 120.

[0472] Note that the semiconductor device shown in Figures 12A and 12B differs from the semiconductor device shown in Figures 8A to 8D in that no interlayer insulating film is provided between the insulator 283 and the insulator 130, and the lower surface of the insulator 130 is in contact with the upper surface of the insulator 283.

[0473] <Semiconductor Device Modification 3> The semiconductor device shown in FIGS. 13A and 13B is a modification of the semiconductor device shown in FIGS. 12A and 12B. The semiconductor device shown in FIGS. 13A and 13B differs from the semiconductor device shown in FIGS. 12A and 12B in that the insulator 283 is in contact with a portion of the top surface of the insulator 212. Therefore, the transistor 200 is disposed within a region sealed by the insulator 283 and the insulator 212. This configuration can prevent hydrogen contained outside the sealed region from entering the sealed region. Although the transistor 200 shown in FIGS. 13A and 13B has a configuration in which the insulators 212 and 283 are provided as single layers, the present invention is not limited thereto. For example, the insulators 212 and 283 may each have a stacked structure of two or more layers.

[0474] <Application examples of semiconductor devices> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

[0475] FIG. 34A shows a top view of semiconductor device 500. The x-axis in FIG. 34A is parallel to the channel length direction of transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 34B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 34A, and is also a cross-sectional view of transistor 200 in the channel length direction. FIG. 34C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in FIG. 34A, and is also a cross-sectional view of opening region 400 and its vicinity. Note that some elements have been omitted from the top view in FIG. 34A for clarity.

[0476] 34A to 34C, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0477] 34A to 34C is a modified example of the semiconductor device shown in FIGS. 8A to 8D. The semiconductor device 500 shown in FIGS. 34A to 34C differs from the semiconductor device shown in FIGS. 8A to 8D in that an opening region 400 is formed in the insulator 282 and the insulator 280. The semiconductor device 500 also differs from the semiconductor device shown in FIGS. 8A to 8D in that a sealing portion 265 is formed to surround the plurality of transistors 200 and the capacitor 100.

[0478] The semiconductor device 500 has a plurality of transistors 200, a plurality of capacitors 100, and a plurality of opening regions 400 arranged in a matrix. Furthermore, a plurality of conductors 260 functioning as gate electrodes of the transistors 200 are provided extending in the y-axis direction. The opening regions 400 are formed in regions that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of capacitors 100, the plurality of conductors 260, and the plurality of opening regions 400. The number, arrangement, and size of the transistors 200, the capacitors 100, the conductors 260, and the opening regions 400 are not limited to the structure shown in FIG. 34 , and may be appropriately set according to the design of the semiconductor device 500.

[0479] As shown in FIGS. 34B and 34C , the sealing portion 265 is provided to surround the multiple transistors 200, the insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is provided to cover the insulators 216, 222, 275, 280, and 282. In the sealing portion 265, the insulator 283 is in contact with the upper surface of the insulator 214. In the sealing portion 265, the insulator 274 is provided between the insulators 283 and 285. The upper surface of the insulator 274 is approximately flush with the uppermost surface of the insulator 283. The insulator 274 may be made of the same material as the insulator 280.

[0480] With this structure, the multiple transistors 200 can be enclosed by the insulators 283, 214, and 212. Here, it is preferable that one or more of the insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from mixing into the region of the sealing portion 265.

[0481] 34C , insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove in opening region 400, overlapping the opening of insulator 282. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 275, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0482] 34C , insulator 283 contacts the side surface of insulator 282, the side surface of insulator 280, and the top surface of insulator 280 inside opening region 400. In addition, a portion of insulator 274 may be formed in opening region 400 so as to fill a recess formed in insulator 283. In this case, the height of the top surface of insulator 274 formed in opening region 400 may roughly match the height of the top surface of insulator 283.

[0483] By performing heat treatment with the opening region 400 formed and the insulator 280 exposed through the opening of the insulator 282, oxygen can be supplied to the oxide 230 while some of the oxygen contained in the insulator 280 diffuses outward from the opening region 400. This allows sufficient oxygen to be supplied from the insulator 280, which contains oxygen released by heating, to a region in the oxide semiconductor that functions as a channel formation region and its vicinity, while preventing excessive oxygen from being supplied.

[0484] At this time, the hydrogen contained in the insulator 280 can be bonded with oxygen and released to the outside through the opening region 400. The hydrogen bonded with oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from mixing into the oxide 230.

[0485] 34A, the shape of the opening region 400 in a top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400 in a top view may be rectangular, elliptical, circular, diamond-shaped, or a combination of these. The area and spacing of the opening regions 400 can be appropriately set in accordance with the design of the semiconductor device including the transistors 200. For example, in a region where the density of the transistors 200 is low, the area of ​​the opening regions 400 can be increased or the spacing between the opening regions 400 can be narrowed. For example, in a region where the density of the transistors 200 is high, the area of ​​the opening regions 400 can be narrowed or the spacing between the opening regions 400 can be widened.

[0486] According to one embodiment of the present invention, a novel transistor can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. According to one embodiment of the present invention, a semiconductor device with favorable frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0487] According to one embodiment of the present invention, a capacitor including a material that can have ferroelectricity can be provided. According to one embodiment of the present invention, the capacitor can be provided with high productivity. According to one embodiment of the present invention, a semiconductor device including the capacitor and a transistor can be provided. According to one embodiment of the present invention, the semiconductor device can be miniaturized or highly integrated.

[0488] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0489] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0490] [Storage device configuration example] 35 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200. The capacitor 100 described in the above embodiment can be used as the capacitor 100. Note that FIG. 35 illustrates an example in which the capacitor 100 and the transistor 200 illustrated in FIG. 11 are used; however, the present invention is not limited thereto, and the capacitor 100 and the transistor 200 can be selected as appropriate.

[0491] The capacitor 100 is made of a material that can have ferroelectricity, which means that polarization occurs inside the capacitor when an external electric field is applied, and the polarization remains even when the electric field is removed to zero. This allows the capacitor 100 to be used to form a nonvolatile memory element. In other words, a one-transistor-one-capacitor type ferroelectric memory can be formed by using a capacitor that functions as a ferroelectric capacitor and a transistor 200.

[0492] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a characteristic of being able to withstand high voltage. Therefore, by using an oxide semiconductor for the transistor 200, a high voltage can be applied to the transistor 200 even when the transistor 200 is miniaturized. Miniaturization of the transistor 200 can reduce the area occupied by a semiconductor device.

[0493] 35, a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, a wiring 1005 is electrically connected to one of the electrodes of the capacitor 100, a wiring 1006 is electrically connected to the second gate of the transistor 200, and a wiring 1007 is electrically connected to the gate of the transistor 300.

[0494] Moreover, the memory device shown in FIG. 35 can be arranged in a matrix to form a memory cell array.

[0495] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0496] Here, in the transistor 300 shown in FIG. 35, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0497] Note that the transistor 300 illustrated in FIG. 35 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0498] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0499] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0500] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0501] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 35, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0502] Similarly, a conductor 218, a conductor constituting the transistor 200 (the conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300.

[0503] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0504] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0505] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0506] Moreover, over the transistor 200, the conductor 112 is provided over the insulator 285 and the conductor 240. Note that the conductor 112 functions as a plug or wiring electrically connected to the transistor 200 or the transistor 300. An insulator 286 is provided to cover the insulator 285 and the conductor 112. An insulator 150 is provided to cover the insulator 286 and the capacitor 100.

[0507] Alternatively, a barrier insulating film against hydrogen may be provided to cover the insulator 285 and the conductor 112. As shown in FIG. 35 , it is preferable to provide, as a barrier insulating film against hydrogen, an insulator 152a that covers the insulator 285 and the conductor 112 and an insulator 152b on the insulator 152a. The insulator 152a and the insulator 152b may be a barrier insulating film that can be used for the above-described insulator 283, etc. By providing such insulator 152a and insulator 152b, it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 286, etc., into the transistor 200 via the conductor 112 and the conductor 240.

[0508] The insulator 152a may be formed by a sputtering method. For example, the insulator 152a may be formed using silicon nitride by a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulator 152a can be reduced. In this manner, the hydrogen concentration in the insulator 152a in contact with the conductor 112 and the insulator 285 is reduced, which can prevent hydrogen from diffusing from the insulator 152a to the conductor 112 and the insulator 285.

[0509] The insulator 152b is preferably formed by an ALD method, particularly a PEALD method. For example, silicon nitride formed by a PEALD method can be used as the insulator 152b. This allows the insulator 152b to be formed with good coverage. Therefore, even if pinholes or discontinuities are formed in the insulator 152a due to unevenness of the base, the insulator 152b can cover them, thereby reducing the diffusion of hydrogen into the conductor 112 and the insulator 285.

[0510] However, the method for forming the insulators 152a and 152b is not limited to sputtering and ALD, and CVD, MBE, PLD, etc. may also be used as appropriate. In addition, although the two-layer structure of the insulators 152a and 152b is shown above, the present invention is not limited to this, and a single-layer structure or a stacked structure of three or more layers may also be used.

[0511] Similarly to the insulators 152a and 152b, the insulators 283 and 212 may also be barrier insulating films with a stacked structure.

[0512] Similarly, a barrier insulating film against hydrogen may be provided to cover the insulator 286 and the capacitor 100. As shown in FIG. 35, it is preferable to provide an insulator 154a covering the insulator 286 and the capacitor 100 and an insulator 154b on the insulator 154a as the barrier insulating film against hydrogen. The insulator 154a can be a barrier insulating film similar to the insulator 152a, and the insulator 154b can be a barrier insulating film similar to the insulator 152b. Providing such insulators 154a and 154b can reduce the diffusion of impurities such as hydrogen contained in the insulator 150 or the like to the transistor 200 via the capacitor 100.

[0513] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0514] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0515] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0516] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0517] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0518] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0519] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metals, alloys, metal nitrides, or metal oxides, each of which is a metal material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, low-resistance conductive materials such as aluminum and copper are preferably used. Using a low-resistance conductive material can reduce wiring resistance. Furthermore, as described in the above embodiment, the ferroelectricity of the insulator 130 in the capacitor 100 can be enhanced without high-temperature baking after formation by depositing the conductor 120a using a method involving substrate heating, such as thermal ALD. Therefore, a semiconductor device can be manufactured without high-temperature baking, and a low-resistance conductive material, such as copper, which has a low melting point, can be used.

[0520] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0521] 35, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0522] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0523] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high blocking property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0524] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 285, and 150 into the insulator 280.

[0525] Here, the conductor 240 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214 and 212. As described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 212, 214, 282, and 283 via the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside. Note that in Figure 35, one transistor 200 is shown in the area sealed with insulator 212 and insulator 283, etc., but this is not limited to this, and multiple transistors 200 can be provided in the sealed area.

[0526] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0527] 35, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 so that the area where the insulator 283 and the insulator 214 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 222, and 216 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0528] That is, insulator 214 and insulator 283 come into contact with each other through openings provided in insulators 282 , 280 , 275 , 222 , and 216 .

[0529] Furthermore, for example, openings may be provided in the insulators 282, 280, 275, 222, 216, and 214. With this configuration, the insulators 212 and 283 are in contact with each other through the openings provided in the insulators 282, 280, 275, 222, 216, and 214. In this case, the insulators 212 and 283 may be formed using the same material and the same method. Providing the insulators 212 and 283 using the same material and the same method can improve adhesion. For example, it is preferable to use silicon nitride.

[0530] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0531] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0532] <Modification 1 of storage device> 35, the capacitor 100 is formed to be embedded in the insulator 285 and the insulator 280, but the present invention is not limited to this. As shown in FIG. 36, a planar capacitor 100 may be provided on the insulator 285.

[0533] The capacitor 100 includes a conductor 110, an insulator 130 covering the conductor 110, and a conductor 120 (conductors 120a and 120b) covering the insulator 130. Preferably, the insulator 130 covers the top and side surfaces of the conductor 110 and separates the conductor 110 from the conductor 120. For details of the conductor 110, the insulator 130, and the conductor 120, refer to the description of [Configuration Example of a Memory Device] and the previous embodiments.

[0534] The conductor 110 is formed in the same layer as the conductor 112 and is in contact with the top surface of the conductor 240. The conductor 110 is electrically connected to one of the source and drain of the transistor 200 via the conductor 240.

[0535] Furthermore, an insulator 155 is preferably provided to cover the conductor 120, the insulator 130, and the conductor 112. The insulator 155 is preferably an insulator having the function of capturing and fixing hydrogen, which can be used for the insulator 214 or the insulator 282, etc. For example, aluminum oxide is preferably used. By providing such an insulator 155 to cover the capacitor 100, hydrogen contained in the insulator 130 of the capacitor 100 can be captured and fixed, thereby reducing the hydrogen concentration in the insulator 130. This can improve the ferroelectricity of the insulator 130. Furthermore, leakage current between the conductor 110 and the conductor 120 can be reduced. Note that this is not a limitation, and a configuration without providing the insulator 155 is also possible.

[0536] 35 , it is preferable to provide insulators 152a and 152b, which function as barrier insulating films against hydrogen, over the conductor 112 and the conductor 120. The insulators 152a and 152b are provided over the insulator 155. Providing such insulators 152a and 152b can reduce the diffusion of impurities such as hydrogen contained in the insulator 286 over the insulator 152b to the transistor 200 through the capacitor 100, the conductor 112, and the conductor 240.

[0537] 36, it is preferable to provide an insulator 287 that functions as a barrier insulating film against hydrogen on the insulator 285. The conductor 112, the conductor 110, and the insulator 155 are provided on and in contact with the insulator 287. Here, the insulator 287 can be a barrier insulating film similar to that of the insulator 283.

[0538] With this configuration, the insulator 155 and the insulator 287 are in contact with each other in a region that does not overlap with the capacitor 100. That is, the capacitor 100 is sealed by the insulator 155, the insulators 152a and 152b, and the insulator 287. If the insulator 155 is not used, the insulator 287 and the insulator 152a are in contact with each other in a region that does not overlap with the capacitor 100, and the capacitor 100 is sealed by the insulators 152a and 152b and the insulator 287. This suppresses diffusion of hydrogen from the outside of the insulators 152b and 287 to the capacitor 100, thereby reducing the hydrogen concentration in the capacitor 100. This improves the ferroelectricity of the insulator 130.

[0539] 36, the transistor 200 is also sealed with the insulators 283, 214, and 212, which function as barrier insulating films against hydrogen. This can suppress diffusion of hydrogen from outside the insulators 283 and 212 to the transistor 200, thereby reducing the hydrogen concentration in the oxide semiconductor film of the transistor 200. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0540] <Modification 2 of Storage Device> 36, the transistor 200 and the capacitor 100 are individually sealed by a barrier insulating film against hydrogen, but the present invention is not limited to this. As shown in FIG. 37, the transistor 200 and the capacitor 100 may be collectively sealed by a barrier insulating film against hydrogen (insulator 212, insulator 152a, and insulator 152b).

[0541] 37, openings reaching insulator 212 are formed in insulators 214, 216, 222, 275, 280, 282, 283, 285, and 155. Insulators 152a and 152b on insulator 155 are formed along the side and bottom surfaces of the openings. Insulator 152a contacts the top surface of insulator 212 at the bottom surface of the opening.

[0542] With this structure, the transistor 200 and the capacitor 100 can be collectively sealed with the insulator 212, the insulator 152a, and the insulator 152b. This can suppress diffusion of hydrogen from the outside of the insulator 212 and the insulator 152b to the capacitor 100 and the transistor 200, thereby reducing the hydrogen concentrations in the insulator 130 of the capacitor 100 and the oxide semiconductor film of the transistor 200. This can increase the ferroelectricity of the insulator 130, and improve the electrical characteristics and reliability of the transistor 200.

[0543] <Storage Device Variation 3> 37, the capacitor 100 is provided over the transistor 200, but the present invention is not limited to this. As shown in FIG. 38, the capacitor 100 may be provided in the same layer as the transistor 200.

[0544] As shown in FIG. 38, the conductor 110 functioning as the lower electrode of the capacitor 100 is preferably formed of a conductor in the same layer as the conductor functioning as the back gate of the transistor 200. An insulator 130 is disposed on the conductor 110, and the conductor 120 (conductor 120a and conductor 120b) is disposed on the insulator 130. Here, the insulator 130 preferably covers the upper surface of the conductor 110 and separates the conductor 110 from the conductor 120. Note that the insulator 130 and the conductor 120 may have a configuration similar to that shown in FIG. 36 and the like, and for details, the descriptions in [Configuration Example of Memory Device] and the previous embodiments can be referred to. An insulator 222 is disposed to cover the insulator 130 and the conductor 120.

[0545] A conductor 240 is provided in contact with the top surface of the conductor 120b, and a conductor 112 is provided in contact with the top surface of the conductor 240. The conductor 112 is in contact with the conductor 240 which is electrically connected to one of the source and drain of the transistor 200. That is, the conductor 120 which functions as the upper electrode of the capacitor 100 shown in FIG. 38 is electrically connected to one of the source and drain of the transistor 200. The conductor 110 which functions as the lower electrode of the capacitor 100 is electrically connected to the wiring 1005.

[0546] 37 , the transistor 200 and the capacitor 100 can be collectively sealed with the insulator 212, the insulator 152a, and the insulator 152b. This can suppress diffusion of hydrogen from the outside of the insulator 212 and the insulator 152b to the capacitor 100 and the transistor 200, thereby reducing the hydrogen concentrations in the insulator 130 of the capacitor 100 and the oxide semiconductor film of the transistor 200. This can increase the ferroelectricity of the insulator 130, and improve the electrical characteristics and reliability of the transistor 200.

[0547] <Modification 4 of the storage device> 36 and the like has a configuration in ...

Claims

1. forming a first conductive film; A HfZrO film is formed on the first conductive film by ALD or CVD. ｘ (x is a real number greater than 0), The HfZrO ｘ a second conductive film is formed over a film containing The second conductive film is formed by an ALD method or a CVD method at a substrate temperature of 300° C. or more and 500° C. or less. A method for manufacturing a capacitor element.

2. In claim 1, the first conductive film is formed in contact with the side and bottom surfaces of the opening formed in the insulating film; A method for manufacturing a capacitor element.

3. In claim 1, The HfZrO ｘ The film containing HfCl as a precursor ４ or ZrCl ４ formed using an ALD method using at least one of A method for manufacturing a capacitor element.

4. In claim 1, the second conductive film is titanium nitride; A method for manufacturing a capacitor element.

5. In claims 1 to 4, The HfZrO ｘ and the second conductive film are processed by a lithography method. A method for manufacturing a capacitor element.

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