Gate driving circuit and touch sensing display device

Abstract

To reduce Q node holding stress in time division driving of a display period and a touch period.SOLUTION: Odd stages include odd main stages that drive odd gate lines connected to odd subpixels during a display period and odd reset dummy stages that are not connected to gate lines, even stages include even main stages that drive even gate lines connected to even subpixels during a display period and at least one even reset dummy stage that is not connected to the gate lines, the odd reset dummy stage resets a Q node of the odd main stage during the corresponding display period, the even reset dummy stage resets a Q node of the even main stage during the corresponding display period, the odd and even reset dummy stages are reset in synchronization with start timing of the corresponding touch period, and all of Q nodes of the odd and even main stages maintain a reset level during the touch period.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a gate driving circuit and a touch-sensing display device. [Background technology]

[0002] A touch-sensing display device can recognize a user's touch input to a display panel and therefore perform various application functions.

[0003] The touch-sensing display device divides time into a display period for display driving and a touch period for touch-sensing driving, and alternately performs display driving and touch-sensing driving.

[0004] In this case, the touch period is located between adjacent display periods. The gate drive circuit outputs scan signals only during the display period and stops outputting scan signals during the touch period. As a result, some stages of the gate drive circuit are subjected to a relatively large amount of Q node retention stress during the touch period. In these stages, if the Q node is not discharged during the touch period and remains charged for a long time, the Q node retention stress on the pull-up element increases. This side effect is more pronounced when the pull-up element is implemented using an oxide transistor. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, this embodiment provides a gate driving circuit that can reduce the Q node retention stress that becomes a problem in at least some stages during time-division driving of the display period and the touch period, and a touch-sensing display device including the same. [Means for solving the problem]

[0006] The gate driving circuit according to this embodiment includes a plurality of first odd-numbered main stages for driving first odd-numbered gate lines of a first display block during a first display period, a plurality of second odd-numbered main stages for driving second odd-numbered gate lines of a second display block adjacent to the first display block during a second display period following the first display period, and an odd-numbered reset dummy stage for resetting a Q node provided in a subsequent operating stage of the first odd-numbered main stage to a reset level during the first display period, and an odd-numbered set dummy stage for setting a Q node provided in a prior operating stage of the second odd-numbered main stage to a set level during the second display period, and the Q nodes of the first odd-numbered main stage and the second odd-numbered main stage both maintain the reset level during a touch period between the first display period and the second display period. [Effects of the Invention]

[0007] This embodiment has the following effects.

[0008] This embodiment can reduce the Q node retention stress that becomes a problem in at least some stages during time-division driving of the display period and the touch period, and further reduce the output deviation between stages.

[0009] The effects of this embodiment are not limited to the above examples, and various other effects are included in this specification. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram schematically illustrating a touch-sensing display device according to an embodiment of the present invention. [Figure 2] 1 is a diagram schematically illustrating a touch-sensing display device according to an embodiment of the present invention. [Figure 3] 10 is a diagram showing an example in which one frame according to the present embodiment is driven in a time-division manner into a display period and a touch period. FIG. [Figure 4] 10A and 10B are diagrams showing an example in which the display panel according to the present embodiment is divided into a plurality of display blocks and driven; [Figure 5] FIG. 10 is a diagram showing that display scanning for a display block is performed during a display period, and that display scanning for the display block is stopped during a touch period. [Figure 6] 10 is a diagram showing the configuration of a gate drive circuit for dividing and driving a plurality of display blocks according to the present embodiment. FIG. [Figure 7] 7 is a diagram showing in detail the configuration of a first gate driver corresponding to an area AR1 in FIG. 6. FIG. [Figure 8] 7 is a diagram showing the operation timing of the first gate driver corresponding to an area AR1 in FIG. 6. FIG. [Figure 9] 7 is a diagram showing in detail the configuration of a second gate driver corresponding to an area AR2 in FIG. 6. FIG. [Figure 10] 7 is a diagram showing the operation timing of the second gate driver corresponding to an area AR2 in FIG. 6. FIG. [Figure 11] FIG. 10 is a diagram illustrating a conventional Q node retention stress. [Figure 12] FIG. 2 is a diagram showing the configuration of a main stage or a dummy stage included in the gate drive circuit of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] The advantages and features of the specification, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the specification is not limited to the embodiments disclosed below, and may be embodied in various forms, the disclosure of which is complete and within the ordinary skill in the art to which the specification pertains. The specification is defined solely by the scope of the claims.

[0012] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary and are not limited to the matters shown in the present specification. The same reference numerals refer to the same components throughout the specification. When "comprises," "has," "achieves," etc. are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0013] When interpreting elements, they are interpreted as including a margin of error even if there is no explicit statement otherwise.

[0014] When describing the location of two parts, e.g., "above," "upper," "below," "next to," etc., one or more other parts may be located between the two parts, unless "to the right" or "directly" is used.

[0015] Although terms such as "first" and "second" may be used to describe various components, these components are not limited by these terms. These terms are used to distinguish only one component from another. Therefore, a "first" component referred to below may be a "second" component within the technical spirit of this specification. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that detailed descriptions of well-known functions or configurations related to the present invention may unnecessarily obscure the gist of the present invention, such detailed descriptions will be omitted.

[0016] 1 and 2 are diagrams schematically showing a touch-sensing display device according to this embodiment.

[0017] 1 and 2, a touch-sensing display device 100 according to an embodiment of the present invention provides a display function for reproducing an input image on a screen and a touch-sensing function for sensing a user's touch input.

[0018] The touch-sensing display device 100 may include a display panel 110 on which data lines DL and gate lines GL are arranged, a display driving circuit for driving the display panel 110, and a timing controller 140.

[0019] From a functional perspective, the display drive circuit can be divided into a gate drive circuit 120 for driving the gate lines GL and a data drive circuit 130 for driving the data lines DL. The display drive circuit can be implemented in one or more integrated circuits.

[0020] The display panel 110 may include an active area AA in which a plurality of subpixels SP are arranged, and a non-active area NA located outside the active area AA. Each of a plurality of touch electrodes TE may be arranged in an area corresponding to two or more subpixels SP. The touch electrodes TE may be referred to as touch nodes.

[0021] A plurality of gate lines GL and a plurality of data lines DL may be arranged on the display panel 110, and sub-pixels SP may be arranged at the intersections of the gate lines GL and the data lines DL. A plurality of touch lines TL may be further arranged on the display panel 110, electrically connected to the plurality of touch electrodes TE.

[0022] First, the configuration for display driving in the touch-sensing display device 100 will be described as follows.

[0023] The gate driving circuit 120 is controlled by the timing controller 140 and sequentially outputs scan signals to a plurality of gate lines GL arranged on the display panel 110 to control the driving timing of a plurality of sub-pixels SP.

[0024] The gate driving circuit 120 includes one or more gate driver integrated circuits (GDICs), and may be located on only one side or both sides of the display panel 110 depending on the driving method.

[0025] Each gate drive circuit integrated circuit GDIC may be connected to a bonding pad of the display panel 110 by tape automated bonding (TAB) or chip on glass (COG). Alternatively, each gate drive circuit integrated circuit GDIC may be realized as a GIP (Gate In Panel) type and disposed directly on the display panel 110. Alternatively, each gate drive circuit integrated circuit GDIC may be disposed integrally on the display panel 110. Alternatively, each gate drive circuit integrated circuit GDIC may be configured as a chip on film (COF) type, in which it is mounted on a film connected to the display panel 110.

[0026] The data driving circuit 130 receives image data from the timing controller 140 and converts the image data into an analog data voltage. The data driving circuit 130 outputs the data voltage to the data line DL in accordance with the timing at which a scan signal is applied via the gate line GL, causing the sub-pixel SP to express brightness according to the image data.

[0027] The data driving circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0028] Each source driver integrated circuit SDIC may be connected to a bonding pad of the display panel 110 by tape automated bonding (TAB) or chip-on-glass (COG). Alternatively, each source driver integrated circuit SDIC may be directly disposed on the display panel 110. Alternatively, each source driver integrated circuit SDIC may be disposed and integrated with the display panel 110. Alternatively, each source driver integrated circuit SDIC may be implemented by a chip-on-film (COF) method. In this case, each source driver integrated circuit SDIC may be mounted on a film connected to the display panel 110 and electrically connected to the display panel 110 via wiring on the film.

[0029] The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 and can control the operation timing of the gate driving circuit 120 and the data driving circuit 130 .

[0030] The timing controller 140 is mounted on a printed circuit board or a flexible printed circuit, and is electrically connected to the gate driving circuit 120 and the data driving circuit 130 via the printed circuit board or the flexible printed circuit.

[0031] The timing controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing set for each frame, and causes the data driving circuit 130 to convert image data into a data voltage and output the data voltage in synchronization with the scan signal.

[0032] The timing controller 140 receives various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), a clock signal (CLK), and the like from an external device (for example, a host system) along with video data.

[0033] The timing controller 140 may generate a gate control signal GCS and a data control signal DCS using various timing signals received from the outside, output the gate control signal GCS to the gate driving circuit 120, and output the data control signal DCS to the data driving circuit 130.

[0034] The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc. The gate start pulse GSP controls the operation start timing of one or more gate drive circuit integrated circuits GDIC that make up the gate drive circuit 120. The gate shift clock GSC is a clock signal commonly input to one or more gate drive circuit integrated circuits GDIC, and controls the shift timing of the scan signal. The gate output enable signal GOE controls the output timing of one or more gate drive circuit integrated circuits GDIC.

[0035] The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), etc. The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits SDIC that make up the data driving circuit 130. The source sampling clock SSC is a clock signal that controls the data sampling timing in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0036] The touch-sensing display device 100 may further include a power management integrated circuit that supplies or controls various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, and the like.

[0037] Next, the configuration for touch-sensing drive in the touch-sensing display device 100 will be described as follows.

[0038] The touch-sensing display device 100 may include a touch screen panel on which a plurality of touch electrodes TE are arranged for touch sensing, a touch circuit 200 for driving and sensing the touch screen panel, and the like.

[0039] The touch screen panel may be an external type manufactured separately from the display panel 110 and bonded to the display panel 110, or it may be an internal type manufactured together with the display panel 110 and located inside the display panel 110.

[0040] In the touch-sensing display device 100 according to this embodiment, the touchscreen panel can be considered as an independent panel having a touch-sensing function, and can refer to the display panel 110 having both a touch-sensing function and a display function. In the following description, it is assumed that the touchscreen panel is an internal type that is present inside the display panel 110.

[0041] The touch circuit 200 drives and senses a plurality of touch electrodes TE arranged on the display panel 110. The touch circuit 200 supplies touch drive signals to the touch electrodes TE, receives and accumulates touch sensing signals from the touch electrodes TE, and detects the presence or absence of a touch input and touch coordinates based on the touch sensing accumulated signal. The touch circuit 200 may be implemented as one or more components (e.g., integrated circuits) and may be implemented separately from the display drive circuit. Alternatively, all or a portion of the touch circuit 200 may be integrated with the display drive circuit or its internal circuitry. For example, a portion of the touch circuit 200 may be implemented as an integrated circuit together with the data drive circuit 130.

[0042] The touch electrode TE may be an electrode formed by dividing a common electrode for display driving. In this case, the touch electrode TE can function as an electrode for touch sensing driving and an electrode for display driving.

[0043] The touch circuit 200 may perform touch sensing by supplying a touch drive signal to the touch electrode TE in a touch period that is temporally separated from the display period.

[0044] FIG. 3 is a diagram showing an example in which one frame according to this embodiment is driven in a time-division manner into a display period and a touch period.

[0045] 3, in the touch-sensing display device according to this embodiment, one frame period may include a plurality of display periods D and a plurality of touch periods T. The display periods D may correspond to a high interval H of a touch synchronization signal SYNC, and the touch periods T may correspond to a low interval L of the touch synchronization signal SYNC. In response to the touch synchronization signal SYNC alternating between the high interval H and the low interval L, the display periods D and the touch periods T may be alternately arranged within one frame.

[0046] Display drive (1) is performed in the display period D, and touch sensing drive (2) is performed in the touch period T. Within one frame, the start timing of touch sensing drive (2) can be delayed by ΔT compared to the start timing of display drive (1).

[0047] Some of the horizontal blanking periods can be used as the touch period T. During the horizontal blanking periods, the display scanning operation and the associated image data writing operation are not performed and are stopped. During the horizontal blanking periods, the data enable signal does not swing between high and low levels but remains at low level.

[0048] The touch-sensing display device according to this embodiment can sense touch input by a user's finger or a stylus pen during the touch period T. In this way, the touch-sensing display device according to this embodiment can perform touch-sensing driving while displaying an image by sensing the user's touch input through the touch period T, which is temporally separated from the display period D within one frame period.

[0049] Fig. 4 is a diagram showing an example of dividing and driving the display panel according to the present embodiment into a plurality of display blocks. Fig. 5 is a diagram showing that display scanning for the display blocks is performed during a display period and that display scanning for the display blocks is stopped during a touch period.

[0050] 4, the display panel 110 according to this embodiment can be divided into a plurality of display blocks LHB1 to LBHj and driven. For each of the display blocks LHB1 to LBHj, a display drive (1) can be performed, followed by a touch sensing drive (2). For each of the display blocks LHB1 to LBHj, the display drive (1) and the touch sensing drive (2) can be alternated with a time difference of ΔT.

[0051] While display drive (1) is being performed on LHB2, touch sensing drive (2) is being performed on LHB1, while display drive (1) is being performed on LHB3, touch sensing drive (2) is being performed on LHB2, and while display drive (1) is being performed on LHBj, touch sensing drive (2) is being performed on LHBj-1.

[0052] 5, the display scan operation (GIP Operation) may be performed only in the display period X, and may not be performed in the touch period Y. That is, the display scan operation is stopped in the touch period Y (GIP GIP Holding).

[0053] The display scan operation is performed by the gate drive circuit 120 of Fig. 1. The gate drive circuit 120 outputs scan signals to the gate lines in the display period X. Then, the gate drive circuit 120 can stop outputting scan signals to the gate lines from the touch period Y. As a result, the scan signals are not output to the gate lines in the touch period Y.

[0054] Since the output of the scanning signal to the gate line is stopped from the touch period Y, some stages of the gate driving circuit 120 may receive a relatively large amount of Q node retention stress during the touch period Y.

[0055] The following embodiments of the present invention provide a method for reducing or minimizing the Q node retention stress that becomes a problem in at least some stages of the gate drive circuit 120 during time-division driving of the display period X and the touch period Y.

[0056] FIG. 6 is a diagram showing the configuration of a gate drive circuit for dividing and driving a plurality of display blocks LHB1 to LBH8 according to this embodiment.

[0057] Referring to FIG. 6, the gate driving circuit 120 according to this embodiment includes a first gate driving unit 120A arranged on the left side (or first side) of the display blocks LHB1 to LBH8 and a second gate driving unit 120B arranged on the right side (or second side) of the display blocks LHB1 to LBH8.

[0058] The first gate driver 120A and the second gate driver 120B interlace-drive the gate lines provided in the display blocks LHB1 to LBH8.

[0059] Eight display periods and eight touch periods are assigned to the eight display blocks LHB1 to LBH8, with the display periods and touch periods alternating one by one.

[0060] The first gate driver 120A includes eight odd-numbered main blocks LBK1 to LBK8 and eight odd-numbered dummy blocks LDM1 to LDM8 to drive the odd-numbered gate lines OL provided in the eight display blocks LHB1 to LBH8.

[0061] The eight odd-numbered main blocks LBK1 to LBK8 and the eight odd-numbered dummy blocks LDM1 to LDM8 are arranged in the left GIP region of the display blocks LHB1 to LBH8. In the left GIP region, any one of the eight odd-numbered main blocks LBK1 to LBK8 and any one of the eight odd-numbered dummy blocks LDM1 to LDM8 are arranged alternately. As a result, in the first gate driver 120A, at least one odd-numbered dummy block LDM is located between a pair of odd-numbered main blocks LBK.

[0062] The eight odd-numbered main blocks LBK1 to LBK8 are provided with operating stages equal in number to the odd-numbered gate lines OL provided in the eight display blocks LHB1 to LBH8.

[0063] Each of the eight odd-numbered dummy blocks LDM1 to LDM8 can include at least one odd-numbered reset dummy stage and at least one odd-numbered set dummy stage.

[0064] The odd-numbered reset dummy stages included in the eight odd-numbered dummy blocks LDM1 to LDM8 maintain the Q nodes of all eight odd-numbered main blocks LBK1 to LBK8 at the reset level during the touch period. That is, during the touch period, the odd-numbered reset dummy stages initialize or change the voltages of the Q nodes to the reset level.

[0065] For this purpose, the output of the odd reset dummy stage of LDM1 resets the Q node provided in the next operating stage included in LBK1, the output of the odd reset dummy stage of LDM2 resets the Q node provided in the next operating stage included in LBK2, the output of the odd reset dummy stage of LDM3 resets the Q node provided in the next operating stage included in LBK3, and similarly, the output of the odd reset dummy stage of LDM8 resets the Q node provided in the next operating stage included in LBK8.

[0066] In this embodiment, the "prior" and "subsequent" are determined according to the order in which the operation stages are arranged. For example, a "subsequent" operation stage may be arranged to operate later than a target operation stage, and a "prior" operation stage may be arranged to operate earlier than a target operation stage.

[0067] The Q node of the odd-numbered reset dummy stage can be reset by any of the external odd-numbered reset signals RST1(L) to RST8(L).

[0068] Furthermore, the output of the odd-numbered set dummy stage of LDM1 sets the Q node provided in the first-order operating stage included in LBK2 to a preset voltage, the output of the odd-numbered set dummy stage of LDM2 sets the Q node provided in the first-order operating stage included in LBK3 to a preset voltage, the output of the odd-numbered set dummy stage of LDM3 sets the Q node provided in the second-order operating stage included in LBK4 to a preset voltage. Similarly, the output of the odd-numbered set dummy stage of LDM7 sets the Q node provided in the first-order operating stage included in LBK8 to a preset voltage.

[0069] The Q node of the odd set dummy stage can be set by any of the external odd set signals VST1(L) to VST8(L).

[0070] Meanwhile, the second gate driver 120B includes eight even-numbered main blocks RBK1 to RBK8 and eight even-numbered dummy blocks RDM1 to RDM8 to drive the even-numbered gate lines EL provided in the eight display blocks LHB1 to LBH8.

[0071] The eight even-numbered main blocks RBK1 to RBK8 and the eight even-numbered dummy blocks RDM1 to RDM8 are arranged in the GIP region on the right side of the display blocks LHB1 to LBH8. In the right GIP region, any one of the eight even-numbered main blocks RBK1 to RBK8 and any one of the eight even-numbered dummy blocks RDM1 to RDM8 are alternately arranged. As a result, in the second gate driver 120B, at least one even-numbered dummy block RDM can be located between a pair of even-numbered main blocks RBK.

[0072] The eight even-numbered main blocks RBK1 to RBK8 are provided with operating stages equal in number to the even-numbered gate lines EL provided in the eight display blocks LHB1 to LBH8.

[0073] Each of the eight even-numbered dummy blocks RDM1 to RDM8 can include at least one or more even-numbered reset dummy stages and at least one or more even-numbered set dummy stages.

[0074] The even-numbered reset dummy stages included in the eight even-numbered dummy blocks RDM1 to RDM8 maintain the reset level of all the Q nodes of the eight even-numbered main blocks RBK1 to RBK8 during the touch period. That is, during the touch period, the even-numbered reset dummy stages initialize or change the voltages of the Q nodes to the reset level.

[0075] For this purpose, the output of the even reset dummy stage of RDM1 resets the Q node provided in the next operating stage included in RBK1, the output of the even reset dummy stage of RDM2 resets the Q node provided in the next operating stage included in RBK2, the output of the even reset dummy stage of RDM3 resets the Q node provided in the next operating stage included in RBK3, and similarly, the output of the even reset dummy stage of RDM8 resets the Q node provided in the next operating stage included in RBK8.

[0076] The Q node of the even reset dummy stage can be reset by any of the external even reset signals RST1(R) to RST8(R).

[0077] The output of the even-set dummy stage of RDM1 sets the Q node provided in the highest-priority operating stage included in RBK2, and the output of the even-set dummy stage of RDM2 sets the Q node provided in the highest-priority operating stage included in RBK3. The output of the even-set dummy stage of RDM3 sets the Q node provided in the lowest-priority operating stage included in RBK4. Similarly, the output of the even-set dummy stage of RDM7 sets the Q node provided in the highest-priority operating stage included in RBK8.

[0078] The Q nodes of the even-numbered set of dummy stages may be set by any of the external even-numbered set signals VST1(R) to VST8(R).

[0079] Fig. 7 is a diagram showing in detail the configuration of the first gate driver 120A corresponding to the area "AR1" in Fig. 6. Fig. 8 is a diagram showing the operation timing of the first gate driver 120A corresponding to the area "AR1" in Fig. 6.

[0080] 6, 7, and 8, the first gate driver 120A of this embodiment includes a plurality of first odd-numbered main stages LBK1 that drive the first odd-numbered gate lines OL of the first display block LHB1 without resetting the Q nodes included in the first-priority operating stage during the first display period, a plurality of second odd-numbered main stages LBK2 that drive the second odd-numbered gate lines OL of the second display block LHB2 adjacent to the first display block LHB1 without setting the Q nodes included in the second-priority operating stage during the second display period, odd-numbered reset dummy stages RST-DMY1 and RST-DMY3 that reset the Q nodes provided in the second-priority operating stages MGIP147 and MGIP149 in the first odd-numbered main stage LBK1 during the first display period, and odd-numbered set dummy stages ST-DMY1 and ST-DMY3 that set the Q node provided in the first-priority operating stage MGIP151 in the second odd-numbered main stage LBK2 during the second display period.

[0081] In one embodiment, each main stage includes a first plurality of main stages and a second plurality of main stages. The second plurality of main stages operate (e.g., output scan signals) after the first plurality of main stages operate. In one embodiment, the second plurality of main stages are arranged behind the first plurality of main stages. For example, in FIG. 7, operating stages MGIP147 and MGIP149 are the last operating stages in the first odd-numbered main stage LBK1 and can be considered to be rear-order operating stages, while operating stages in the first odd-numbered main stage LBK1 arranged before operating stages MGIP147 and MGIP149 can be considered to be front-order operating stages because they operate before operating stages MGIP147 and MGIP149.

[0082] Both the odd reset dummy stages RST-DMY1, RST-DMY3 and the odd set dummy stages ST-DMY1, ST-DMY3 are not connected to the first odd gate line OL of the first display block LHB1 and the second odd gate line OL of the second display block LHB2.

[0083] The voltage of the Q node of the subsequent operating stage MGIP147 in the first odd main stage LBK1 is reset to the low potential voltage VSS at the first timing T1 during the first display period by the output RST-CRY1 of the odd reset dummy stage RST-DMY1.

[0084] The voltage of the Q node provided in the subsequent operating stage MGIP149 in the first odd main stage LBK1 is reset to the low potential voltage VSS at the second timing T2 during the first display period by the output RST-CRY3 of the odd reset dummy stage RST-DMY3.

[0085] Therefore, during the touch period, both the Q node of the first odd-numbered main stage LBK1 and the Q node of the second odd-numbered main stage LBK2 maintain the reset level, and the Q node retention stress that has been a problem in the past can be minimized.

[0086] The conventional problem of Q node retention stress is illustrated in Figure 11. Referring to Figure 11, Q nodes Q147, Q149, and Q151 in some stages of the gate drive circuit are not reset during the touch period and maintain a set state, so the output characteristics change due to the degradation deviation between the pull-up elements connected to the Q nodes.

[0087] This embodiment solves the existing problem by resetting both the Q node of the first odd-numbered main stage LBK1 and the Q node of the second odd-numbered main stage LBK2 in the first display period preceding the touch period.

[0088] The voltages of the Q nodes provided in the odd reset dummy stages RST-DMY1 and RST-DMY3 are reset to the low potential voltage VSS at the third timing T3 within the first display period in response to the external odd reset signal RST1(L), which can be synchronized with the start timing of the touch period.

[0089] The voltage of the Q node provided in the odd set dummy stages ST-DMY1 and ST-DMY3 becomes the high potential voltage VDD at the fourth timing T4 within the touch period in response to the external odd set signal VST2(L). At this time, the external odd set signal VST2(L) can be synchronized with the end timing of the touch period.

[0090] The voltage of the Q node provided in the priority operating stage MGIP151 in the second odd main stage LBK2 is set to the high potential voltage VDD at the fifth timing T5 within the second display period by being supplied to the outputs ST-CRY1 and ST-CRY3 of the odd set dummy stages ST-DMY1 and ST-DMY2.

[0091] In FIG. 8, GOUT147 indicates the output of the operating stage MGIP147, GOUT149 indicates the output of the operating stage MGIP149, GOUT151 indicates the output of the operating stage MGIP151, and GOUT153 indicates the output of the operating stage MGIP153.

[0092] Fig. 9 is a diagram showing in detail the configuration of the second gate driver 120B corresponding to the area AR2 in Fig. 6. Fig. 10 is a diagram showing the operation timing of the second gate driver 120B corresponding to the area AR2 in Fig. 6.

[0093] 6, 9, and 10, the second gate driver 120B of this embodiment includes a plurality of first even main stages RBK1 for driving the first even gate lines EL of the first display block LHB1 during the first display period, a plurality of second even main stages RBK2 for driving the second even gate lines EL of the second display block LHB2 adjacent to the first display block LHB1 during the second display period, even reset dummy stages RST-DMY2 and RST-DMY4 for resetting the Q nodes provided in the subsequent operating stages MGIP148 and MGIP150 in the first even main stage RBK1 during the first display period, and even set dummy stages ST-DMY2 and ST-DMY4 for setting the Q nodes provided in the prior operating stage MGIP152 in the second even main stage RBK2 during the second display period.

[0094] Both the even reset dummy stages RST-DMY2, RST-DMY4 and the even set dummy stages ST-DMY2, ST-DMY4 are not connected to the first even gate line EL of the first display block LHB1 and the second even gate line EL of the second display block LHB2.

[0095] The voltage of the Q node of the subsequent operating stage MGIP148 in the first even main stage RBK1 is reset to the low potential voltage VSS at the first timing T1' in the first display period by the output RST-CRY2 of the even reset dummy stage RST-DMY2.

[0096] The voltage of the Q node of the subsequent operating stage MGIP150 in the first even main stage RBK1 is reset to the low potential voltage VSS at the second timing T2' within the first display period by the output RST-CRY4 of the even reset dummy stage RST-DMY4.

[0097] Therefore, during the touch period, the Q node of the first even main stage RBK1 and the Q node of the second even main stage RBK2 are both maintained at the reset level of the low potential voltage VSS, minimizing the Q node retention stress that has been a conventional problem.

[0098] The voltage of the Q node provided in the even reset dummy stages RST-DMY2 and RST-DMY4 is reset to a low potential voltage (VSS) at the third timing T3' within the first display period in response to the external even reset signal RST1(R). At this time, the external even reset signal RST1(R) can be synchronized with the start timing of the touch period.

[0099] The voltages of the Q nodes of the even set dummy stages ST-DMY2 and ST-DMY4 are set to the high potential voltage VDD at the fourth timing T4' within the touch period in response to the external even set signal VST2(R), which can be synchronized with the end timing of the touch period.

[0100] The voltage of the Q node provided in the priority operating stage MGIP152 in the second even main stage RBK2 is set to the high potential voltage VDD at the fifth timing T5' within the second display period by the outputs ST-CRY2 and ST-CRY4 of the even set dummy stages ST-DMY2 and ST-DMY2.

[0101] In FIG. 10, GOUT148 indicates the output of working stage MGIP148, GOUT150 indicates the output of working stage MGIP150, GOUT152 indicates the output of working stage MGIP152, and GOUT154 indicates the output of working stage MGIP154.

[0102] 12 is a diagram showing the configuration of a main stage (or a dummy stage) included in the gate drive circuit of this embodiment. The main stage and dummy stage described above can be designed in the same manner as in FIG.

[0103] 12, the main stage included in the gate drive circuit of this embodiment may include multiple transistors and at least one capacitor. Although each transistor is illustrated as a single transistor, in some cases, at least one transistor may be configured as a dual transistor in which two or more transistors are connected. Each transistor may be configured as an oxide semiconductor.

[0104] The main stage may include a pull-up transistor T6 and a pull-down transistor T7 that control the output of a scan signal synchronized with the current stage clock signal CLK(N). The main stage may include a pull-up transistor T6c and a pull-down transistor T7c that control the output of a current stage carry signal CRY(N) synchronized with the current stage clock signal CLK(N).

[0105] The main stage may include a capacitor CB connected between the Q node and the scan output node.

[0106] The main stage may include a transistor T1 that turns on in accordance with a carry signal CRY(N-2) of the previous stage output from the previous stage to set the voltage of the Q node.

[0107] The main stage may include a transistor T3 that turns on according to the voltage of the QB node to reset the voltage of the Q node.

[0108] The main stage may include a transistor T4 that applies a high potential voltage VDD to the QB node.

[0109] The main stage may include a transistor T5c that turns on in accordance with the previous stage carry signal CRY(N-2) to apply the low potential voltage VSS to the QB node.

[0110] The main stage may include a transistor T5q that turns on in response to the voltage at the Q node and applies a low potential voltage VSS to the QB node.

[0111] The main stage may include a transistor T3n that turns on according to the next-order carry signal CRY(N+4) output from the next-order stage to reset the voltage of the Q node.

[0112] The main stage may include a transistor T3no that is turned on according to the next-order carry signal CRY(N+4) and applies a low potential voltage (VGL) to the scan output node.

[0113] From the above description, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0114] 100 Touch-sensing display device 110 Display panel 120 Gate drive circuit

Claims

1. a display panel including subpixels; a gate driving circuit for driving a gate line connected to the subpixel; Including, One frame includes two or more display periods and two or more touch periods that are alternately arranged, the gate drive circuit comprises a plurality of odd stages and a plurality of even stages; The plurality of odd stages include: a plurality of odd main stages configured to drive odd gate lines among the gate lines connected to odd subpixels among the subpixels during the two or more display periods; at least one odd reset dummy stage not connected to the gate line; Including, The plurality of even stages include: a plurality of even main stages configured to drive even gate lines among the gate lines connected to even subpixels among the subpixels during the two or more display periods; at least one even reset dummy stage that is not connected to the gate line; Including, the at least one odd-numbered reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of odd-numbered main stages during a corresponding display period of the two or more display periods; the at least one even reset dummy stage is configured to reset a Q node included in one even main stage of the plurality of even main stages during a corresponding display period of the two or more display periods; the at least one odd-numbered reset dummy stage and the at least one even-numbered reset dummy stage are reset in synchronization with start timings of corresponding touch periods among the two or more touch periods; During the two or more touch periods, all Q nodes of the plurality of odd-numbered main stages and all Q nodes of the plurality of even-numbered main stages maintain a reset level. Touch-sensing display device.

2. 2. The touch-sensing display device according to claim 1, wherein a Q node included in the at least one odd-reset dummy stage is reset according to an external odd-reset signal, and a Q node included in the at least one even-reset dummy stage is reset according to an external even-reset signal.

3. the plurality of odd stages further include at least one odd-set dummy stage not connected to the gate line; the plurality of even stages further includes at least one even-set dummy stage not connected to the gate line; the at least one odd-numbered set dummy stage sets a Q node included in a corresponding one of the plurality of odd-numbered main stages during a corresponding display period of the two or more display periods; the at least one even-numbered set dummy stage sets a Q node included in a corresponding one of the plurality of even-numbered main stages during a corresponding display period of the two or more display periods; The touch-sensing display device of claim 1 .

4. The touch-sensing display device according to claim 3 , wherein the at least one odd-set dummy stage and the at least one even-set dummy stage are set in synchronization with end timings of corresponding touch periods among the two or more touch periods.

5. 5. The touch-sensing display device of claim 4, wherein a Q node included in the at least one odd-set dummy stage is set according to an external odd-set signal, and a Q node included in the at least one odd-set dummy stage is set according to an external even-set signal.

6. the display panel includes at least a first display block and a second display block disposed behind the first display block; the plurality of odd main stages include a plurality of first odd main stages and a plurality of second odd main stages; Each of the plurality of first odd main stages drives a corresponding first odd gate line among the gate lines connected to a corresponding first odd sub-pixel included in the first display block; Each of the plurality of second odd main stages drives a corresponding second odd gate line among the gate lines connected to a corresponding second odd sub-pixel included in the second display block; the at least one odd reset dummy stage includes at least one first odd reset dummy stage; the at least one first odd-numbered reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of first odd-numbered main stages in synchronization with a start timing of a first touch period; the first touch period is arranged between a first display period in which the first display block is driven and a second display period in which the second display block is driven; the at least one odd reset dummy stage includes at least one second odd set dummy stage; the at least one second odd-numbered set dummy stage is configured to set a Q node included in a corresponding one of the plurality of second odd-numbered main stages in synchronization with an end timing of the first touch period; The touch-sensing display device of claim 1 .

7. the plurality of even main stages includes a plurality of first even main stages and a plurality of second even main stages; Each of the plurality of first even main stages drives a corresponding first even gate line among the gate lines connected to a corresponding first even sub-pixel included in the first display block; Each of the plurality of second even main stages drives a corresponding second even gate line among the gate lines connected to a corresponding second even sub-pixel included in the second display block; the at least one even reset dummy stage includes at least one first even reset dummy stage; the at least one first even reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of second odd main stages in synchronization with a start timing of a first touch period; the at least one even reset dummy stage includes at least one second even set dummy stage; the at least one second even-numbered set dummy stage is configured to set a Q node included in a corresponding one of the plurality of second even-numbered main stages in synchronization with an end timing of the first touch period; The touch-sensing display device of claim 6 .

8. 2. The touch-sensing display device according to claim 1, wherein all Q nodes of the at least one odd-numbered reset dummy stage and all Q nodes of the at least one even-numbered reset dummy stage maintain the reset level during the two or more touch periods.

9. a plurality of odd stages and a plurality of even stages; The plurality of odd stages include: a plurality of odd main stages configured to drive odd gate lines connected to odd sub-pixels arranged on a display panel during two or more display periods; at least one odd reset dummy stage; Including, The plurality of even stages include: a plurality of even main stages configured to drive even gate lines connected to even sub-pixels arranged on the display panel during the two or more display periods; at least one even reset dummy stage; Including, the at least one odd reset dummy stage is not connected to the odd gate line; the at least one even reset dummy stage is not connected to the even gate line; One frame includes two or more display periods and two or more touch periods that are alternately arranged, the at least one odd-numbered reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of odd-numbered main stages during a corresponding display period of the two or more display periods; the at least one even reset dummy stage is configured to reset a Q node included in one even main stage of the plurality of even main stages during a corresponding display period of the two or more display periods; the at least one odd-numbered reset dummy stage and the at least one even-numbered reset dummy stage are reset in synchronization with start timings of corresponding touch periods among the two or more touch periods; During the two or more touch periods, all Q nodes of the plurality of odd-numbered main stages and all Q nodes of the plurality of even-numbered main stages maintain a reset level. Gate drive circuit.

10. 10. The gate drive circuit according to claim 9, wherein a Q node included in the at least one odd reset dummy stage is reset according to an external odd reset signal, and a Q node included in the at least one even reset dummy stage is reset according to an external even reset signal.

11. At least one odd-set dummy stage not connected to the odd gate lines; At least one even-set dummy stage not connected to the even gate lines; further comprising the at least one odd-numbered set dummy stage sets a Q node included in a corresponding one of the plurality of odd-numbered main stages during a corresponding display period of the two or more display periods; the at least one even-numbered set dummy stage sets a Q node included in a corresponding one of the plurality of even-numbered main stages during a corresponding display period of the two or more display periods; 10. The gate drive circuit of claim 9.

12. 12. The gate drive circuit according to claim 11, wherein the at least one odd-set dummy stage and the at least one even-set dummy stage are set in synchronization with end timings of corresponding touch periods among the two or more touch periods.

13. 13. The gate drive circuit of claim 12, wherein a Q node included in the at least one odd-set dummy stage is set according to an external odd-set signal, and a Q node included in the at least one odd-set dummy stage is set according to an external even-set signal.

14. the display panel includes at least a first display block and a second display block disposed behind the first display block; the plurality of odd main stages include a plurality of first odd main stages and a plurality of second odd main stages; Each of the plurality of first odd main stages drives a corresponding first odd gate line among the odd gate lines connected to a corresponding first odd sub-pixel included in the first display block; Each of the plurality of second odd main stages drives a corresponding second odd gate line among the odd gate lines connected to a corresponding second odd sub-pixel included in the second display block; the at least one odd reset dummy stage includes at least one first odd reset dummy stage; the at least one first odd-numbered reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of first odd-numbered main stages in synchronization with a start timing of a first touch period; the first touch period is arranged between a first display period in which the first display block is driven and a second display period in which the second display block is driven; the at least one odd reset dummy stage includes at least one second odd set dummy stage; the at least one second odd-numbered set dummy stage is configured to set a Q node included in a corresponding one of the plurality of second odd-numbered main stages in synchronization with an end timing of the first touch period; 10. The gate drive circuit of claim 9.

15. the plurality of even main stages includes a plurality of first even main stages and a plurality of second even main stages; Each of the plurality of first even main stages drives a corresponding first even gate line among the even gate lines connected to a corresponding first even sub-pixel included in the first display block; Each of the plurality of second even main stages drives a corresponding second even gate line among the even gate lines connected to a corresponding second even sub-pixel included in the second display block; the at least one even reset dummy stage includes at least one first even reset dummy stage; the at least one first even reset dummy stage is configured to reset a Q node included in a corresponding one of the plurality of second odd main stages in synchronization with a start timing of a first touch period; the at least one even reset dummy stage includes at least one second even set dummy stage; the at least one second even-numbered set dummy stage is configured to set a Q node included in a corresponding one of the plurality of second even-numbered main stages in synchronization with an end timing of the first touch period; 15. The gate drive circuit of claim 14.

16. 10. The gate drive circuit of claim 9, wherein all Q nodes of the at least one odd reset dummy stage and all Q nodes of the at least one even reset dummy stage maintain the reset level during the two or more touch periods.

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