Semiconductor device and manufacturing method thereof

Abstract

To provide a technology in which degradation of breakdown voltage is suppressed in a semiconductor device that comprises a connection region connecting a SJ structure and a body region.SOLUTION: A semiconductor device 1 comprises a plurality of second conductivity type connection regions 17 that are provided in a cell part 10A and a boundary part 10B. The plurality of connection regions are arranged between a plurality of bottom regions 14, 15, and a body region 18 in a thickness direction of a semiconductor layer 10, contact with the plurality of bottom regions and the body region, and are repetitively arranged so as to be spaced from each other along at least one direction. This permits drift regions 16 to be arranged between their spaces.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Semiconductor devices equipped with trench gates are being developed. The semiconductor layer of this type of semiconductor device is partitioned into a cell portion, a peripheral portion arranged around the cell portion, and a boundary portion arranged between the cell portion and the peripheral portion and around the cell portion. A trench gate is provided in the cell portion of the semiconductor layer. A breakdown voltage structure such as a guard ring region is provided in the peripheral portion of the semiconductor layer. The boundary portion of the semiconductor layer is the region between the cell portion and the peripheral portion.

[0003] Patent Document 1 discloses a semiconductor device having a super junction structure (hereinafter referred to as "SJ structure") between a cell section and a boundary section. The SJ structure is a structure in which n-type regions and p-type regions are alternately arranged repeatedly along at least one direction. A semiconductor device having an SJ structure can achieve both high breakdown voltage and low on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-149761 Summary of the Invention [Problem to be solved by the invention]

[0005] In semiconductor devices with trench gates, the SJ structure may be formed deeper than the trench gate. In this case, a p-type junction region is required to connect the p-type region that constitutes the SJ structure with the p-type body region provided in the surface layer of the semiconductor layer. This specification provides a technology for suppressing a decrease in breakdown voltage in semiconductor devices with a junction region that connects the SJ structure and the body region. [Means for solving the problem]

[0006] The semiconductor device (1, 2, 3) disclosed in this specification can include a semiconductor layer (10) partitioned into a cell portion (10A), an outer peripheral portion (10C) arranged so as to surround the periphery of the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion and arranged so as to surround the periphery of the cell portion, and a trench gate (30) provided on one main surface of the semiconductor layer. The semiconductor layer can have a first conductivity type drift region (12, 16) provided in the cell portion, the boundary portion, and the outer periphery; a second conductivity type body region (18) provided at least between the cell portion and the boundary portion and disposed on the drift region; a first conductivity type source region (19) provided in the cell portion and disposed on the body region; a plurality of second conductivity type bottom regions (14, 15) provided between the cell portion and the boundary portion, the plurality of bottom regions being located deeper than the trench gate and repeatedly arranged at intervals along at least one direction, whereby the drift region is disposed at the intervals between them; and a plurality of second conductivity type connecting regions (17) provided between the cell portion and the boundary portion, the plurality of connecting regions being located between the plurality of bottom regions and the body region in the thickness direction of the semiconductor layer, contacting the plurality of bottom regions and the body region, and repeatedly arranged at intervals along at least one direction, whereby the drift region is disposed at the intervals between them. The trench gate is provided in the cell portion and extends from the one main surface of the semiconductor layer, across the source region and the body region, to the drift region disposed between the plurality of connecting regions.

[0007] In the semiconductor device, the plurality of connecting regions are formed at the boundary portion of the semiconductor layer, as well as at the cell portion of the semiconductor layer, and are repeatedly spaced apart from one another. Therefore, the plurality of connecting regions arranged at the cell portion and the boundary portion of the semiconductor layer can have a generally uniform shape. As a result, unintended electric field concentration at the boundary portion of the semiconductor layer is suppressed, and a decrease in breakdown voltage is suppressed.

[0008] This specification further discloses a method for manufacturing a semiconductor device (1, 2, 3) comprising a semiconductor layer (10) partitioned into a cell portion (10A), an outer peripheral portion (10C) arranged to surround the periphery of the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion and arranged to surround the periphery of the cell portion, and a trench gate (30) provided on one main surface of the semiconductor layer. This manufacturing method can include the steps of forming a plurality of bottom regions (14, 15) of a second conductivity type on an upper surface of a lower drift region (12) of a first conductivity type, forming an upper drift region (16) of a first conductivity type on the lower drift region and the plurality of bottom regions, patterning a mask on the upper drift region and introducing second conductivity type impurities into the upper surface of the upper drift region through the mask to form a plurality of junction regions (17), forming a body region (18) of the second conductivity type on the upper drift region and the plurality of junction regions, and forming a source region (19) of the first conductivity type on the body region. The lower drift region is provided in the cell portion, the boundary portion, and the outer periphery. The plurality of bottom regions are provided at least in the cell portion and the boundary portion, are located deeper than the trench gate, and are repeatedly arranged at intervals along at least one direction, whereby the lower drift region is arranged at the intervals between them. The upper drift region is provided at least in the cell portion and the boundary portion. The plurality of connecting regions are provided at least in the cell portion and the boundary portion and are repeatedly arranged at intervals along at least one direction, whereby the upper drift region is arranged at the intervals between them. The trench gate is provided in the cell portion and extends from the one main surface of the semiconductor layer, across the source region and the body region, to the upper drift region arranged between the plurality of connecting regions.

[0009] In the manufacturing method, the plurality of connecting regions are formed in the boundary portion of the semiconductor layer, as well as in the cell portion of the semiconductor layer, with the connecting regions being spaced apart from one another. Therefore, when forming the plurality of connecting regions in each of the cell portion and the boundary portion of the semiconductor layer, differences in the depth of etching of the upper surfaces of the cell portion and the boundary portion due to differences in the size of the mask openings are suppressed. As a result, the plurality of connecting regions arranged in each of the cell portion and the boundary portion of the semiconductor layer can have a generally uniform shape. As a result, unintended electric field concentration at the boundary portion of the semiconductor layer is suppressed, and a decrease in breakdown voltage is suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing the positional relationship between a cell portion, a boundary portion, and an outer periphery portion partitioned in a semiconductor layer when the semiconductor layer is viewed in plan; [Figure 2] 2 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment, and is a diagram schematically showing a cross-sectional view corresponding to line II-II in FIG. 1. [Figure 3] FIG. 2 is a perspective view schematically illustrating a main part of a cell portion of a semiconductor layer. [Figure 4] 3 is a diagram showing the layout of a guard ring region, a boundary bottom region, a cell bottom region, and a connection region of the semiconductor device of the first embodiment. FIG. [Figure 5] 1 is a diagram showing a flow of a method for manufacturing a semiconductor device; [Figure 6] 10A to 10C are diagrams schematically showing cross-sectional views of essential parts in a process for manufacturing a semiconductor device of a comparative example. [Figure 7] 10A to 10C are diagrams schematically showing cross-sectional views of essential parts in a process for manufacturing a semiconductor device of a comparative example. [Figure 8] 10A to 10C are diagrams schematically showing cross-sectional views of essential parts in a process for manufacturing a semiconductor device of a comparative example. [Figure 9] 2 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment, and is a diagram schematically showing a cross-sectional view corresponding to line II-II in FIG. 1. [Figure 10]10 is a diagram showing the layout of a guard ring region, a boundary bottom region, a cell bottom region, and a connection region of a semiconductor device according to a second embodiment. FIG. [Figure 11] 10 is a diagram showing the layout of a guard ring region, a boundary bottom region, a cell bottom region, and a connection region of a semiconductor device according to a third embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a semiconductor device to which the technology disclosed in this specification is applied and a manufacturing method thereof will be described with reference to the drawings. In the following drawings, for the purpose of clarity of illustration, only some of the common components may be designated by reference numerals. Furthermore, common components in each embodiment are designated by common reference numerals, and their description will be omitted.

[0012] (First embodiment) 1 to 3, the semiconductor device 1 is a type of power device called a MOSFET, and is configured using a semiconductor layer 10. The material of the semiconductor layer 10 is not particularly limited, but may be, for example, silicon carbide (SiC). The semiconductor device 1 may also be a type of power device called an IGBT.

[0013] As shown in FIG. 1, when the semiconductor layer 10 is viewed from above (hereinafter referred to as "when viewed in a plan view"), the semiconductor layer 10 is partitioned into a cell portion 10A, a boundary portion 10B, and a peripheral portion 10C. The cell portion 10A is a region partitioned inside the center of the semiconductor layer 10, and is a region in which a switching structure is formed, as described below. The boundary portion 10B is a region partitioned between the cell portion 10A and the peripheral portion 10C, and surrounds the periphery of the cell portion 10A. The peripheral portion 10C is a region partitioned around the periphery of the cell portion 10A and the boundary portion 10B, and surrounds the periphery of the cell portion 10A and the boundary portion 10B. In the peripheral portion 10C, a breakdown voltage structure is formed, as described below.

[0014] 2, the semiconductor device 1 includes a semiconductor layer 10, a drain electrode 22, a source electrode 24, and multiple trench gates 30. The semiconductor layer 10 includes a drain region 11, a lower drift region 12, multiple guard ring regions 13, multiple boundary bottom regions 14, multiple cell bottom regions 15, an upper drift region 16, multiple junction regions 17, a body region 18, multiple source regions 19, and multiple contact regions 20. The cell region 10A is a region where multiple trench gates 30 are provided and where current flows between the drain electrode 22 and the source electrode 24. The outer peripheral region 10C is a region where multiple guard ring regions 13 are provided and is located outside the innermost guard ring region 13. The boundary portion 10B is the region between the cell portion 10A and the outer periphery portion 10C, and is the region from the outermost edge of the trench gate 30 provided in the cell portion 10A to the innermost guard ring region 13 in the outer periphery portion 10C.

[0015] The upper surface of the semiconductor layer 10 is recessed in an area corresponding to the outer periphery 10C, and a step is formed between the boundary 10B and the outer periphery 10C. In other words, the portion of the semiconductor layer 10 between the cell portion 10A and the boundary 10B is configured in a mesa shape and protrudes above the upper surface of the outer periphery 10C.

[0016] The drain electrode 22 is provided to cover the lower surface of the semiconductor layer 10. The drain electrode 22 is disposed across the cell portion 10A, the boundary portion 10B, and the outer periphery portion 10C, and is in contact with the entire lower surface of the semiconductor layer 10.

[0017] The source electrode 24 is provided to cover the upper surface of the semiconductor layer 10. The source electrode 24 is disposed across the cell portion 10A and part of the boundary portion 10B, and is in contact with the upper surface of the semiconductor layer 10 exposed from an opening in the interlayer insulating film formed on the upper surface of the semiconductor layer 10.

[0018] The drain region 11 is an n-type region containing a high concentration of n-type impurities. The drain region 11 is provided across the cell portion 10A, the boundary portion 10B, and the outer periphery portion 10C, and is disposed on the lower surface of the semiconductor layer 10. The drain region 11 is in ohmic contact with the drain electrode 22.

[0019] The lower drift region 12 is an n-type region with a lower n-type impurity concentration than the drain region 11. The lower drift region 12 is provided across the cell portion 10A, the boundary portion 10B, and the outer periphery portion 10C. The lower drift region 12 is formed by growing crystals from the surface of the drain region 11 using, for example, a crystal growth technique. The lower drift region 12, together with the upper drift region 16 described below, is referred to as the drift region.

[0020] The multiple guard ring regions 13 are p-type regions containing p-type impurities. Each of the multiple guard ring regions 13 is provided in the outer periphery 10C and is arranged so as to surround the cell portion 10A and the boundary portion 10B along the outer periphery 10C (see FIG. 4). The multiple guard ring regions 13 are repeatedly arranged at intervals along the inner-outer direction (the direction connecting the center of the cell portion 10A and the outer periphery 10C) when the semiconductor layer 10 is viewed in plan. A portion of the lower drift region 12 is arranged between adjacent guard ring regions 13. The multiple guard ring regions 13 are formed by introducing p-type impurities into a portion of the upper surface of the lower drift region 12 using, for example, ion implantation technology. The multiple guard ring regions 13 are an example of a voltage-resistant structure. The potential of the multiple guard ring regions 13 is floating.

[0021] The multiple boundary bottom regions 14 are p-type regions containing p-type impurities. Each of the multiple boundary bottom regions 14 is provided in the boundary 10B and is arranged so as to surround the periphery of the cell portion 10A along the boundary 10B (see FIG. 4). The multiple boundary bottom regions 14 are arranged deeper than the trench gate 30. The multiple boundary bottom regions 14 are repeatedly arranged at intervals along the inner-outer direction when the semiconductor layer 10 is viewed in plan. A portion of the lower drift region 12 is arranged between adjacent boundary bottom regions 14. The widths and impurity concentrations of the multiple boundary bottom regions 14 and the portions of the lower drift region 12 arranged between the boundary bottom regions 14 are adjusted to achieve charge balance, thereby forming an SJ structure. Note that the portions of the lower drift region 12 arranged between adjacent boundary bottom regions 14 may be adjusted to have a higher impurity concentration than other regions of the lower drift region 12. The plurality of boundary bottom regions 14 are formed by, for example, using ion implantation technology, introducing p-type impurities into a portion of the upper surface of the lower drift region 12. The plurality of boundary bottom regions 14, together with the plurality of cell portion bottom regions 15 described below, are referred to as the bottom region.

[0022] As shown in FIGS. 2 and 3 , the multiple cell portion bottom regions 15 are p-type regions containing p-type impurities. Each of the multiple cell portion bottom regions 15 is provided in the cell portion 10A and is located deeper than the trench gate 30. When the semiconductor layer 10 is viewed from above, the multiple cell portion bottom regions 15 extend along at least one direction (the y direction in this example, a direction perpendicular to the longitudinal direction of the trench gate 30) and are repeatedly arranged at intervals along a direction perpendicular to the one direction (the x direction in this example, a direction parallel to the longitudinal direction of the trench gate 30). A portion of the lower drift region 12 is arranged between adjacent cell portion bottom regions 15. The multiple cell portion bottom regions 15 and the portions of the lower drift region 12 arranged between the cell portion bottom regions 15 have widths and impurity concentrations adjusted to achieve charge balance, thereby forming an SJ structure. Note that a portion of the lower drift region 12 disposed between adjacent cell portion bottom regions 15 may be adjusted to have a higher concentration of n-type impurities than other regions of the lower drift region 12. The multiple cell portion bottom regions 15 are formed by introducing p-type impurities into a portion of the upper surface of the lower drift region 12 using, for example, ion implantation technology.

[0023] The upper drift region 16 is an n-type region containing n-type impurities. The upper drift region 16 is provided across the cell section 10A and the boundary section 10B. The concentration of n-type impurities in the upper drift region 16 may be the same as that in the lower drift region 12, or may be higher than that in the lower drift region 12. The upper drift region 16 contacts the lower portions of the bottom and side surfaces of the trench gate 30. The upper drift region 16 also contacts a portion of the lower drift region 12 located between adjacent cell section bottom regions 15. The upper drift region 16 is formed by crystal growth from the upper surfaces of the lower drift region 12 and the bottom regions 14 and 15, for example, using a crystal growth technique.

[0024] The multiple connection regions 17 are p-type regions containing p-type impurities. The multiple connection regions 17 are provided across the cell portion 10A and the boundary portion 10B, and are arranged between the multiple bottom regions 14, 15 and the body region 18 in the thickness direction of the semiconductor layer 10 (the z direction in this example). Each of the multiple connection regions 17 contacts the multiple bottom regions 14, 15 at its lower surface and contacts the body region 18 at its upper surface. As a result, the multiple bottom regions 14, 15 are electrically connected to the body region 18 via the multiple connection regions 17. When the semiconductor layer 10 is viewed in plan, each of the multiple connection regions 17 extends in a direction different from the longitudinal direction of the cell portion bottom region 15. In this example, when the semiconductor layer 10 is viewed in plan, each of the multiple bridging regions 17 extends in a direction perpendicular to the longitudinal direction of the cell portion bottom region 15 (the x direction in this example, a direction parallel to the longitudinal direction of the trench gate 30), and is repeatedly arranged at intervals along a direction perpendicular to the x direction (the y direction in this example, a direction perpendicular to the longitudinal direction of the trench gate 30). The upper drift region 16 is arranged between adjacent bridging regions 17. The multiple bridging regions 17 are formed by introducing p-type impurities into parts of the upper surface of the upper drift region 16 using, for example, ion implantation technology.

[0025] 4, each of the multiple connecting regions 17 extends long along the x direction when the semiconductor layer 10 is viewed in a plan view. Some of the multiple connecting regions 17 extend beyond the cell portion 10A into the boundary portion 10B. Some of the multiple connecting regions 17 intersect with each of the multiple cell portion bottom regions 15 and also with each of the multiple boundary portion bottom regions 14.

[0026] 2 and 3, the body region 18 is a p-type region containing p-type impurities. The body region 18 is provided across the cell portion 10A and the boundary portion 10B, and is arranged on the upper drift region 16 and a plurality of connecting regions 17. The body region 18 contacts the side surface of the trench gate 30 and separates the upper drift region 16 from the source region 19. The body region 18 is formed by growing crystals from the top surface of the upper drift region 16 using, for example, a crystal growth technique.

[0027] The multiple source regions 19 are n-type regions containing a high concentration of n-type impurities. The multiple source regions 19 are provided in the cell section 10A and are arranged on the body region 18 and on the upper surface of the semiconductor layer 10. Each of the multiple source regions 19 contacts an upper portion of a side surface of the trench gate 30. When the semiconductor layer 10 is viewed in plan, each of the multiple source regions 19 extends parallel to the longitudinal direction of the trench gate 30. Each of the multiple source regions 19 is exposed from an opening in an interlayer insulating film formed on the upper surface of the semiconductor layer 10 and is in ohmic contact with the source electrode 24. The multiple source regions 19 are formed by an n-type layer grown from the upper surface of the body region 18 using, for example, a crystal growth technique.

[0028] The contact regions 20 are p-type regions containing a higher concentration of p-type impurities than the body region 18. The contact regions 20 are provided in the cell section 10A and are arranged on the body region 18 and on the upper surface of the semiconductor layer 10. When the semiconductor layer 10 is viewed in plan, each of the contact regions 20 extends parallel to the longitudinal direction of the trench gate 30. Each of the contact regions 20 is exposed through an opening in an interlayer insulating film formed on the upper surface of the semiconductor layer 10 and is in ohmic contact with the source electrode 24. The contact regions 20 are formed by introducing p-type impurities into an n-type layer used to form the source regions 19, for example, using ion implantation technology. The source regions 19 are formed as remnants of the ion implantation of the contact regions 20 into the n-type layer.

[0029] The plurality of trench gates 30 are provided in the cell portion 10A and extend from the upper surface of the semiconductor layer 10, past the source region 19 and the body region 18, and into the upper drift region 16. When the semiconductor layer 10 is viewed from above, the plurality of trench gates 30 extend along at least one direction (the x direction in this example) and are repeatedly arranged at intervals along a direction perpendicular to the one direction (the y direction in this example). Thus, when the semiconductor layer 10 is viewed from above, the plurality of trench gates 30 are arranged in a stripe pattern. Note that the stripe pattern is just an example, and the plurality of trench gates 30 may be arranged in other layouts. Each of the plurality of trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the upper drift region 16, the body region 18, and the source region 19 by the gate insulating film 34 and from the source electrode 24 by the interlayer insulating film.

[0030] In this way, a switching structure is formed in the cell section 10A by the drain electrode 22, the drain region 11, the lower drift region 12, the cell section bottom region 15, the upper drift region 16, the connecting region 17, the body region 18, the source region 19, the contact region 20, the source electrode 24, the trench gate 30, etc.

[0031] Next, the operation of the semiconductor device 1 will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 32 while a voltage is applied between the drain and source such that the drain electrode 22 has a higher potential than the source electrode 24, a channel is formed in the body region 18 adjacent to the gate insulating film 34. Electrons supplied from the source region 19 flow into the upper drift region 16 through this channel. Electrons that flow into the upper drift region 16 flow into the drain region 11 via the lower drift region 12. This establishes electrical continuity between the drain electrode 22 and the source electrode 24, turning the semiconductor device 1 on. On the other hand, when a voltage less than the gate threshold voltage is applied to the gate electrode 32, the channel disappears, turning the semiconductor device 1 off. In this way, the semiconductor device 1 can operate as a switching element that controls the current flowing between the drain electrode 22 and the source electrode 24 depending on the voltage applied to the gate electrode 32.

[0032] Next, some steps in the manufacturing process of the semiconductor device 1 will be described with reference to Fig. 5. For the other steps, conventionally known steps can be adopted.

[0033] First, in step S1, a SiC substrate that functions as drain region 11 is prepared, and lower drift region 12 is formed by crystal growth from the upper surface of drain region 11 using a crystal growth technique.

[0034] Next, in step S2, a mask is patterned on lower drift region 12, and then p-type impurities are introduced into a portion of the upper surface of lower drift region 12 through the mask using ion implantation technology to form guard ring region 13, boundary bottom region 14, and cell section bottom region 15. After ion implantation, the mask is removed. Note that the step of forming guard ring region 13 and the step of forming boundary bottom region 14 and cell section bottom region 15 may be performed separately.

[0035] Next, in step S3, upper drift region 16 is formed by crystal growth from the upper surface of lower drift region 12 including guard ring region 13, boundary bottom region 14, and cell bottom region 15 using a crystal growth technique.

[0036] Next, in step S4, a mask is patterned on upper drift region 16, and then ion implantation technology is used to introduce p-type impurities into part of the top surface of upper drift region 16 through the mask to form connecting region 17. After ion implantation, the mask is removed.

[0037] Next, in step S5, the body region 18 is formed by crystal growth from the top surface of the upper drift region 16 including the plurality of connecting regions 17 using a crystal growth technique.

[0038] Next, in step S6, a crystal growth technique is used to form an n-type layer by crystal growth from the upper surface of the body region 18. Next, an ion implantation technique is used to introduce p-type impurities into a portion of the n-type layer to form contact regions 20. The remaining portions of the n-type layer after ion implantation of the multiple contact regions 20 become multiple source regions 19.

[0039] Next, in step S7, a trench gate 30 is formed that extends beyond the source region 19 and the body region 18 and reaches the upper drift region 16.

[0040] Thereafter, the drain electrode 22, the source electrode 24, etc. are formed, and the semiconductor device 1 can be completed.

[0041] Next, the multiple connection regions 17 will be described. Among the multiple connection regions 17, the multiple connection regions 17 arranged in the cell portion 10A are repeatedly arranged at intervals in the surface direction of the semiconductor layer 10 to ensure a current path, i.e., to provide the upper drift region 16. On the other hand, the boundary portion 10B is not a region through which current flows, so a connection region 17 of such a shape is not necessary in the boundary portion 10B. For example, it is conceivable to form a single connection region 17 across the entire range of the boundary portion 10B. However, it has been found that the following problems arise when such a single connection region 17 is formed in the boundary portion 10B.

[0042] 6 to 8, a problem in a comparative example in which a single connecting region 17 is formed in the boundary portion 10B will be described. Figures 6 to 8 are cross-sectional views of a main part corresponding to the boundary between the cell portion 10A and the boundary portion 10B, and correspond to views for explaining the process of step S4 in Figure 5 in the comparative example.

[0043] First, as shown in FIG. 6, a mask 42 is deposited on the upper drift region 16. Next, as shown in FIG. 7, the mask 42 is patterned. The opening formed in the mask 42 in the boundary region 10B corresponds to a single connecting region 17 and is wider than the opening formed in the mask 42 in the cell region 10A. Therefore, during etching to form the opening in the mask 42, more etchant is supplied to the upper surface of the boundary region 10B than to the upper surface of the cell region 10A. As a result, the depth D1 to which the upper surface of the boundary region 10B is removed is greater than the depth D2 to which the upper surface of the cell region 10A is removed, and the upper surface of the boundary region 10B is removed more deeply than the upper surface of the cell region 10A. Next, as shown in FIG. 8, p-type impurities are introduced into a portion of the upper drift region 16 using ion implantation technology to form connecting regions 17. At this time, the upper surface of boundary portion 10B is cut deeper than the upper surface of cell portion 10A, so that single connecting region 17 formed at boundary portion 10B is formed deeper than the multiple connecting regions 17 formed at cell portion 10A. In this way, in the comparative example in which single connecting region 17 is formed at boundary portion 10B, the depth of connecting region 17 between cell portion 10A and boundary portion 10B varies within the plane, and there is a concern that unintended electric field concentration may occur, particularly at boundary portion 10B, resulting in a decrease in breakdown voltage.

[0044] On the other hand, in the semiconductor device 1 of this embodiment, similar to the cell region 10A, multiple connection regions 17 are formed in the boundary region 10B, spaced apart from one another. Therefore, the multiple connection regions 17 arranged in each of the cell region 10A and the boundary region 10B can have a generally uniform shape. As a result, unintended electric field concentration at the boundary region 10B is suppressed, and a decrease in breakdown voltage is suppressed. To suppress in-plane variations such as those in the comparative example, the width in the lateral direction (the width in the y direction in FIG. 2 ) of the multiple connection regions 17 arranged in the boundary region 10B may be 10 times or less the width in the lateral direction (the width in the y direction in FIG. 2 ) of the multiple connection regions 17 arranged in the cell region.

[0045] (Second embodiment) 9 and 10 show a semiconductor device 2 of the second embodiment. As with the semiconductor device 1 of the first embodiment, in the semiconductor device 2, each of the plurality of boundary bottom regions 14 is arranged so as to surround the periphery of the cell portion 10A along the boundary 10B. Therefore, when the semiconductor layer 10 is viewed in plan, each of the plurality of boundary bottom regions 14 has a portion extending along the x direction and a portion extending along the y direction.

[0046] Each of the multiple connection regions 17 extends long along the x direction when the semiconductor layer 10 is viewed in a plan view. Therefore, in a portion where each of the multiple boundary bottom regions 14 extends along the y direction, each of the multiple connection regions 17 extends perpendicular to each of the multiple boundary bottom regions 14 arranged below it when the semiconductor layer 10 is viewed in a plan view, and intersects with each of the multiple boundary bottom regions 14. This allows the multiple boundary bottom regions 14 and the multiple connection regions 17 to contact each other over many areas. Furthermore, in a portion where each of the multiple boundary bottom regions 14 extends along the x direction, each of the multiple connection regions 17 extends parallel to the corresponding bottom region 14 arranged below it when the semiconductor layer 10 is viewed in a plan view, so as to overlap with the corresponding bottom region 14. This allows the multiple boundary bottom regions 14 and the multiple connection regions 17 to contact each other over a large area.

[0047] In the semiconductor device 2, the multiple connecting regions 17 and the multiple boundary bottom regions 14 can contact each other over a large area in the boundary region 10B, so that the potential of the boundary bottom region 14 can be stabilized.

[0048] (Third embodiment) 11 shows a semiconductor device 3 according to a third embodiment. In the semiconductor device 3, in a portion where each of the boundary bottom regions 14 extends along the y direction, each of the plurality of connecting regions 17 extends perpendicular to each of the plurality of boundary bottom regions 14 disposed thereunder when the semiconductor layer 10 is viewed in plan, and intersects with each of the plurality of boundary bottom regions 14. Also, in a portion where each of the plurality of boundary bottom regions 14 extends along the x direction, each of the plurality of connecting regions 17 extends perpendicular to each of the plurality of boundary bottom regions 14 disposed thereunder when the semiconductor layer 10 is viewed in plan, and intersects with each of the plurality of boundary bottom regions 14. Note that in a portion where each of the plurality of boundary bottom regions 14 extends along the x direction, each of the plurality of connecting regions 17 may extend in a direction oblique to each of the plurality of boundary bottom regions 14 disposed thereunder when the semiconductor layer 10 is viewed in plan.

[0049] In the semiconductor device 3 as well, the plurality of connecting regions 17 and the plurality of boundary bottom regions 14 can contact each other in many areas at the boundary 10B, so that the potential of the boundary bottom region 14 can be stabilized.

[0050] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0051] (Feature 1) The semiconductor device disclosed in this specification can include a semiconductor layer partitioned into a cell portion, an outer peripheral portion arranged to surround the cell portion, and a boundary portion between the cell portion and the outer peripheral portion arranged to surround the cell portion, and a trench gate provided on one main surface of the semiconductor layer. The semiconductor layer can have: a drift region of a first conductivity type provided between the cell portion, the boundary portion, and the outer periphery; a body region of a second conductivity type provided at least between the cell portion and the boundary portion and disposed on the drift region; a source region of the first conductivity type provided in the cell portion and disposed on the body region; a plurality of bottom regions of the second conductivity type provided between the cell portion and the boundary portion, the bottom regions being located deeper than the trench gates and repeatedly arranged at intervals along at least one direction, whereby the drift region is disposed at the intervals between the bottom regions; and a plurality of connecting regions of the second conductivity type provided between the cell portion and the boundary portion, the connecting regions being located between the bottom regions and the body region in the thickness direction of the semiconductor layer, being in contact with the bottom regions and the body region, and being repeatedly arranged at intervals along at least one direction, whereby the drift region is disposed at the intervals between the connecting regions. The trench gate is provided in the cell portion and extends from the one main surface of the semiconductor layer, across the source region and the body region, to the drift region disposed between the plurality of connecting regions.

[0052] (Feature 2) In the semiconductor device of Feature 1, the plurality of bottom regions disposed in the cell portion may be repeatedly arranged at intervals along a first direction when the semiconductor layer is viewed in a planar state. Furthermore, the plurality of bottom regions disposed in the boundary portion may be repeatedly arranged at intervals along an inner-outer direction around the cell portion. Furthermore, the plurality of connecting regions disposed in the cell portion may be repeatedly arranged at intervals along a second direction different from the first direction when the semiconductor layer is viewed in a planar state.

[0053] (Feature 3) In the semiconductor device of Feature 2, each of the plurality of connecting regions that are arranged at the boundary portion may extend parallel to and overlap with a corresponding bottom region arranged below it when the semiconductor layer is viewed in a plan view.

[0054] (Feature 4) In the semiconductor device of Features 2 or 3, each of the plurality of connecting regions that are arranged at the boundary portion may extend so as to intersect with each of the plurality of bottom regions that are arranged below it when the semiconductor layer is viewed in a plane.

[0055] (Feature 5) In the semiconductor device of Feature 4, each of the plurality of connecting regions that are arranged at the boundary portion may extend in a direction perpendicular to each of the plurality of bottom regions that are arranged below it when the semiconductor layer is viewed in a plan view.

[0056] (Feature 6) In the semiconductor device described in any one of Features 1 to 5, the width in the short side of the plurality of connecting regions that are arranged in the boundary portion among the plurality of connecting regions may be 10 times or less the width in the short side of the plurality of connecting regions that are arranged in the cell portion among the plurality of connecting regions.

[0057] (Feature 7) In the semiconductor device according to any one of Features 1 to 6, the semiconductor layer may be made of silicon carbide.

[0058] (Feature 8) The present specification discloses a method for manufacturing a semiconductor device including a semiconductor layer partitioned into a cell region, an outer periphery region surrounding the cell region, and a boundary region between the cell region and the outer periphery region surrounding the cell region, and a trench gate provided on one main surface of the semiconductor layer. The method may include forming a plurality of bottom regions of a second conductivity type on an upper surface of a lower drift region of a first conductivity type, forming an upper drift region of a first conductivity type on the lower drift region and the plurality of bottom regions, patterning a mask on the upper drift region and introducing second conductivity type impurities into the upper surface of the upper drift region through the mask to form a plurality of junction regions, forming a body region of the second conductivity type on the upper drift region and the plurality of junction regions, and forming a source region of the first conductivity type on the body region. The lower drift region is provided in the cell region, the boundary region, and the outer periphery. The plurality of bottom regions are provided at least in the cell portion and the boundary portion, are positioned deeper than the trench gate, and are repeatedly arranged at intervals along at least one direction, whereby the lower drift region is disposed at the intervals between them. The upper drift region is provided at least in the cell portion and the boundary portion. The plurality of connecting regions are provided at least in the cell portion and the boundary portion, and are repeatedly arranged at intervals along at least one direction, whereby the upper drift region is disposed at the intervals between them. The trench gate is provided in the cell portion and extends from the one main surface of the semiconductor layer, across the source region and the body region, to the upper drift region disposed between the plurality of connecting regions.

[0059] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0060] 1, 2, 3: semiconductor device, 10: semiconductor layer, 10A: cell portion, 10B: boundary portion, 10C: peripheral portion, 11: drain region, 12: lower drift region, 13: guard ring region, 14: boundary portion bottom region, 15: cell portion bottom region, 16: upper drift region, 17: connection region, 18: body region, 19: source region, 20: contact region, 22: drain electrode, 24: source electrode, 30: trench gate

Claims

1. A semiconductor device (1, 2, 3), a semiconductor layer (10) partitioned into a cell portion (10A), an outer peripheral portion (10C) arranged so as to surround the periphery of the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion and arranged so as to surround the periphery of the cell portion; a plurality of trench gates (30) provided on one main surface of the semiconductor layer; The semiconductor layer is a first conductivity type drift region (12, 16) provided in the cell portion, the boundary portion, and the outer periphery; a body region (18) of a second conductivity type provided at least in the cell portion and the boundary portion and disposed on the drift region; a first conductivity type source region (19) provided in the cell portion and arranged on the body region; a plurality of second conductivity type bottom regions (14, 15) provided in the cell portion and the boundary portion, the plurality of bottom regions being arranged at positions deeper than the plurality of trench gates and repeatedly arranged at intervals along an arbitrary direction, whereby the drift region is arranged at the intervals between the plurality of bottom regions; a plurality of second conductivity type connecting regions (17) provided in the cell portion and the boundary portion, the connecting regions being arranged between the plurality of bottom regions and the body region in the thickness direction of the semiconductor layer, contacting the plurality of bottom regions and the body region, and repeatedly arranged at intervals along an arbitrary direction, whereby the drift region is arranged at the intervals between the plurality of connecting regions; a plurality of guard ring regions (13) of a second conductivity type provided in the outer periphery, the guard ring regions encircling the cell portion and the boundary portion when the semiconductor layer is viewed in plan, and repeatedly arranged at intervals along an inner-outer direction; the plurality of trench gates are provided in the cell portion, and extend from the one main surface of the semiconductor layer across the source region and the body region to the drift region disposed between the plurality of connecting regions; the boundary portion is defined as a region from an outermost edge of the trench gate to the innermost guard ring region, The plurality of connection regions include a plurality of connection regions arranged in the cell portion and a plurality of connection regions arranged in the boundary portion.

2. a plurality of bottom regions arranged in the cell portion among the plurality of bottom regions are repeatedly arranged at intervals along a first direction when the semiconductor layer is viewed in a plan view, the plurality of bottom regions arranged in the boundary portion are arranged to go around the cell portion and are repeatedly arranged at intervals along an inner-outer direction when the semiconductor layer is viewed in a plan view, 2. The semiconductor device according to claim 1, wherein each of the plurality of connection regions arranged in the cell portion among the plurality of connection regions is repeatedly arranged at intervals along a second direction different from the first direction when the semiconductor layer is viewed in a plan view.

3. 3. The semiconductor device according to claim 2, wherein each of the plurality of connecting regions arranged at the boundary portion extends parallel to a corresponding bottom region arranged below it so as to overlap the corresponding bottom region when the semiconductor layer is viewed in a plane.

4. 3. The semiconductor device according to claim 2, wherein each of the plurality of connecting regions arranged at the boundary portion extends so as to intersect with each of the plurality of bottom regions arranged below it when the semiconductor layer is viewed in a plane.

5. 5. The semiconductor device according to claim 4, wherein each of the plurality of connecting regions arranged at the boundary portion extends in a direction perpendicular to each of the plurality of bottom regions arranged thereunder when the semiconductor layer is viewed in a plane.

6. A semiconductor device according to any one of claims 1 to 5, wherein the width in the short side of the plurality of connecting regions that are arranged in the boundary portion among the plurality of connecting regions is 10 times or less the width in the short side of the plurality of connecting regions that are arranged in the cell portion among the plurality of connecting regions.

7. The semiconductor device according to claim 1 , wherein the semiconductor layer is made of silicon carbide.

8. a semiconductor layer (10) partitioned into a cell portion (10A), an outer peripheral portion (10C) arranged so as to surround the periphery of the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion and arranged so as to surround the periphery of the cell portion; A method for manufacturing a semiconductor device (1, 2, 3) comprising: forming a plurality of bottom regions (14, 15) of a second conductivity type and a plurality of guard ring regions (13) of the second conductivity type on an upper surface of a lower drift region (12) of the first conductivity type; forming an upper drift region (16) of a first conductivity type on the lower drift region and the plurality of bottom regions; a step of patterning a mask on the upper drift region and introducing second conductivity type impurities into the upper surface of the upper drift region through the mask to form a plurality of connecting regions (17); forming a body region (18) of a second conductivity type on the upper drift region and the plurality of tie regions; forming a source region (19) of a first conductivity type on the body region; the lower drift region is provided in the cell portion, the boundary portion, and the outer periphery portion, the plurality of bottom regions are provided in at least the cell portion and the boundary portion, are disposed at a position deeper than the trench gate, and are repeatedly disposed at intervals along an arbitrary direction, whereby the lower drift region is disposed at the intervals between the bottom regions; the upper drift region is provided in at least the cell portion and the boundary portion, the plurality of connecting regions are provided at least in the cell portion and the boundary portion, and are repeatedly arranged at intervals along an arbitrary direction, whereby the upper drift region is arranged at those intervals; the plurality of guard ring regions are provided in the outer periphery, and when the semiconductor layer is viewed in plan, are arranged so as to surround the cell portion and the boundary portion and are repeatedly arranged at intervals along an inner-outer direction, the plurality of trench gates are provided in the cell portion, and extend from the one main surface of the semiconductor layer across the source region and the body region to the upper drift region disposed between the plurality of connecting regions; the boundary portion is defined as a region from an outermost edge of the trench gate to the innermost guard ring region, A method for manufacturing a semiconductor device, wherein the plurality of connection regions include a plurality of connection regions arranged in the cell portion and a plurality of connection regions arranged in the boundary portion.

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