Memory device using semiconductor element

Abstract

To provide a device structure together with a memory cell for easily and reliably detecting whether the contents of a memory are in a written state or an erased state.SOLUTION: On a p-layer 1 on a substrate 20, an n-layer 3 is formed, with an n-layer 3b extending vertically as a part of it and a columnar p-layer 4 on the top of it, an insulating layer 2 covering the part of the n-layer 3, with a gate insulating layer 5 in contact with this, with a gate conductor layer 22 in contact with the gate insulating layer 5 and the insulating layer 2, with the insulating layer 6 in contact with this, and on the top of the p-layer 4, there is p-layer 8, with a gate insulating layer 9 on the top of that, and a memory cell consisting of the n+ layers 7a and 7b at both ends and gate conductor layer 10. All components of this memory cell except for the n-layer 3 are the same MOSFETs on the same chip, and the same voltage is applied when reading from the memory, and the memory contents are determined by whether the voltage is greater or less than the cell current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device using a semiconductor element. [Background technology]

[0002] In recent years, with the development of LSI (Large Scale Integration) technology, there has been a demand for memory devices that can incorporate logic circuits using semiconductor elements with higher integration, higher performance, lower power consumption, and higher functionality.

[0003] Dynamic Random Access Memory (DRAM) is widely used as memory for integrated circuits. To improve the density of DRAM memory, an SGT structure extending perpendicular to the upper surface of the semiconductor substrate has been used (see, for example, Patent Document 1 and Non-Patent Document 1). DRAMs (see, for example, Non-Patent Document 2) have also been developed. DRAM memory cells without a capacitor are also available (see, for example, Non-Patent Documents 3 to 6). These are commonly referred to as "1TDRAM." For example, a logical "1" is written by retaining some or all of the holes in the channel of an n-channel MOS transistor, which generates holes and electrons through impact ionization caused by a current between the source and drain of the transistor. Then, a logical "0" is written by removing the holes from the channel.

[0004] There is also a twin-transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in the SOI layer (see, for example, Patent Documents 2 and 3, and Non-Patent Document 7). Furthermore, there is a dynamic flash memory (DFM) in which one memory cell is composed of two gate electrodes without a capacitor (see Patent Document 4 and Non-Patent Document 8). In this memory cell, the carrier concentration in the floating body is changed by manipulating the voltages of the four electrodes, creating a conductive or non-conductive state to enable memory operation. A structure in which a body that stores carriers is connected to the bottom of the MOS transistor has also been proposed (see Patent Document 5). Memories using these floating bodies make it difficult and complex to design a circuit that derives the reference voltage and current to determine whether information has been written or erased in the memory cell. Furthermore, the circuit characteristics vary depending on expected changes in conditions (voltage and temperature), narrowing the margin for determination. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2-188966 [Patent Document 2] US2008 / 0137394 A1 [Patent Document 3] US2003 / 0111681 A1 [Patent Document 4] US2023 / 11776620 B2 [Patent Document 5] US 2023 / 0077140 A1 [Non-patent literature]

[0006] [Non-Patent Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991);

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[0007] SUMMARY OF THE INVENTION It is an object of the present invention to provide a device structure together with a memory cell for easily and reliably detecting whether the contents of the memory are in a written state or an erased state.

[0008] In order to solve the above problems, a memory device using a semiconductor element according to the present invention comprises: A substrate; a first semiconductor region on the substrate; a first impurity region on a surface of a portion of the first semiconductor region; a second semiconductor region extending vertically in a columnar shape in contact with the first impurity region; a first insulating layer covering a portion of the first impurity region; a first gate insulating layer covering and surrounding at least a portion of a side surface of the second semiconductor region disposed on the first impurity region; a first gate conductor layer on the first insulating layer and in contact with a side surface of the first gate insulating layer; a second insulating layer formed on the first gate conductor layer so as to contact the first gate insulating layer and arranged to insulate the second semiconductor region from the first gate conductor layer together with the first gate insulating layer; a third semiconductor region formed on the second semiconductor region; a second gate insulating layer formed on the third semiconductor region so as to cover a part or all of the third semiconductor region; a second gate conductor layer formed on the second gate insulating layer so as to cover a part or the whole of the second gate insulating layer; a memory cell including a second impurity region and a third impurity region connected to both ends of the third semiconductor region, respectively; a MOSFET formed on the substrate, the MOSFET having all the same components as those of the memory cell except for the first impurity region and having the same design dimensions as those of the memory cell in a plan view; During memory read, a voltage applied to a bit line connected to the third impurity region is applied to the drain of the MOSFET, and a voltage applied to the word line connected to the second gate conductor layer is applied to the gate of the MOSFET. The drain current that flows when the voltage is applied to the bit line connected to the third impurity region is applied to the drain of the MOSFET, and the gate of the MOSFET is applied to the word line connected to the second gate conductor layer. The memory is configured to determine whether it is in a written state or an erased state based on whether the drain current is larger or smaller than the read current of the memory cell. It is characterized by:

[0009] The memory device is The memory cell a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; a memory write operation is performed by controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer, and generating electron groups and hole groups in the third semiconductor region and the second semiconductor region by impact ionization or gate-induced drain leakage current caused by a current flowing between the second impurity region and the third impurity region; removing either the electron group or the hole group, which are minority carriers in the third semiconductor region and the second semiconductor region, from the generated electron group and hole group; and causing a part or all of the electron group or the hole group, which are majority carriers in the third semiconductor region and the second semiconductor region, to remain in the third semiconductor region and the second semiconductor region; voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer are controlled to extract either the group of electrons or the group of holes, which are majority carriers in the second semiconductor region or the third semiconductor region remaining in at least one of the first impurity region, the second impurity region, the third impurity region, and the third impurity region, by recombining them with majority carriers in the first impurity region, the second impurity region, the third impurity region, and the third impurity region, thereby performing a memory erase operation; It is desirable.

[0010] The memory device is the first wiring conductor layer connected to the second impurity region of the memory cell is a source line, the second wiring conductor layer connected to the third impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line; voltages are applied to the source line, bit line, plate line, word line, and control line, respectively, to perform the memory write operation and the memory erase operation; It is desirable.

[0011] The memory device is Preferably, the majority carriers of the first impurity region are different from the majority carriers of the first semiconductor region.

[0012] The memory device is It is desirable that the majority carriers in the second impurity region and the majority carriers in the first impurity region are the same, and that the majority carriers in the second impurity region and the majority carriers in the first semiconductor region are different.

[0013] The memory device is Preferably, the majority carriers in the second semiconductor region are the same as the majority carriers in the first semiconductor region.

[0014] The memory device is It is desirable that the majority carriers in the second impurity region and the third impurity region are the same as the majority carriers in the first impurity region.

[0015] The memory device is It is desirable that the vertical distance from the bottom of the third semiconductor region to the top of the second impurity region is shorter than the vertical distance from the bottom of the third semiconductor region to the bottom of the first gate conductor layer.

[0016] The memory device is It is desirable that the bottom of the first impurity region be located lower than the bottom of the first insulating layer in the vertical direction.

[0017] The memory device is In the vertical direction, it is desirable that the top surface of the first impurity region is located higher than the top surface of the first insulating layer.

[0018] The memory device is It is desirable to provide a MOSFET on the substrate, in which all components other than the first impurity region and the first gate conductor layer in the memory cell are the same and which has the same design dimensions as the memory cell in plan view. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are diagrams showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment and a cross-sectional structure of a MOSFET used to determine the contents of a memory cell. [Figure 2] 4A and 4B are diagrams for explaining the accumulation of hole carriers and the cell current during a write operation of the memory device using the semiconductor element according to the first embodiment. [Figure 3] 4A to 4C are diagrams illustrating an erase operation of the memory device using the semiconductor element according to the first embodiment. [Figure 4]10A and 10B are diagrams showing a method for determining whether a memory cell according to the first embodiment is written or erased using the proposed nMOSFET. [Figure 5] This is an example of a decision circuit in a memory. [Figure 6] 10 is a cross-sectional view of an additional example of an nMOSFET using the semiconductor element according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, the structure, driving method, behavior of stored carriers, and signal detection of a memory device using semiconductor elements according to an embodiment of the present invention will be described with reference to the drawings.

[0021] (First embodiment) Using Figures 1 to 6, we will explain the cell structure and operation of a memory using a semiconductor element according to this embodiment, and how to determine the state of a memory cell by comparing the drain current of an nMOSFET with an applied voltage under the same conditions as when reading the cell. Using Figure 1, we will explain the cell structure of a memory using a semiconductor element according to this embodiment and the structure of an nMOSFET used to determine whether the memory is in a written or erased state. Using Figure 2, we will explain the write mechanism and carrier behavior of a memory cell using a semiconductor element. Using Figure 3, we will explain the memory erase mechanism and carrier behavior. Using Figure 4, we will explain the relationship between the cell current and the current of the determination nMOSFET when writing and erasing the memory according to this embodiment. Using Figure 5, we will show an example of a circuit configuration for determining the cell contents of a memory according to this embodiment. Furthermore, using Figure 6, we will explain an application example of the determination nMOSFET structure according to this embodiment.

[0022] FIG. 1(a) shows a vertical cross-sectional structure of a memory using a semiconductor device according to an embodiment of the present invention. A p-layer 1 (an example of a "first semiconductor region" in the claims) of silicon containing acceptor impurities and having p-type conductivity is located on a substrate 20 (an example of a "substrate" in the claims). A semiconductor having an n-layer 3 (an example of a "first impurity region" in the claims) containing donor impurities is located in contact with the p-layer 1. A columnar p-layer 4 (an example of a "second semiconductor region" in the claims) containing acceptor impurities and having a rectangular horizontal cross section is located in contact with the n-layer 3. A first insulating layer 2 (an example of a "first insulating layer" in the claims) covers the p-layer 1, the n-layer 3, and a portion of the p-layer 4. A first gate insulating layer 5 (an example of a "first gate insulating layer" in the claims) is located on and in contact with the first insulating layer 2, covering the side surface of the columnar p-layer 4. Furthermore, a first gate conductor layer 22 (an example of the "first gate conductor layer" in the claims) is disposed on the first insulating layer 2 and contacts the side surface of the first gate insulating layer 5. As a result, the gate conductor layer 22 surrounds all or part of the periphery of the p-layer 4. There is a second insulating layer 6 (an example of the "second insulating layer" in the claims) that contacts the side surface of the upper part of the gate insulating layer 5 and is disposed on top of the gate conductor layer 22. There is a p-layer 8 (an example of the "third semiconductor region" in the claims) that contains acceptor impurities and is in contact with the p-layer 4.

[0023] An n+ layer 7a (an example of the "second impurity region" in the claims) containing donor impurities and an n+ layer 7b (an example of the "third impurity region" in the claims) are in contact with both ends of the horizontal p layer 8 and are electrically insulated from each other (hereinafter, the semiconductor region containing a high concentration of donor impurities will be referred to as the "n+ layer").

[0024] A second gate insulating layer 9 (an example of the "second gate insulating layer" in the claims) is located on the upper surface of the p-layer 8. This gate insulating layer 9 is in contact with or close to the n+ layers 7a and 7b, respectively. In the vertical direction, a second gate conductor layer 10 (an example of the "second gate conductor layer" in the claims) is located on this gate insulating layer 9.

[0025] In FIG. 1(a), the boundary between the n layer 3 and the p layer 4 is drawn so as to coincide with the top surface of the insulating layer 2. However, this boundary may be above or below the top surface of the first insulating layer 2. The top of the p layer 4 is covered by the first gate insulating layer 5, but it may be in contact with the second insulating layer 6 for ease of fabrication. The first insulating layer 2, gate insulating layer 5, and second insulating layer 6 may be arranged so as to insulate the n layer 3 and p layer 4 from the first gate conductor layer 22. For example, the gate insulating layer 5 may cover the entire p layer 4 except for its upper side surface (at least partially covering the side surface of the p layer 4), and instead of the gate insulating layer 5 covering the upper side surface of the p layer 4, the second insulating layer 6 may directly cover the side surface of the p layer 4. Alternatively, the gate insulating layer 5 may be arranged directly on the n layer 3, directly covering the n layer 3. In this case, the second insulating layer 6, together with the gate insulating layer 5, insulates the upper side surface of the p-layer 4 from the first gate conductor layer 22. Also, the first insulating layer 2, together with the gate insulating layer 5, insulates the lower side surfaces of the n-layer 3 and p-layer 4 from the first gate conductor layer 22.

[0026] This forms a memory device using a semiconductor element consisting of substrate 20, p layer 1, insulating layer 2, first gate insulating layer 5, first gate conductor layer 22, second insulating layer 6, n layer 3, p layer 4, n+ layer 7a, n+ layer 7b, p layer 8, second gate insulating layer 9, and second gate conductor layer 10. Then, n+ layer 7a is connected to a source line SL (an example of a "source line" in the claims) which is a first wiring conductive layer, n+ layer 7b is connected to a bit line BL (an example of a "bit line" in the claims) which is a second wiring conductive layer, gate conductor layer 10 is connected to a word line WL (an example of a "word line" in the claims) which is a third wiring conductive layer, gate conductor layer 22 is connected to a plate line PL (an example of a "plate line" in the claims) which is a fourth wiring conductive layer, and n layer 3 is connected to a control line CDC (an example of a "control line" in the claims) which is a fifth wiring conductive layer. The memory operates by controlling the voltages applied to the source line SL, bit line BL, plate line PL, word line WL, and control line CDC. This memory device will be referred to as KFBM ( K eye shapeF Loating B ody M It is called emory.

[0027] FIG. 1(b) shows a cross-sectional view of an nMOSFET used for memory cell determination according to this embodiment. When the numerals in the symbols indicating the components of the nMOSFET are the same as those in the memory cell components shown in FIG. 1(a), they indicate that they are formed from the same layers. Furthermore, the same numerals indicate that the film thickness, impurity concentration, profile, planar dimensions, vertical dimensions, etc. are the same as the design dimensions of the memory. However, the only difference between the memory and the nMOSFET is that the n-layer 3 of the memory cell does not exist in the nMOSFET. As will be described later, the characteristics of this nMOSFET are used to determine whether the memory cell is written or erased.

[0028] In the actual memory device of this embodiment, one or more KFBM memory cells of Figure 1(a) are arranged two-dimensionally on a substrate 20, and Figure 1(b) is arranged around the memory cell and is used to determine the contents of the memory.

[0029] In FIG. 1, p layer 1 is a p-type semiconductor, but the impurity concentration may have a profile. The impurity concentrations of n layer 3, p layer 4, and p layer 8 may also have profiles. The p layer 4 and p layer 8 may have independent impurity concentrations and profiles. The p layer 4 and p layer 8 may be formed of different semiconductor material layers. In plan view, the cross section of p layer 4 may have the same shape at the connection surface between p layer 4 and p layer 8. Alternatively, the horizontal length of p layer 8 in the direction connecting to n+ layers 7a and 7b may be longer or shorter than the width of p layer 4. A lightly doped drain (LDD) region having a donor concentration lower than the donor impurity concentration of n+ layers 7a and 7b may be provided between p layer 8 and n+ layers 7a and 7b.

[0030] 1, the insulating layer 2 and the gate insulating layer 5 are shown separately, but they may be formed as one piece. Hereinafter, the insulating layer 2 and the gate insulating layer 5 will also be referred to as the gate insulating layer 5 collectively.

[0031] In addition, although the p-layer 8 is a p-type semiconductor in FIG. 1, the p-layer 8 may be any of p-type, n-type, or i-type depending on the majority carrier concentration of the p-layer 4, the thickness of the p-layer 8, the material and thickness of the gate insulating layer 9, and the material of the gate conductor layer 10.

[0032] Furthermore, the substrate 20 may be made of any material, whether it is an insulator, a semiconductor, or a conductor, as long as it can support the p-layer 1 .

[0033] Furthermore, the first to fifth wiring conductive layers may be formed in multiple layers as long as they do not contact each other.

[0034] Furthermore, the gate insulating layers 5 and 9 may be made of any insulating film used in a normal MOS process, such as an SiO2 film, a SiON film, an HfSiON film, or a stacked film of SiO2 / SiN.

[0035] Furthermore, as long as the first gate conductor layer 22 can change the potential of part of the memory cell via the gate insulating layer 5, and the second gate conductor layer 10 can change the potential of part of the memory cell via the gate insulating layer 9, they may be made of metals such as W, Pd, Ru, Al, TiN, TaN, and WN, metal nitrides, or alloys thereof (including silicides), such as a stacked structure such as TiN / W / TaN, or may be made of a highly doped semiconductor.

[0036] In addition, in FIG. 1, the memory cell and nMOSFET are described as having a rectangular vertical cross-sectional structure of the P layer 4 and p layer 8 relative to the paper surface, but they may be trapezoidal or polygonal, and the cross section of the p layer 4 may be circular or elliptical in plan view.

[0037] Furthermore, the MOSFET consisting of n+ layers 7a, 7b, p layer 8, gate insulating layer 9, and gate conductor layer 10 may be a planar type or a fin type FET. In the planar type, the second gate insulating layer 9 is formed on the upper surface of the p layer 8, and the second gate conductor layer 10 is formed on that gate insulating layer. In the fin type, the second gate insulating layer 9 is formed on the upper surface and both side surfaces of the p layer 8, and the second gate conductor layer 10 is formed to cover that gate insulating layer. In addition, the FET may be one in which the shape of the p layer 8, which is the channel, is U-shaped.

[0038] Furthermore, the thicknesses of insulating layer 2 and insulating layer 6 and gate insulating layer 5 can be formed simultaneously or from the same material. Furthermore, by adjusting the thicknesses of gate insulating layer 5 and insulating films 2 and 6, respectively, the voltage applied to gate conductor layer 22 can also be adjusted.

[0039] 1(a), the first gate conductor layer 22 may surround the entire p-layer 22 or may cover only a portion of it in plan view. The first gate conductor layer 22 may be divided into multiple pieces in plan view. The first gate conductor layer 22 may also be divided into multiple pieces in the vertical direction. Also, in the cross-sectional structure of FIG. 1, the first gate conductor layers 22 are present on both sides of the p-layer 4, but the presence of the first gate conductor layers 22 on either side of the p-layer 4 also enables KFBM operation.

[0040] Referring to Figure 2, we will explain the carrier behavior, accumulation, and cell current during a write operation (an example of the "write operation" in the claims) of the KFBM shown in Figure 1(a) according to the first embodiment of the present invention. First, we will explain the case where the majority carriers in n layer 3, n layer 7a, and n layer 7b are electrons, and where, for example, polysilicon containing a high concentration of donor impurities (hereinafter, polysilicon containing a high concentration of donor impurities will be referred to as "n+poly") is used for gate conductor layer 22 connected to plate line PL and gate conductor layer 10 connected to WL, and a p-type semiconductor is used for third semiconductor region 8. As shown in Figure 2(a), the MOSFET in this memory cell operates using n+ layer 7a as the source, n+ layer 7b as the drain, gate insulating layer 9, gate conductor layer 10 as the gate, and p layer 8 as the substrate. For example, 0V is applied to the p-layer 1, 0.5V is applied to the n-layer 3 connected to the control line (CDC), 0V is input to the n+ layer 7a connected to the source line SL, 1.2V is input to the n+ layer 7b connected to the bit line BL, and -1V is applied to the gate conductor layer 22 connected to the plate line PL. Here, the threshold voltage of the MOSFET using the gate conductor layer 10 as the gate electrode before writing is set to 1.0V when the voltage of the plate line PL is -1V. Next, if 1.5V is input to the gate conductor layer 10 connected to the word line WL, a partial inversion layer 12 is formed directly below the gate insulating layer 9 below the gate conductor layer 10, and a pinch-off point 13 is present. Therefore, the MOSFET having the gate conductor layer 10 operates in the saturation region.

[0041] As a result, the electric field becomes maximum between the pinch-off point 13 and the boundary region of the n+ layer 7b in the MOSFET having the gate conductor layer 10, and impact ionization occurs in this region. Due to this impact ionization, electrons accelerated from the n layer 7a connected to the source line SL toward the n+ layer 7b connected to the bit line BL collide with the Si lattice, and their kinetic energy generates electron-hole pairs. Due to their concentration gradient, the generated holes diffuse toward the area with lower hole concentration. Furthermore, some of the generated electrons flow into the gate conductor layer 10, but the majority flow into the n+ layer 7b connected to the bit line BL. As a result, holes 11 accumulate in the p layer 4 and the p layer 8.

[0042] In the above example, the plate line PL is set to -1 V, which prevents the depletion layer from expanding into the p-layer and contributes to the accumulation of holes generated by impact ionization.

[0043] In the above example, n+poly is used for the gate conductor layer 22 and a negative voltage is biased, but the same effect as applying a negative voltage can be achieved by using a material with a higher work function than the material for the gate conductor layer 10.

[0044] Instead of causing the impact ionization phenomenon, a gate-induced drain leakage (GIDL) current may be passed to generate a group of holes (see, for example, Non-Patent Document 7).

[0045] Figure 2(b) shows the hole clusters 11 in the p-layer 4 and p-layer 8 immediately after programming when the plate line PL is at -1V, the word line WL, source line SL, and bit line BL are biased at 0V, and the control line CDC is biased at 0.5V. The generated hole clusters 11 are majority carriers in the p-layer 4 and p-layer 8. However, the generated holes temporarily become highly concentrated in the p-layer 8 and then diffuse toward the p-layer 4 due to the concentration gradient. Furthermore, by applying a negative potential to the first gate conductor layer 22, the p-layer 4 accumulates at a higher concentration near the first gate insulating layer 5. Because the p-layer 4 and p-layer 8 are electrically connected, the p-layer 8, which is essentially the substrate of the MOSFET with the gate conductor layer 10, is positively biased. The threshold voltage of the MOSFET with the gate conductor layer 10 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p-layer 4 and p-layer 8. In this example, the threshold voltage of the MOSFET after programming is 0.6V. As a result, as shown in Figure 2(c), the threshold voltage of the MOSFET having the gate conductor layer 10 connected to the word line WL becomes approximately 0.3 V, which is lower than before writing. This write state is assigned to logical storage data "1." This is the so-called "write" state.

[0046] According to the structure of this embodiment, the p-layer 8 of the MOSFET having the gate conductor layer 10 connected to the word line WL is electrically connected to the p-layer 4, so that the capacity for storing generated holes can be freely changed by the volume of the p-layer 4.

[0047] In addition to the above examples, if the voltages applied to the bit line BL, plate line PL, and word line WL are abbreviated as V-BL, V-PL, and V-PL, respectively, the voltage application conditions can be 1.0V (V-BL) / -1V (V-PL) / 2.0V (V-WL), 1.0V (V-BL) / -0.5V (V-PL) / 1.2V (V-WL), or 1.5V (V-BL) / -1V (V-PL) / 2.0V (V-WL), with SL set to 0V. The voltage relationships between the bit line BL and source line SL may also be reversed. However, if 1.0V is applied to the bit line BL, 0V to the source line SL, 2V to the word line WL, and -1V to the plate line PL, the threshold voltage will decrease during programming, gradually shifting the pinch-off point 13 toward the n layer 7b, and the MOSFET may operate linearly.

[0048] Next, the mechanism of the erase operation (an example of the "erase operation" in the claims) will be explained using Figure 3. Figure 3(a) shows the state immediately after the hole group 11 generated by impact ionization in the previous cycle is stored in the p-layer 4 and p-layer 8 before the erase operation. The voltages of the source line SL, bit line BL, and control line CDC are 0.5V, and the voltage of the plate line PL of the word line WL is -1V.

[0049] As shown in Figure 3(b), during an erase operation, the source line SL, bit line BL, and word line WL are set to 0V, and the control line CDC is set to 0.5V. The voltage of the plate line PL is set to, for example, 2V. As a result, an electron inversion layer 14 is formed at the interface between the insulating film 5 and the p-layer 4, regardless of the initial potential of the p-layer 8. A portion of this inversion layer 14 contacts the n-layer 3. As a result, holes accumulated in the p-layer 4 flow from the p-layer 4 to the inversion layer 14 and recombine with electrons. Electrons lost due to recombination are replenished through the n-layer 3 from the inversion layer 14. Although Figure 3(b) shows the inversion layer 14 divided into left and right sections, these are formed around the p-layer 4, so they are electrically connected. Therefore, reducing the contact area between the p-layer 4 and the n-layer 3b has no effect. As a result of this hole-electron recombination, the hole concentration in the p-layer 4 and the p-layer 8 decreases over time, and the threshold voltage of the MOSFET becomes higher than when a "1" was written. For example, if the plate line PL voltage is -1V, the threshold voltage of the MOSFET becomes 1.2V. As a result, as shown in FIG. 3(c), the MOSFET having the gate conductor layer 10 connected to this word line WL returns to its original threshold voltage. The erased state of this KFBM becomes logical memory data "0." This is the so-called "erased" state.

[0050] According to the structure of this embodiment, the recombination area of ​​electrons and holes can be effectively increased during data erasure compared to during data storage. Therefore, a stable state of logical information data "0" can be achieved in a short time, improving the operating speed of this KFBM. Furthermore, the power consumption during data erasure is approximately equal to the total number of holes stored in the p-layer 4 and p-layer 8, and no other current flows, resulting in a significant reduction in power consumption.

[0051] In addition, as a method of erasing data other than the examples given, if the voltages applied to the above-mentioned bit line BL, plate line PL, and word line WL are abbreviated as V-BL, V-PL, and V-WL, respectively, the voltage application conditions can be combinations such as 0V for the source line SL and 0.5V for the control line CDC, such as 0V(V-BL) / 2V(W-PL) / -1V(V-WL), 0.4V(V-BL) / 2V(V-PL) / 0.5V(V-WL), or 1V(V-BL) / 1.5V(V-PL) / 0V(V-WL).The voltage conditions applied to the above-mentioned bit line BL, source line SL, word line WL, and plate line PL are examples for performing a memory erase operation, and other operating conditions for performing a memory erase operation may also be used.

[0052] In addition, although the control line CDC has been described as being 0.5V in both cases of writing and erasing memory, the control line CDC can also be set to the ground voltage, i.e., 0V.

[0053] Next, we will use Figure 4 to explain the relationship between the cell current during write and erase and the drain current of the nMOSFET used for determination. This figure shows the relationship between the WL voltage and cell current when reading a cell after writing "1" as shown in Figure 2(c), and the relationship between the WL voltage and cell current in the erased state of "0" as shown in Figure 3(c). Figure 4 also shows the relationship between the drain current and gate voltage VG when applying the same drain voltage VD as the bit line voltage during cell read of the nMOSFET shown in Figure 1(b).

[0054] As can be seen from Figure 4, if the same voltages as when reading a memory cell are applied to the nMOSFET, that is, if the same voltage V-BL as when reading is applied to the drain voltage VD and the same voltage V-WL is applied to the gate voltage VG, the drain current ID flowing through the nMOSFET will always be between the cell read currents for "1" and "0." Therefore, by comparing the current flowing through an nMOSFET with the cross-sectional structure of Figure 1(b) with the cell current, it is possible to determine whether the memory cell is in a "1" written state or an erased "0" state.

[0055] According to this embodiment, even if the temperature during memory cell operation changes or the read voltage applied to the memory cell changes, the memory cell current and the nMOSFET drain current move in a linked manner, either rising or falling, so their relationship remains constant. Furthermore, even if the gate oxide film thickness, impurity concentration, etc., change or become distributed during manufacturing, the cell current and the nMOSFET drain current also change in a linked manner, so this relationship remains unchanged. Therefore, even with variations in the operating environment and all variations related to manufacturing, these relationships remain unchanged, allowing the contents of the memory cell to be determined with a wide margin.

[0056] Next, using Figure 5, we will show an example of how to determine the state of a memory cell in an actual circuit. Let Icell be the cell current that flows when the memory cell read voltage, bit line voltage V-BL, and word line voltage V-WL are applied. At this time, the drain voltage VD of the nMOSFET is given the same voltage as V-BL, and the gate voltage VG is given the same voltage as V-WL, and the current that flows is called ID. A comparison circuit between Icell and ID is used to determine which current is larger; if Icell is larger than ID, it is determined that the program state is "1," and if it is smaller, it is determined that the erase state is "0." The current comparison circuit can be a general circuit used worldwide. Of course, it is also possible to convert the current to a voltage and determine whether it is larger or smaller.

[0057] This comparison circuit is placed in the peripheral circuitry of the memory cell, but does not require complex circuitry, so the decision circuit can be designed in a small area, contributing to higher memory density.

[0058] Next, an example of adding an nMOSFET to FIG. 1(b) will be explained using FIG. 6. In FIG. 6, components that are the same as or similar to those in FIG. 1 are given the same reference numerals. As shown in FIG. 6(a), the gate conductor layer 22 in FIG. 1(b) is present on only one side. Also, in FIG. 6(b), the gate conductor layer 22 does not exist, and instead is replaced by an insulating layer 6. The rest is the same as FIG. 1. Even with such an nMOSFET, the memory cell can be determined to be "1" or "0" in the same way. Even with this structure, the relationship with the cell current shown in FIG. 4 is maintained.

[0059] 1, the device structure consisting of p layer 8, n+ layers 7a and 7b, gate insulating layer 9, and gate conductor layer 10 can be formed in common not only with this memory cell but also with other MOS circuits, including general CMOS structures. For example, p layer 1, p layer 4, and p layer 8 can be shared as part of the CMOS structure. Therefore, this memory cell can be easily combined with conventional CMOS circuits.

[0060] In addition, in FIG. 1, the first semiconductor region 1 is a p-type semiconductor, but if an n-type semiconductor substrate is used for the substrate 20, a p-well is formed, and this is used as the first semiconductor region 1, and the memory cell of the present invention is arranged, the KFBM will still operate.

[0061] Furthermore, since the memory cell of the present invention is formed in the area of ​​one MOSFET in plan view, by sharing the source line and bit line with adjacent memory cells, a higher density memory cell array than conventional dynamic RAM can be realized.

[0062] Furthermore, when n+ layer 7a and n+ layer 7b are formed of p+ layers in which holes are the majority carrier (hereinafter, a semiconductor region containing a high concentration of acceptor impurities will be referred to as a "p+ layer"), if p-layers 1, 4, and 8 are made of n-type semiconductors and n-layer 3 is made of a p-type semiconductor, KFBM operation will be performed, with electrons as the write carriers.

[0063] Furthermore, in this embodiment, an example has been described in which the p-layers 4 and 8 are formed perpendicular to the substrate 20, but the present invention can also be applied to a case in which the p-layers 4 and 8 are formed horizontally to the substrate 20.

[0064] This embodiment has the following features. (Feature 1) The KFBM according to the first embodiment of the present invention is composed of gate conductor layers 10 and 22, insulating layer 2, gate insulating layer 5, n layer 3, and p layer 4 and p layer 8 surrounded by n layers 7a and 7b. By changing the applied voltage, it is possible to change the write and erase states by storing or removing holes in p layer 4 and p layer 8. Then, by using an nMOSFET with the same structure as the memory cell and comparing its drain current with the cell current, it is possible to determine whether the memory cell is in a written state or an erased state.

[0065] (Feature 2) By comparing the drain current of the nMOSFET according to the first embodiment of the present invention with the cell current during read of the KFBM, it is possible to make a judgment that is not affected by environmental changes such as operating voltage and temperature. Furthermore, the judgment is not affected by fluctuations in the memory cell dimensions of the KFBM, impurity concentration, film thickness, etc. In other words, according to the present invention, it is possible to design a wide operating voltage margin for the KFBM.

[0066] (Feature 3) The memory cell according to the first embodiment of the present invention and the nMOSFET for determination are fabricated at the same time, and do not require any additional process. (Feature 4) The KFBM according to the first embodiment of the present invention can provide a high density memory cell array and a CMOS compatible structure. [Industrial Applicability]

[0067] By using the semiconductor element according to the present invention, it is possible to provide a semiconductor memory device that is denser, faster, and has a higher operating margin than conventional devices. [Explanation of symbols]

[0068] 1. First semiconductor region 2, 2f First insulating layer 3 First impurity layer 4, 4f Second semiconductor region 5, 5f First gate insulating layer 6, 6f Second insulating layer 7a, 7c, 7f, 7g n+ layer 8, 8f Third semiconductor region 9, 9f Second gate insulating layer 10, 10f Second gate conductor layer 11 hole group 12 Inversion layer 13 Pinch-off point 14 Inversion Layer 20 PCB 22, 22f First gate conductor layer SL Source Line PL plate line WL Word Line BL bit line CDC control line

Claims

1. A substrate; a first semiconductor region on the substrate; a first impurity region located on a surface of a portion of the first semiconductor region; a second semiconductor region extending in a columnar shape in a vertical direction in contact with the first impurity region; a first insulating layer covering a portion of the first impurity region; a first gate insulating layer covering and surrounding at least a portion of a side surface of the second semiconductor region disposed on the first impurity region; a first gate conductor layer on the first insulating layer and in contact with a side surface of the first gate insulating layer; a second insulating layer formed on the first gate conductor layer so as to contact the first gate insulating layer and to insulate the second semiconductor region from the first gate conductor layer together with the first gate insulating layer; a third semiconductor region formed on the second semiconductor region; a second gate insulating layer formed on the third semiconductor region so as to cover a part or all of the third semiconductor region; a second gate conductor layer formed on the second gate insulating layer so as to cover a part or the whole of the second gate insulating layer; a memory cell including a second impurity region and a third impurity region connected to both ends of the third semiconductor region, respectively; a MOSFET formed on the substrate, the MOSFET having all the same components as those of the memory cell except for the first impurity region and having the same design dimensions as those of the memory cell in a plan view; During memory read, a voltage applied to a bit line connected to the third impurity region is applied to the drain of the MOSFET, and a voltage applied to the word line connected to the second gate conductor layer is applied to the gate of the MOSFET. The drain current that flows when the voltage is applied to the bit line connected to the third impurity region is applied to the drain of the MOSFET, and the drain current that flows when the voltage is applied to the word line connected to the second gate conductor layer is applied to the gate of the MOSFET is determined to be larger or smaller than the read current of the memory cell, thereby determining whether the memory is in a written state or an erased state. A memory device using a semiconductor element characterized by:

2. The memory cell a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; a memory write operation is performed by controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer, and generating electron groups and hole groups in the third semiconductor region and the second semiconductor region by impact ionization or gate induced drain leakage current caused by a current flowing between the second impurity region and the third impurity region; removing either the electron group or the hole group, which are minority carriers in the third semiconductor region and the second semiconductor region, from the generated electron group and hole group; and causing a part or all of the electron group or the hole group, which are majority carriers in the third semiconductor region and the second semiconductor region, to remain in the third semiconductor region and the second semiconductor region; voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer are controlled to extract either the group of electrons or the group of holes, which are majority carriers in the second semiconductor region or the third semiconductor region remaining in at least one of the first impurity region, the second impurity region, and the third impurity region, by recombining them with majority carriers in the first impurity region, the second impurity region, and the third impurity region, thereby performing a memory erase operation; 2. A memory device using the semiconductor element according to claim 1.

3. the first wiring conductor layer connected to the second impurity region of the memory cell is a source line, the second wiring conductor layer connected to the third impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line; voltages are applied to the source line, bit line, plate line, word line, and control line, respectively, to perform the memory write operation and the memory erase operation; 3. A memory device using the semiconductor element according to claim 2.

4. 2. The memory device according to claim 1, wherein majority carriers in said first impurity region are different from majority carriers in said first semiconductor region.

5. 2. The memory device using a semiconductor element according to claim 1, wherein majority carriers in the second impurity region and majority carriers in the first impurity region are the same, and majority carriers in the second impurity region and majority carriers in the first semiconductor region are different.

6. 2. The memory device according to claim 1, wherein majority carriers in said second semiconductor region are the same as majority carriers in said first semiconductor region.

7. 2. The memory device according to claim 1, wherein majority carriers in the second impurity region and the third impurity region are the same as majority carriers in the first impurity region.

8. 2. A memory device using a semiconductor element according to claim 1, wherein the vertical distance from the bottom of the third semiconductor region to the top of the second impurity region is shorter than the vertical distance from the bottom of the third semiconductor region to the bottom of the first gate conductor layer.

9. 2. The memory device using a semiconductor element according to claim 1, wherein the bottom of said first impurity region is located lower than the bottom of said first insulating layer in the vertical direction.

10. 2. The memory device using a semiconductor element according to claim 1, wherein the upper surface of said first impurity region is located higher than the upper surface of said first insulating layer in the vertical direction.

11. a MOSFET having the same design dimensions as the memory cell in plan view, and having all the same components except for the first impurity region and the first gate conductor layer in the memory cell, on the substrate; 2. A memory device using the semiconductor element according to claim 1.

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