Semiconductor device

Abstract

To provide a semiconductor device that can easily store an operation history in a nonvolatile manner and that can confirm the stored operation history without opening the package.SOLUTION: The semiconductor device according to the embodiment includes an electronic circuit including a voltage regulator circuit that outputs a DC output voltage, a memory circuit including N (N is an integer equal to or greater than 2) electronic fuses, a soft start circuit that controls the voltage regulator circuit to change the DC output voltage from a first voltage value to a second voltage value over time during a start period in which generation of the DC output voltage begins, and a waveform control circuit that changes the waveform of the DC output voltage during the start period depending on the position or number of blown electronic fuses among the N electronic fuses.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Systems are known that store the number of times an abnormality has occurred in a device or the number of times the device has operated (for example, Patent Document 1). Such systems can analyze the cause of a failure based on the stored number of times. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2-213395 Summary of the Invention [Problem to be solved by the invention]

[0004] In addition, in such a system, by blowing one of the multiple electronic fuses formed in the semiconductor device every time an abnormality occurs or operation is started, the operation history can be easily stored in a non-volatile manner. However, whether or not the electronic fuse has blown is usually detected by opening the semiconductor device and analyzing it using an electron microscope or various analytical devices. Therefore, if the operation history is stored in the electronic fuse, etc., it is not easy for a user to check the operation history when the semiconductor device is mounted in an appliance, etc.

[0005] The present invention has been made in view of the above, and provides a semiconductor device that stores an operation history easily and non-volatilely and allows the stored operation history to be checked without opening the package. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, the semiconductor device of the present invention comprises an electronic circuit including a voltage regulator circuit that outputs a DC output voltage, a memory circuit including N (N is an integer of 2 or more) electronic fuses, a soft start circuit that controls the voltage regulator circuit to change the DC output voltage from a first voltage value to a second voltage value over time during a start period in which generation of the DC output voltage begins, and a waveform control circuit that changes the waveform of the DC output voltage during the start period depending on the position or number of blown electronic fuses among the N electronic fuses. [Effects of the Invention]

[0007] According to the present invention, the operation history can be stored easily and non-volatilely, and the stored operation history can be checked without opening the package. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of the output control circuit according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of the counter and the waveform control circuit. [Figure 4] FIG. 4 is a diagram showing the waveform of the DC output voltage during the start period when none of the N electronic fuses has been blown. [Figure 5] FIG. 5 is a diagram showing the waveform of the DC output voltage in the start period when the xth electronic fuse or x electronic fuses are blown. [Figure 6] FIG. 6 is a diagram showing the waveform of the DC output voltage in the start period when the yth electronic fuse or y electronic fuses are blown. [Figure 7] FIG. 7 is a diagram showing the configuration of an output control circuit according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing the waveform of the DC output voltage in the start period according to the second embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of a semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of a semiconductor device according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram showing the configuration of a memory circuit according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing the order of operations of the memory circuit according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram showing the configuration of the disconnection control circuit together with the memory circuit. [Figure 14] FIG. 14 is a diagram showing the sequence of operations of the disconnection control circuit. [Figure 15] FIG. 15 is a diagram showing the configuration of the status readout circuit together with the circuit configuration of the storage device. DETAILED DESCRIPTION OF THE INVENTION

[0009] (First embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device 10 according to the first embodiment.

[0010] The semiconductor device 10 according to the first embodiment includes an electronic circuit 20, a detection circuit 22, a memory circuit 24, and a disconnection control circuit 26. The electronic circuit 20, the detection circuit 22, the memory circuit 24, and the disconnection control circuit 26 are circuits formed on a semiconductor substrate. The voltage regulator circuit 30 also includes a voltage input terminal 12 and a voltage output terminal 14 as connection terminals for connecting to an external circuit.

[0011] The electronic circuit 20 includes a voltage regulator circuit 30. The voltage regulator circuit 30 receives a DC input voltage Vin from an external DC power supply via a voltage input terminal 12. The voltage regulator circuit 30 generates a stabilized DC output voltage Vout based on the DC input voltage Vin received via the voltage input terminal 12. The voltage regulator circuit 30 supplies the generated DC output voltage Vout to an external load via a voltage output terminal 14. Note that the electronic circuit 20 may be the voltage regulator circuit 30 itself, or may include any other circuit in addition to the voltage regulator circuit 30.

[0012] The detection circuit 22 detects the occurrence of a predetermined abnormality or a predetermined event in the electronic circuit 20. The detection circuit 22 detects, as the predetermined abnormality, for example, heat generation above a predetermined temperature, the flow of a current above a predetermined value, or the application of a voltage above a predetermined value. The detection circuit 22 also detects, as the predetermined event, for example, the activation of the voltage regulator circuit 30 or the performance of a predetermined operation by the electronic circuit 20. When the predetermined abnormality or a predetermined event occurs in the electronic circuit 20, the detection circuit 22 provides an instruction signal to the disconnection control circuit 26.

[0013] The memory circuit 24 includes N electronic fuses 40-1 to 40-N, where N is an integer equal to or greater than 2. The memory circuit 24 includes the N electronic fuses 40, namely, a first electronic fuse 40-1 to an N-th electronic fuse 40-N.

[0014] Each of the N electronic fuses 40-1 to 40-N is a fuse manufactured on a semiconductor substrate by a semiconductor process. Each of the N electronic fuses 40-1 to 40-N is a two-terminal element that melts when a current that flows therethrough is equal to or greater than a threshold. That is, each of the N electronic fuses 40-1 to 40-N is an element in which the resistance between the two terminals is approximately zero when the current that flows is less than the threshold, and electrically disconnects the two terminals after the current that flows reaches or exceeds the threshold. Note that each of the N electronic fuses 40-1 to 40-N may be configured to melt when a current equal to or greater than the threshold continues to flow for a predetermined period of time. That is, each of the N electronic fuses 40-1 to 40-N may be configured not to melt even if the current that flows therethrough instantaneously exceeds the threshold.

[0015] The cutoff control circuit 26 receives an instruction signal from the detection circuit 22. When the cutoff control circuit 26 receives the instruction signal, it passes a current equal to or greater than a threshold through any one of the N electronic fuses 40-1 to 40-N included in the memory circuit 24 to blow it.

[0016] For example, the disconnection control circuit 26 sequentially blows the N electronic fuses 40-1 to 40-N from the top each time it receives an instruction signal from the detection circuit 22. In this case, if the disconnection control circuit 26 receives an instruction signal when none of the N electronic fuses 40-1 to 40-N have been blown, it blows the first electronic fuse 40-1. Furthermore, if the disconnection control circuit 26 receives an instruction signal when the n-th electronic fuse 40-n (n is an integer between 2 and N) among the N electronic fuses 40-1 to 40-N has not been blown and all of the first to (n-1)-th electronic fuses 40-1 to 40-(n-1) among the N electronic fuses 40-1 to 40-N have been blown, it blows the n-th electronic fuse 40-n.

[0017] Each of the N electronic fuses 40-1 to 40-N may be previously associated with a specific type of abnormality or event. For example, each of the N electronic fuses 40-1 to 40-N may be associated with an abnormality such as heat generation above a predetermined temperature, current flow above a predetermined value, or voltage application above a predetermined value. Each of the N electronic fuses 40-1 to 40-N may be associated with, for example, activation of the voltage regulator circuit 30 or a predetermined operation of the electronic circuit 20. In this case, the cutoff control circuit 26 receives an instruction signal indicating the type of abnormality or event from the detection circuit 22. Upon receiving the instruction signal, the cutoff control circuit 26 blows one or more of the N electronic fuses 40-1 to 40-N that correspond to the type of abnormality or event indicated in the received instruction signal.

[0018] The output control circuit 28 detects the position of the blown electronic fuse 40 among the N electronic fuses 40-1 to 40-N, or the number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N.

[0019] Furthermore, during a start period in which the voltage regulator circuit 30 starts generating the DC output voltage Vout, the output control circuit 28 controls the voltage regulator circuit 30 to change the DC output voltage Vout from a first voltage value to a second voltage value over time. That is, during the start period in which the generation of the DC output voltage Vout starts, the output control circuit 28 does not suddenly increase the DC output voltage Vout in a short period of time, but rather increases the DC output voltage Vout over a long period of time. That is, the output control circuit 28 soft-starts the voltage regulator circuit 30 when the DC output voltage Vout is generated.

[0020] Furthermore, the output control circuit 28 changes the waveform of the DC output voltage Vout in the start period according to the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N included in the memory circuit 24. In this case, the waveform of the DC output voltage Vout in the start period is predetermined according to the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N.

[0021] For example, the output control circuit 28 generates, in the waveform of the DC output voltage Vout, a first waveform that is different from the normal waveform when none of the N electronic fuses 40-1 to 40-N is a blown electronic fuse 40, at a timing during the start period that corresponds to the positions or number of the blown electronic fuses 40. In this case, the timing at which the first waveform is generated during the start period is determined in advance in accordance with the positions or number of the blown electronic fuses 40.

[0022] Furthermore, for example, the output control circuit 28 may change the delay amount of the start timing of the start period depending on the positions or number of blown electronic fuses 40. In this case, the delay amount of the start timing of the start period is determined in advance in accordance with the positions or number of blown electronic fuses 40.

[0023] FIG. 2 is a diagram showing the configuration of the output control circuit 28 according to the first embodiment, together with the voltage regulator circuit 30 and the memory circuit 24.

[0024] The voltage regulator circuit 30 includes, for example, a reference voltage source 42 , an operational amplifier 44 , an npn transistor 46 , a pnp transistor 48 , and a first feedback resistor 50 .

[0025] The reference voltage source 42 generates a reference voltage Vr, which is a DC voltage lower than the DC input voltage Vin. The operational amplifier 44 has the reference voltage Vr applied to its non-inverting input terminal and the feedback voltage Vf generated at the internal node 16 applied to its inverting input terminal.

[0026] The base of the npn transistor 46 is connected to the output terminal of the operational amplifier 44. The emitter of the npn transistor 46 is connected to the ground terminal.

[0027] The emitter of the pnp transistor 48 is connected to the voltage input terminal 12. The collector of the pnp transistor 48 is connected to the voltage output terminal 14. The base of the pnp transistor 48 is connected to the collector of the npn transistor 46.

[0028] The first feedback resistor 50 is connected between the voltage output terminal 14 and the internal node 16. The first feedback resistor 50 has a resistance value of Rf1, for example.

[0029] The internal node 16 is connected to a variable feedback resistor realized by the output control circuit 28. The variable feedback resistor realized by the output control circuit 28 is connected between the internal node 16 and a ground terminal.

[0030] The voltage regulator circuit 30 configured as described above adjusts the amount of power output from the voltage output terminal 14 so that the feedback voltage Vf generated at the internal node 16 matches the reference voltage Vr. This allows the voltage regulator circuit 30 to output a stabilized DC output voltage Vout even if the load connected to the voltage output terminal 14 fluctuates.

[0031] The feedback voltage Vf is determined by the ratio between the reference voltage Vr, Rf1, which is the resistance value of the first feedback resistor 50, and Rf2, which is the resistance value of the variable feedback resistor realized by the output control circuit 28. Therefore, the DC output voltage Vout of the voltage regulator circuit 30 changes according to Rf2, which is the resistance value of the variable feedback resistor realized by the output control circuit 28.

[0032] The output control circuit 28 according to the first embodiment includes a soft start circuit 52, a read circuit 54, a waveform control circuit 56, and a waveform change circuit 58.

[0033] The soft-start circuit 52 receives an enable signal EN and a clock. The enable signal EN is provided from an external circuit and switches between operating and non-operating states of the voltage regulator circuit 30. The voltage regulator circuit 30 generates the DC output voltage Vout when the enable signal EN is at a logical H, and does not generate the DC output voltage Vout when the enable signal EN is at a logical L.

[0034] When the enable signal EN changes from a logical L to a logical H, the soft-start circuit 52 causes the voltage regulator circuit 30 to start generating the DC output voltage Vout. Furthermore, during a start period in which generation of the DC output voltage Vout starts, the soft-start circuit 52 controls the voltage regulator circuit 30 to change the DC output voltage Vout from a first voltage value to a second voltage value over time. After the DC output voltage Vout reaches the second voltage value, the soft-start circuit 52 controls the voltage regulator circuit 30 to fix the DC output voltage Vout at the second voltage value.

[0035] In this embodiment, the soft-start circuit 52 increases the DC output voltage Vout from a first voltage value to a second voltage value over time by changing the resistance value Rf2 of the variable feedback resistor between the internal node 16 and the ground terminal during a start period in which the voltage regulator circuit 30 starts generating the DC output voltage Vout. After the DC output voltage Vout reaches the second voltage value, the soft-start circuit 52 fixes the resistance value Rf2 of the variable feedback resistor to fix the DC output voltage Vout at the second voltage value.

[0036] For example, the soft-start circuit 52 includes a counter 60 and a variable resistance circuit 62 .

[0037] The counter 60 outputs a binary counter value. In this embodiment, the counter 60 outputs an M-digit counter value. In this embodiment, the counter value has a smallest digit value of C1 and a largest digit value of CM. In the example of FIG. 2, M is 6.

[0038] The counter 60 receives an enable signal EN and a clock. The counter 60 increments the counter value by one for each clock while the enable signal EN is being provided, for example, while the enable signal EN is at logic H. After the enable signal EN changes from logic L to logic H, the counter 60 increments the value by one for each clock from a first value (for example, binary 000000) to a second value (binary 111111), and when the second value is reached, stops incrementing the count value while fixing it at the second value.

[0039] The variable resistor circuit 62 is a variable feedback resistor connected between the internal node 16 and a ground terminal. The variable resistor circuit 62 changes its resistance value in accordance with the counter value output from the counter 60.

[0040] The variable resistance circuit 62 includes M nMOSFETs 64-1 to 64-M (MOSFETs: Metal-Oxide-Semiconductor Field-Effect Transistors) and M resistors 66-1 to 66-M. In the example of Fig. 2, the variable resistance circuit 62 includes six nMOSFETs 64-1 to 64-6 and six resistors 66-1 to 66-6.

[0041] The M nMOSFETs 64-1 to 64-M correspond one-to-one to the digits of the M-digit counter value output from the counter 60. The source of each of the M nMOSFETs 64-1 to 64-M is connected to the ground terminal. The nMOSFET 64-1 corresponding to the first digit has its gate supplied with C1', which is the value output from the waveform modification circuit 58. The nMOSFETs 64-2 to 64-M corresponding to the second to M-th digits have their gates supplied with C2 to CM, which are the values ​​of the corresponding digits in the counter value.

[0042] The M resistors 66-1 to 66-M correspond one-to-one to the digits of the M-digit counter value output from the counter 60. One terminal of each of the M resistors 66-1 to 66-M is connected to the internal node 16, and the other terminal is connected to the drain of the corresponding nMOSFET 64 among the M nMOSFETs 64-1 to 64-M. That is, the terminal of the m-th digit (m is an integer greater than or equal to 1 and less than or equal to M) resistor 66-m among the M resistors 66-1 to 66-M that is not connected to the internal node 16 is connected to the drain of the m-th digit nMOSFET 64-m among the M nMOSFETs 64-1 to 64-M.

[0043] The resistance value of the mth digit resistor 66-m is 2 (m-1) ×R, where R is any positive real number. For example, the resistance value of resistor 66-1 corresponding to the first digit is R. The resistance value of resistor 66-2 corresponding to the second digit is 2R. The resistance value of resistor 66-6 corresponding to the sixth digit is 32R. In this variable resistor circuit 62, Rf2, which is the resistance value of the variable feedback resistor between internal node 16 and the ground terminal, can be set to the counter value multiplied by R.

[0044] The soft-start circuit 52 configured as described above can control the voltage regulator circuit 30 to start generating the DC output voltage Vout when the enable signal EN changes from a logical low to a logical high. Furthermore, during a start period in which generation of the DC output voltage Vout is started, the soft-start circuit 52 increases the resistance value Rf2 of the variable feedback resistor for each clock by incrementing the counter value by one. This allows the soft-start circuit 52 to control the voltage regulator circuit 30 to increase the DC output voltage Vout from a first voltage value to a second voltage value over time. After the counter value reaches its maximum value, the soft-start circuit 52 fixes the counter value at the maximum value. This allows the soft-start circuit 52 to control the voltage regulator circuit 30 to fix the DC output voltage Vout at the second voltage value after the DC output voltage Vout reaches the second voltage value.

[0045] The read circuit outputs N read signals S1 to SN that indicate the positions or the number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N included in the memory circuit .

[0046] For example, the read circuit 54 outputs N read signals S1 to SN corresponding one-to-one to the N electronic fuses 40-1 to 40-N. For example, each of the read signals S1 to SN is logical H when the corresponding electronic fuse 40 is blown, and is logical L when the corresponding electronic fuse 40 is not blown.

[0047] The read circuit 54 may also output N read signals S1 to SN representing the number of blown electronic fuses 40. For example, if none of the N electronic fuses 40-1 to 40-N are blown, the read circuit 54 sets each of the N read signals S1 to SN to L logic. For example, if x (x is an integer greater than or equal to 1 and less than or equal to N) electronic fuses 40 out of the N electronic fuses 40-1 to 40-N are blown, the read circuit 54 sets the x-th read signal Sx out of the N read signals S1 to SN to H logic, and sets all other read signals Sx except the x-th read signal Sx to L logic.

[0048] The waveform control circuit 56 acquires the N read signals S1 to SN output from the read circuit 54. The waveform control circuit 56 changes the waveform of the DC output voltage Vout in the start period according to the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N.

[0049] In this embodiment, the waveform control circuit 56 generates a first waveform that is different from the normal waveform when no blown electronic fuse 40 is included among the N electronic fuses 40-1 to 40-N, at a timing that is pre-assigned depending on the position or number of blown electronic fuses 40 during the start period.

[0050] For example, a value within the range of possible count values ​​is assigned to each position of the electronic fuse 40 or each number of blown electronic fuses 40. In this case, multiple values ​​may be assigned to each position of the electronic fuse 40 or each number of blown electronic fuses 40. However, one value can only be assigned to a maximum of one type of position or one type of number.

[0051] During the start period, the waveform control circuit 56 outputs a non-change signal that becomes logical L when the count value generated by the counter 60 becomes a value corresponding to the position of each blown electronic fuse 40 or the number of blown electronic fuses 40, and becomes logical H when the count value becomes any other value.

[0052] The waveform modification circuit 58 receives the non-modification signal from the waveform control circuit 56. The waveform modification circuit 58 also obtains the value C1 of the least significant digit of the counter value from the counter 60. For example, the waveform modification circuit 58 is a NAND circuit that receives the non-modification signal and the value C1 of the least significant digit of the counter value and outputs C1'.

[0053] When the non-change signal is logical H, the waveform modification circuit 58 outputs the value C1 of the least significant digit of the counter value as C1' without modification. In other words, when the non-change signal is logical H, the waveform modification circuit 58 provides the variable resistance circuit 62 with a normal count value.

[0054] Furthermore, when the non-change signal is logic L, the waveform change circuit 58 sets C1' to logic L regardless of the value C1 of the least significant digit of the counter value. In other words, when the non-change signal is logic L, the waveform change circuit 58 provides the variable resistance circuit 62 with a value that is different from the normal count value.

[0055] The waveform modification circuit 58 causes the variable resistance circuit 62 to output a normal count value when the non-change signal is at logic H, thereby causing the soft-start circuit 52 to generate a normal waveform. Furthermore, the waveform modification circuit 58 causes the variable resistance circuit 62 to output a count value different from the normal value when the non-change signal is at logic L, thereby causing the soft-start circuit 52 to generate a first waveform different from the normal waveform. This allows the waveform control circuit 56 to generate a first waveform different from the normal waveform when no blown electronic fuse 40 is included among the N electronic fuses 40-1 to 40-N, at a timing during the start period that is assigned in advance in accordance with the positions or number of blown electronic fuses 40.

[0056] FIG. 3 is a diagram showing an example of the configuration of the counter 60 and the waveform control circuit 56 together with the waveform change circuit 58.

[0057] Counter 60 includes, for example, (M-1) D flip-flops 68-2 to 68-M. Each of (M-1) D flip-flops 68-2 to 68-M receives an enable signal EN and operates when enable signal EN is at H logic.

[0058] The D flip-flop 68-2 receives a clock from the clock terminal, and receives at its input terminal D the inverted signal output from the inverted output terminal QB of the D flip-flop 68-2.

[0059] D flip-flop 68-p (p is an integer between 3 and M) receives at its clock terminal the signal output from output terminal Q of D flip-flop 68-(p-1). D flip-flop 68-p receives at its input terminal D the inverted signal output from inverted output terminal QB of D flip-flop 68-p.

[0060] Counter 60 configured as described above outputs the clock as the least significant digit C1 of the counter value. Counter 60 also outputs the inverted signals output from the inverting output terminals QB of each of (M-1) D flip-flops 68-2 to 68-M as the second digit C2 to the Mth digit CM of the counter value.

[0061] The waveform control circuit 56 includes N coincidence circuits 70-1 to 70-N, N NAND circuits 72-1 to 72-N, a composite NAND circuit 74, and an inversion circuit .

[0062] The N match circuits 70-1 to 70-N correspond one-to-one to the N read signals S1 to SN output from the read circuit 54. That is, when the N read signals S1 to SN indicate the positions of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N, the N match circuits 70-1 to 70-N correspond one-to-one to the N electronic fuses 40-1 to 40-N. When the N read signals S1 to SN indicate the number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N, the N match circuits 70-1 to 70-N correspond one-to-one to the N numbers from 1 to N.

[0063] Each of the N coincidence circuits 70-1 to 70-N is set with a value assigned to the corresponding position or number. Each of the N coincidence circuits 70-1 to 70-N outputs a coincidence signal that is logic H when the count value of the counter 60 reaches the set value, and logic L when the count value is other than the set value.

[0064] In the example of Fig. 3, a different 3-bit value is set in each of the N match circuits 70-1 to 70-N. In the example of Fig. 3, each of the N match circuits 70-1 to 70-N outputs a match signal that is logic H when the 3-bit values ​​of the second, third, and fourth digits of the count value become the set value.

[0065] The N NAND circuits 72-1 to 72-N correspond one-to-one to the N read signals S1 to SN output from the read circuit 54. The x-th NAND circuit 72-x of the N NAND circuits 72-1 to 72-N obtains a match signal from the x-th match circuit 70-x of the N match circuits 70-1 to 70-N. Furthermore, the x-th NAND circuit 72-x obtains the x-th read signal Sx of the N read signals S1 to SN.

[0066] The xth NAND circuit 72-x outputs a signal that is L logic when both the match signal output from the xth match circuit 70-n and the xth read signal Sx are H logic, and outputs a signal that is H logic when at least one of the match signal output from the xth match circuit 70-x and the xth read signal Sx is L logic.

[0067] The composite NAND circuit 74 acquires signals output from the N NAND circuits 72-1 to 72-N. The composite NAND circuit 74 outputs a signal that is H logic when at least one of the signals output from the N NAND circuits 72-1 to 72-N is L logic, and outputs a signal that is L logic when all of the signals output from the N NAND circuits 72-1 to 72-N are H logic.

[0068] The inverter circuit 76 inverts the logic of the signal output from the composite NAND circuit 74 and supplies the resulting signal to the waveform modification circuit 58 as an unmodified signal.

[0069] The waveform control circuit 56 configured in this manner can output a non-change signal that becomes logical L when the count value generated by the counter 60 during the start period in which generation of the DC output voltage Vout begins becomes a value assigned to each position of the blown electronic fuse 40 or the number of blown electronic fuses 40, and becomes logical H when the count value is any other value.

[0070] FIG. 4 is a diagram showing the waveform of the DC output voltage Vout during the start period when none of the N electronic fuses 40-1 to 40-N is blown.

[0071] The soft start circuit 52 causes the voltage regulator circuit 30 to start generating the DC output voltage Vout from the timing when the enable signal EN changes from a logical L to a logical H.

[0072] The soft-start circuit 52 generates a DC output voltage Vout of a first voltage value when the enable signal EN changes from logic L to logic H. When none of the N electronic fuses 40-1 to 40-N are blown, the soft-start circuit 52 increases the DC output voltage Vout by a predetermined voltage value for each clock during a start period in which generation of the DC output voltage Vout begins. When the DC output voltage Vout reaches a second voltage value, the soft-start circuit 52 stops increasing the DC output voltage Vout and thereafter fixes the DC output voltage Vout to the second voltage value.

[0073] In this way, when none of the N electronic fuses 40-1 to 40-N are blown, the soft-start circuit 52 controls the voltage regulator circuit 30 during the start period to increase the DC output voltage Vout from the first voltage value to the second voltage value over time.

[0074] FIG. 5 is a diagram showing the waveform of the DC output voltage Vout in the start period when the xth electronic fuse 40-x or x electronic fuses 40 among the N electronic fuses 40-1 to 40-N are blown.

[0075] The waveform control circuit 56 changes the waveform of the DC output voltage Vout in the start period depending on the position or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N.

[0076] For example, when the values ​​represented by the second, third, and fourth digits of the 6-bit counter value are a predetermined value, the waveform control circuit 56 fixes the value of the first digit to 0. As a result, every time the values ​​represented by the second, third, and fourth digits of the 6-bit counter value become a predetermined value, the waveform control circuit 56 can generate a first waveform that is different from the normal waveform in the waveform of the DC output voltage Vout.

[0077] 6 is a diagram showing the waveform of the DC output voltage Vout during the start period when the y-th electronic fuse 40-y or y electronic fuses 40 among the N electronic fuses 40-1 to 40-N are blown, where y is an integer greater than or equal to 1 and less than or equal to N, and is any integer different from x.

[0078] The waveform control circuit 56 changes the position in the waveform of the DC output voltage Vout at which the first waveform is generated, depending on the position or number of blown electronic fuses 40. For example, the waveform control circuit 56 changes the values ​​represented by the second, third, and fourth digits at which the first waveform is generated, depending on the position or number of blown electronic fuses 40. This allows the waveform control circuit 56 to vary the timing at which the first waveform is generated, depending on the position or number of blown electronic fuses 40.

[0079] In the semiconductor device 10 according to the first embodiment, during a start period when generation of the DC output voltage Vout begins, the voltage waveform of the voltage output terminal 14 is observed using, for example, an oscilloscope to detect the timing at which the first waveform is generated, thereby making it possible to identify the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N. As a result, according to the semiconductor device 10 according to the first embodiment, the N electronic fuses 40-1 to 40-N can easily and non-volatilely store the operation history, and the stored operation history can be confirmed without opening the package.

[0080] (Second embodiment) Next, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment has substantially the same functions and configuration as the semiconductor device 10 according to the first embodiment described with reference to Figures 1 to 6, so elements having the same functions and configurations are given the same reference numerals, and detailed descriptions will be omitted except for differences. The same applies to the third and subsequent embodiments.

[0081] 7 is a diagram showing the configuration of the output control circuit 28 according to the second embodiment. The output control circuit 28 according to the second embodiment includes a variable delay circuit 80 instead of the waveform change circuit 58.

[0082] The variable delay circuit 80 delays the start timing of the start period during which generation of the DC output voltage Vout begins. Furthermore, the variable delay circuit 80 can change the amount of delay in the start timing.

[0083] For example, the variable delay circuit 80 acquires the enable signal EN, delays the acquired enable signal EN, and provides the delayed signal to the counter 60. Furthermore, for example, the variable delay circuit 80 is capable of changing the amount of delay of the enable signal EN.

[0084] In the second embodiment, the waveform control circuit 56 sets the delay amount of the variable delay circuit 80 to a value that is assigned in advance depending on the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N. For example, the waveform control circuit 56 sets the delay amount of the enable signal EN by the variable delay circuit 80 to a value that is assigned in advance depending on the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N.

[0085] Fig. 8A shows the waveform of the DC output voltage Vout during the start period when none of the N electronic fuses 40-1 to 40-N are blown. Fig. 8B shows the waveform of the DC output voltage Vout during the start period when the xth electronic fuse 40-x or x electronic fuses 40 are blown.

[0086] The waveform control circuit 56 according to the second embodiment changes the amount of delay in the waveform of the DC output voltage Vout depending on the positions or number of blown electronic fuses 40. In this case, the amount of delay in the start timing of the start period is determined in advance depending on the positions or number of blown electronic fuses 40.

[0087] In the semiconductor device 10 according to the second embodiment, the position or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N can be identified by measuring the delay amount of the voltage waveform at the voltage output terminal 14 using, for example, an oscilloscope during a start period when generation of the DC output voltage Vout begins. As a result, the semiconductor device 10 according to the second embodiment can easily and non-volatilely store the operation history using the N electronic fuses 40-1 to 40-N, and can check the stored operation history without opening the package.

[0088] (Third embodiment) Next, a semiconductor device 10 according to a third embodiment will be described.

[0089] 9 is a diagram showing the configuration of a semiconductor device 10 according to the third embodiment. The output control circuit 28 according to the third embodiment includes a variable power consumption circuit 82 and a power consumption setting circuit 84. The variable power consumption circuit 82 and the power consumption setting circuit 84, together with the electronic circuit 20, the detection circuit 22, the memory circuit 24, and the disconnection control circuit 26, are circuits formed on a semiconductor substrate.

[0090] The variable power consumption circuit 82 consumes the power generated by the voltage regulator circuit 30. Furthermore, the variable power consumption circuit 82 is capable of changing the amount of power consumption. However, the power consumed by the variable power consumption circuit 82 is sufficiently smaller than the power consumed by the load connected to the voltage output terminal 14.

[0091] The power consumption setting circuit 84 sets the amount of power consumed by the variable power consumption circuit 82 to a value assigned in advance depending on the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N included in the memory circuit 24.

[0092] For example, the power consumption setting circuit 84 outputs N setting signals D1 to DN that indicate the positions or the number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N included in the memory circuit 24.

[0093] For example, the power consumption setting circuit 84 outputs N setting signals D1 to DN that correspond one-to-one to the N electronic fuses 40-1 to 40-N. For example, each of the N setting signals D1 to DN becomes logical H when the corresponding electronic fuse 40 is blown, and becomes logical L when the corresponding electronic fuse 40 is not blown.

[0094] The power consumption setting circuit 84 may also output N setting signals D1 to DN representing the number of blown electronic fuses 40. For example, if none of the N electronic fuses 40-1 to 40-N are blown, the power consumption setting circuit 84 sets each of the N setting signals D1 to DN to L logic. For example, if x electronic fuses 40 out of the N electronic fuses 40-1 to 40-N are blown, the power consumption setting circuit 84 sets the x-th setting signal Dx out of the N setting signals D1 to DN to H logic, and sets all other setting signals Dx than the x-th setting signal Dx to L logic.

[0095] Furthermore, for example, the variable power consumption circuit 82 includes N nMOSFETs 86-1 to 86-N and N resistors 88-1 to 88-N.

[0096] The N nMOSFETs 86-1 to 86-N correspond one-to-one to the N setting signals D1 to DN. The source of each of the N nMOSFETs 86-1 to 86-N is connected to a ground terminal. The gate of each of the N nMOSFETs 86-1 to 86-N is supplied with a corresponding setting signal D of the N setting signals D1 to DN.

[0097] The N resistors 88-1 to 88-N correspond one-to-one to the N nMOSFETs 86-1 to 86-N. One terminal of each of the N resistors 88-1 to 88-N is connected to the voltage output terminal 14, and the other terminal is connected to the drain of the corresponding nMOSFET 86 among the N nMOSFETs 86-1 to 86-N.

[0098] Each of the N nMOSFETs 86-1 to 86-N switches whether or not the terminal of the corresponding resistor 88 among the N resistors 88-1 to 88-N that is not connected to voltage output terminal 14 is connected to the ground terminal, depending on the logic of a setting signal D applied to its gate. Each of the N resistors 88-1 to 88-N consumes power generated by the voltage regulator circuit 30 when the terminal not connected to voltage output terminal 14 is connected to the ground terminal, and does not consume power generated by the voltage regulator circuit 30 when the terminal not connected to voltage output terminal 14 is not connected to the ground terminal.

[0099] Therefore, the variable power consumption circuit 82 configured as described above changes the power it consumes depending on the position or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N included in the memory circuit 24.

[0100] In the semiconductor device 10 according to the third embodiment, the amount of power consumed by the variable power consumption circuit 82 is a value corresponding to the positions or number of blown electronic fuses 40 among the N electronic fuses 40-1 to 40-N. The amount of power consumed by the variable power consumption circuit 82 can be determined by measuring the amount of power consumed by the entire circuit of the semiconductor device 10 and calculating the difference between the measured amount of power and the amount of power consumed by the entire circuit when none of the N electronic fuses 40-1 to 40-N are blown. As a result, the semiconductor device 10 according to the third embodiment allows the N electronic fuses 40-1 to 40-N to easily and non-volatilely store an operation history, and allows the stored operation history to be confirmed without opening the package.

[0101] (Fourth embodiment) Next, a semiconductor device 10 according to a fourth embodiment will be described.

[0102] 10 is a diagram showing the configuration of a semiconductor device 10 according to the fourth embodiment. The semiconductor device 10 according to the fourth embodiment includes a status readout circuit 92 instead of the output control circuit 28. The semiconductor device 10 according to the fourth embodiment also includes a status output terminal 94 as a connection terminal with an external circuit.

[0103] In the fourth embodiment, the memory circuit 24 has a first terminal 136. The memory circuit 24 sequentially blows the N electronic fuses 40 one by one every time a predetermined first voltage is applied to the first terminal 136.

[0104] More specifically, when a first voltage is applied to the first terminal 136 while the first electronic fuse 40-1 of the N electronic fuses 40 is not blown, the memory circuit 24 causes a current equal to or greater than the threshold value to flow through the first electronic fuse 40-1 and does not cause a current equal to or greater than the threshold value to flow through any electronic fuse other than the first electronic fuse 40-1 among the N electronic fuses 40. In other words, when a first voltage is applied to the first terminal 136 while the first electronic fuse 40-1 of the N electronic fuses 40 is not blown, the memory circuit 24 blows only the first electronic fuse 40-1.

[0105] Furthermore, when a first voltage is applied to the first terminal 136 in a state where the n-th electronic fuse 40-n of the N electronic fuses 40 is not blown (n is an integer greater than or equal to 2 and less than or equal to N) and the first to (n-1)-th electronic fuses 40-1 to 40-(n-1) of the N electronic fuses 40 are blown, the memory circuit 24 causes a current equal to or greater than the threshold to flow through the n-th electronic fuse 40-n and does not cause a current equal to or greater than the threshold to flow through electronic fuses 40 other than the n-th electronic fuse 40-n of the N electronic fuses 40. In other words, when a first voltage is applied to the first terminal 136 in a state where the n-th electronic fuse 40-n is not blown and the first to (n-1)-th electronic fuses 40-1 to 40-(n-1) are blown, the memory circuit 24 blows only the n-th electronic fuse 40-n. In addition, if the first voltage continues to be applied to the first terminal 136 for a certain period of time or more after the nth electronic fuse 40-n has blown due to a current greater than or equal to the threshold flowing through the nth electronic fuse 40-n, the memory circuit 24 will blow the (n+1)th electronic fuse 40-(n+1) after the certain period of time.

[0106] The disconnection control circuit 26 receives a disconnection instruction signal from the detection circuit 22. When the disconnection control circuit 26 receives the disconnection instruction signal, the disconnection control circuit 26 applies a first voltage to the first terminal 136 of the memory circuit 24, and stops applying the first voltage to the first terminal 136 after the (n-1)th electronic fuse 40-(n-1) of the N electronic fuses 40-1 to 40-N has blown and before the nth electronic fuse 40-n has blown. The disconnection control circuit 26 can blow one electronic fuse 40 out of the N electronic fuses 40 every time it receives a disconnection instruction signal. More specifically, the disconnection control circuit 26 can blow the electronic fuses 40 one by one, starting from the first electronic fuse 40-1, every time it receives a disconnection instruction signal.

[0107] The status readout circuit 92 outputs information indicating the number of blown electronic fuses 40 out of the N electronic fuses 40 to an external circuit from a status output terminal 94. For example, when a predetermined DC voltage is applied from an external circuit to the status output terminal 94, the status readout circuit 92 causes a current of an amount corresponding to the number of blown electronic fuses 40 out of the N electronic fuses 40 to flow through the status output terminal 94.

[0108] For example, the status readout circuit 92 receives a predetermined DC voltage from an external circuit via a status output terminal 94. The status readout circuit 92 then applies a predetermined DC voltage from the external circuit to each of at least two or more of the N electronic fuses 40-1 to 40-N, one terminal of which is connected to the ground terminal, via a resistor with a predetermined resistance value, from the terminal not connected to the ground terminal. When blown, the N electronic fuses 40-1 to 40-N do not pass a current even when a predetermined voltage is applied, but when not blown, they pass a predetermined current when a predetermined voltage is applied. Therefore, the status readout circuit 92 can pass a current of an amount corresponding to the number of blown electronic fuses 40 among the at least two or more electronic fuses 40, one terminal of which is connected to the ground terminal, to the status output terminal 94.

[0109] FIG. 11 is a diagram showing the configuration of a storage circuit 24 according to the fourth embodiment.

[0110] The memory circuit 24 includes N electronic fuses 40 , a reference transistor 150 , a constant current source 152 , N blow transistors 154 , (N−1) resistors 156 , and (N−1) coupling transistors 158 .

[0111] The memory circuit 24 includes a first electronic fuse 40-1 through an N-th electronic fuse 40-N as the N electronic fuses 40. The memory circuit 24 includes a first fusible transistor 154-1 through an N-th fusible transistor 154-N as the N fusible transistors 154. The memory circuit 24 includes a first resistor 156-1 through an (N-1)th resistor 156-(N-1) as the (N-1) resistors 156. The memory circuit 24 includes a first linking transistor 158-1 through an (N-1)th linking transistor 158-(N-1) as the (N-1) linking transistors 158.

[0112] The reference transistor 150 is a three-terminal element, including a control terminal, a positive terminal, and a negative terminal. In this embodiment, the reference transistor 150 is a bipolar transistor. In a bipolar transistor, the control terminal is the base terminal, and the positive terminal and negative terminal are the emitter terminal and collector terminal. When the positive terminal is the emitter terminal, the negative terminal is the collector terminal. When the positive terminal is the collector terminal, the negative terminal is the emitter terminal.

[0113] The reference transistor 150 may also be a field effect transistor such as a MOSFET. In a field effect transistor, the control terminal is the gate terminal, and the positive terminal and negative terminal are the drain terminal and source terminal. When the positive terminal is the drain terminal, the negative terminal is the source terminal. When the positive terminal is the source terminal, the negative terminal is the drain terminal. The same applies to other transistors as the reference transistor 150.

[0114] The reference transistor 150 is diode-connected. That is, if the reference transistor 150 is a bipolar transistor, the base terminal and the collector terminal are connected. Also, if the reference transistor 150 is a field-effect transistor, the gate terminal and the drain terminal are connected.

[0115] When power is supplied, the constant current source 152 passes a constant current. The positive and negative terminals of the reference transistor 150 and the constant current source 152 are connected in series between the first terminal 136 and the ground terminal. When a first voltage is applied to the first terminal 136, the constant current source 152 passes a predetermined first current through the diode-connected reference transistor 150.

[0116] In this embodiment, the reference transistor 150 is a pnp bipolar transistor, with an emitter terminal connected to the first terminal 136 and a base terminal connected to a collector terminal. The positive side of the constant current source 152 is connected to the collector terminal of the reference transistor 150, and the negative side is connected to the ground terminal. When a first voltage is applied to the first terminal 136, the reference transistor 150 causes a predetermined first current to flow between the emitter terminal and the collector terminal.

[0117] The positive and negative terminals of the first electronic fuse 40-1 and the first fusible transistor 154-1 of the N fusible transistors 154 are connected in series between the first terminal 136 and the ground terminal. The positive and negative terminals of the n-th fusible transistor 154-n and the n-th electronic fuse 40-n of the N fusible transistors 154 are connected in series between the first terminal 136 and the ground terminal.

[0118] The (n-1)th resistor 156-(n-1) of the (N-1) resistors 156 is provided between the control terminal of the nth fusible transistor 154-n and the ground terminal when n is an even number. The (n-1)th resistor 156-(n-1) is provided between the control terminal of the nth fusible transistor 154-n and the first terminal 136 when n is an odd number.

[0119] In this embodiment, the odd-numbered fusible transistors 154-1, 154-3, 154-5, ... of the N fusible transistors 154 are pnp-type bipolar transistors. The emitter terminals of the odd-numbered fusible transistors 154-1, 154-3, 154-5, ... are connected to the first terminal 136. Furthermore, the odd-numbered electronic fuses 40-1, 40-3, 40-5, ... of the N electronic fuses 40 are connected between the collector terminals of the corresponding odd-numbered fusible transistors 154-1, 154-3, 154-5, ... and the ground terminal.

[0120] In this embodiment, the even-numbered fusible transistors 154-2, 154-4, 154-6, ... of the N fusible transistors 154 are npn-type bipolar transistors. The emitter terminals of the even-numbered fusible transistors 154-2, 154-4, 154-6, ... are connected to the ground terminal. Furthermore, the corner-numbered electronic fuses 40-2, 40-4, 40-6, ... of the N electronic fuses 40 are connected between the collector terminals of the corresponding even-numbered fusible transistors 154-2, 154-4, 154-6, ... and the first terminal 136.

[0121] When a first current flows through the diode-connected reference transistor 150, a voltage is applied via the control terminal of the first fusible transistor 154-1 of the N fusible transistors 154, causing a current equal to or greater than the threshold to flow between the positive terminal and the negative terminal. This allows the first fusible transistor 154-1 to blow the first electronic fuse 40-1 when the first current flows through the reference transistor 150.

[0122] In this embodiment, the base terminal of the first fusible transistor 154-1 is connected to the base terminal of the reference transistor 150. As a result, the first fusible transistor 154-1 forms a current mirror circuit together with the reference transistor 150, and a current corresponding to the first current flowing through the diode-connected reference transistor 150 can flow between the emitter terminal and the collector terminal.

[0123] When a current flows through the (n-1)th resistor 156-(n-1), a voltage is applied to the control terminal of the nth blowing transistor 154-n, causing a current equal to or greater than the threshold value to flow between the positive terminal and the negative terminal. This allows the nth blowing transistor 154-n to blow the nth electronic fuse 40-n when a current flows through the (n-1)th resistor 156-(n-1).

[0124] In this embodiment, when n is an even number, the base terminal of the nth fusible transistor 154-n is connected to the ground terminal via the (n-1)th resistor 156-(n-1). Therefore, when n is an even number, a voltage whose value is obtained by multiplying the resistance value of the (n-1)th resistor 156-(n-1) by the value of the current flowing through the (n-1)th resistor 156-(n-1) is applied to the base terminal of the nth fusible transistor 154-n.

[0125] In this embodiment, when n is an odd number, the base terminal of the nth fusible transistor 154-n is connected to the first terminal 136 via the (n-1)th resistor 156-(n-1). Therefore, when n is an odd number, a voltage whose value is obtained by subtracting from the first voltage a voltage value obtained by multiplying the resistance value of the (n-1)th resistor 156-(n-1) and the current value of the current flowing through the (n-1)th resistor 156-(n-1) is applied to the base terminal of the nth fusible transistor 154-n.

[0126] Thus, in this embodiment, when a current flows through the (n-1)th resistor 156-(n-1), a voltage is applied to the base terminal of the nth fusible transistor 154-n, causing a current equal to or greater than the threshold to flow between the emitter terminal and the collector terminal. As a result, in this embodiment, when a current flows through the (n-1)th resistor 156-(n-1), the nth fusible transistor 154-n can blow the nth electronic fuse 40-n.

[0127] When the (n-1)th electronic fuse 40-(n-1) is not blown, the (n-1)th connecting transistor 158(n-1) of the (N-1) connecting transistors 158 sets the current flowing through the (n-1)th resistor 156-(n-1) to 0. Therefore, when the (n-1)th electronic fuse 40-(n-1) is not blown, no current flows through the (n-1)th resistor 156-(n-1), and the nth electronic fuse 40-n does not blow.

[0128] When the (n-1)th electronic fuse 40-(n-1) is blown, the (n-1)th connecting transistor 158(n-1) passes the current flowing through the (n-1)th blow transistor 154-(n-1) of the N blow transistors 154 to the (n-1)th resistor 156-(n-1). When a current flows through the (n-1)th resistor 156-(n-1), a voltage is applied to the control terminal of the nth blow transistor 154-n via the (n-1)th resistor 156-(n-1), causing a current greater than or equal to the threshold to flow between the positive terminal and the negative terminal. Therefore, when the (n-1)th electronic fuse 40-(n-1) is blown, the nth electronic fuse 40-n becomes blown-enabled.

[0129] In this embodiment, the odd-numbered linking transistors 158-1, 158-3, 158-5, ... of the (N-1) linking transistors 158 are pnp bipolar transistors. The odd-numbered linking transistors 158-2, 158-4, 158-6, ... of the (N-1) linking transistors 158 are npn bipolar transistors.

[0130] In this embodiment, the (n-1)th connecting transistor 158(n-1) has an emitter terminal connected to the collector terminal of the (n-1)th blow transistor 154(n-1). The (n-1)th connecting transistor 158(n-1) has a collector terminal connected to the base terminal of the nth blow transistor 154-n. The (n-1)th connecting transistor 158(n-1) has a base terminal connected to the base terminal of the (n-1)th blow transistor 154(n-1). As a result, when the (n-1)th electronic fuse 40-(n-1) is not blown, the (n-1)th connecting transistor 158(n-1) is turned off and does not allow current to flow through the (n-1)th resistor 156-(n-1). In addition, when the (n-1)th electronic fuse 40-(n-1) is blown, the (n-1)th linking transistor 158(n-1) turns on and allows current to flow through the (n-1)th resistor 156-(n-1).

[0131] 12 is a diagram showing the sequence of operations of the storage circuit 24 according to the fourth embodiment. In the fourth embodiment, the storage circuit 24 operates as follows.

[0132] First, the electronic fuses 40 are not blown. In S11, the blow control circuit 26 applies a first voltage to the first terminal 136 in response to receiving a blow instruction signal. When the first voltage is applied to the first terminal 136, the reference transistor 150 passes a first current between the emitter terminal and the collector terminal. When the first current flows through the reference transistor 150, as shown in S12, the first blown transistor 154-1 passes a current equal to or greater than the threshold between the emitter terminal and the collector terminal.

[0133] When the first electronic fuse 40-1 is not blown, its resistance is approximately 0. When the first electronic fuse 40-1 is not blown, the current flowing through the first blowing transistor 154-1 is supplied to the first electronic fuse 40-1. Therefore, the first electronic fuse 40-1 blows, as shown in S13.

[0134] When the first electronic fuse 40-1 is blown, the resistance value seen from the first terminal 136 increases. Therefore, after the first electronic fuse 40-1 is blown, the voltage at the first terminal 136 increases as shown in S14. Subsequently, in S15, when the cutoff control circuit 26 detects an increase in the voltage at the first terminal 136, it stops applying the first voltage to the first terminal 136. As a result, the memory circuit 24 enters a state in which the first electronic fuse 40-1 of the multiple electronic fuses 40 is blown and the second to N-th electronic fuses 40-2 to 40-N are not blown.

[0135] Subsequently, in S16, in response to receiving the next disconnection instruction signal, the disconnection control circuit 26 applies a first voltage to the first terminal 136. When the first voltage is applied to the first terminal 136, the first fusible transistor 154-1 passes a current between the emitter terminal and the collector terminal.

[0136] When the first electronic fuse 40-1 is blown, its resistance is nearly infinite. Therefore, as shown in S17, the current flowing through the first fusible transistor 154-1 is not supplied to the first electronic fuse 40-1, but is supplied to the first resistor 156-1. When a current is supplied to the first resistor 156-1, the voltage at the base terminal of the second fusible transistor 154-2 rises. As a result, as shown in S18, the second fusible transistor 154-2 passes a current greater than or equal to the threshold between its emitter terminal and collector terminal.

[0137] When the second electronic fuse 40-2 is not blown, its resistance is approximately 0. Therefore, when the second electronic fuse 40-2 is not blown, the current flowing through the second blowing transistor 154-2 also flows through the second electronic fuse 40-2. Therefore, the second electronic fuse 40-2 blows, as shown in S19.

[0138] When the second electronic fuse 40-2 is blown, the resistance value seen from the first terminal 136 increases. Therefore, as shown in S20, the voltage at the first terminal 136 increases. Subsequently, in S21, when the cutoff control circuit 26 detects an increase in the voltage at the first terminal 136, it stops applying the first voltage to the first terminal 136. As a result, the memory circuit 24 enters a state in which the first electronic fuse 40-1 and the second electronic fuse 40-2 of the multiple electronic fuses 40 are blown, and the third to N-th electronic fuses 40-3 to 40-N are not blown.

[0139] The memory circuit 24 performs the same operation for the third electronic fuse 40-3 and onwards. As a result, the memory circuit 24 can blow the multiple electronic fuses 40 one by one, starting from the first electronic fuse 40-1, every time the first voltage is supplied from the blow control circuit 26.

[0140] The timing at which the application of the first voltage to the first terminal 136 in the disconnection control circuit 26 is stopped after the first electronic fuse 40-1 has blown is sufficiently earlier than the timing at which the second electronic fuse 40-2 will blow following the first electronic fuse 40-1 due to continued application of the first voltage to the first terminal 136. The same applies to the timing at which the application of the first voltage to the first terminal 136 in the disconnection control circuit 26 is stopped after the second electronic fuse 40-2 and subsequent electronic fuses have blown.

[0141] If the first voltage continues to be applied to the first terminal 136, a predetermined delay time occurs due to a capacitance component and the like between the time when the first electronic fuse 40-1 blows and the time when the second blow transistor 154-2 turns on. Therefore, even if the blow control circuit 26 detects a rise in voltage at the first terminal 136 after the first electronic fuse 40-1 blows and then stops applying the first voltage, it can stop applying the first voltage before the second electronic fuse 40-2 blows.

[0142] In this way, after the (n-1)th electronic fuse 40-(n-1) is blown, the memory circuit 24 does not blow the nth electronic fuse 40-n before the blow control circuit 26 receives the next blow instruction signal. Therefore, the memory circuit 24 can sequentially blow the N electronic fuses 40 one by one every time the first voltage is applied from the blow control circuit 26.

[0143] 13 is a diagram showing the configuration of the disconnection control circuit 26 together with the memory circuit 24. The disconnection control circuit 26 includes a first bias resistor 162, an SR latch circuit 164, and a voltage application circuit 166.

[0144] The SR latch circuit 164 holds a first value or a second value. For example, the first value is H logic, and the second value is L logic.

[0145] A set pulse and a reset pulse are applied to the SR latch circuit 164. When a reset pulse is applied while the SR latch circuit 164 is holding a first value (logic H), the value it holds changes to a second value (logic L). When a set pulse is applied while the SR latch circuit 164 is holding the second value (logic L), the value it holds changes to the first value (logic H).

[0146] The SR latch circuit 164 outputs a voltage representing a value that is the inverse of the value it holds from the QB terminal. For example, when the SR latch circuit 164 holds a second value (L logic), it outputs an H logic voltage from the QB terminal. For example, when the SR latch circuit 164 holds a first value (H logic), it outputs an L logic voltage from the QB terminal.

[0147] When the SR latch circuit 164 holds the second value (L logic), the voltage application circuit 166 applies the power supply voltage to the first terminal 136 of the memory circuit 24 via the first bias resistor 162. When the SR latch circuit 164 holds the first value (H logic), the voltage application circuit 166 stops applying the power supply voltage to the first terminal 136 of the memory circuit 24.

[0148] Furthermore, the voltage application circuit 166 receives a disconnection instruction signal from the detection circuit 22. When the voltage application circuit 166 receives the disconnection instruction signal, it provides a reset pulse to the SR latch circuit 164. Therefore, when the voltage application circuit 166 receives the disconnection instruction signal, it changes the value held by the SR latch circuit 164 to a second value (L logic) and applies the power supply voltage to the first terminal 136 of the memory circuit 24 via the first bias resistor 162. This allows the voltage application circuit 166 to apply the first voltage to the first terminal 136 of the memory circuit 24.

[0149] When the voltage at the first terminal 136 rises while the power supply voltage is being applied to the first terminal 136 of the memory circuit 24 via the first bias resistor 162, the voltage application circuit 166 applies a set pulse to the SR latch circuit 164. Therefore, when the voltage at the first terminal 136 rises while the power supply voltage is being applied to the first terminal 136 of the memory circuit 24 via the first bias resistor 162, the voltage application circuit 166 changes the value held by the SR latch circuit 164 from the second value (L logic) to the first value (H logic), and stops the application of the power supply voltage to the first terminal 136 of the memory circuit 24. This allows the voltage application circuit 166 to stop the application of the first voltage to the first terminal 136 of the memory circuit 24.

[0150] For example, the voltage application circuit 166 includes a one-shot pulse circuit 172 , a power supply transistor 174 , a start transistor 176 , a current source 178 , a resistor 180 , a capacitor 182 , and a stop transistor 184 .

[0151] The one-shot pulse circuit 172 receives the disconnection instruction signal from the detection circuit 22. When the one-shot pulse circuit 172 receives the disconnection instruction signal, it supplies a pulse signal with a predetermined duration to the SR latch circuit 164 as a reset pulse.

[0152] The power supply transistor 174 has a positive terminal and a negative terminal connected between the power supply voltage terminal and one terminal of the first bias resistor 162. The terminal of the first bias resistor 162 that is not connected to the power supply transistor 174 is connected to the first terminal 136 of the memory circuit 24. Therefore, the positive terminal and the negative terminal of the power supply transistor 174 and the first bias resistor 162 are connected in series between the power supply voltage terminal and the first terminal 136.

[0153] In this embodiment, the power supply transistor 174 is a pnp bipolar transistor. The power supply transistor 174 has an emitter terminal connected to a power supply voltage terminal and a collector terminal connected to the terminal of the first bias resistor 162 that is not connected to the first terminal 136.

[0154] The control terminal of the starting transistor 176 is connected to the QB terminal of the SR latch circuit 164. The positive and negative terminals of the starting transistor 176 are connected between the ground terminal and the current-outlet terminal of the current source 178. The current-input terminal of the current source 178 is connected to the control terminal of the power supply transistor 174. Therefore, the positive and negative terminals of the starting transistor 176 and the current source 178 are connected in series between the control terminal of the power supply transistor 174 and the ground terminal.

[0155] In this embodiment, the initiation transistor 176 is an npn-type bipolar transistor. The base terminal of the initiation transistor 176 is connected to the QB terminal of the SR latch circuit 164. The emitter terminal of the initiation transistor 176 is connected to the ground terminal, and the collector terminal is connected to the current output terminal of the current source 178.

[0156] The resistor 180 is connected between the set pulse input terminal of the SR latch circuit 164 and the ground terminal. The capacitor 182 is connected between the set pulse input terminal of the SR latch circuit 164 and the ground terminal.

[0157] The stop transistor 184 has a positive terminal and a negative terminal connected between the first terminal 136 of the memory circuit 24 and the set pulse input terminal of the SR latch circuit 164. The stop transistor 184 has a control terminal connected to the control terminal of the power supply transistor 174.

[0158] In this embodiment, the stopping transistor 184 is a pnp bipolar transistor. The base terminal of the stopping transistor 184 is connected to the base terminal of the power supply transistor 174. The emitter terminal of the stopping transistor 184 is connected to the first terminal 136 of the memory circuit 24, and the collector terminal is connected to the set pulse input terminal of the SR latch circuit 164.

[0159] 14 is a diagram showing the sequence of operations of the disconnection control circuit 26. The disconnection control circuit 26 operates as follows.

[0160] First, as shown in S31, in the initial state, the SR latch circuit 164 holds the first value (logical H). Also, in the initial state, the power supply transistor 174, the start transistor 176, and the stop transistor 184 are off.

[0161] Subsequently, in S32, the one-shot pulse circuit 172 receives the disconnection instruction signal and provides a reset pulse to the SR latch circuit 164. As a result, as shown in S33, the SR latch circuit 164 changes the value it holds from the first value (logical H) to the second value (logical L).

[0162] When the value held by the SR latch circuit 164 becomes the second value (logic L), the start transistor 176 is turned on in S34. When the start transistor 176 is turned on, the power supply transistor 174 is turned on in S35. When the power supply transistor 174 is turned on, the disconnection control circuit 26 supplies the power supply voltage to the first terminal 136 of the memory circuit 24 via the first bias resistor 162 in S36.

[0163] The power supply voltage is applied to the first terminal 136 of the memory circuit 24 via the first bias resistor 162, and thus a first voltage is applied to the first terminal 136. As a result, the memory circuit 24 blows one of the electronic fuses 40. When one of the electronic fuses 40 is blown, the resistance value of the memory circuit 24 as seen from the first terminal 136 increases. As a result, in S37, the voltage at the first terminal 136 rises to near the power supply voltage.

[0164] When the voltage at the first terminal 136 rises to near the power supply voltage, the stopping transistor 184 turns on in S38. As a result of the stopping transistor 184 turning on, in S39 the disconnection control circuit 26 applies a set pulse to the SR latch circuit 164. As a result, the SR latch circuit 164 changes the value it holds from the second value (logic L) to the first value (logic H), as shown in S40.

[0165] When the value held by the SR latch circuit 164 becomes the first value (logical H), the start transistor 176 is turned off in S41. When the start transistor 176 is turned off, the power supply transistor 174 is turned off in S42. When the power supply transistor 174 is turned off, the disconnection control circuit 26 stops supplying the power supply voltage to the first terminal 136 of the memory circuit 24.

[0166] In this way, when the disconnection control circuit 26 receives a disconnection instruction signal, it can apply the first voltage to the first terminal 136 of the memory circuit 24 by supplying the power supply voltage to the first terminal 136 via the first bias resistor 162. Furthermore, if the voltage at the first terminal 136 rises after applying the first voltage, the disconnection control circuit 26 can stop applying the first voltage.

[0167] FIG. 15 is a diagram showing the configuration of the status readout circuit 92 together with the circuit configuration of the storage circuit 24.

[0168] The state readout circuit 92 includes P readout resistors 192-1 to 192-P and P switches 194-1 to 194-P, where P is a positive integer and is equal to N / 2.

[0169] One terminal of each of the P read resistors 192-1 to 192-P is connected to the status output terminal 94.

[0170] The P switches 194-1 to 194-P correspond one-to-one to the P read resistors 192-1 to 192-P. The pth switch 194-p (p is an integer greater than or equal to 1 and less than or equal to P) among the P switches 194-1 to 194-P corresponds to the pth read resistor 192-p among the P read resistors 192-1 to 192-P.

[0171] The pth switch 194-p is provided between a terminal (first internal node A) of the pth read resistor 192-p that is not connected to the status output terminal 94 and a terminal (second internal node B) that is not connected to the ground terminal of the odd-numbered (2×p−1)th electronic fuse 40-(2×p−1) of the N electronic fuses 40. The pth switch 194-p short-circuits the first internal node A and the second internal node B when the (2×p−1)th electronic fuse 40-(2×p−1) is blown and a predetermined DC voltage is applied to the status output terminal 94, and disconnects the first internal node A and the second internal node B in other cases.

[0172] The p-th switch 194-p is, for example, an nMOSFET. In this case, the drain is connected to the first internal node A, the source is connected to the second internal node B, and the gate is connected to the status output terminal 94.

[0173] When a predetermined DC voltage is applied to the status output terminal 94, the status readout circuit 92 configured as described above can pass a current to the status output terminal 94 that corresponds to the number of odd-numbered electronic fuses 40-1, 40-3, 40-5, ... 40-(N-1) that are blown out of the N electronic fuses 40.

[0174] By including such a state reading circuit 92, the semiconductor device 10 according to the fourth embodiment can easily check the blown state of the N electronic fuses 40 without opening the package and analyzing it.

[0175] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. Various modifications can be made to the embodiments. [Explanation of symbols]

[0176] 10 semiconductor device, 20 electronic circuit, 22 detection circuit, 24 memory circuit, 26 disconnection control circuit, 28 output control circuit, 30 voltage regulator circuit, 40 electronic fuse, 52 soft start circuit, 54 read circuit, 56 waveform control circuit, 58 waveform modification circuit, 80 variable delay circuit, 82 variable power consumption circuit, 84 power consumption setting circuit, 92 status output circuit

Claims

1. an electronic circuit including a voltage regulator circuit that outputs a DC output voltage; a memory circuit including N electronic fuses (N is an integer of 2 or more); a soft start circuit that controls the voltage regulator circuit to change the DC output voltage from a first voltage value to a second voltage value over time during a start period in which generation of the DC output voltage is started; a waveform control circuit that changes the waveform of the DC output voltage during the start period in accordance with the positions or number of blown electronic fuses among the N electronic fuses; A semiconductor device comprising:

2. The waveform control circuit generates, at a timing in the start period that is assigned in advance in accordance with the positions or the number of the blown electronic fuses, a first waveform that is different from a normal waveform when no blown electronic fuse is included in the N electronic fuses. The semiconductor device according to claim 1 .

3. a variable delay circuit that delays the start timing of the start period and is capable of changing the delay amount of the start timing; The waveform control circuit sets the delay amount of the variable delay circuit to a value that is assigned in advance in accordance with the position or number of blown electronic fuses among the N electronic fuses. The semiconductor device according to claim 1 .

4. an electronic circuit including a voltage regulator circuit for outputting a DC output voltage; a memory circuit including N electronic fuses (N is an integer of 2 or more); a variable power consumption circuit that consumes the power generated by the voltage regulator circuit and is capable of varying the amount of power consumed; a power consumption setting circuit that sets the amount of power consumed by the variable power consumption circuit to a value that is pre-assigned depending on the positions or the number of blown electronic fuses among the N electronic fuses; A semiconductor device comprising:

5. a memory circuit including N electronic fuses (N is an integer of 2 or more); a disconnection control circuit; a state readout circuit; Equipped with Each of the N electronic fuses melts when a current flowing therethrough is equal to or greater than a threshold value; The memory circuit When a first voltage is applied to a first terminal in a state where a first electronic fuse among the N electronic fuses is not blown, a current equal to or greater than the threshold value is passed through the first electronic fuse; When an n-th electronic fuse (n is an integer of 2 or more and N or less) among the N electronic fuses is not blown and all of the first to (n-1)-th electronic fuses among the N electronic fuses are blown, when the first voltage is applied to the first terminal, a current equal to or greater than the threshold value flows through the n-th electronic fuse; the disconnection control circuit, when receiving a disconnection instruction signal, applies the first voltage to the first terminal, and stops applying the first voltage to the first terminal after an (n-1)th electronic fuse among the N electronic fuses has been blown but before the nth electronic fuse has been blown; The state readout circuit applies a predetermined DC voltage provided from an external circuit to each of at least two or more electronic fuses, one terminal of which is connected to a ground terminal, from the terminal not connected to the ground terminal via a resistor having a predetermined resistance value. Semiconductor device.

6. further comprising a detection circuit for detecting the occurrence of a predetermined abnormality or event; When the abnormality or the event occurs, the detection circuit blows out an electronic fuse among the N electronic fuses according to the content of the abnormality or the event that has occurred. The semiconductor device according to claim 1 .

7. further comprising a detection circuit for detecting the occurrence of a predetermined abnormality or event; The detection circuit blows one of the N electronic fuses every time it detects the abnormality or the event. The semiconductor device according to claim 1 .

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