Switching circuit

Abstract

To suppress inrush current and surge voltage in a switching circuit in a short period of time.SOLUTION: A switching circuit has a first switching portion of a plurality of switch elements connected in series, and a second switching portion having one end connected to one end of the first switching portion, the switch elements include a first switch element and a second switch element provided with a capacitor, the other end of the first switching portion is connected to voltage having a high absolute value, the other end of the second switching portion is connected to voltage having a low absolute value, and a load circuit is connected between an output end between the first switching portion and the second switching portion and the voltage having a lower absolute value. In switching between the first switching portion and the second switching portion at a first frequency, ON timings of the switch elements of the first switching portion are shifted at the first-time ON timing and the second switch element is lastly turned ON, and the switching is performed while the ON state is maintained after the second switch element is lastly turned ON.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a switching circuit. [Background technology]

[0002] Conventionally, circuits having switching elements, such as converters and inverters, are sometimes provided with a soft start function to prevent damage to the switching elements due to inrush currents and surge voltages at startup.

[0003] A typical soft start function prevents damage to a switch element by limiting the ON time over several cycles in which the switch element is switched (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4853003 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when a soft start function is provided, there is a problem in that it takes several to several tens of cycles from the start of startup until the voltage rises.

[0006] The present invention has been made in view of the above problems, and has an object to provide a switching circuit that can suppress inrush current and surge voltage in a short period of time. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, a switching circuit according to the present invention includes a first switching unit having a plurality of switch elements connected in series, and a second switching unit having one end connected to one end of the first switching unit, the plurality of switch elements including the first switch element and a second switch element provided with a capacitor, the other end of the first switching unit being connected to a voltage line having a high absolute value and the other end of the second switching unit being connected to a voltage line having a low absolute value, and a load circuit being connected between an output terminal between one end of the first switching unit and one end of the second switching unit and the other end of the second switching unit, and is characterized in that, in a switching operation that switches on and off the first switching unit and the second switching unit at a first frequency, the first switching unit staggers the turn-on timings of the plurality of switch elements of the first switching unit at a timing when the first switching unit is initially turned on, and turns on the second switch element last, and after turning on the second switch element last, performs the switching operation while maintaining the second switch element on. [Effects of the Invention]

[0008] According to the present invention, inrush current and surge voltage can be suppressed in a short period of time. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a switching circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of the switch elements of the first switching unit and the second switching unit. [Figure 3] FIG. 3 is a diagram for explaining the principle of generation of inrush current. [Figure 4] FIG. 4 is a diagram showing an example of changes in the output terminal voltage and load current at the output terminal. [Figure 5]FIG. 5 is a diagram showing an example of changes in the drain-source voltage (potential difference) of each FET of the first switching unit observed when the timing of turning on each FET of the first switching unit is shifted. [Figure 6] FIG. 6 is an explanatory diagram of a timing chart of timing signals that turn on and off each FET of the first switching section. [Figure 7] FIG. 7 is a diagram showing an example of changes in the drain-source voltage (potential difference) of each FET of the first switching unit observed in the switching circuit of this embodiment. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a switching circuit according to the first modification of the embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of a configuration according to the second modification of the embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of an FET according to the third modification of the embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of the timing signal output unit. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A switching circuit according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the present embodiment.

[0011] (Embodiment) 1 is a diagram showing a schematic configuration of a switching circuit according to an embodiment. The switching circuit 1 shown in FIG. 1 includes a first switching unit 11, a second switching unit 12, and a timing signal output unit 13.

[0012] In the switching circuit 1, one end of the first switching unit 11 and one end of the second switching unit are connected. In addition, in the switching circuit 1, a node Nin1 at the other end of the first switching unit 11 is connected to a voltage line (DC voltage source) on the side with a higher absolute value of potential, and a node Nin2 at the other end of the second switching unit 12 is connected to a voltage line on the side with a lower absolute value of potential.

[0013] 1 has a negative voltage output configuration in which, for example, a node Nin1 at the other end of the first switching unit 11 is connected to a negative power supply line (-E), and a node Nin2 at the other end of the second switching unit 12 is connected to a line of reference potential. The reference potential is ground, which is, for example, 0 V.

[0014] The output terminal TMout is provided at a node Nout between one end of the first switching unit 11 and one end of the second switching unit 12.

[0015] The first switching unit 11 and the second switching unit 12 each have a switch element.

[0016] The timing signal output unit 13 outputs timing signals t1 and t2 for turning on and off each switch element to the first switching unit 11 and the second switching unit 12. In the following, on is synonymous with on, and off is synonymous with off.

[0017] The switching circuit 1 causes the first switching unit 11 and the second switching unit 12 to perform switching operations based on timing signals t1 and t2 from the timing signal output unit 13. The switching operations of the first switching unit 11 and the second switching unit 12 refer to operations in which each unit alternates between an on state and an off state, and an off state and an on state.

[0018] Specifically, the first switching unit 11 and the second switching unit 12 perform switching operations in which they repeatedly turn on and off complementarily at a first frequency (e.g., 400 kHz) that is higher than a predetermined second frequency (e.g., 2 kHz) during a continuous operation period defined by a predetermined on-duty ratio (e.g., 10%) during a repetition period of the predetermined second frequency (e.g., 2 kHz), and both the first switching unit 11 and the second switching unit 12 pause their switching operations during a pause period defined by a predetermined off-duty ratio (e.g., 90%).

[0019] In the manufacturing process of semiconductor manufacturing equipment, the output control described above is sometimes called PDM control (Pulse Density Modulation control).

[0020] The second frequency can be set, for example, between 0.01 kHz and 50 kHz, and the on-duty ratio corresponding to the second frequency can be set in the range of 1% to 99%. The first frequency can be set, for example, between 100 kHz and 1 MHz, and the on-duty ratio corresponding to the first frequency can be set in the range of 1% to 99%. Of course, this is not limited to the above. For example, the second frequency may be set in the range of 0.1 kHz to 100 kHz, and the first frequency may be set in the range of 100 kHz to several tens of MHz. The second frequency is set to a frequency lower than the first frequency.

[0021] It should be noted that a dead time may be provided during which the first switching unit 11 and the second switching unit 12 are both turned off at the time of switching so that they are not both turned on.

[0022] During a continuous operation period, the switching circuit 1 outputs a pulse voltage from the output terminal TMout in which the reference potential and a negative potential are alternately repeated, as the first switching unit 11 and the second switching unit 12 repeat complementary operations through switching operations of the first switching unit 11 and the second switching unit 12.

[0023] Fig. 2 is a diagram showing an example of the configuration of the switch elements of the first switching section 11 and the second switching section 12. Fig. 2 shows an example in which FETs (Field Effect Transistors) are provided as the switch elements.

[0024] Although other switching devices such as an IGBT (Insulated Gate Bipolar Transistor) can be used as the switch element, the present embodiment will be described assuming that the switch element is an FET.

[0025] The switching elements of the first switching unit 11 and the second switching unit 12 have a first terminal that is at a high potential when the switching unit to which they belong is off, and a second terminal that is at a low potential when the switching unit is off. In the case of an FET, the drain is the first terminal and the source is the second terminal. Therefore, an external capacitor 200 (described later) is provided between the first terminal and the second terminal.

[0026] As shown in FIG. 2, the first switching unit 11 has eight FETs connected in series. Similarly, the second switching unit 12 has eight FETs connected in series. Each FET is turned on and off based on timing signals t1 and t2 from the timing signal output unit 13. In this embodiment, the first switching unit 11 and the second switching unit 12 have eight FETs each, for a total of 16 FETs, but the number of FETs is not limited to this. As will be explained later, the first switching unit 11 may be composed of two or more FETs, and the second switching unit 12 may have a smaller number of FETs than the first switching unit 11 if FETs with a high voltage resistance are used.

[0027] 2, FET100-1 to FET100-16 are the eight FETs connected in series in the second switching section 12. FET100-9, FET100-10, FET100-11, FET100-12, FET100-13, FET100-14, FET100-15, and FET100-16 are the eight FETs connected in series in the first switching section 11.

[0028] In this embodiment, each FET represented by FET100-n (n=1, 2, . . . ) may be described as an individual name such as FETn (n=1, 2, . . . ). For example, in a description using FETn, FET1, FET2, . . . correspond to FET100-1, FET100-2, . . . , respectively. The explanation using FETn is mainly given in FIGS. 5, 6, 7, and 11.

[0029] An external capacitor 200 is provided between the drain and source of one of the eight series-connected FETs in the first switching unit 11. In FIG. 2, as an example, the external capacitor 200 is provided between the drain and source of FET 100-9. The capacitor 200 has a predetermined capacitance that is larger than the parasitic capacitance of FET 100-9, for example. In other words, the FET is an example of a switch element in the present disclosure.

[0030] In this embodiment, the FET 100-9 functions as the second switch, and the other FETs in the first switching section 11 function as the first switch. That is, the first switch does not refer to a single FET.

[0031] As shown in FIG. 2, a node Nin1 on the source side of the FET 100-16 is connected to a negative power supply line (-E), and a node Nin2 on the drain side of the FET 100-1 is connected to a reference potential line. A load circuit 14 is connected between the output terminal TMout and the reference potential line. The load circuit 14 is, for example, a load circuit such as a transformer or plasma. The configuration of the load circuit 14 is not particularly limited. A load circuit other than a transformer or plasma may also be used.

[0032] 1 shifts the timing at which the eight series-connected FETs of the first switching unit 11 are initially turned on, and outputs a timing signal t1 that turns on FET 100-9, which is provided with capacitor 200, last among the eight series-connected FETs of the first switching unit 11. As an example, the order in which the timing signal output unit 13 turns on the eight series-connected FETs of the first switching unit 11 is FET 100-16, FET 100-15, FET 100-14, FET 100-13, FET 100-12, FET 100-11, FET 100-10, and FET 100-9.

[0033] After the first on during the continuous operation period, the timing signal output unit 13 keeps FET 100-9 in the on state, and outputs on and off signals for the remaining FETs of the first switching unit 11, namely FET 100-10, FET 100-11, FET 100-12, FET 100-13, FET 100-14, FET 100-15, and FET 100-16, at the usual simultaneous on and simultaneous off timing.

[0034] For the eight FETs connected in series in the second switching section 12, the timing signal output section 13 outputs the timing signal t2 with the timing of simultaneous on and simultaneous off as usual from the first time.

[0035] Furthermore, when the pause period begins and the switching operations of the first switching unit 11 and the second switching unit 12 pause, all eight FETs connected in series in the first switching unit 11 are turned off.

[0036] Then, when a certain period of time passes and the second continuous operation period begins, the timing of the initial turn-on of each FET in the first switching unit 11 is shifted, as in the first continuous operation period, and FET 100-9, which is provided with capacitor 200, is turned on last. Similarly, FET 100-9 remains on after the first turn-on during the second continuous operation period. Then, when the pause period begins, the switching operations of the first switching unit 11 and the second switching unit 12 are paused. The above process is repeated thereafter. Of course, when output to the load is stopped, the switching operations of the first switching unit 11 and the second switching unit 12 are paused.

[0037] It has been found that the switching circuit 1 of this embodiment is effective in suppressing the surge voltage that occurs when the switching circuit is first turned on, thereby preventing damage to the FET.

[0038] The principle by which a switch element is damaged and the effect of the switching circuit 1 of this embodiment in suppressing surge voltages will be described in detail below with reference to FIGS.

[0039] Fig. 3 is a diagram for explaining the principle of inrush current generation. Fig. 3 shows an equivalent circuit of first switching unit 11 in a state where capacitor 200 is not provided. Consider a case where first switching unit 11 and second switching unit 12 perform switching operations by simultaneously turning on and off in the circuit shown in Fig. 3.

[0040] In the initial state, the first switching unit 11 is in the off state, and the second switching unit 12 is in the on state. In the initial state, current flows between the drain and source of each FET in the second switching unit 12, so the output terminal TMout has the same potential as the reference potential (0 V). In contrast, it is estimated that a voltage E of 0 V and -EV of the power supply line is applied across both ends of the first switching unit 11, so it is thought that an electric charge is stored in the parasitic capacitance (parasitic capacitance between the drain and source) of each FET in the first switching unit 11.

[0041] In this state, when second switching unit 12 turns off and first switching unit 11 turns on, the potential at output terminal TMout changes suddenly from the reference potential (0 V) to the potential (-E) of the power supply line, and the charge stored in the parasitic capacitance of each FET in first switching unit 11 is suddenly discharged. Since no current flows in load circuit 14 in the initial state, an inrush current I flows in the direction of the reference potential from first switching unit 12 toward second switching unit 12 on a path including the negative power supply line of power source E.

[0042] The inrush current I when the first switching unit 11 is turned on for the first time resonates with an LC circuit between the parasitic capacitance C (parasitic capacitance between drain and source) of the FET of the second switching unit 12, which is in the charge / discharge path of the charge of the parasitic capacitance (parasitic capacitance between drain and source) of the FET of the first switching unit 11, and the inductance L (L1+L2) of the wiring connected to the power supply E, and the resulting surge voltage may cause the FET to exceed its withstand voltage, resulting in damage to the FET.

[0043] Next, when the second switching unit 12 is turned off and the first switching unit 11 is turned on, the potential of the output terminal TMout becomes -E, and it is estimated that a voltage E of 0V and -EV of the power supply line is applied to both ends of the second switching unit 12, and therefore it is considered that an electric charge is stored in the parasitic capacitance (parasitic capacitance between the drain and source) of each FET that the second switching unit 12 has.

[0044] In this state, when the first switching unit 11 turns off and the second switching unit 12 turns on, the potential of the output terminal TMout changes suddenly from the potential of the power supply line (-E) to the reference potential (0V), and the charge stored in the parasitic capacitance of each FET of the second switching unit 12 is suddenly discharged. This discharge charges the parasitic capacitance of each switch element of the first switching unit 11. When the first switching unit 11 turns off, the charging time for the parasitic capacitance of each switch element is determined by the load current, so the magnitude of the surge voltage is smaller than the magnitude of the surge voltage immediately after the switching circuit 1 is started.

[0045] Thereafter, when first switching unit 11 is turned on again, the charge stored in the parasitic capacitance of each switch element of first switching unit 11 is discharged. This discharge charges the parasitic capacitance of each switch element of second switching unit 12. However, because a load current is already flowing at this point, a large surge voltage like that which occurs when first switching unit 11 is turned on immediately after switching circuit 1 is started up is not generated.

[0046] In this way, during the continuous operation period, charging and discharging of the parasitic capacitance of each switching element is repeated at a fixed cycle (the cycle of the first frequency). At this time, the charging and discharging conditions differ depending on the magnitude of the parasitic capacitance, the first frequency, etc., but because a current corresponding to the switching operation flows through the load, the magnitude of the surge voltage due to the above-mentioned resonance decreases. For this reason, it is important to take measures against the surge voltage during the first switching operation during the continuous operation period.

[0047] Of course, even in the case of output control that does not repeat continuous operation periods and pause periods as described above, but rather does not repeat continuous operation periods and pause periods (output stops when the continuous operation period ends), the inrush current is large and the absolute value of the surge voltage is large at the time of the first switching operation during the continuous operation period, as described above, so measures are required.

[0048] 4A and 4B are diagrams showing an example of changes in the output terminal voltage and load current at the output terminal TMout. The pulse voltage waveform V1 shown in Fig. 4A is the waveform of the output terminal voltage. The current waveform I1 is the waveform of the load current.

[0049] As an example, FIG. 4(a) shows a pulse voltage waveform V1 and a current waveform I1 during a continuous operation period and a pause period when the first frequency is 400 kHz, the second frequency is 2 kHz, and the predetermined on-duty ratio during the repetition period of the second frequency is 10% (the off-duty ratio is 90%).

[0050] In the pulse voltage waveform V1 in Figure 4(a), the continuous operation period defined by the second frequency and the on-duty ratio appears four times: on1, on2, on3, and on4. In other words, within the displayed section, there are four continuous operation periods and four pause periods.

[0051] In the example of FIG. 4, switching operations are performed 20 times (400 kHz / 2 kHz*10%) during the continuous operation period, followed by a rest period.

[0052] The voltage waveform in Figure 4(b) and the current waveform in Figure 4(c) are enlarged views of the output terminal voltage waveform and load current waveform during the first four cycles of switching operation during the continuous operation period on3 shown in Figure 4(a). Note that similar waveforms are also obtained during the other continuous operation periods (on1, on2, on4). One example is when the "-E" of the power supply line is set to -3000V.

[0053] As shown in the output terminal voltage waveform in Fig. 4(b), during the initial ON period of the first switching unit 11 during the continuous operation period, the voltage value of the output terminal TMout fluctuates greatly due to resonance, exceeding the "-3000 V" of the power supply line and reaching approximately "-6000 V." As shown in the load current waveform in Fig. 4(c), it can be seen that a large inrush current I exceeding approximately "-70 A" occurs during the initial ON period.

[0054] 4(b), from the second ON operation of the first switching unit 11 during the continuous operation period, current is also supplied to the load circuit 14. When current is supplied to the load circuit 14, the load circuit 14 becomes an LPF (Low-Pass Filter) and an RLC circuit, which reduces the speed of charging and discharging the parasitic capacitance of the FET and alleviates current inrush.

[0055] Therefore, in the switching circuit 1 of this embodiment, the inrush current I is suppressed by first shifting the timing at which each FET of the first switching unit 11 is turned on for each continuous operation period (on1, on2, ...) as shown in Figure 4(b).

[0056] By staggering the timing at which each FET in the first switching unit 11 is turned on, the timing at which the charge stored in the parasitic capacitance of each FET moves is staggered, slowing the initial current rise speed as shown in Figure 4(c). This suppresses the inrush current I, which can reach -70A, and also suppresses the output terminal voltage, which could reach -6000V due to a surge voltage. Next, we will consider the drain-source voltage of each FET.

[0057] 5 is a diagram showing an example of changes in the drain-source voltage (potential difference) of each FET of the first switching section 11 observed when the timing of turning on each FET of the first switching section 11 is shifted. Fig. 5 shows changes in voltage value when FET100-16, FET100-15, FET100-14, FET100-13, FET100-12, FET100-11, FET100-10, and FET100-9 are turned on in this order.

[0058] So far, we have seen that by sequentially turning on each FET in the first switching unit 11, the initial inrush current shown in Figure 4 is suppressed, and the surge voltage at the output terminal TMout also tends to be suppressed overall. However, when looking at the voltages of the FETs on the first switching unit 11 side individually, as shown in Figure 5, compared to FET 100-16, which turns on first, the drain-source voltage of the FETs that turn on later increases from the voltage value (approximately -400V) that is applied equally to each FET when it is off. It was also found that the voltage of FET 100-9, which turns on last, increases to -850V.

[0059] Therefore, in the switching circuit 1 of this embodiment, the FETs of the first switching section 11 are turned on in sequence, and a capacitor 200 is provided for FET 100-9, which is the last to be turned on after the inrush current has sufficiently decreased, to suppress the rise in the drain-source voltage.

[0060] Fig. 6 is an explanatory timing chart of the timing signal t1 that turns on and off each FET of the first switching unit 11. The output terminal voltage waveform shown in Fig. 6(a) is an enlarged view of the voltage waveform that first swings during the first on-operation of the first switching unit 11 during the continuous operation period shown in Fig. 4(b). The eight series-connected FETs of the first switching unit 11 are turned on with a staggered turn-on so that all eight series-connected FETs are turned on by the time T required for the voltage waveform to reach its first peak.

[0061] For example, as shown in FIG. 6(b), the time T is set to 7 (eight, the number of FETs in the first switching unit 11, minus one) divided by 7 (hereinafter referred to as the staggered time). FETs in the first switching unit 11 are turned on in the following order, FET16 (corresponding to FET100-16), FET15 (corresponding to FET100-15), FET14 (corresponding to FET100-14), FET13 (corresponding to FET100-13), FET12 (corresponding to FET100-12), FET11 (corresponding to FET100-11), FET10 (corresponding to FET100-10), and FET9 (corresponding to FET100-9), with a staggered time Δt (=T / 7). In FIG. 6(a), the time T is approximately 47 ns, so each staggered time is approximately 6.7 ns. The staggered time may be constant or may be varied depending on the characteristics of the FETs to be turned on with a staggered time. Furthermore, although the shift time is divided by 7 based on time T, it is not limited to time T. The value shifted from time T may also be divided by 7. In that case, FET 9 is turned on before or after time T. Furthermore, although the shift time is divided by 7 in this embodiment, this may be changed depending on the number of FETs in the first switching unit 11. For example, if the first switching unit 11 is configured with four FETs, the shift time is set to a value obtained by dividing time T by 3, which is the number of FETs in the first switching unit 11, which is four, minus one.

[0062] The time T required for the above voltage waveform to reach its first peak can be calculated. For example, if the inductance L is the sum of the inductance of the wiring on the power supply line side and the wiring on the reference potential side, the resonant frequency is given by the following equation:

[0063] Resonance frequency f=1 / 2π(LC) 1 / 2

[0064] Therefore, the period is the reciprocal of the resonance frequency, so it is 2π(LC). 1 / 2 The time T to reach the peak voltage is the half cycle π(LC) 1 / 2 is.

[0065] The time T shown in Figure 6(b) corresponds to the time it takes for the voltage waveform to reach its first peak during the first continuous operation period after startup. Figure 6(c) shows the timing chart for the first two continuous operation periods. The explanation for the third and subsequent periods is repeated and will be omitted.

[0066] Sync in Figure 6(c) indicates the timing of switching between a continuous operation period and a pause period, with a high level indicating a continuous operation period and a low level indicating a pause period. Here, the second continuous operation period and the pause period are shown.

[0067] FET16, FET15, ..., FET10 in Figures 6(b) and 6(c) each show the timing of switching between on and off at the first frequency, with a high level indicating on and a low level indicating off.

[0068] FET16, FET15, ..., FET10 have different timings for starting to turn on only during the first on-period of the continuous operation period, so the pulse widths of the timing signals during this on-period are different for each. From the first off-period of the continuous operation period, on- and off-periods are repeated at the same timing, and from the second on-period of the continuous operation period, the pulse widths of the timing signals for FET16, FET15, ..., FET10 become the same. Note that when Sync goes low and a pause period begins, the switching operations of the first switching unit 11 and the second switching unit 12 are paused. Because of this pause period, no current flows through the load circuit 14, and so in the next continuous operation period, the timings for starting to turn on each FET are controlled to be different during the first on-period of the continuous operation period, just as in the first continuous operation period after startup.

[0069] FET9 is the last to be turned on, following FET16, FET15, FET14, FET13, FET12, FET11, and FET10. FET9, which is turned on last, has the highest drain-source voltage rise, but the voltage rise is suppressed by capacitor 200. After being turned on, FET9 does not turn on and off during the continuous operation period like the other FETs, but remains on during the continuous operation period. However, FET9 also turns off during the pause period.

[0070] In the above example, the FETs of the first switching unit 11 are turned on in the following order: FET16, FET15, FET14, FET13, FET12, FET11, FET10, and FET9. However, the order is not limited to this. For example, the FETs may be turned on in the following order: FET9, FET10, FET11, FET12, FET13, FET14, FET15, and FET16.

[0071] This is because, considering the stray capacitance between the source terminal of each FET and the reference potential, the apparent drain-source capacitance of FET 16 on the power supply line (-E) side is larger than that of FET 9 on the output terminal TMout side, so it is thought that the voltage rise of each FET can be suppressed while suppressing the voltage rise of the output terminal TMout. Of course, the FETs may be turned on in a different order.

[0072] FIG. 7 is a diagram showing an example of changes in the drain-source voltage (potential difference) of each FET of the first switching section 11 observed in the switching circuit 1 of this embodiment.

[0073] As shown in Figure 7(a), during the off period before each FET is turned on, FET 9 shows a lower voltage value than the other FETs because of the presence of capacitor 20. FET 9 is turned on last, but the voltage rise is suppressed to 800 V compared to Figure 5.

[0074] 7(b) shows the change in the drain-source voltage of FET 9 of first switching unit 11 and the other FETs of first switching unit 11 up to the second on-period of the continuous operation period. As shown in FIG. 7(b), FET 9 remains on during the continuous operation period, so the drain-source voltage value of FET 9 converges to 0 V. The voltage values ​​of the other FETs converge during their off-periods.

[0075] As described above, in the switching circuit 1 of this embodiment, during the initial on-period in which the first switching unit 11 is turned on during a continuous operation period, the timing at which each FET in the first switching unit 11 is turned on is staggered, and the FET provided with capacitor 200 is turned on last. Thereafter, during the continuous operation period, the FET provided with capacitor 200 remains on, and the other FETs are switched on and off simultaneously as usual. This suppresses the overall surge voltage that occurs during the initial on-period in the continuous operation period, and also suppresses the rise in drain-source voltage of each FET in the first switching unit 11 that occurs when each FET in the first switching unit 11 is turned on in sequence, further improving the effectiveness of preventing FET damage.

[0076] The configuration of the switching circuit 1 of this embodiment is advantageous in terms of cost and response speed compared to a method of controlling the input voltage of a converter or inverter by placing a DC-DC converter with a soft start function in the upstream stage.

[0077] Although the soft start function can suppress inrush current and surge voltage, it takes several to several tens of cycles for the voltage to rise. Therefore, when the first switching unit 11 and the second switching unit 12 perform a switching operation in which they repeatedly turn on and off complementarily at a first frequency higher than the second frequency during a continuous operation period as described above, if the soft start function is applied, the continuous operation period ends during the soft start, and sufficient voltage cannot be generated.

[0078] In contrast, with the configuration of the switching circuit 1 of this embodiment, as shown in FIG. 7(b), it is possible to suppress inrush current and surge voltage even for a short time, such as within one cycle of the first frequency, and generate a desired voltage in a short time.

[0079] (Modification 1 of the embodiment) This embodiment can be appropriately applied to any configuration in which a first switching unit and a second switching unit are connected in series to switch elements, the output terminal is connected to a load circuit, and the voltage at the output terminal gradually increases. This embodiment is not limited to the configuration shown as an example of the switching circuit 1, and may be appropriately modified.

[0080] 8A and 8B are diagrams illustrating an example of the configuration of a switching circuit 1 according to a first modification of the embodiment. Fig. 8A shows an example in which the capacitor 200 is provided in the FETs 10-16 as a modification of the position of the capacitor 200 provided in the FETs. The capacitor 200 may be disposed in a position other than that shown in Fig. 8A, and it is sufficient that the capacitor 200 is provided for any one of the FETs in the first switching unit 11.

[0081] The order in which the FETs of the first switching unit 11 are turned on is the same as in the previous explanation, with the FET provided with the capacitor 200 being turned on last. The order in which the FETs other than the FET provided with the capacitor 200 are turned on is not particularly limited. Even if the order is changed as appropriate depending on the design, the same effect can be obtained in either case.

[0082] 8(b) shows a modified example of the number of FETs. As an example, the first switching unit 11 has nine FETs, and the second switching unit 12 has eight FETs, for a total of 17 FETs. The FETs in the first switching unit 11 are composed of FETs (FETs 100-9 to FET 100-16) as first switch elements and FET 100-17 as a second switch element. In other words, by providing the capacitor 200, even after turning on the FET 100-17 functioning as the second switch element, the first switching unit 11 and the second switching unit 12 can have the same number of FETs, allowing for simultaneous on / off operations of eight FETs each.

[0083] In this way, even if the number of FETs in the first switching section 11 is different from the number of FETs in the second switching section 12, the capacitor 200 can be externally attached to any FET among FETs 100-9 to FETs 100-17, and that FET can function as a second switch element.

[0084] In the above, an example is shown in which the number of FETs on the first switching unit 11 side is equal to or greater than the number of FETs on the second switching unit 12 side, but the number of FETs on the first switching unit 11 side may be less than the number of FETs on the second switching unit 12 side.

[0085] FIG. 8(c) shows the configuration of the switching circuit 1 for positive voltage output. In the case of positive voltage output, node Nin1 at the other end of the first switching unit 11 is connected to the positive power supply line (+E), and node Nin2 at the other end of the second switching unit 12 is connected to a reference potential (for example, 0 V). The configuration of the FETs in the first switching unit 11 and the second switching unit 12 is the same as that for the configuration for negative voltage output. In other words, in the configuration for positive voltage output, as in the configuration for negative voltage output, for example, a capacitor 200 is provided for FETs 100-9 in the first switching unit 11, and the FETs in the first switching unit 11 are turned on in order, with the last FET 100-9 being turned on. The same effect as that of the configuration for negative voltage output can be obtained with the configuration for positive voltage output.

[0086] As with the negative voltage output configuration, the positive voltage output configuration is not limited in terms of the number of FETs or the arrangement of the FETs where the capacitor 200 is provided, and may be modified as appropriate.

[0087] (Modification 2 of the embodiment) In the embodiment, an example in which the capacitor 200 is provided in the FET has been shown, but the present invention is not limited to the capacitor 200 .

[0088] FIG. 9 is a diagram illustrating an example of a configuration according to Modification 2 of the embodiment. As an example, FET 100-9 (see FIG. 2) that functions as a second switch element is illustrated, and an example configuration is shown in which the element connected between the drain and source is different from the capacitor 200 shown in the embodiment. As an example, a configuration including a resistor 300 is shown. By providing the resistor, the impedance between the drain and source becomes lower than that of the other FETs in the first switching unit 11, so that the drain-source voltage is low even when the first switching unit 11 is off. Therefore, as shown in FIG. 7(a), in the off period before each FET in the first switching unit 11 is turned on, FET 9 exhibits a lower voltage value than the other FETs.

[0089] 9(a) shows an example of the configuration of a CR circuit in which a capacitor 200 and a resistor 300 are connected in series between the drain and source of an FET 100-9. Adding the capacitor 200 can reduce the generated vibration.

[0090] 9(b) shows an example in which only a resistor 300 is provided between the drain and source of the FET 100-9. Since inrush current can be suppressed even when only the resistor 300 is provided, either the capacitor 200 or the resistor 300 may be appropriately selected and applied.

[0091] 9(c) is an example of a CR parallel circuit configuration in which a capacitor 200 and a resistor 300 are connected in parallel between the drain and source of an FET 100-9. In the configurations of FIGS. 9(a) and 9(b), the inrush current I is large, and care must be taken to ensure that a voltage exceeding the withstand voltage of the FET is not applied due to the resistance value R multiplied by the inrush current I. Therefore, a CR parallel circuit configuration in which CRs are connected in parallel may also be used.

[0092] Any of the configurations shown in Figures 9(a), 9(b), and 9(c) has the effect of suppressing the rise in voltage between the drain and source of each FET of the first switching section 11 that occurs when each FET of the first switching section 11 is turned on in sequence.

[0093] (Modification 3 of the embodiment) The number of FETs in the first switching unit 11 and the second switching unit 12 may be determined appropriately depending on the circuit used and the withstand voltage. As long as there are at least a plurality of FETs in the first switching unit 11, and the number of FETs in the second switching unit 12 is not limited as long as they have the withstand voltage.

[0094] 10 is a diagram showing an example of the configuration of FETs according to Modification 3 of the embodiment. As an example, the first switching unit 11 and the second switching unit 12 each have two FETs, resulting in a four-FET configuration. In this case, since the first switching unit 11 has two FETs, a capacitor 200 is provided on the FET 100-3. Of course, the capacitor 200 may also be provided on the FET 100-4 side.

[0095] The order in which the FETs of the first switching unit 11 are turned on is the same as in the previous explanations, with the FET provided with the capacitor 200 being turned on last. The configuration according to the third modification can also achieve the same effects as those of the embodiment.

[0096] 2 or the element shown in Fig. 9 can be provided to the FET that functions as the first switch element among the FETs in the first switching section 11. In short, it is sufficient that the FET that functions as the second switch element is the last to be turned on in the first switching section 11.

[0097] (Timing signal output section) FIG. 11 illustrates an exemplary configuration of the timing signal output unit 13. The timing signal output unit 13 illustrated in FIG. 11 is, for example, a digital configuration, in which a counter counts the shift time (T / 7) based on the oscillation frequency of an oscillator. The counter outputs a signal to the signal output unit at time intervals corresponding to the shift time. The signal output unit then shifts the on-timing of the pulse voltage waveform of timing signal t1 and outputs timing signals with shifted initial on-timings to the gate drive circuits of FETs 16, 15, 14, 13, 12, 11, 10, and 9. The pulse voltage waveform of timing signal t1 is also shown in FIG. 6(c), and therefore further description thereof is omitted. The configuration of the timing signal output unit 13 is merely an example, and a circuit for generating and adjusting timing and outputting timing may be provided as appropriate.

[0098] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. This novel embodiment can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as set forth in the claims. [Explanation of symbols]

[0099] 1 Switching circuit 11 First Switching Section 12 Second Switching Section 13 Timing signal output section 14 Load circuit 100-1, ... 100-16 FET (switch element) 200 capacitors 300 resistor E power supply I inrush current L1, L2 inductance T time Δt Shift time TMout output terminal t1, t2 timing signals

Claims

1. a first switching unit having a plurality of switch elements connected in series; a second switching unit having one end connected to one end of the first switching unit; and The plurality of switch elements include: a first switch element and a second switch element provided with a capacitor; and The other end of the first switching unit is connected to a voltage line having a high absolute value; The other end of the second switching unit is connected to a voltage line having a low absolute value; a load circuit is connected between an output terminal between one end of the first switching unit and one end of the second switching unit and the other end of the second switching unit; In a switching operation of switching on and off the first switching unit and the second switching unit at a first frequency, the first switching unit shifts the timings at which the plurality of switch elements of the first switching unit are turned on at a first on timing, and turns on the second switch element last; After the second switch element is finally turned on, the switching operation is performed while the second switch element is maintained on. A switching circuit characterized by:

2. the first switching unit and the second switching unit perform a switching operation of repeating turn-on and turn-off complementarily at the first frequency during a continuous operation period defined by a predetermined on-duty ratio in a repetition cycle period of a second frequency lower than the first frequency, and the first switching unit and the second switching unit are configured to suspend their switching operations during a suspend period defined by a predetermined off-duty ratio; the first switching unit shifts the timings at which the plurality of switch elements of the first switching unit are turned on at a first on timing of the continuous operation period, and turns on the second switch element last; After the second switch element is finally turned on, the switching operation is performed while the second switch element is maintained on during a continuous operation period.

2. The switching circuit according to claim 1.

3. the second switch element has a capacitor provided between a terminal that becomes a high potential side when the first switching unit is off and a terminal that becomes a low potential side; 3. The switching circuit according to claim 1 or 2.

4. The second switch element is provided with a resistor instead of the capacitor.

3. The switching circuit according to claim 1 or 2.

5. the second switch element is provided with a CR circuit or a CR parallel circuit of the capacitor and resistor; 3. The switching circuit according to claim 1 or 2.

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