Display device

Abstract

To provide a display device capable of preventing a leakage current through a common layer between adjacent pixels.SOLUTION: A display device according to the present invention includes a first light-emitting element located on a first reflective electrode, a second light-emitting element located on a second reflective electrode, and a third light-emitting element located on a third reflective electrode, and the first light-emitting element, the second light-emitting element, and the third light-emitting element share a light-emitting structure and a cathode electrode, and the light-emitting structure includes a first light-emitting portion, a second light-emitting portion, and a third light-emitting portion stacked sequentially, and the thickness of the third light-emitting portion is greater than the sum of the thickness of the first light-emitting portion and the thickness of the second light-emitting portion.SELECTED DRAWING: Figure 11b

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a medium connecting users with information, is increasing. Accordingly, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) is increasing.

[0003] Display devices use pixels to display images. To realize AR (Augmented Reality), VR (Virtual Reality), and MR (Mixed Reality), display devices are required to have as many pixels as possible on a small display surface.

[0004] As the spacing between pixels becomes smaller, leakage current through the common layer of adjacent pixels can become a problem. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Application Publication No. 2021-0017179 Summary of the Invention [Problem to be solved by the invention]

[0006] A technical problem to be solved is to provide a display device that can prevent leakage current through a common layer between adjacent pixels. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first light-emitting element positioned on a first reflective electrode, a second light-emitting element positioned on a second reflective electrode, and a third light-emitting element positioned on a third reflective electrode, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element share a light-emitting structure and a cathode electrode, the light-emitting structure includes a first light-emitting section, a second light-emitting section, and a third light-emitting section stacked in sequence, and the thickness of the third light-emitting section is greater than the sum of the thickness of the first light-emitting section and the thickness of the second light-emitting section.

[0008] The thickness of the third light emitting section may be 2.5 times or more the sum of the thickness of the first light emitting section and the thickness of the second light emitting section.

[0009] The thickness of the hole transport section included in the third light emitting section may be greater than the sum of the thickness of the first light emitting section and the thickness of the second light emitting section.

[0010] The display device may further include a separator positioned between the first light-emitting element, the second light-emitting element, and the third light-emitting element, and the light-emitting structure may further include a first charge generation layer positioned between the first light-emitting unit and the second light-emitting unit, and a second charge generation layer positioned between the second light-emitting unit and the third light-emitting unit, the first light-emitting unit, the first charge generation layer, the second light-emitting unit, and the second charge generation layer being separated by the separator, and the cathode electrode being connected to an upper part of the separator.

[0011] The distance between the first transparent electrode and the first reflective electrode of the first light emitting element may be smaller than the distance between the second transparent electrode and the second reflective electrode of the second light emitting element.

[0012] The distance between the second transparent electrode and the second reflective electrode of the second light emitting element may be smaller than the distance between the third transparent electrode and the third reflective electrode of the third light emitting element.

[0013] The first light-emitting unit may include a first light-emitting layer configured to emit light of a first color, the second light-emitting unit may include a second light-emitting layer configured to emit light of a second color, and the third light-emitting unit may include a third light-emitting layer configured to emit light of a third color, and the first color, the second color, and the third color may be different colors from each other.

[0014] The first color may be green, the second color may be blue, and the third color may be red.

[0015] The first light-emitting layer may be located in a first resonance layer of five resonance layers for the first color, the second light-emitting layer may be located in a second resonance layer of six resonance layers for the second color, and the third light-emitting layer may be located in a fourth resonance layer of four resonance layers for the third color.

[0016] The first light-emitting layer may be spaced apart from the third reflective electrode by a distance of 550 Å to 750 Å, the second light-emitting layer may be spaced apart from the second reflective electrode by a distance of 1400 Å to 1600 Å, and the third light-emitting layer may be spaced apart from the first reflective electrode by a distance of 5600 Å to 5800 Å.

[0017] The second transparent electrode and the second reflective electrode of the second light emitting device may be spaced apart by a distance of 150 Å to 350 Å, and the third transparent electrode and the third reflective electrode of the third light emitting device may be spaced apart by a distance of 400 Å to 600 Å.

[0018] The first color may be red, the second color may be blue, and the third color may be green.

[0019] The first light-emitting layer may be located in a first resonance layer of four resonance layers for the first color, the second light-emitting layer may be located in a second resonance layer of six resonance layers for the second color, and the third light-emitting layer may be located in a fifth resonance layer of five resonance layers for the third color.

[0020] The first light-emitting layer may be spaced apart from the first reflective electrode by a distance of 500 Å to 700 Å, the second light-emitting layer may be spaced apart from the second reflective electrode by a distance of 1400 Å to 1600 Å, and the third light-emitting layer may be spaced apart from the third reflective electrode by a distance of 6400 Å to 6600 Å.

[0021] The second transparent electrode and the second reflective electrode of the second light emitting device may be spaced apart by a distance of 200 Å to 400 Å, and the third transparent electrode and the third reflective electrode of the third light emitting device may be spaced apart by a distance of 600 Å to 800 Å.

[0022] The display device may further include a substrate, and a distance between the substrate and the first reflective electrode, a distance between the substrate and the second reflective electrode, and a distance between the substrate and the third reflective electrode may be the same.

[0023] The distance between the cathode electrode of the first light emitting element and the substrate, the distance between the cathode electrode of the second light emitting element and the substrate, and the distance between the cathode electrode of the third light emitting element and the substrate may be different from each other.

[0024] The display device may further include a substrate, and a distance between the substrate and the first reflective electrode, a distance between the substrate and the second reflective electrode, and a distance between the substrate and the third reflective electrode may be different from one another.

[0025] The distance between the cathode electrode of the first light-emitting element and the substrate, the distance between the cathode electrode of the second light-emitting element and the substrate, and the distance between the cathode electrode of the third light-emitting element and the substrate may be the same.

[0026] A wearable device according to one embodiment of the present invention includes a first display panel and a second display panel, each of which includes a first light-emitting element located on a first reflective electrode, a second light-emitting element located on a second reflective electrode, and a third light-emitting element located on a third reflective electrode, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element share a light-emitting structure and a cathode electrode, and the light-emitting structure includes a first light-emitting section, a second light-emitting section, and a third light-emitting section stacked in sequence, and the thickness of the third light-emitting section is greater than the sum of the thickness of the first light-emitting section and the thickness of the second light-emitting section. [Effects of the Invention]

[0027] The display device according to the present invention can prevent leakage current through a common layer between adjacent pixels. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a block diagram illustrating an embodiment of a display device. [Figure 2] FIG. 2 is a block diagram illustrating a sub-pixel. [Figure 3] FIG. 10 is a diagram for explaining an embodiment of a sub-pixel. [Figure 4] FIG. 2 is a plan view showing an embodiment of the display panel of FIG. [Figure 5] FIG. 5 is an exploded perspective view showing a part of the display panel of FIG. [Figure 6] 6 is a plan view showing an embodiment of one of the pixels of FIG. 5. FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line II' in FIG. [Figure 8a] FIG. 8 is a cross-sectional view showing another embodiment of FIG. 7. [Figure 8b] FIG. 8 is a cross-sectional view showing another embodiment of FIG. 7. [Figure 9] 7, 8a, or 8b. FIG. 8B is a cross-sectional view showing an embodiment of a light emitting structure included in any one of the first to third light emitting devices shown in FIG. [Figure 10]7, 8a, or 8b. FIG. 8B is a cross-sectional view showing another embodiment of a light emitting structure included in one of the first to third light emitting devices of FIG. [Figure 11a] FIG. 2 is a diagram illustrating first to third light emitting elements according to an embodiment of the present invention. [Figure 11b] FIG. 2 is a diagram illustrating first to third light emitting elements according to an embodiment of the present invention. [Figure 12] FIG. 2 is a diagram illustrating first to third light emitting elements according to an embodiment of the present invention. [Figure 13a] FIG. 10 is a diagram illustrating first to third light emitting elements according to another embodiment of the present invention. [Figure 13b] FIG. 10 is a diagram illustrating first to third light emitting elements according to another embodiment of the present invention. [Figure 14] FIG. 10 is a diagram illustrating first to third light emitting elements according to another embodiment of the present invention. [Figure 15] 11a, 11b, 13a, and 13b are diagrams illustrating the luminous efficiency of the first to third light-emitting elements according to the examples. [Figure 16] 6 is a plan view showing another embodiment of any one of the pixels of FIG. 5. FIG. [Figure 17] 6 is a plan view showing yet another embodiment of any one of the pixels of FIG. 5. FIG. [Figure 18] FIG. 1 is a block diagram illustrating an embodiment of a display system. [Figure 19] FIG. 19 is a perspective view showing an application example of the display system of FIG. [Figure 20] FIG. 20 shows a head-mounted display device worn by the user of FIG. 19. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0030] In order to clearly explain the present invention, parts that are not relevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components. Therefore, the reference numerals previously described may be used in other drawings.

[0031] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses may be exaggerated to clearly show multiple layers and regions.

[0032] Furthermore, the expression "same" in the explanation can mean "substantially the same." In other words, it can be the same to the extent that a person with ordinary skill in the art would be convinced that it is the same. Other expressions can also be expressions in which "substantially" is omitted.

[0033] FIG. 1 is a block diagram showing an embodiment of a display device. Referring to FIG. 1, a display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0034] The display panel 110 includes sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 via first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 via first to n-th data lines DL1 to DLn.

[0035] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. This allows each of the sub-pixels SP to generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP may constitute one pixel PXL. For example, as shown in FIG. 1, three sub-pixels may constitute one pixel PXL.

[0036] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction via the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to gate control signals GCS. In this embodiment, the gate control signals GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with the timing at which a data signal is applied, etc.

[0037] The gate driver 120 may be arranged on one side of the display panel 110. However, embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be arranged on one side of the display panel 110 and the other side of the display panel 110 opposite to the one side. In this manner, the gate driver 120 may be arranged around the periphery of the display panel 110 in various forms depending on the embodiment.

[0038] The data driver 130 is connected to the sub-pixels SP arranged in a column direction via first to n-th data lines DL1 to DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0039] The data driver 130 can apply data signals having grayscale voltages corresponding to the video data DATA to the first to n-th data lines DL1 to DLn using the voltages from the voltage generator 140. When gate signals are applied to the first to m-th gate lines GL1 to GLm, the data signals corresponding to the video data DATA can be applied to the data lines DL1 to DLn. This allows the corresponding sub-pixels SP to generate light corresponding to the data signals. This allows an image to be displayed on the display panel 110.

[0040] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0041] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 can be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and regulate the adjusted voltage to generate the plurality of voltages.

[0042] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS may be provided to the subpixels SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. In another embodiment, the first power supply voltage VDD or the second power supply voltage VSS may be provided by a device external to the display device 100.

[0043] Additionally, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the subpixel SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the subpixel SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such reference voltage.

[0044] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG from the outside and a control signal CTRL for controlling the display of the input image data IMG. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0045] The controller 150 can convert the input image data IMG to be compatible with the display device 100 or the display panel 110 and output the image data DATA. In an embodiment, the controller 150 can align the input image data IMG to be compatible with the arrangement of the sub-pixels SP and output the image data DATA.

[0046] Two or more of the data driver 130, the voltage generator 140, and the controller 150 can be implemented in a single integrated circuit. As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. In such a case, the data driver 130, the voltage generator 140, and the controller 150 can be functionally separate components within a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a separate component from the driver integrated circuit DIC.

[0047] According to an embodiment, the display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature around the display device 100 and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0048] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In the embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0049] FIG. 2 is a block diagram illustrating a sub-pixel. 2, a sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixels SP is exemplarily shown. The sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0050] The light emitting element LD is connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN, where the first power supply voltage node VDDN is a node that transfers the first power supply voltage VDD of FIG. 1, and the second power supply voltage node VSSN is a node that transfers the second power supply voltage VSS of FIG. 1.

[0051] The anode electrode AE ​​of the light emitting element LD may be connected to a first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to a second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0052] The sub-pixel circuit SPC may be connected to the ith gate line GLi among the first to mth gate lines GL1 to GLm in Fig. 1 and the jth data line DLj among the first to nth data lines DL1 to DLn in Fig. 1. The sub-pixel circuit SPC is configured to control the light emitting element LD in response to signals received via these signal lines.

[0053] The sub-pixel circuit SPC can operate in response to a gate signal received via the ith gate line GLi. The sub-pixel circuit SPC can receive a data signal via the jth data line DLj. For example, the sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to the gate signal. Based on the voltage stored in the sub-pixel circuit SPC, the light-emitting element LD can generate light of a brightness corresponding to the data signal.

[0054] FIG. 3 is a diagram for explaining an embodiment of a sub-pixel. 3, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD. The sub-pixel circuit SPC may include first to fourth transistors T1 to T4 and a storage capacitor Cst.

[0055] The first transistor T1 may have a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to an anode electrode AE ​​of the light emitting element LD. The first transistor T1 may include sub-transistors T1-1 and T1-2 connected in series. The first transistor T1 may be a driving transistor.

[0056] The second transistor T2 may have a gate electrode connected to the ith gate line GLi, a first electrode connected to the jth data line DLj, and a second electrode connected to the first node N1.

[0057] The third transistor T3 may have a gate electrode connected to the second node N2, a first electrode connected to the first power supply voltage node VDDN, and a second electrode connected to the second node N2.

[0058] The fourth transistor T4 has a gate electrode and a first electrode connected to the anode electrode AE ​​of the light emitting element LD, and a second electrode receiving a reference voltage GND. The reference voltage GND may be set to be lower than the first power supply voltage VDD. In one embodiment, the reference voltage GND may be the same as the second power supply voltage VSS. In another embodiment, the reference voltage GND may be different from the second power supply voltage VSS.

[0059] The storage capacitor Cst may have a first electrode connected to a first power supply voltage node VDDN and a second electrode connected to a first node N1.

[0060] The light emitting device LD may include an anode electrode AE, a cathode electrode CE, and a light emitting structure, which may be disposed between the anode electrode AE ​​and the cathode electrode CE.

[0061] When a gate signal of a turn-on level (e.g., a low level) is applied to the ith gate line GLi, the second transistor T2 may be turned on. At this time, a data signal applied to the jth data line DLj may be applied to the first node N1 through the second transistor T2. The storage capacitor Cst may maintain the voltage of the data signal. In response to the voltage of the data signal, the first transistor T1 may determine the amount of driving current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light with a brightness corresponding to the amount of driving current.

[0062] The third transistor T3 and the fourth transistor T4 are transistors connected in the form of a diode, and can limit the direction of current so that current does not flow in the reverse direction. Depending on the embodiment, the third transistor T3 and the fourth transistor T4 may be omitted from the sub-pixel circuit SPC. When the third transistor T3 is omitted, the second node N2 may be directly connected to the first power supply voltage node VDDN.

[0063] The first to fourth transistors T1 to T4 may be P-type transistors. Each of the transistors T1 to T4 may be a MOSFET (Metal Oxide Silicon Field Effect Transistor). However, embodiments are not limited thereto. For example, at least one of the transistors T1 to T4 may be replaced with an N-type transistor.

[0064] In an embodiment, the transistors T1 to T4 may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0065] FIG. 4 is a plan view showing an embodiment of the display panel of FIG. 4, an embodiment of the display panel 110 (DP) of FIG. 1 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0066] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0067] When the display panel DP is used as a display screen for a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to the user's eyes. In such cases, sub-pixels SP with a relatively high degree of integration are required. To increase the integration degree of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the silicon substrate SUB. A display device 100 (see FIG. 1) including the display panel DP formed on the silicon substrate SUB may be called an OLEDoS (OLED on Silicon) display device.

[0068] The sub-pixels SP are arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a pentile pattern. TM The first direction DR1 may be the row direction, and the second direction DR2 may be the column direction.

[0069] Two or more sub-pixels among the plurality of sub-pixels SP can form one pixel PXL.

[0070] Components for controlling the sub-pixels SP may be arranged in the non-display area NDA on the substrate SUB. For example, wiring connected to the sub-pixels SP, such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn in FIG. 1, may be arranged in the non-display area NDA.

[0071] At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 of FIG. 1 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 of FIG. 1 is implemented in the display panel DP but can be disposed in the non-display area NDA. In another embodiment, the gate driver 120 can be realized as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0072] Pads PD are arranged in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP via wiring. For example, the pads PD may be connected to the sub-pixels SP via first to n-th data lines DL1 to DLn.

[0073] The pads PD may interface the display panel DP with other components of the display device 100 (see FIG. 1). In this embodiment, voltages and signals required for operation of the components included in the display panel DP may be provided from the driver integrated circuit DIC of FIG. 1 via the pads PD. For example, the first to n-th data lines DL1 to DLn may be connected to the driver integrated circuit DIC via the pads PD. For example, the first and second power supply voltages VDD and VSS may be received from the driver integrated circuit DIC via the pads PD. For example, if the gate driver 120 is implemented in the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pads PD.

[0074] In one embodiment, the circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film. The driver integrated circuit (DIC) may be mounted on the circuit board and electrically connected to the pads PD.

[0075] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight and / or curved sides. For example, the display area DA can have a polygonal, circular, semicircular, elliptical, or other shape.

[0076] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have an at least partially round display surface. In some embodiments, the display panel DP may be bendable, foldable, or rollable. In such cases, the display panel DP and / or the substrate SUB may comprise a material having flexible properties.

[0077] Figure 5 is an exploded perspective view showing a portion of the display panel of Figure 4. For clarity and simplicity, Figure 5 shows only a schematic representation of the portion of the display panel DP corresponding to two of the pixels PXL1 and PXL2 of Figure 4. The portions of the display panel DP corresponding to the remaining pixels can be similarly configured.

[0078] 4 and 5, each of the first and second pixels PXL1 and PXL2 may include first to third sub-pixels SP1, SP2, and SP3. However, embodiments are not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0079] 5, the first to third sub-pixels SP1, SP2, and SP3 are shown as having a rectangular shape and the same size when viewed in a third direction DR3 that intersects with the first and second directions DR1 and DR2. However, the embodiment is not limited thereto. The first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0080] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a sealing layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0081] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0082] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, wiring, etc. The conductive pattern may include copper, although examples are not limited thereto.

[0083] The circuit elements may include subpixel circuits SPC (see FIG. 2) for the first to third subpixels SP1, SP2, and SP3, respectively. The subpixel circuits SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In an embodiment, if the substrate SUB is a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, if the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes spaced apart from each other in the third direction DR3 with an insulating layer sandwiched therebetween.

[0084] The wirings of the pixel circuit layer PCL may include signal lines, such as gate lines, emission control lines, and data lines, connected to the first to third sub-pixels SP1, SP2, and SP3, respectively. The wirings may further include a wiring connected to the first power supply voltage node VDDN of FIG. 2. The wirings may also include a wiring connected to the second power supply voltage node VSSN of FIG. 2.

[0085] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0086] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can be in contact with circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can include at least one of a reflective electrode and a transparent electrode, but the embodiment is not limited thereto. For example, in the example of FIG. 7 , the anode electrode AE ​​includes a reflective electrode and a transparent electrode. However, the anode electrode AE ​​may be configured to include a reflective electrode without including a transparent electrode.

[0087] A pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include openings OP that expose portions of the anode electrode AE. The openings OP in the pixel defining layer PDL can be understood as light-emitting regions corresponding to the first to third sub-pixels SP1 to SP3, respectively.

[0088] In some embodiments, the pixel defining layer PDL may include an inorganic material. In such cases, the pixel defining layer PDL may include multiple stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiOx) and silicon nitride (SiNx). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0089] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0090] In this embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL, but may be entirely disposed on top of the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first to third sub-pixels SP1 to SP3. In this case, at least a portion of a layer in the light emitting structure EMS may be cut or bent at the boundary between the first to third sub-pixels SP1 to SP3. However, this embodiment is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of them may be disposed within the opening OP of the pixel defining layer PDL.

[0091] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. In this manner, the cathode electrode CE may serve as a common electrode for the first to third sub-pixels SP1 to SP3.

[0092] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0093] Any one of the anode electrodes AE, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode electrode CE overlapping it can be understood to constitute one light emitting element LD (see FIG. 2). In other words, each of the light emitting elements of the first to third subpixels SP1 to SP3 includes one anode electrode, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode electrode CE overlapping it. In each of the first to third subpixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported into the light emitting layer of the light emitting structure EMS to form excitons. When the excitons transition from an excited state to a ground state, light can be generated. The brightness of the light can be determined depending on the amount of current flowing through the light emitting layer. The wavelength range of the generated light can be determined depending on the configuration of the light emitting layer.

[0094] An encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE can include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film can include silicon nitride, silicon oxide, silicon oxynitride (SiOxNy), or the like. For example, the organic film can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic film and inorganic film of the sealing layer TFE are not limited to these.

[0095] In order to improve the sealing efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include a thin film containing aluminum oxide (AlOx). The thin film containing aluminum oxide may be located on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0096] The thin film including aluminum oxide may be formed by atomic layer deposition (ALD). However, embodiments are not limited thereto. The encapsulation layer TFE may further include a thin film formed from at least one of various materials suitable for improving encapsulation efficiency.

[0097] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0098] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter light emitted from the light emitting structures EMS to selectively output light of a wavelength range or color corresponding to each subpixel. The color filter layer CFL includes color filters CF corresponding to the first to third subpixels SP1 to SP3, respectively, and each of these color filters CF can transmit light of a wavelength range corresponding to the corresponding subpixel. For example, the color filter corresponding to the first subpixel SP1 can transmit red light, the color filter corresponding to the second subpixel SP2 can transmit blue light, and the color filter corresponding to the third subpixel SP3 can transmit green light. Depending on the light emitted from the light emitting structures EMS of each subpixel, at least some of the color filters CF may be omitted.

[0099] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0100] In this embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first and second directions DR1 and DR2 relative to the apertures OP of the pixel definition layer PDL. Specifically, in the central region of the display area DA, the centers of the color filters and the lenses may be aligned with or overlap with the centers of the apertures OP of the corresponding pixel definition layer PDL when viewed from the third direction DR3. For example, in the central region of the display area DA, the apertures OP of the pixel definition layer PDL may completely overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. In a region adjacent to the non-display area NDA in the display area DA, the centers of the color filters and the lenses may be shifted in a planar direction relative to the centers of the apertures OP of the corresponding pixel definition layer PDL when viewed from the third direction DR3. For example, in a region adjacent to the non-display area NDA in the display area DA, the apertures OP of the pixel definition layer PDL may partially overlap with the corresponding color filters of the color filter layer CFL and the corresponding lenses of the lens array LA. As a result, light emitted from the light emitting structure EMS at the center of the display area DA can be efficiently output in the normal direction of the display surface, and light emitted from the light emitting structure EMS at the periphery of the display area DA can be efficiently output in a direction inclined at a predetermined angle with respect to the normal direction of the display surface.

[0101] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust and moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC may include epoxy, but examples are not limited thereto. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0102] The cover window CW can be disposed on the overcoat layer OC. The cover window CW is configured to protect layers below it. The cover window CW can have a higher refractive index than the overcoat layer OC. The cover window CW can include glass, but examples are not limited thereto. For example, the cover window CW can be encapsulation glass configured to protect components disposed below it. In other embodiments, the cover window CW can be omitted.

[0103] Figure 6 is a plan view showing an embodiment of any one of the pixels of Figure 5. For clarity and simplicity, Figure 6 only shows a first pixel PXL1 of the first and second pixels PXL1 and PXL2 of Figure 5. The remaining pixels may be configured similarly to the first pixel PXL1.

[0104] 5 and 6, the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0105] The first sub-pixel SP1 includes a first light-emitting region EMA1 and a non-light-emitting region NEA around the first light-emitting region EMA1. The second sub-pixel SP2 includes a second light-emitting region EMA2 and a non-light-emitting region NEA around the second light-emitting region EMA2. The third sub-pixel SP3 includes a third light-emitting region EMA3 and a non-light-emitting region NEA around the third light-emitting region EMA3.

[0106] The first light-emitting region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EMS (see FIG. 5) corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 5, each light-emitting region can be understood as an opening OP in the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0107] FIG. 7 is a cross-sectional view taken along line II' in FIG.

[0108] Referring to FIG. 7, a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0109] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0110] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for the first to third subpixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 for the first subpixel SP1, a transistor T_SP2 for the second subpixel SP2, and a transistor T_SP3 for the third subpixel SP3. The transistor T_SP1 for the first subpixel SP1 may be one of the transistors included in the subpixel circuit SPC for the first subpixel SP1 (see FIG. 2 ), the transistor T_SP2 for the second subpixel SP2 may be one of the transistors included in the subpixel circuit SPC for the second subpixel SP2, and the transistor T_SP3 for the third subpixel SP3 may be one of the transistors included in the subpixel circuit SPC for the third subpixel SP3. For clarity and conciseness, FIG. 7 shows only one of the transistors for each subpixel, and omits the remaining circuit elements.

[0111] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0112] The source region SRA and the drain region DRA may be disposed in a substrate SUB. A well WL formed through an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed spaced apart from each other in the well WL. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0113] The gate electrode GE may be disposed in the pixel circuit layer PCL, overlapping the channel region between the source region SRA and the drain region DRA. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0114] The pixel circuit layer PCL includes a plurality of layers, each of which includes an insulating layer and a conductive pattern disposed between the insulating layer, and the conductive pattern may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connector DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connector SRC that penetrates one or more insulating layers.

[0115] The gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or wiring, so that the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0116] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can each be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0117] In this way, the substrate SUB and the pixel circuit layer PCL can include the circuit elements of each of the first to third sub-pixels SP1 to SP3.

[0118] A via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL but may have an overall flat surface. The via layer VIAL is configured to flatten steps on the pixel circuit layer PCL. The via layer VIAL may be configured to include an inorganic material. For example, the via layer VIAL may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon carbon nitride (SiCN), but examples are not limited thereto. The via layer VIAL may also be configured to include an organic material.

[0119] The light-emitting element layer LDL is disposed on the via layer VIAL. The light-emitting element layer LDL can include first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, first to third transparent electrodes TE1 to TE3, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE. The first anode electrode AE1 includes a first reflective electrode RE1 and a first transparent electrode TE1, the second anode electrode AE2 includes a second reflective electrode RE2 and a second transparent electrode TE2, and the third anode electrode AE3 includes a third reflective electrode RE3 and a third transparent electrode TE3.

[0120] First to third reflective electrodes RE1 to RE3 are disposed on the via layer VIAL for the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 can be in contact with a circuit element disposed in the pixel circuit layer PCL through a via that penetrates the via layer VIAL.

[0121] The first to third reflective electrodes RE1 to RE3 may function as full mirrors that reflect light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom, but examples are not limited thereto.

[0122] In an embodiment, a connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode may improve electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multi-layer structure. The multi-layer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be located between multiple layers of connecting electrodes.

[0123] At least one buffer pattern BFP1, BFP2 may be disposed under at least one of the first to third reflective electrodes RE1, RE2, RE3. The buffer patterns BFP1, BFP2 may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. By disposing the buffer patterns BFP1, BFP2, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the first buffer pattern BFP1 and the second buffer pattern BFP2 are disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1. The first buffer pattern BFP1 is disposed between the second reflective electrode RE2 and the via layer VIAL to adjust the height of the second reflective electrode RE2. Therefore, the distance between the substrate SUB and the first reflective electrode RE1, the distance between the substrate SUB and the second reflective electrode RE2, and the distance between the substrate SUB and the third reflective electrode RE3 may be different from one another. Here, the distance refers to the distance in the third direction DR3.

[0124] The first to third reflective electrodes RE1 to RE3 may function as full mirrors, and the cathode electrode CE may function as a half mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially traveling back and forth between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE may be understood to be a resonance distance for the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0125] The first subpixel SP1 may have a shorter resonance distance than the second and third subpixels SP2 and SP3 due to the first and second buffer patterns BFP1 and BFP2. This adjusted resonance distance allows light in a specific wavelength range to be effectively and efficiently amplified. This allows the first subpixel SP1 to effectively and efficiently output light in the corresponding wavelength range. For example, light in a specific wavelength range having a resonance distance corresponding to the distance between the first reflective electrode RE1 and the cathode electrode CE is effectively and efficiently amplified and output from the first subpixel SP1. The second subpixel SP2 may have a longer resonance distance than the first subpixel SP1 but shorter than the third subpixel SP3 due to the first buffer pattern BFP1. For example, light in a specific wavelength range having a resonance distance corresponding to the distance between the second reflective electrode RE2 and the cathode electrode CE (> the distance between the first reflective electrode RE1 and the cathode electrode CE) is effectively and efficiently amplified and output from the second subpixel SP2. The third sub-pixel SP3 may not include a buffer pattern and may have a longer resonance distance than the first and second sub-pixels SP1 and SP2. For example, light in a specific wavelength range having a resonance distance corresponding to the distance between the third reflective electrode RE3 and the cathode electrode CE (> the distance between the second reflective electrode RE2 and the cathode electrode CE) is effectively and efficiently amplified and output from the third sub-pixel SP3.

[0126] In other embodiments, the third subpixel SP3 may be configured to include a buffer pattern, and the first subpixel SP1 and the second subpixel SP2 may be configured not to include a buffer pattern. That is, whether each subpixel includes a buffer pattern may vary depending on the embodiment.

[0127] In order to flatten the steps of the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL entirely covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, but may have a flat surface. Therefore, the distance between the portion of the cathode electrode CE corresponding to the first light-emitting element LD1 and the substrate SUB, the distance between the portion of the cathode electrode CE corresponding to the second light-emitting element LD2 and the substrate SUB, and the distance between the portion of the cathode electrode CE corresponding to the third light-emitting element LD3 and the substrate SUB may be the same.

[0128] In some embodiments, at least a portion of the planarization layer PLNL may be omitted. In one embodiment, the planarization layer PLNL may not be present on at least one reflective electrode (e.g., the first reflective electrode RE1). In the example of FIG. 7, the first transparent electrode TE1 is directly connected to the first reflective electrode RE1, as described below, and no planarization layer PLNL is present between the first reflective electrode RE1 and the first transparent electrode TE1.

[0129] First to third transparent electrodes TE1 to TE3 are disposed on the planarization layer PLNL, overlapping the first to third reflective electrodes RE1 to RE3, respectively. The first to third transparent electrodes TE1 to TE3 may have shapes similar to the first to third light-emitting regions EMA1 to EMA3 of FIG. 6 when viewed from the third direction DR3. The first to third transparent electrodes TE1 to TE3 are connected to the first to third reflective electrodes RE1 to RE3, respectively. The first transparent electrode TE1 may be directly connected to the first reflective electrode RE1. In another example, the first transparent electrode TE1 may be connected to the first reflective electrode RE1 through a first via that penetrates the planarization layer PLNL. The second transparent electrode TE2 may be connected to the second reflective electrode RE2 through a second via VIA2 that penetrates the planarization layer PLNL. The third transparent electrode TE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the planarization layer PLNL. 7, the first to third transparent electrodes TE1 to TE3 are formed on a planarizing layer PLNL, and the height positions of the first to third transparent electrodes TE1 to TE3 are approximately the same. Therefore, the distances between the first to third transparent electrodes TE1 to TE3 and the cathode electrode CE are approximately the same. In other words, the distances in the height direction (third direction DR3) of a light-emitting structure EMS (described below) located between the first to third transparent electrodes TE1 to TE3 and the cathode electrode CE are approximately the same.

[0130] In an embodiment, the first to third transparent electrodes TE1 to TE3 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). However, the material of the first to third transparent electrodes TE1 to TE3 is not limited thereto. For example, the first to third transparent electrodes TE1 to TE3 may include titanium nitride.

[0131] In the embodiment, an insulating layer may be further provided to adjust the height of one or more of the first to third transparent electrodes TE1 to TE3. The insulating layer may be disposed between one or more of the first to third transparent electrodes TE1 to TE3 and the corresponding reflective electrode. In this case, the planarizing layer PLNL and / or the buffer pattern BFP may be omitted. For example, in the third sub-pixel SP3, the third reflective electrode RE3 is formed on the via layer VIAL. In the second sub-pixel SP2, an insulating layer having a predetermined second thickness is formed on the via layer VIAL, and the second reflective electrode RE2 is formed on the insulating layer having the second thickness. In the first sub-pixel SP1, an insulating layer having a predetermined first thickness (>second thickness) is formed on the via layer VIAL, and the first reflective electrode RE1 is formed on the insulating layer having the second thickness. In an example similar to that shown in Figure 7, an insulating layer is arranged to cover the second and third reflective electrodes RE2 and RE3, a first transparent electrode TE1 is formed on the first reflective electrode RE1, and second and third transparent electrodes TE2 and TE3 are formed to overlap the second and third reflective electrode RE2, respectively, via the insulating layer. 7, the first transparent electrode TE1 is formed so as to be in contact with the first reflective electrode RE1. However, layers such as a planarizing layer PLNL and an insulating layer may be disposed between the first reflective electrode RE1 and the first transparent electrode TE1.

[0132] A pixel defining film PDL is disposed on portions of the first to third transparent electrodes TE1 to TE3 and the planarizing layer PLNL. The pixel defining film PDL may include openings OP that expose portions of the first to third transparent electrodes TE1 to TE3. The openings OP in the pixel defining film PDL can define the light-emitting regions of the first to third sub-pixels SP1 to SP3. In this way, the pixel defining film PDL can define the first to third light-emitting regions EMA1 to EMA3 in FIG. 6 by being disposed in the non-light-emitting region NEA in FIG. 6. The first to third light-emitting regions EMA1 to EMA3 in FIG. 6 correspond to the first to third light-emitting elements LD1 to LD3 in the example of FIG. 7, respectively.

[0133] In an embodiment, the pixel defining film PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx). For example, the pixel defining film PDL may include first to third inorganic insulating layers stacked in sequence, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited thereto. The first to third inorganic insulating layers may have a stepped cross section in a region adjacent to the opening OP. In an embodiment, the pixel defining film PDL may be configured to include an organic material.

[0134] A separator SPR may be provided in the boundary region BDA between adjacent sub-pixels, in other words, a separator SPR may be provided in each of the boundary regions between the sub-pixels SP in FIG.

[0135] The separator SPR may cause a discontinuity to form in the light emitting structure EMS at the boundary region BDA, for example, the separator SPR may cause the light emitting structure EMS to break or bend at the boundary region BDA.

[0136] The separator SPR may be provided in or on the pixel defining film PDL. The pixel defining film PDL may include one or more trenches TRCH1, TRCH2 as separators SPR in the boundary region BDA. In an embodiment, as shown in FIG. 7, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and partially penetrate the planarization layer PLNL. In another embodiment, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and the planarization layer PLNL and partially penetrate the via layer VIAL. In another embodiment, one or more trenches TRCH1, TRCH2 may partially penetrate the pixel defining film PDL. In another embodiment, one or more trenches TRCH1, TRCH2 may at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining film PDL may be disposed within one or more trenches TRCH1, TRCH2.

[0137] 7 illustrates two trenches TRCH1 and TRCH2 provided in the boundary region BDA. However, embodiments are not limited thereto. For example, the pixel definition layer PDL may include one trench in the boundary region BDA. Alternatively, the pixel definition layer PDL may include three or more trenches in the boundary region BDA.

[0138] The first and second trenches TRCH1 and TRCH2 may form discontinuous portions such as a first void VD1 and a second void VD2 in the boundary region BDA in the light emitting structure EMS. Some of the layers stacked in the light emitting structure EMS may be cut or bent by the first and second voids VD1 and VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be cut by the first and second voids VD1 and VD2. In this way, the first and second trenches TRCH1 and TRCH2 may at least partially separate the portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3.

[0139] 7, first and second voids VD1 and VD2 are formed in the light emitting structure EMS at the boundary region BDA, but this is merely an example and the embodiment is not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS at the boundary region BDA. The discontinuities formed in the light emitting structure EMS may be variously changed depending on the shapes of the first and second trenches TRCH1 and TRCH2. Furthermore, as long as it is possible to reduce the current flowing between adjacent subpixels, the shape and number of the trenches TRCH1 and TRCH2 and the shape and number of the first and second voids VD1 and VD2 are not limited to the above embodiments. For example, the trenches TRCH1 and TRCH2 may be formed to completely penetrate the pixel definition film PDL or only partially penetrate it. The trenches TRCH1 and TRCH2 may be formed to completely penetrate the planarization layer PLNL or only partially penetrate it. The trenches TRCH1 and TRCH2 may be formed to penetrate across adjacent layers above and below. The trenches TRCH1 and TRCH2 may be formed from the planarization layer PLNL to the via layer VIAL below it. The length of the trenches TRCH1 and TRCH2 penetrating the pixel definition film PDL and the like in the vertical direction (third direction DR3) can be set in consideration of the degree to which current flowing between adjacent subpixels can be reduced. The voids VD1 and VD2 may be formed to completely penetrate the light emitting structure EMS or only partially penetrate it. The voids VD1 and VD2 may be formed to completely penetrate the pixel defining film PDL or only partially penetrate it. The voids VD1 and VD2 may be formed to penetrate across adjacent layers above and below. The voids VD1 and VD2 may be formed from the pixel defining film PDL to the underlying planarization layer PLNL. The length of the voids VD1 and VD2 penetrating the light emitting structure EMS in the vertical direction (third direction DR3) can be set in consideration of the degree to which current flowing between adjacent subpixels can be reduced. In the above description, the trenches TRCH1, TRCH2 and the voids VD1, VD2 are defined separately, and in one embodiment, the voids VD1, VD2 are formed so as to be continuous with the trenches TRCH1, TRCH2 above. However, the trenches TRCH1, TRCH2 and the voids VD1, VD2 may be defined as an isolation portion or the like as a single entity. 7, for example, between the second subpixel SP2 and the third subpixel SP3, the trench TRCH1 and the void VD1 are formed on the side adjacent to the second subpixel SP2, and between the second subpixel SP2 and the third subpixel SP3, the trench TRCH2 and the void VD2 are formed on the side adjacent to the third subpixel SP3. However, as long as the current flowing between adjacent subpixels can be reduced, only one trench and void may be formed between adjacent subpixels, or three or more trenches and voids may be formed. The trenches TRCH1, TRCH2 and the voids VD1, VD2 may be cavities formed in the light emitting structure EMS, the pixel defining layer PDL, the planarization layer PLML, etc. The hollow trenches TRCH1, TRCH2 and the voids VD1, VD2 can be formed, for example, but not limited to, by etching the portions where the trenches TRCH1, TRCH2 and the voids VD1, VD2 will be formed after the planarization layer PLNL and the pixel defining layer PDL are formed. Alternatively, the hollow trenches TRCH1, TRCH2 and the voids VD1, VD2 can be formed by filling the portions formed by etching with a filler such as a volatile organic substance, laminating the light emitting structure EMS, and volatilizing the filler by, for example, heat treatment. However, the formation method is not limited thereto, as long as the trenches TRCH1, TRCH2 and the voids VD1, VD2 can be formed. Furthermore, the trenches TRCH1, TRCH2 and the voids VD1, VD2 are not limited to being hollow, and may be formed of, for example, a material that can prevent current from flowing between adjacent subpixels, such as an insulating layer, etc. For example, but not limited to, the trenches TRCH1, TRCH2 and the voids VD1, VD2 can be formed by filling the hollow portions with a material such as an insulating layer.

[0140] In the embodiment, the light emitting structure EMS may be formed through a process such as vacuum deposition, inkjet printing, etc. In this case, the same material as the light emitting structure EMS may be located on the bottom surfaces adjacent to the via layers VIAL in the first and second trenches TRCH1 and TRCH2.

[0141] The separator SPR may be provided in various modifications so that the light emitting structure EMS has a discontinuous portion in the boundary region BDA. In some embodiments, an inorganic insulating pattern may be additionally stacked on the pixel defining layer PDL in the boundary region BDA without the first and second trenches TRCH1 and TRCH2. That is, in the above example, the first and second trenches TRCH1 and TRCH2 in the boundary region BDA are at least a part of the separator SPR. However, instead of the first and second trenches TRCH1 and TRCH and the first and second voids VD1 and VD2, the inorganic insulating pattern additionally stacked on the pixel defining layer PDL in the boundary region BDA may be at least a part of the separator SPR for blocking current flow between adjacent subpixels. The width (width in a cross-sectional view) of the uppermost inorganic insulating pattern among the additionally stacked inorganic insulating patterns may be larger than the width of the inorganic insulating pattern disposed directly below it. For example, in the boundary region BDA, the first to third inorganic insulating patterns may be sequentially stacked from the pixel defining layer PDL, and the uppermost third inorganic insulating pattern may have a width greater than that of the second inorganic insulating pattern. For example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross section in a cross-sectional view of the boundary region BDA. Depending on the shape of the pixel defining layer PDL, multiple layers included in the light emitting structure EMS may be at least partially cut or bent in the boundary region BDA.

[0142] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and be disposed entirely over the first to third sub-pixels SP1 to SP3. As described above, the light emitting structure EMS may be at least partially torn or bent in the boundary region BDA by the separator SPR. This reduces current flowing from each of the first to third sub-pixels SP1 to SP3 to its adjacent sub-pixel through a layer included in the light emitting structure EMS during operation of the display panel DP. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0143] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be provided commonly to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0144] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE overlapping the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 may constitute a third light emitting element LD3.

[0145] A sealing layer TFE is disposed on the cathode electrode CE. The sealing layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0146] An optically functional layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optically functional layer OFL may be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optically functional layer OFL may be fabricated separately and attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL may also serve to protect underlying layers, including the encapsulation layer TFE.

[0147] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may transmit light of different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red, blue, and green light, respectively.

[0148] In some embodiments, the first to third color filters CF1 to CF3 may partially overlap each other in a border area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0149] The lens array LA is disposed on the color filter layer CFL. The lens array LA can include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 output the light emitted from the first to third light-emitting elements LD1 to LD3, respectively, along intended paths, thereby improving light output efficiency.

[0150] Figures 8a and 8b are cross-sectional views showing another embodiment of Figure 7. In explaining Figures 8a and 8b, explanations of the same content as in Figure 7 will be omitted.

[0151] 8a, unlike the embodiment of FIG 7, the light emitting element layer LDL does not include the planarization layer PLNL and the buffer patterns BFP1, BFP2. The light emitting element layer LDL may include at least one differential film DFL1, DFL2.

[0152] The first to third reflective electrodes RE1, RE2, and RE3 may be located on the via layer VIAL. That is, in the example of FIG. 8a, the first to third reflective electrodes RE1, RE2, and RE3 are located at approximately the same height in the third direction DR3. Because there is no buffer pattern below the first to third reflective electrodes RE1, RE2, and RE3, the distance between the substrate SUB and the first reflective electrode RE1, the distance between the substrate SUB and the second reflective electrode RE2, and the distance between the substrate SUB and the third reflective electrode RE3 may be the same. Here, the distance refers to the distance in the third direction DR3.

[0153] At least one differential insulating film DFL1, DFL2 may be disposed on at least one of the first to third reflective electrodes RE1 to RE3. For example, the first differential insulating film DFL1 may be disposed on the second reflective electrode RE2 and the third reflective electrode RE3. The second differential insulating film DFL2 may be disposed on the third reflective electrode RE3. Thus, as shown in FIG. 8a, in the first sub-pixel SP1, the first transparent electrode TE1 is disposed on the first reflective electrode RE1 so as to be directly connected to the first reflective electrode RE1. In the second sub-pixel SP2, the second transparent electrode TE2 is disposed to overlap the second reflective electrode RE2 with the first differential insulating film DFL1 interposed therebetween. In the third sub-pixel SP3, the third transparent electrode TE3 is disposed to overlap the third reflective electrode RE3 with the first and second differential insulating films DFL1, DFL2 interposed therebetween. Each of the differential insulating films DFL1, DFL2 may include, but is not limited to, at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

[0154] The differential films DFL1 and DFL2 can adjust the height of the cathode electrode CE in the third direction DR3. Therefore, the distance between the portion of the cathode electrode CE corresponding to the first light emitting element LD1 and the substrate SUB, the distance between the portion of the cathode electrode CE corresponding to the second light emitting element LD2 and the substrate SUB, and the distance between the portion of the cathode electrode CE corresponding to the third light emitting element LD3 and the substrate SUB can be different from one another. For example, after forming the first to third reflective electrodes RE1 to RE3, the first to third transparent electrodes TE1 to TE3, and the first and second differential electrodes DFL1 and DFL2, a pixel defining layer PDL having an opening OP and a predetermined height is formed thereon. The depth of the opening OP (the distance between the top surface of each reflective electrode and the top surface of the pixel defining layer PDL) of each of the first to third sub-pixels SP1 to SP3 is different. Next, a light emitting structure EMS is formed on the pixel defining layer OP having the opening OP through a process such as vacuum deposition or inkjet printing. The light emitting structure EMS is formed so that the height of the opening OP of each of the first to third sub-pixels SP1 to SP3 is different. In the example of FIG. 8a, the light emitting structures EMS are stacked so that the distance between the first reflective electrode RE1 and the cathode electrode CE is smaller than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE is smaller than the distance between the third reflective electrode RE3 and the cathode electrode CE. 8a, the light emitting structure EMS is laminated so that the distance between the pixel defining film PDL and the cathode electrode CE is approximately the same in the portions other than the openings OP. Also, in the example of Fig. 8a, the cathode electrode CE is recessed downward in the portions corresponding to the openings OP of the first and second sub-pixels SP1 and SP2, and is formed to be at approximately the same height position in other regions.

[0155] For example, the first subpixel SP1 can have a shorter resonance distance than the second and third subpixels SP2 and SP3 because it does not include a differential isotropy film. The second subpixel SP2 can have a longer resonance distance than the first subpixel SP1 but shorter than the third subpixel SP3 because of the first differential isotropy film DFL1. The third subpixel SP3 can have a longer resonance distance than the first and second subpixels SP1 and SP2 because of the first and second differential isotropy films DFL1 and DFL2.

[0156] In other embodiments, the first subpixel SP1 may be configured to include at least one differential isotropic film DFL1, DFL2, and the second subpixel SP2 and the third subpixel SP3 may be configured to not include a differential isotropic film. That is, whether or not each subpixel includes a differential isotropic film may vary depending on the embodiment.

[0157] The first to third transparent electrodes TE1 to TE3 are connected to the first to third reflective electrodes RE1 to RE3, respectively. The first transparent electrode TE1 may be directly connected to the first reflective electrode RE1. In another example, the first transparent electrode TE1 may be connected to the first reflective electrode RE1 through a first via that penetrates the differential film. The second transparent electrode TE2 may be connected to the second reflective electrode RE2 through a second via VIA2 that penetrates the first differential film DFL1. The third transparent electrode TE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the first differential film DFL1 and the second differential film DFL2.

[0158] In the embodiment of Fig. 8b, unlike the embodiment of Fig. 8a, the light-emitting element layer LDL does not include differential films DFL1, DFL2 The light-emitting element layer LDL may include at least one differential pattern DFP1, DFP2.

[0159] At least one differential pattern DFP1, DFP2 may be disposed on at least one of the first to third reflective electrodes RE1 to RE3. For example, the first differential pattern DFP1 may be located on the second reflective electrode RE2. The second differential pattern DFP2 may be located on the third reflective electrode RE3. Each of the differential patterns DFP1, DFP2 may include, but is not limited to, at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

[0160] Each of the differential patterns DFP1 and DFP2 may have an island shape and may have a shape similar to that of the corresponding opening OP of the pixel defining film PDL on a plane. For example, each of the differential patterns DFP1 and DFP2 may be located within the opening OP of the pixel defining film PDL on a plane. For example, the differential patterns DFP1 and DFP2 may overlap with the corresponding opening OP of the pixel defining film PDL in the third direction DR3, but may not overlap with the pixel defining film PDL in the third direction DR3.

[0161] The differential patterns DFP1 and DFP2 can adjust the height of the cathode electrode CE in the third direction DR3. For example, the thickness of the second differential pattern DFP2 may be greater than the thickness of the first differential pattern DFP1. Therefore, the distance between the portion of the cathode electrode CE corresponding to the first light-emitting element LD1 and the substrate SUB, the distance between the portion of the cathode electrode CE corresponding to the second light-emitting element LD2 and the substrate SUB, and the distance between the portion of the cathode electrode CE corresponding to the third light-emitting element LD3 and the substrate SUB may be different from one another.

[0162] For example, the first subpixel SP1 can have a shorter resonance distance than the second and third subpixels SP2 and SP3 by not including a differential pattern. The second subpixel SP2 can have a longer resonance distance than the first subpixel SP1 but shorter than the third subpixel SP3 by including the first differential pattern DFP1. The third subpixel SP3 can have a longer resonance distance than the first and second subpixels SP1 and SP2 by including the second differential pattern DFP2.

[0163] In other embodiments, the first subpixel SP1 may be configured to include at least one differential pattern DFP1, DFP2, and the second subpixel SP2 and the third subpixel SP3 may be configured to not include a differential pattern. That is, whether or not each subpixel includes a differential pattern may vary depending on the embodiment.

[0164] The first to third transparent electrodes TE1 to TE3 are connected to the first to third reflective electrodes RE1 to RE3, respectively. The first transparent electrode TE1 covers the first reflective electrode RE1, and a lower surface of the first transparent electrode TE1 may be connected to an upper surface of the first reflective electrode RE1. The second transparent electrode TE2 covers the first differential pattern DFP1, and at least a portion of an edge of the lower surface of the second transparent electrode TE2 may be connected to the second reflective electrode RE2. The third transparent electrode TE3 covers the second differential pattern DFP2, and at least a portion of an edge of the lower surface of the third transparent electrode TE3 may be connected to the third reflective electrode RE3. For example, a first differential pattern DFP1 is formed on the second reflective electrode RE2 on the via layer VIAL, and a second differential pattern DFP2 is formed on the third reflective electrode RE3 on the via layer VIAL. Then, a first transparent electrode TE1 is patterned on the first reflective electrode RE1 on the via layer VIAL, a second transparent electrode TE2 is patterned on the second reflective electrode RE2 to cover the first differential pattern DFP1, and a third transparent electrode TE3 is patterned on the third reflective electrode RE3 to cover the second differential pattern DFP2. Then, a pixel defining layer OP having an opening OP is formed, and a light emitting structure EMS is formed through processes such as vacuum deposition and inkjet printing.

[0165] FIG. 9 is a cross-sectional view showing an embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG. 7, FIG. 8a, or FIG. 8b.

[0166] 9, the light emitting structure EMS may have a tandem structure in which the first and second light emitting units EU1 and EU2 are stacked. The light emitting structure EMS may be configured in substantially the same manner in each of the first to third light emitting elements LD1 to LD3 of FIG. 7, 8a, or 8b.

[0167] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0168] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first and second hole transport units HTU1 and HTU2 may have the same configuration as each other or different configurations.

[0169] Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first and second electron transport units ETU1 and ETU2 may have the same configuration as each other or different configurations.

[0170] A connection layer may be disposed between the first light-emitting portion EU1 and the second light-emitting portion EU2 to connect them to each other. The connection layer may be provided in the form of a charge generation layer CGL. In an embodiment, the charge generation layer CGL may have a sequentially stacked structure of an n-dopant layer and a p-dopant layer. The n-dopant layer may be an electron generation layer, and the p-dopant layer may be a hole generation layer. For example, the n-dopant layer of the charge generation layer CGL may be located on the first electron transport portion ETU1, the p-dopant layer of the charge generation layer CGL may be located on the n-dopant layer, and the second hole transport portion HTU2 may be located on the p-dopant layer. For example, the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof, and the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9. However, embodiments are not limited thereto.

[0171] In an embodiment, the first and second light-emitting layers EML1 and EML2 can generate light of different colors. The light emitted from the first and second light-emitting layers EML1 and EML2 can be mixed and viewed as white light. For example, the first light-emitting layer EML1 can generate blue light, and the second light-emitting layer EML2 can generate yellow light. In an embodiment, the second light-emitting layer EML2 can include a stacked structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red and green lights can be mixed to provide yellow light. In such a case, an intermediate layer configured to transport holes and / or block electron transport can be further disposed between the first and second sub-light-emitting layers.

[0172] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of the same color.

[0173] The light emitting structure EMS may be formed by a method such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0174] The first light-emitting unit EU1 and the charge generation layer CGL may be separated by a separator SPR (see FIG. 7, FIG. 8a, or FIG. 8b). According to an embodiment, at least a portion of the second light-emitting unit EU2 may be separated by the separator SPR. This prevents wetting current from flowing through the common layer between adjacent subpixels. The cathode electrode CE may be connected to the top of the separator SPR.

[0175] FIG. 10 is a cross-sectional view showing another embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG. 7, FIG. 8a, or FIG. 8b.

[0176] 10, the light emitting structure EMS' may have a longitudinal structure in which the first to third light emitting units EU1' to EU3' are stacked. The light emitting structure EMS' may be configured in substantially the same manner as the first to third light emitting elements LD1 to LD3 of FIG. 7, 8a, or 8b.

[0177] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0178] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same configuration as each other or different configurations.

[0179] Each of the first to third electron transport units ETU1' to ETU3' can include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' may have the same configuration as each other or different configurations.

[0180] The first charge generation layer CGL1' is disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' is disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0181] In this embodiment, the first to third light emitting layers EML1' to EML3' may generate light of different colors. The light emitted from the first to third light emitting layers EML1' to EML3' may be mixed and perceived as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0182] In other embodiments, two or more of the first to third light emitting layers EML1' to EML3' may generate light of the same color.

[0183] Unlike the illustrations of FIGS. 9 and 10, the light emitting structure EMS of FIG. 7, 8a, or 8b may include one light emitting portion in each of the first to third light emitting elements LD1 to LD3. For example, the first light emitting element LD1 may include a first light emitting portion EU1, the second light emitting element LD2 may include a second light emitting portion EU2, and the third light emitting element LD3 may include a third light emitting portion EU3. In this case, the light emitting portions included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting portion of the first light emitting element LD1 may emit red light, the light emitting portion of the second light emitting element LD2 may emit blue light, and the light emitting portion of the third light emitting element LD3 may emit green light. In this case, unlike the illustrations of FIG. 7, 8a, or 8b, the light emitting portions of the first to third sub-pixels SP1 to SP3 may be separated from each other and each may be disposed within an opening OP of the pixel defining layer PDL. That is, in FIG. 7, FIG. 8a, or FIG. 8b, the light emitting structure EMS is continuously formed across the first to third sub-pixels SP1 to SP3. Therefore, for example, the first light emitting portion EU1 of the first light emitting element LD1, the second light emitting portion EU2 of the second light emitting element LD2, and the third light emitting portion EU3 of the third light emitting element LD3 may be continuously formed adjacent to one another. However, for example, the first light emitting portion EU1 of the first light emitting element LD1 may be formed within the opening OP of the pixel defining film PDL, the second light emitting portion EU2 of the second light emitting element LD2 may be formed within the opening OP of the pixel defining film PDL, and the third light emitting portion EU3 of the third light emitting element LD3 may be formed within the opening OP of the pixel defining film PDL. In this case, the first to third light emitting portions EU1 to EU3 may be separated by the pixel defining film PDL. In such a case, at least some of the color filters CF1 to CF3 may be omitted.

[0184] The first light emitting unit EU1', the first charge generation layer CGL1', the second light emitting unit EU2', and the second charge generation layer CGL2' may be separated by a separator SPR (see FIG. 7, FIG. 8a, or FIG. 8b). According to an embodiment, at least a portion of the third light emitting unit EU3' may be separated by the separator SPR. This prevents leakage current through a common layer between adjacent subpixels. The cathode electrode CE may be connected to the top of the separator SPR.

[0185] 11a, 11b, and 12 are diagrams illustrating first to third light emitting elements according to an embodiment of the present invention.

[0186] Referring to Figures 11a and 11b, a first light-emitting element LD1 located on a first reflective electrode RE1, a second light-emitting element LD2 located on a second reflective electrode RE2, and a third light-emitting element LD3 located on a third reflective electrode RE3 are shown. 11a and 11b, for simplicity, the first to third transparent electrodes TE1 to TE3 are depicted as being at the same height in the third direction DR3. However, in reality, the first to third transparent electrodes TE1 to TE3 are at different height positions in the third direction DR3, as shown in FIGS. 8a and 8b. In the third direction DR3, the first transparent electrode TE1 is positioned lower than the second transparent electrode TE2, and the second transparent electrode TE2 is positioned lower than the third transparent electrode TE3. 11a and 11b, for simplicity, the cathode electrode CE is depicted at the same height in the first direction DR1. However, in reality, the height position of the cathode electrode CE in the third direction DR3 varies depending on the portion of the cathode electrode CE corresponding to each of the first to third reflective electrodes RE1 to RE3, as shown in FIGS. 8a and 8b. In the third direction DR3, the portion of the cathode electrode CE corresponding to the first reflective electrode RE1 is located lower than the portion of the cathode electrode CE corresponding to the second reflective electrode RE2, and the portion of the cathode electrode CE corresponding to the second reflective electrode RE2 is located lower than the portion of the cathode electrode CE corresponding to the third reflective electrode RE3.

[0187] The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may share the light emitting structure EMSa and the cathode electrode CE. The light emitting structure EMSa may include a first light emitting portion EU1a, a second light emitting portion EU2a, and a third light emitting portion EU3a, which are sequentially stacked. The layered structure of the light emitting structure EMSa may be the same as the layered structure of the light emitting structure EMS′ of FIG. 10.

[0188] For example, the first light-emitting unit EU1a may include a first hole transport unit HTU1a, a first light-emitting layer GEML1a, and a first electron transport unit ETU1a. The first light-emitting layer GEML1a may be disposed between the first hole transport unit HTU1a and the first electron transport unit ETU1a. The second light-emitting unit EU2a may include a second hole transport unit HTU2a, a second light-emitting layer BEML2a, and a second electron transport unit ETU2a. The second light-emitting layer BEML2a may be disposed between the second hole transport unit HTU2a and the second electron transport unit ETU2a. The third light-emitting unit EU3a may include a third hole transport unit HTU3a, a third light-emitting layer REML3a, and a third electron transport unit ETU3a. The third light-emitting layer REML3a may be disposed between the third hole transport unit HTU3a and the third electron transport unit ETU3a. The first charge generation layer CGL1a is disposed between the first light emitting unit EU1a and the second light emitting unit EU2a, and the second charge generation layer CGL2a is disposed between the second light emitting unit EU2a and the third light emitting unit EU3a.

[0189] As described above, the separator SPR separates the first light-emitting unit EU1a, the first charge generation layer CGL1a, the second light-emitting unit EU2a, and the second charge generation layer CGL2a, thereby preventing leakage current through the common layer between adjacent subpixels. The separator SPR may also separate at least a portion of the third light-emitting unit EU3a. However, the separator SPR must not cut the cathode electrode CE, which is the common electrode. If the separator SPR separates the cathode electrode CE, the second power supply voltage VSS from the second power supply voltage node VSSN may not be transmitted to the cathode electrodes CE of the light-emitting elements LD1, LD2, and LD3, or an IR drop (i.e., voltage drop) of the second power supply voltage VSS may occur.

[0190] In this embodiment, the thickness of the third light-emitting portion EU3a may be greater than the sum of the thicknesses of the first light-emitting portion EU1a and the second light-emitting portion EU2a. For example, the thickness of the third hole transport portion HTU3a included in the third light-emitting portion EU3a may be greater than the sum of the thicknesses of the first light-emitting portion EU1a and the second light-emitting portion EU2a. Here, the thickness refers to the length along the third direction DR3.

[0191] For example, the thickness of the third light-emitting unit EU3a may be 2.5 times or more the sum of the thicknesses of the first light-emitting unit EU1a and the second light-emitting unit EU2a. For example, the thickness of the third hole transport unit HTU3a included in the third light-emitting unit EU3a may be 2.5 times or more the sum of the thicknesses of the first light-emitting unit EU1a and the second light-emitting unit EU2a. For example, the thickness of the third light-emitting unit EU3a may correspond to approximately 2.65 times the sum of the thicknesses of the first light-emitting unit EU1a, the first charge generation layer CGL1a, and the second light-emitting unit EU2a.

[0192] According to this embodiment, the first light-emitting unit EU1a, the first charge generation layer CGL1a, the second light-emitting unit EU2a, and the second charge generation layer CGL2a are separated by the separator SPR, and the cathode electrode CE can be unseparated by the separator SPR.

[0193] In this case, the thickness of the third light emitting unit EU3a or the third hole transport unit HTU3a can be increased, but this increases the power consumption for emitting light at the same brightness and makes it difficult to adjust the resonance distance. Below, a configuration for adjusting the resonance distance according to the thickness conditions will be described.

[0194] 11a, 11b, and 12, the first light-emitting layer GEML1a can be configured to emit green light, the second light-emitting layer BEML2a can be configured to emit blue light, and the third light-emitting layer REML3a can be configured to emit red light.

[0195] For example, a first color filter CF1 that transmits red light may be disposed above the first light emitting element LD1 (see FIG. 7, 8a, or 8b). The first light emitting element LD1 is an element for emitting red light, and the resonance distance between the cathode electrode CE and the first reflective electrode RE1 must be set so that the red light emitted from the third light emitting layer REML3a is constructively interfered with. A second color filter CF2 that transmits blue light may be disposed above the second light emitting element LD2. The second light emitting element LD2 is an element for emitting blue light, and the resonance distance between the cathode electrode CE and the second reflective electrode RE2 must be set so that the blue light emitted from the second light emitting layer BEML2a is constructively interfered with. A third color filter CF3 that transmits green light may be disposed above the third light emitting element LD3. In this case, the third light-emitting element LD3 is an element for emitting green light, and it is necessary to set the resonance distance between the cathode electrode CE and the third reflective electrode RE3 so that the green light emitted from the first light-emitting layer GEML1a is constructively interfered with.

[0196] Referring to FIG. 11a, as described with reference to FIG. 8a, a differential layer may not be present between the first transparent electrode TE1 and the first reflective electrode RE1 of the first light-emitting element LD1. A first differential layer DFL1 may be present between the second transparent electrode TE2 and the second reflective electrode RE2 of the second light-emitting element LD2. A first differential layer DFL1 and a second differential layer DFL2 may be present between the third transparent electrode TE3 and the third reflective electrode RE3 of the third light-emitting element LD3. Therefore, as can be seen from FIG. 8a, the distance between the first transparent electrode TE1 and the first reflective electrode RE1 may be shorter than the distance between the second transparent electrode TE2 and the second reflective electrode RE2. Furthermore, the distance between the second transparent electrode TE2 and the second reflective electrode RE2 may be shorter than the distance between the third transparent electrode TE3 and the third reflective electrode RE3. Also, as can be seen more clearly by referring to FIG. 8a, the distance between the cathode electrode CE and the first reflective electrode RE1 may be smaller than the distance between the cathode electrode CE and the second reflective electrode RE2, and the distance between the cathode electrode CE and the second reflective electrode RE2 may be smaller than the distance between the cathode electrode CE and the third reflective electrode RE3.

[0197] Referring to FIG. 11b, as described with reference to FIG. 8b, a differential pattern may not be present between the first transparent electrode TE1 and the first reflective electrode RE1 of the first light-emitting element LD1. A first differential pattern DFP1 may be present between the second transparent electrode TE2 and the second reflective electrode RE2 of the second light-emitting element LD2. A second differential pattern DFP2 may be present between the third transparent electrode TE3 and the third reflective electrode RE3 of the third light-emitting element LD3. The length of the second differential pattern DFP2 in the third direction DR3 may be greater than the length of the first differential pattern DFP1. Therefore, as can be seen from FIG. 8b, the distance between the first transparent electrode TE1 and the first reflective electrode RE1 may be smaller than the distance between the second transparent electrode TE2 and the second reflective electrode RE2. Furthermore, the distance between the second transparent electrode TE2 and the second reflective electrode RE2 may be smaller than the distance between the third transparent electrode TE3 and the third reflective electrode RE3. Also, as can be seen more clearly by referring to Figure 8b, the distance between the cathode electrode CE and the first reflective electrode RE1 may be smaller than the distance between the cathode electrode CE and the second reflective electrode RE2, and the distance between the cathode electrode CE and the second reflective electrode RE2 may be smaller than the distance between the cathode electrode CE and the third reflective electrode RE3.

[0198] According to the stacking order of the light-emitting layers GEML1a, BEML2a, and REML3a and the structures of the differential layers DFL1 and DFL2 (or the structures of the differential patterns DFP1 and DFP2), the first resonance distance of the first light-emitting element LD1 (i.e., the distance between the first reflective electrode RE1 and the cathode electrode CE) can be set to have four resonance layers r1r, r2r, r3r, and r4r for the wavelength of red light. When the third light-emitting layer REML3a is located in one of the four resonance layers r1r, r2r, r3r, and r4r, the first light-emitting element LD1 can emit red light with maximized brightness due to constructive interference. The first resonance layer r1r can be spaced from the first reflective electrode RE1 by ¼ the wavelength of the red light. The second resonance layer r2r can be spaced from the first reflective electrode RE1 by ¾ the wavelength of the red light. The third resonant layer r3r may be spaced from the first reflective electrode RE1 by 5 / 4 of the wavelength of the red light. The fourth resonant layer r4r may be spaced from the first reflective electrode RE1 by 7 / 4 of the wavelength of the red light. The fourth resonant layer r4r may be spaced from the cathode electrode CE by 1 / 4 of the wavelength of the red light. Considering the thickness conditions of this embodiment, the third light emitting layer REML3a may be located in the fourth resonant layer r4r of the four resonant layers r1r, r2r, r3r, and r4r.

[0199] The second light emitting element LD2 may have a second resonance distance (i.e., the distance between the second reflective electrode RE2 and the cathode electrode CE) of six resonance layers b1r, b2r, b3r, b4r, b5r, and b6r for the wavelength of blue light. When the second light emitting layer BEML2a is located in any one of the six resonance layers b1r, b2r, b3r, b4r, b5r, and b6r, the second light emitting element LD2 may emit blue light with maximized brightness due to constructive interference. The first resonance layer b1r may be spaced apart from the second reflective electrode RE2 by ¼ of the wavelength of the blue light. The second resonance layer b2r may be spaced apart from the second reflective electrode RE2 by ¾ of the wavelength of the blue light. The third resonance layer b3r may be spaced apart from the second reflective electrode RE2 by ¾ of the wavelength of the blue light. The fourth resonance layer b4r may be spaced apart from the second reflective electrode RE2 by 7 / 4 of the wavelength of the blue light. The fifth resonant layer b5r may be spaced from the second reflective electrode RE2 by 9 / 4 of the wavelength of blue light. The sixth resonant layer b6r may be spaced from the second reflective electrode RE2 by 1 1 / 4 of the wavelength of blue light. The sixth resonant layer b6r may be spaced from the cathode electrode CE by 1 / 4 of the wavelength of blue light. Considering the thickness conditions of this embodiment, the second light emitting layer BEML2a may be located in the second resonant layer b2r of the six resonant layers b1r, b2r, b3r, b4r, b5r, and b6r.

[0200] The third light emitting element LD3 may have a third resonance distance (i.e., the distance between the third reflective electrode RE3 and the cathode electrode CE) set to have five resonance layers g1r, g2r, g3r, g4r, and g5r with respect to the wavelength of green light. When the first light emitting layer GEML1a is located in any one of the five resonance layers g1r, g2r, g3r, g4r, and g5r, the third light emitting element LD3 may emit green light with maximized brightness due to constructive interference. The first resonance layer g1r may be spaced apart from the third reflective electrode RE3 by ¼ of the wavelength of the green light. The second resonance layer g2r may be spaced apart from the third reflective electrode RE3 by ¾ of the wavelength of the green light. The third resonance layer g3r may be spaced apart from the third reflective electrode RE3 by ¾ of the wavelength of the green light. The fourth resonance layer g4r may be spaced apart from the third reflective electrode RE3 by 7 / 4 of the wavelength of the green light. The fifth resonant layer g5r may be spaced from the third reflective electrode RE3 by 9 / 4 of the wavelength of the green light. The fifth resonant layer g5r may be spaced from the cathode electrode CE by 1 / 4 of the wavelength of the green light. Considering the thickness conditions of this embodiment, the first light-emitting layer GEML1a may be located in the first resonant layer g1r among the five resonant layers g1r, g2r, g3r, g4r, and g5r. In the example of FIG. 12, the resonant layer r4r, the resonant layer b2r, and the resonant layer g1r are located in this order from highest to lowest relative to the substrate SUB.

[0201] Specifically, the first light emitting layer GEML1a may be spaced apart from the third reflective electrode RE3 by a distance of 550 Å to 750 Å (Angstroms). The second light emitting layer BEML2a may be spaced apart from the second reflective electrode RE2 by a distance of 1400 Å to 1600 Å. The third light emitting layer REML3a may be spaced apart from the first reflective electrode RE1 by a distance of 5600 Å to 5800 Å.

[0202] The second transparent electrode TE2 and the second reflective electrode RE2 of the second light emitting element LD2 may be spaced apart by a distance of 150 Å to 350 Å, and the third transparent electrode TE3 and the third reflective electrode TE3 of the third light emitting element LD3 may be spaced apart by a distance of 400 Å to 600 Å.

[0203] In explaining this embodiment, a structure including differential equalizer films DFL1 and DFL2 in Fig. 8a or differential equalizer patterns DFP1 and DFP2 in Fig. 8b has been described, but the above-described concept of the first, second, and third resonance distances can also be adopted in a configuration employing buffer patterns BFP1 and BFP2 and a planarization layer PLNL as in Fig. 7. Therefore, this embodiment can also be applied to the structure in Fig. 7.

[0204] 13a, 13b, and 14 are diagrams illustrating first to third light emitting elements according to another embodiment of the present invention.

[0205] Referring to Figures 13a and 13b, a first light-emitting element LD1 located on a first reflective electrode RE1, a second light-emitting element LD2 located on a second reflective electrode RE2, and a third light-emitting element LD3 located on a third reflective electrode RE3 are shown. 13a and 13b, for simplicity, the first to third transparent electrodes TE1 to TE3 are depicted as being at the same height in the third direction DR3. However, in reality, the first to third transparent electrodes TE1 to TE3 are at different height positions in the third direction DR3, as in FIGS. 8a and 8b. In the third direction DR3, the first transparent electrode TE1 is positioned lower than the second transparent electrode TE2, and the second transparent electrode TE2 is positioned lower than the third transparent electrode TE3. 13a and 13b, for the sake of simplicity, the cathode electrode CE is depicted at the same height in the first direction DR1. However, in reality, the height position of the cathode electrode CE in the third direction DR3 varies depending on the portion of the cathode electrode CE corresponding to each of the first to third reflective electrodes RE1 to RE3, as in FIGS. 8a and 8b. In the third direction DR3, the portion of the cathode electrode CE corresponding to the first reflective electrode RE1 is located lower than the portion of the cathode electrode CE corresponding to the second reflective electrode RE2, and the portion of the cathode electrode CE corresponding to the second reflective electrode RE2 is located lower than the portion of the cathode electrode CE corresponding to the third reflective electrode RE3.

[0206] The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may share the light emitting structure EMSb and the cathode electrode CE. The light emitting structure EMSb may include a first light emitting portion EU1b, a second light emitting portion EU2b, and a third light emitting portion EU3b, which are sequentially stacked. The layered structure of the light emitting structure EMSb may be the same as the layered structure of the light emitting structure EMS′ of FIG. 10.

[0207] For example, the first light-emitting unit EU1b may include a first hole transport unit HTU1b, a first light-emitting layer REML1b, and a first electron transport unit ETU1b. The first light-emitting layer REML1b may be disposed between the first hole transport unit HTU1b and the first electron transport unit ETU1b. The second light-emitting unit EU2b may include a second hole transport unit HTU2b, a second light-emitting layer BEML2b, and a second electron transport unit ETU2b. The second light-emitting layer BEML2b may be disposed between the second hole transport unit HTU2b and the second electron transport unit ETU2b. The third light-emitting unit EU3b may include a third hole transport unit HTU3b, a third light-emitting layer GEML3b, and a third electron transport unit ETU3b. The third light-emitting layer GEML3b may be disposed between the third hole transport unit HTU3b and the third electron transport unit ETU3b. The first charge generation layer CGL1b is disposed between the first light emitting unit EU1b and the second light emitting unit EU2b, and the second charge generation layer CGL2b is disposed between the second light emitting unit EU2b and the third light emitting unit EU3b.

[0208] As described above, the separator SPR separates the first light-emitting unit EU1b, the first charge generation layer CGL1b, the second light-emitting unit EU2b, and the second charge generation layer CGL2b, thereby preventing leakage current through the common layer between adjacent subpixels. The separator SPR may also separate at least a portion of the third light-emitting unit EU3b. However, the separator SPR must not cut the cathode electrode CE, which is the common electrode. If the separator SPR separates the cathode electrode CE, the second power supply voltage VSS from the second power supply voltage node VSSN may not be transmitted to the cathode electrodes CE of the light-emitting elements LD1, LD2, and LD3, or an IR drop (i.e., voltage drop) of the second power supply voltage VSS may occur.

[0209] In this embodiment, the thickness of the third light-emitting portion EU3b may be greater than the sum of the thicknesses of the first light-emitting portion EU1b and the second light-emitting portion EU2b. For example, the thickness of the third hole transport portion HTU3b included in the third light-emitting portion EU3b may be greater than the sum of the thicknesses of the first light-emitting portion EU1b and the second light-emitting portion EU2b. Here, the thickness refers to the length along the third direction DR3.

[0210] For example, the thickness of the third light-emitting unit EU3b may be 2.5 times or more the sum of the thicknesses of the first light-emitting unit EU1b and the second light-emitting unit EU2b. For example, the thickness of the third hole transport unit HTU3b included in the third light-emitting unit EU3b may be 2.5 times or more the sum of the thicknesses of the first light-emitting unit EU1b and the second light-emitting unit EU2b. For example, the thickness of the third light-emitting unit EU3b may be approximately 2.60 times the sum of the thicknesses of the first light-emitting unit EU1b, the first charge generation layer CGL1b, and the second light-emitting unit EU2b.

[0211] According to this embodiment, the first light-emitting unit EU1b, the first charge generation layer CGL1b, the second light-emitting unit EU2b, and the second charge generation layer CGL2b are separated by the separator SPR, and the cathode electrode CE can be unseparated by the separator SPR.

[0212] In this case, the thickness of the third light emitting unit EU3b or the third hole transport unit HTU3b can be increased, but the power consumption for emitting light at the same brightness also increases, and it may be difficult to adjust the resonance distance. Below, a configuration for adjusting the resonance distance according to the above-mentioned thickness conditions will be described.

[0213] 13a, 13b, and 14, the first light-emitting layer REML1b can be configured to emit red light, the second light-emitting layer BEML2b can be configured to emit blue light, and the third light-emitting layer GEML3b can be configured to emit green light.

[0214] For example, a first color filter CF1 that transmits red light may be disposed above the first light emitting element LD1 (see FIG. 7, 8a, or 8b). The first light emitting element LD1 is an element for emitting red light, and the resonance distance between the cathode electrode CE and the first reflective electrode RE1 must be set so that the red light emitted from the first light emitting layer REML1b is constructively interfered with. A second color filter CF2 that transmits blue light may be disposed above the second light emitting element LD2. The second light emitting element LD2 is an element for emitting blue light, and the resonance distance between the cathode electrode CE and the second reflective electrode RE2 must be set so that the blue light emitted from the second light emitting layer BEML2b is constructively interfered with. A third color filter CF3 that transmits green light may be disposed above the third light emitting element LD3. In this case, the third light-emitting element LD3 is an element for emitting green light, and it is necessary to set the resonance distance between the cathode electrode CE and the third reflective electrode RE3 so that the green light emitted from the third light-emitting layer GEML3b is constructively interfered with.

[0215] Referring to FIG. 13a, as described with reference to FIG. 8a, a differential layer may not be present between the first transparent electrode TE1 and the first reflective electrode RE1 of the first light-emitting element LD1. A first differential layer DFL1 may be present between the second transparent electrode TE2 and the second reflective electrode RE2 of the second light-emitting element LD2. A first differential layer DFL1 and a second differential layer DFL2 may be present between the third transparent electrode TE3 and the third reflective electrode RE3 of the third light-emitting element LD3. Therefore, as can be seen from FIG. 8a, the distance between the first transparent electrode TE1 and the first reflective electrode RE1 may be shorter than the distance between the second transparent electrode TE2 and the second reflective electrode RE2. Furthermore, the distance between the second transparent electrode TE2 and the second reflective electrode RE2 may be shorter than the distance between the third transparent electrode TE3 and the third reflective electrode RE3. Also, as can be seen more clearly by referring to FIG. 8a, the distance between the cathode electrode CE and the first reflective electrode RE1 may be smaller than the distance between the cathode electrode CE and the second reflective electrode RE2, and the distance between the cathode electrode CE and the second reflective electrode RE2 may be smaller than the distance between the cathode electrode CE and the third reflective electrode RE3.

[0216] Referring to FIG. 13b, as described with reference to FIG. 8b, a differential pattern may not be present between the first transparent electrode TE1 and the first reflective electrode RE1 of the first light-emitting element LD1. A first differential pattern DFP1 may be present between the second transparent electrode TE2 and the second reflective electrode RE2 of the second light-emitting element LD2. A second differential pattern DFP2 may be present between the third transparent electrode TE3 and the third reflective electrode RE3 of the third light-emitting element LD3. The length of the second differential pattern DFP2 in the third direction DR3 may be greater than the length of the first differential pattern DFP1. Therefore, as can be seen from FIG. 8b, the distance between the first transparent electrode TE1 and the first reflective electrode RE1 may be smaller than the distance between the second transparent electrode TE2 and the second reflective electrode RE2. Furthermore, the distance between the second transparent electrode TE2 and the second reflective electrode RE2 may be smaller than the distance between the third transparent electrode TE3 and the third reflective electrode RE3. Also, as can be seen more clearly by referring to Figure 8b, the distance between the cathode electrode CE and the first reflective electrode RE1 may be smaller than the distance between the cathode electrode CE and the second reflective electrode RE2, and the distance between the cathode electrode CE and the second reflective electrode RE2 may be smaller than the distance between the cathode electrode CE and the third reflective electrode RE3.

[0217] According to the stacking order of the light-emitting layers REML1b, BEML2b, and GEML3b and the structures of the differential layers DFL1 and DFL2 (or the structures of the differential patterns DFP1 and DFP2), the first resonance distance of the first light-emitting element LD1 (i.e., the distance between the first reflective electrode RE1 and the cathode electrode CE) can be set to have four resonance layers r1r, r2r, r3r, and r4r for the wavelength of red light. When the first light-emitting layer REML1b is located in one of the four resonance layers r1r, r2r, r3r, and r4r, the first light-emitting element LD1 can emit red light with maximized brightness due to constructive interference. The first resonance layer r1r can be spaced from the first reflective electrode RE1 by ¼ the wavelength of the red light. The second resonance layer r2r can be spaced from the first reflective electrode RE1 by ¾ the wavelength of the red light. The third resonant layer r3r may be spaced apart from the first reflective electrode RE1 by 5 / 4 of the wavelength of the red light. The fourth resonant layer r4r may be spaced apart from the first reflective electrode RE1 by 7 / 4 of the wavelength of the red light. The fourth resonant layer r4r may be spaced apart from the cathode electrode CE by 1 / 4 of the wavelength of the red light. Considering the thickness conditions of this embodiment, the first light emitting layer REML1b may be located in the first resonant layer r1r of the four resonant layers r1r, r2r, r3r, and r4r.

[0218] The second light emitting element LD2 may have a second resonance distance (i.e., the distance between the second reflective electrode RE2 and the cathode electrode CE) of six resonance layers b1r, b2r, b3r, b4r, b5r, and b6r for the wavelength of blue light. When the second light emitting layer BEML2b is located in any one of the six resonance layers b1r, b2r, b3r, b4r, b5r, and b6r, the second light emitting element LD2 may emit blue light with maximized brightness due to constructive interference. The first resonance layer b1r may be spaced apart from the second reflective electrode RE2 by ¼ of the wavelength of the blue light. The second resonance layer b2r may be spaced apart from the second reflective electrode RE2 by ¾ of the wavelength of the blue light. The third resonance layer b3r may be spaced apart from the second reflective electrode RE2 by ¾ of the wavelength of the blue light. The fourth resonance layer b4r may be spaced apart from the second reflective electrode RE2 by 7 / 4 of the wavelength of the blue light. The fifth resonant layer b5r may be spaced from the second reflective electrode RE2 by 9 / 4 of the wavelength of blue light. The sixth resonant layer b6r may be spaced from the second reflective electrode RE2 by 1 1 / 4 of the wavelength of blue light. The sixth resonant layer b6r may be spaced from the cathode electrode CE by 1 / 4 of the wavelength of blue light. Considering the thickness conditions of this embodiment, the second light emitting layer BEML2b may be located in the second resonant layer b2r of the six resonant layers b1r, b2r, b3r, b4r, b5r, and b6r.

[0219] The third light emitting element LD3 may have a third resonance distance (i.e., the distance between the third reflective electrode RE3 and the cathode electrode CE) of five resonance layers g1r, g2r, g3r, g4r, and g5r for the wavelength of green light. When the third light emitting layer GEML3b is located in any one of the five resonance layers g1r, g2r, g3r, g4r, and g5r, the third light emitting element LD3 may emit green light with maximized brightness due to constructive interference. The first resonance layer g1r may be spaced apart from the third reflective electrode RE3 by ¼ of the wavelength of the green light. The second resonance layer g2r may be spaced apart from the third reflective electrode RE3 by ¾ of the wavelength of the green light. The third resonance layer g3r may be spaced apart from the third reflective electrode RE3 by ¾ of the wavelength of the green light. The fourth resonance layer g4r may be spaced apart from the third reflective electrode RE3 by 7 / 4 of the wavelength of the green light. The fifth resonant layer g5r may be spaced from the third reflective electrode RE3 by 9 / 4 of the wavelength of the green light. The fifth resonant layer g5r may be spaced from the cathode electrode CE by 1 / 4 of the wavelength of the green light. Considering the thickness conditions of this embodiment, the third light-emitting layer GEML3b may be located in the fifth resonant layer g5r among the five resonant layers g1r, g2r, g3r, g4r, and g5r. In the example of FIG. 14, the resonant layer r1r, the resonant layer b2r, and the resonant layer g5r are located in this order from lowest to highest relative to the substrate SUB.

[0220] Specifically, the first light emitting layer REML1b may be spaced from the first reflective electrode RE1 by a distance of 500 Å to 700 Å, the second light emitting layer BEML2b may be spaced from the second reflective electrode RE2 by a distance of 1400 Å to 1600 Å, and the third light emitting layer GEML3b may be spaced from the third reflective electrode RE3 by a distance of 6400 Å to 6600 Å.

[0221] In addition, the second transparent electrode TE2 and the second reflective electrode RE2 of the second light emitting element LD2 may be spaced apart by a distance of 200 Å to 400 Å, and the third transparent electrode TE3 and the third reflective electrode RE3 of the third light emitting element LD3 may be spaced apart by a distance of 600 Å to 800 Å.

[0222] In explaining this embodiment, a structure including differential equalizer films DFL1 and DFL2 in Fig. 8a or differential equalizer patterns DFP1 and DFP2 in Fig. 8b has been described, but the above-described concept of the first, second, and third resonance distances can also be adopted in a configuration employing buffer patterns BFP1 and BFP2 and a planarization layer PLNL as in Fig. 7. Therefore, this embodiment can also be applied to the structure in Fig. 7.

[0223] FIG. 15 is a diagram for explaining the luminous efficiency of the first to third light-emitting elements according to the examples of FIGS. 11a, 11b, 13a, and 13b.

[0224] Referring to Figure 15, a table is shown listing the red driving voltage R_V, red color coordinates R_x, R_y, red luminous efficiency R_E, green driving voltage G_V, green color coordinates G_x, G_y, green luminous efficiency G_E, blue driving voltage B_V, blue color coordinates B_x, B_y, blue luminous efficiency B_E, and white luminous efficiency W_E for the comparative example ref, the light-emitting structure EMSa of Figure 11a or Figure 11b, and the light-emitting structure EMSb of Figure 13a or Figure 13b.

[0225] The driving voltage may refer to the voltage across the anode and cathode electrodes, the color coordinates may refer to the color coordinates of the International Commission on Illumination (CIE), and the luminous efficiency may refer to the luminance relative to the power consumption.

[0226] The comparative example ref has the structure of the light emitting structure EMS of Fig. 9, but the second resonance distance of the second light emitting element LD emitting blue light may be the same as the second resonance distances of the light emitting structures EMSa and EMSb. In the comparative example ref, the red light emitting layer may be located on the fourth resonance layer r4r, the green light emitting layer may be located on the fifth resonance layer g5r, and the blue light emitting layer may be located on the second resonance layer b2r (see Fig. 12 or 14).

[0227] According to the experimental results, the light emitting structure EMSa of Fig. 11a or 11b can have a white light emitting efficiency of 127% compared to the comparative example ref. Also, the light emitting structure EMSb of Fig. 13a or 13b can have a white light emitting efficiency of 164% compared to the comparative example ref. In addition, the separator SPR can separate the first light emitting unit EU1a or EU1b, the first charge generation layer CGL1a or CGL1b, the second light emitting unit EU2a or EU2b, and the second charge generation layer CGL2a or CGL2b without separating the cathode electrode CE.

[0228] FIG. 16 is a plan view showing another embodiment of any one of the pixels of FIG. Referring to FIG. 16, the first pixel PXL1' may include first to third sub-pixels SP1' to SP3'.

[0229] The first sub-pixel SP1' may include a first light-emitting region EMA1' and a non-light-emitting region NEA' around the first light-emitting region EMA1'. The second sub-pixel SP2' may include a second light-emitting region EMA2' and a non-light-emitting region NEA' around the second light-emitting region EMA2'. The third sub-pixel SP3' may include a third light-emitting region EMA3' and a non-light-emitting region NEA' around the third light-emitting region EMA3'.

[0230] The first and second sub-pixels SP1′ and SP2′ may be arranged in the second direction DR2, and the third sub-pixel SP3′ may be arranged in the first direction DR1 relative to the first and second sub-pixels SP1′ and SP2′.

[0231] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Thus, the second light-emitting region EMA2' may have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' may have a larger area than the second light-emitting region EMA2'. However, embodiments are not limited thereto. For example, the first and second sub-pixels SP1' and SP2' may have substantially the same area, and the third sub-pixel SP3' may have a larger area than the first and second sub-pixels SP1' and SP2'. As such, the areas of the first to third sub-pixels SP1' to SP3' may vary in various ways depending on embodiments.

[0232] FIG. 17 is a plan view showing yet another embodiment of any one of the pixels of FIG.

[0233] Referring to FIG. 17, the first subpixel SP1″ may include a first light-emitting region EMA1″ and a non-light-emitting region NEA″ around the first light-emitting region EMA1″. The second subpixel SP2″ may include a second light-emitting region EMA2″ and a non-light-emitting region NEA″ around the second light-emitting region EMA2″. The third subpixel SP3″ may include a third light-emitting region EMA3″ and a non-light-emitting region NEA″ around the third light-emitting region EMA3″.

[0234] The first to third sub-pixels SP1" to SP3" may have a polygonal shape when viewed in the third direction DR3 (in a plan view). For example, the first to third sub-pixels SP1" to SP3" may have a hexagonal shape as shown in FIG.

[0235] The first to third light-emitting regions EMA1'' to EMA3'' may have a circular shape when viewed from the third direction DR3. However, the embodiment is not limited thereto. For example, each of the first to third light-emitting regions EMA1'' to EMA3'' may have a polygonal shape (e.g., a hexagon).

[0236] The first and third sub-pixels SP1" and SP3" may be arranged in the first direction DR1. The second sub-pixel SP2" may be arranged in a direction inclined at an acute angle (or diagonal direction) with respect to the first sub-pixel SP1" based on the second direction DR2. The second sub-pixel SP2" is positioned at a position offset from the first and third sub-pixels SP1" and SP3" in the first and second directions DR1 and DR2.

[0237] The sub-pixel arrangements shown in Figures 6, 16, and 17 are exemplary and not limiting examples. Each pixel includes two or more sub-pixels, and the sub-pixels can be arranged in various ways, each of the sub-pixels can have various shapes, and each of their light-emitting areas can also have various shapes.

[0238] FIG. 18 is a block diagram illustrating an embodiment of a display system.

[0239] Referring to FIG. 18, a display system 1000 may include a processor 1100 and one or more display devices 1210, 1220.

[0240] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 can include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be coupled to and control other components of the display system 1000 via a bus system.

[0241] 18, a display system 1000 is shown as including first and second display devices 1210, 1220. The processor 1100 may be coupled to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0242] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to FIG. 1. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0243] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured similarly to the display device 100 described with reference to FIG. 1. In such a case, the second image data IMG2 and the second control signal CTRL2 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0244] The display system 1000 may include a computing system that provides a video display function, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 1000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0245] FIG. 19 is a perspective view showing an application example of the display system of FIG.

[0246] 19, the display system 1000 of FIG. 18 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0247] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing case 2200. The head-mounted band 2100 may be connected to the display device housing case 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the sides of the user's head, and the vertical band may be configured to surround the top of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band 2100 may be realized in the form of a glasses frame, a helmet, or the like.

[0248] The display device housing case 2200 can house the first and second display devices 1210 and 1220 of Figure 12. The display device housing case 2200 can further house the processor 1100 of Figure 18.

[0249] FIG. 20 is a diagram showing the head-mounted display device worn by the user of FIG.

[0250] 20, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 are arranged in a head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS, RLNS.

[0251] Within the display device housing 2200, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye, and the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0252] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to direct it toward the user's right eye. The right eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0253] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to direct it toward the user's left eye. The left eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0254] In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS may include an optical lens having a pancake-shaped cross section, for example, a cross section that is flat on the side closer to the user's eye and convex on the side farther from the user's eye. In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel outputs images corresponding to the sub-regions of the multi-channel lens, and the output images pass through the corresponding sub-regions to be viewed by the user. The present invention is applicable not only to display devices but also to devices such as wearable devices.

[0255] The drawings and detailed description of the invention referred to above are merely illustrative of the present invention, and are used merely for the purpose of explaining the present invention, and are not used to limit the meaning or the scope of the present invention described in the claims. Therefore, a person skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. [Explanation of symbols]

[0256] LD1, LD2, LD3: first, second, and third light-emitting elements RE1, RE2, RE3 1st, 2nd, 3rd reflective electrode EMSa, EMSb light-emitting structures CE cathode electrode EU1a, EU1b First light-emitting unit EU2a, EU2b Second light-emitting section EU3a, EU3b Third light-emitting section

Claims

1. a first light-emitting element located on the first reflective electrode; a second light-emitting element located on the second reflective electrode; a third light-emitting element located on the third reflective electrode; the first light emitting device, the second light emitting device, and the third light emitting device share a light emitting structure and a cathode electrode; The light emitting structure includes a first light emitting unit, a second light emitting unit, and a third light emitting unit, which are sequentially stacked, A display device, wherein the thickness of the third light-emitting section is greater than the sum of the thickness of the first light-emitting section and the thickness of the second light-emitting section.

2. further comprising a separator positioned between the first light emitting element, the second light emitting element, and the third light emitting element; The light emitting structure is a first charge generation layer located between the first light-emitting section and the second light-emitting section; a second charge generation layer located between the second light-emitting unit and the third light-emitting unit, the first light-emitting unit, the first charge generation layer, the second light-emitting unit, and the second charge generation layer are separated by the separator; The display device of claim 1 , wherein the cathode electrode is connected to an upper portion of the separator.

3. The display device according to claim 2 , wherein a distance between the first transparent electrode of the first light-emitting element and the first reflective electrode is smaller than a distance between the second transparent electrode of the second light-emitting element and the second reflective electrode.

4. The display device according to claim 3 , wherein a distance between the second transparent electrode and the second reflective electrode of the second light-emitting element is smaller than a distance between the third transparent electrode and the third reflective electrode of the third light-emitting element.

5. the first light-emitting portion includes a first light-emitting layer configured to emit light of a first color; the second light-emitting portion includes a second light-emitting layer configured to emit light of a second color; the third light-emitting unit includes a third light-emitting layer configured to emit light of a third color; The display device according to claim 4 , wherein the first color, the second color, and the third color are different from each other.

6. the first color is green; the second color is blue; The display device of claim 5 , wherein the third color is red.

7. the first light-emitting layer is located in a first resonant layer among five resonant layers for the first color; the second light-emitting layer is located in a second resonant layer among six resonant layers for the second color; The display device according to claim 6 , wherein the third light-emitting layer is located in a fourth resonant layer among four resonant layers for the third color.

8. the first color is red; the second color is blue; The display device of claim 5 , wherein the third color is green.

9. the first light-emitting layer is located in a first resonant layer among four resonant layers for the first color; the second light-emitting layer is located in a second resonant layer among six resonant layers for the second color; The display device according to claim 8 , wherein the third light-emitting layer is located in a fifth resonant layer among five resonant layers for the third color.

10. The display device according to claim 1 , wherein a thickness of the hole transport section included in the third light-emitting section is greater than a sum of a thickness of the first light-emitting section and a thickness of the second light-emitting section.

Images