Programmable device having hardened circuits for predetermined digital signal processing functionality

Abstract

To provide a programmable device having hardened circuits for predetermined digital signal processing functionality.SOLUTION: A signal processing system 300 implemented in a programmable device includes a configuration memory 26 to store configuration data; a programmable subsystem 308 having configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit 66; a digital processing circuit 301; and an endpoint circuit 306 coupled to the signal conversion circuit through the digital processing circuit. The digital processing circuit 301 includes first one or more digital processing functions implemented as hardened circuits 90 each having predetermined functionality; and second one or more processing functions implemented by the configurable functionality of the programmable subsystem 308.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] Technical Field Examples of the present disclosure relate generally to programmable devices, and more particularly to programmable devices having hardened circuits for predetermined digital signal processing functions. [Background technology]

[0002] Background technology An integrated circuit (IC) can be implemented to perform a specific function. One type of IC is a programmable IC, such as a field programmable gate array (FPGA) or a system-on-chip (SoC) that includes an FPGA-based programmable fabric. The FPGA fabric typically includes an array of programmable tiles. These programmable tiles can include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay-locked loops (DLLs), etc.

[0003] Each programmable tile typically includes both programmable interconnect circuitry and programmable logic circuitry. The programmable interconnect circuitry typically includes multiple interconnect lines of various lengths interconnected by programmable interconnect points (PIPs). The programmable logic circuitry implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, etc.

[0004] Programmable interconnect circuits and programmable logic circuits are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

[0005] Some applications of programmable ICs involve frequently executed functions. To conserve resources and reduce power within the programmable fabric, it is desirable to provide hardened implementations of such frequently executed functions within the programmable IC, thereby allowing for greater integration than would be possible due to thermal or die size limitations. Summary of the Invention [Means for solving the problem]

[0006] Summary of the Invention Techniques are described for providing a programmable device having hardening circuits. In one example, the programmable device includes a configuration memory configured to store configuration data, programmable logic having configurable functions based on the configuration data in the configuration memory, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, the digital processing circuit including first one or more digital processing functions implemented as hardening circuits each having a predetermined function, and a second one or more processing functions implemented by configurable functions of the programmable logic.

[0007] In another example, the programmable device may include a configuration subsystem and a programmable controller configured by the configuration subsystem. the signal conversion circuit; a digital processing circuit; and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, the digital processing circuit including at least one conversion circuit or at least one digital front-end (DFE) circuit each implemented as a hardening circuit having a predetermined function.

[0008] In another example, a programmable device comprises a configuration subsystem, at least one programmable subsystem having a configurable function determined by the configuration subsystem, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, the digital processing circuit including first one or more digital processing functions implemented as hardened circuits each having a predetermined function, and second one or more digital processing functions implemented by the configurable function of the at least one programmable subsystem.

[0009] These and other aspects can be understood with reference to the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS So that the features described above may be understood in detail, a more particular description thereof may be had by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical exemplary implementations and are therefore not to be considered limiting of the scope thereof. [Brief explanation of the drawings]

[0010] [Figure 1A] FIG. 1 is a block diagram illustrating a programmable IC according to an example. [Figure 1B] An example of a field programmable gate array (FPGA) implementation of a programmable IC is presented. [Figure 1C] 1 is a block diagram illustrating a multi-integrated circuit (IC) programmable device according to an example. [Figure 2] FIG. 1 is a block diagram illustrating a floor plan of a programmable device according to an example. [Figure 3] 1 is a block diagram illustrating a signal processing system implemented in a programmable device according to an example. [Figure 4] FIG. 1 is a block diagram illustrating a curing circuit according to an example. [Figure 5] 1 is a block diagram illustrating a signal processing system implemented in a programmable device according to an example. [Figure 6] 1 is a block diagram illustrating a signal processing system implemented in a programmable device according to an example. [Figure 7] 1 is a block diagram illustrating a signal processing system implemented in a programmable device according to an example. [Figure 8] 1 is a block diagram illustrating a signal processing system implemented in a programmable device according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0011] For ease of understanding, wherever possible, identical reference numerals have been used to designate identical elements common to the figures, and it is believed that elements of one example may be beneficially incorporated into other examples.

[0012] Detailed Description Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention. These and other aspects and advantages are not intended as limitations on the scope of the inventions or claimed inventions. Moreover, an illustrated example need not have all of the illustrated aspects or advantages. An aspect or advantage discussed in connection with a particular example is not necessarily limited to that example and may be implemented in any other example even if not so shown or explicitly described.

[0013] 1A is a block diagram illustrating a programmable device 1 according to an example. The programmable device 1 includes programmable logic (PL) 3 (also referred to as programmable fabric), input / output (IO) circuitry 68, serial transceiver 67, signal conversion circuitry 66, hardening circuitry 90, configuration logic 25, and configuration memory 26. The programmable device 1 can be coupled to external circuitry such as non-volatile memory 27, dynamic random access memory (DRAM) 28, and other circuitry 29. In various examples, the programmable device 1 further includes a processing system (PS) 2, a network-on-chip (NOC) 55, a data processing engine (DPE) array 56, peripheral interconnect 61, peripheral circuitry 62, and inter-die interconnect circuitry 64.

[0014] The PL3 includes logic cells 30, support circuits 31, and programmable interconnect 32. The logic cells 30 include circuits that can be configured to perform a general logic function of multiple inputs. The support circuits 31 include specialized circuits such as digital signal processors, memories, etc. The logic cells and support circuits 31 can be interconnected using programmable interconnect 32. Information for programming the logic cells 30, setting parameters of the support circuits 31, and programming the programmable interconnect 32 is stored in configuration memory 26 by configuration logic 25. The configuration logic 25 can obtain configuration data from non-volatile memory 27 or any other source (e.g., from DRAM 28, or other circuits 29). In some examples, the configuration logic 25 includes a platform management controller (PMC) 72. The PMC 72 is configured to boot and configure subsystems of the programmable device 1, such as the PL3, the PS2, the NoC 55, the DPE array 56, the signal conversion circuit 66, and the hardening circuit 90.

[0015] The IO circuit 68 provides an external interface for subsystems of the programmable device 1, such as the PL3 and PS2. In some examples, the IO circuit 68 includes a memory controller 70 configured to interface with external memory (e.g., DRAM 28). Other connection circuits can include a peripheral interconnect 61, peripheral circuits 62, and inter-die interconnect circuit 64. The peripheral interconnect 61 includes bus interface circuitry such as Peripheral Component Interconnect Express (PCIe) circuitry. The peripheral circuits 62 include Universal Serial Bus (USB) ports, Ethernet ports, Universal Asynchronous Transceiver (UART) ports, Serial Peripheral Interface (SPI) ports, General-Purpose IO (GPIO) ports, Serial Advanced Technology Attachment (SATA) ports, etc. The inter-die interconnect circuit 64 includes circuitry configured to interface with inter-die interconnect circuitry in other programmable devices (e.g., when the programmable device 1 is one die in a multi-die integrated circuit package). The serial transceiver 67 includes high-speed transmit / receive circuitry configured to provide an external IO interface for the programmable device 1.

[0016] The PS2 may include a microprocessor, memory, support circuits, IO circuits, etc. The NOC 55 is configured to provide communication between subsystems of the programmable device 1, such as between the PS2, the PL3, the hardening circuit 90, and the DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. The signal conversion circuit 66 may include an ADC (Analog to Digital Converter) or a DAC (Digital Converter). Includes Digital to Digital Converter (DAC) and Digital to Analog Converter (DAC).

[0017] The hardening circuit 90 comprises circuitry having predetermined functions. A given hardening circuit 90 can include one or more predetermined functions. Exemplary hardening circuits 90 include filters, mixers, sample rate converters, conversion circuits (e.g., Fast Fourier Transform (FFT)), etc. The hardening circuit 90 can be programmable to configure a particular predetermined function or to select from among predetermined functions. However, in contrast to the circuitry of PL3, the hardening circuit 90 cannot be configured or reconfigured with different functions. For example, the hardening circuit 90 can include a filter having two predetermined, selectable functions. It is not possible to add a third function to the hardening circuit 90, nor is it possible to remove one of the two functions from the hardening circuit 90. In contrast, the filters configured in PL3 can be reconfigured to add one or more additional functions or to remove one or more functions. Also, the filters configured in PL3 can be removed altogether and replaced with other circuits. In contrast, the hardening circuit 90 cannot be removed from the programmable device 1 (but can be unused if desired).

[0018] 1B illustrates an example field-programmable gate array (FPGA) implementation of PL3. PL3 illustrated in FIG. 1B can be used in any of the example programmable devices described herein. PL3 includes a number of different programmable tiles, including configurable logic blocks (“CLBs”) 33, random access memory blocks (“BRAMs”) 34, input / output blocks (“IOBs”) 36, configuration and clocking logic (“CONFIG / CLOCKS”) 42, digital signal processing blocks (“DSPs”) 35, specialized input / output blocks (“I / Os”) 41 (e.g., configuration and clock ports), and other programmable logic 39, such as digital clock managers, analog-to-digital converters, and system monitoring logic.

[0019] In some PLs, each programmable tile may include at least one programmable interconnect element (“INT”) 43 having connections to input and output terminals 48 of programmable logic elements within the same tile, as shown by the example included at the top of FIG. 1B . Each programmable interconnect element 43 may also include connections for interconnecting segments 49 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 43 may also include connections for interconnecting segments 50 of general-purpose routing resources between logic blocks (not shown). The general-purpose routing resources may include routing channels between logic blocks (not shown) that comprise tracks of interconnect segments (e.g., interconnect segment 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of the general-purpose routing resources (e.g., interconnect segment 50) may span one or more logic blocks. The programmable interconnect elements 43, together with the general-purpose routing resources, implement a programmable interconnect structure (“programmable interconnect”) for the illustrated PL.

[0020] In an exemplary implementation, the CLB 33 may include a configurable logic element ("CLE") 44 that can be programmed to implement a single programmable interconnect element ("INT") 43 in addition to user logic. The BRAM 34 may include a BRAM logic element ("BRL") 45 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as five CLBs, although other numbers (e.g., four) may be used. The DSP tile 35 may include a DSP logic element ("DSPL") 46 in addition to an appropriate number of programmable interconnect elements. The IOB 36 may, for example, include a In addition to one instance of programmable interconnect element 43, two instances of input / output logic element ("IOL") 47 may be included. Those skilled in the art will appreciate that, for example, the actual I / O pads connected to I / O logic element 47 are typically not limited to the area of ​​input / output logic element 47.

[0021] In the illustrated example, a horizontal region near the center of the die (shown in FIG. 1B) is used for configuration, clocks, and other control logic. Vertical columns 51 extending from this horizontal region or column are used to distribute clock and configuration signals across the width of the PL.

[0022] Some PLs utilizing the architecture shown in Figure 1B include additional logic blocks that break up the regular columnar structure that makes up the majority of the PL. The additional logic blocks can be programmable blocks and / or dedicated logic.

[0023] Note that Figure 1B is intended to illustrate only an exemplary PL architecture. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementation included in the upper portion of Figure 1B are purely exemplary. For example, in an actual PL, multiple adjacent CLB rows are typically included where a CLB appears to facilitate efficient implementation of user logic, although the number of adjacent CLB rows will vary depending on the overall size of the PL.

[0024] 1C is a block diagram illustrating a multi-die programmable device 54 according to an example. The multi-die programmable device 54 includes multiple programmable devices 1, e.g., programmable devices 1A, 1B, 1C, and 1D. In one example, each programmable device 1 is an IC die disposed on an interposer 60. Each programmable device 1 comprises a super logic region (SLR) 53 of the programmable device 54, e.g., SLRs 53A, 53B, 53C, and 53D. The programmable devices 1 are interconnected via conductors (called super long lines (SLLs) 52) on the interposer 60 and inter-die interconnect circuitry 64 disposed within each of the programmable devices 1.

[0025] FIG. 2 is a block diagram illustrating a floor plan 200 of a programmable device 1 according to an example. In this example, the programmable device 1 includes columns of tiles containing the various circuits described above. For clarity of the example, some circuits have been omitted. In this example, the floor plan 200 shows columns of tiles having PL3; columns of tiles having DAC circuitry 204; columns of tiles having ADC circuitry 206; columns of tiles having inter-die interconnect circuitry 64; columns of tiles having hardening circuitry 90; and columns of tiles having serial transceivers 67. The columnar tile structure can be interrupted by several subsystems, such as PS2, NOC 55, and DPE array 56.

[0026] In the examples described herein, the hardening circuit 90 is used to implement digital processing circuitry between the DAC 204 / ADC 206 and endpoint circuitry, such as the serial transceiver 67 and / or circuitry configured within PL3. To facilitate the formation of the digital processing circuitry, the hardening circuit 90 can be connected to PL3, the signal conversion circuit 66, the NOC 55, the inter-die circuitry 54, and the transceiver 67. The connection can be made using programmable interconnects within PL3, through the NOC 55, by direct connection, or by some combination thereof. In some examples, the floorplan 200 includes multiple tiles, each of which can include some or all of the hardening circuit 90. This allows for scalability based on the number of ADC circuits 206 and DAC circuits 204.

[0027] In various applications, the programmable device 1 may utilize various radio frequency (RF) technologies. The ADC 206 can be used to transmit and receive data received wirelessly using a DAC 204. The ADC 206 is configured to generate a digital signal from an analog signal received from an external antenna (not shown). The resulting digital signal is then processed by some digital processing circuitry and provided to an endpoint circuit, which may be circuitry within the PL3, the transceiver 67, or some other subsystem. Conversely, the digital processing circuitry can process a digital signal transmitted from the endpoint circuit and provide it to the DAC 204. The DAC 204 generates an analog signal from the digital signal, which is then transmitted using the external antenna (not shown).

[0028] In some applications, the digital processing circuitry used in the applications described above can be formed in PL3. However, this requires the use of PL resources that are not currently available for use by other circuits. Therefore, in some examples, at least a portion of the digital processing circuitry is implemented using hardening circuitry 90. This frees up PL resources for use by other circuits in the system. However, because hardening circuitry 90 includes connections to PL3, there is flexibility to implement portions of the digital processing circuitry within PL3. This allows users to provide custom logic along with hardening circuitry 90 to implement the digital processing circuitry according to their specific application. Custom logic may also be used to implement the control paths of the digital processing circuitry, which provides increased flexibility while maintaining power efficiency when data processing remains in the hardened domain.

[0029] FIG. 3 is a block diagram illustrating a signal processing system 300 implemented in the programmable device 1 according to an example. The signal processing system 300 includes a signal conversion circuit 66, a digital processing circuit 301, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital and digital-to-analog conversion as described above. The digital processing circuit 301 is configured to process inputs and outputs to the signal conversion circuit 66. In one example, the digital processing circuit 301 includes first digital processing functions implemented as hardening circuits 90, each having a predetermined function, and second digital processing functions implemented by configurable functions of the programmable subsystem 308 (e.g., configurable functions of the PL3, the DPE array 56, and / or the PS2). By implementing some digital processing functions as hardening circuits 90, the digital processing circuit 301 conserves power and area on the programmable device. Types of digital processing functions that can be hardened include common functions across various applications or common functions used by various standards to which applications comply (e.g., 4G / 5G wireless communications). Examples include FFT / iFFT transformations, channel filtering, up / down sample rate conversion, crest factor reduction (CFR), etc. The types of digital processing functions that can be programmed using the configurable features of the programmable subsystem 308 include those that are non-standard or specific to a particular application. For example, the custom logic 304 can include digital pre-distortion (DPD) logic (e.g., DPD circuitry), calibration logic (e.g., calibration circuits), beamforming, automatic gain control (AGC), timing and synchronization, etc.

[0030] In one example, the digital processing circuit 301 includes multiple hardening circuits 90. The hardening circuits 90 may include, for example, one or more transform circuits 320 (e.g., transform functions) and one or more digital front-end (DFE) circuits 322 (e.g., DFE functions). The transform circuits 320 may include transform and inverse transform circuits such as FFT, iFFT, etc. The DFE circuits 322 may include filters, sample rate converters, mixers, signal combiners, etc.

[0031] In one example, the digital processing circuit 301 also includes one or more custom logics 304 programmed into at least one programmable subsystem 308 of the device. The programmable subsystem 308 may be, for example, a PL3, a PS2, a DPE array 56, etc. For example, the custom logic 304 may include custom circuitry configured in the PL3. The custom logic 304 may include a custom processor configured in the DPE array 56. The custom logic 304 may include a processor executing custom software in the PS2. In an example, the custom logic 304 may include a combination of such implementations. The programmable subsystem 308 is programmed based on a configuration subsystem comprising the configuration memory 26 and the PMC 72. The configuration memory 26 contains configuration data 302 for configuring custom circuitry in the PL3. The PMC 72 provides the configuration data to the DPE array 56 and the PS2, as well as to the curing circuit 90. The curing circuit 90 and the custom logic 304 may be connected in any of a variety of serial, parallel, or similar types of arrangements.

[0032] FIG. 4 is a block diagram illustrating an example hardening circuit 90. The hardening circuit 90 includes various interfaces, including an interface 402 with one or more other hardening circuits 90, an interface 404 with the PL 3, and an interface 406 with the NOC 55. Note that a given hardening circuit 90 can include all or some of the interfaces 402, 404, and 406. In some examples, the hardening circuit 90 includes an interface 408 with the PMC 72 due to its configuration. The hardening circuit 90 can also include an interface 410 coupled to specific control circuitry (e.g., another hardening circuit 90 or custom logic within a programmable subsystem). The control circuitry can control the operation of the hardening circuit 90 (e.g., the control circuitry can be a state machine or similar type of circuitry).

[0033] FIG. 5 is a block diagram illustrating a signal processing system 500 implemented in the programmable device 1 according to an example. The signal processing system 500 includes a signal conversion circuit 66, multiple hardening circuits 90, multiple custom circuits 304 configured within the PL 3, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital and digital-to-analog conversion as described above. The hardening circuits 90 each perform one or more functions, such as filtering, sample rate conversion, mixing, carrier combining / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with the PL 3. Configuration data 302 loaded into the configuration memory 26 configures the PL 3 using the custom circuits 304. Each custom circuit 304 can be connected to one or more hardening circuits 90. Each custom circuit 304 can be connected to one or more other custom circuits 304. One or more custom circuits 304 can be connected to an endpoint circuit 306. One or more custom circuits 304 can be coupled to the signal conversion circuit 66. One or more curing circuits 90 can be coupled to the endpoint circuit 306.

[0034] The hardening circuit 90 and custom circuit 304 form a digital processing circuit 301 disposed between the signal conversion circuit 66 and the endpoint circuit 306. Although the endpoint circuit 306 is shown as external to PL3 (e.g., a serial transceiver), the endpoint circuit 306 can be configured within PL3.

[0035] During operation, the PMC 72 receives information to program the programmable device 1. The PMC 72 loads configuration data for the PL3 into the configuration memory 26. The PMC 72 also programs one or more hardening circuits 90 to initialize, select functions, etc. As noted above, each hardening circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information to program them may be received and provided by the PMC 72. In contrast to the hardening circuits 90, the PL3 has configurable functions based on configuration data 302 stored in the configuration memory 26. After programming and configuration, the programmable device 1 is programmed to read and write the signal conversion circuit 6. 6 and the endpoint circuitry 306, which includes the hardening circuitry 90 and the custom circuitry 304, is implemented with a digital processing circuit 301.

[0036] FIG. 6 is a block diagram illustrating a signal processing system 600 implemented in the programmable device 1 according to an example. The signal processing system 600 includes a signal conversion circuit 66, multiple hardening circuits 90, multiple custom logic 304 configured within the DPE array 56, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital and digital-to-analog conversion as described above. The hardening circuits 90 each perform one or more functions, such as filtering, sample rate conversion, mixing, carrier combining / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with the DPE array 56 (e.g., via the NOC 55). Each custom logic 304 may be connected to one or more hardening circuits 90. Each custom logic 304 may be connected to one or more other custom logic 304. One or more custom logic 304 may be connected to an endpoint circuit 306. One or more custom logic 304 may be coupled to the signal conversion circuit 66. One or more hardening circuits 90 may be coupled to the endpoint circuit 306.

[0037] The hardening circuit 90 and custom circuit 304 form a digital processing circuit 301 disposed between the signal conversion circuit 66 and the endpoint circuit 306. Although the endpoint circuit 306 is shown as external to PL3 (e.g., a serial transceiver), the endpoint circuit 306 can be configured within PL3.

[0038] During operation, the PMC 72 receives information to program the programmable device 1. The PMC 72 loads configuration data for the DPE array 56. The PMC 72 also programs one or more hardening circuits 90 to initialize, select functions, etc. As described above, each hardening circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information for programming them may be received and provided by the PMC 72. In contrast to the hardening circuits 90, the DPE array 56 has configurable functions based on configuration data provided by the PMC 72. After programming and configuration, the programmable device 1 implements digital processing circuitry 301 between the signal conversion circuitry 66 and endpoint circuitry 306, which includes the hardening circuits 90 and custom logic 304.

[0039] FIG. 7 is a block diagram illustrating a signal processing system 700 implemented in the programmable device 1 according to an example. The signal processing system 700 includes a signal conversion circuit 66, multiple hardening circuits 90, multiple custom logic 304 configured within the PS2, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital and digital-to-analog conversion as described above. The hardening circuits 90 each perform one or more functions, such as filtering, sample rate conversion, mixing, carrier combining / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with the DPE array 56 (e.g., via the NOC 55). Each custom logic 304 is implemented by a processor executing software within the PS2 and may be connected to one or more hardening circuits 90. Each custom logic 304 may be connected to one or more other custom logic 304. One or more custom logic 304 may be connected to an endpoint circuit 306. One or more custom logic 304 may be coupled to the signal conversion circuit 66. One or more hardening circuits 90 may be coupled to the endpoint circuit 306.

[0040] The curing circuit 90 and the custom circuit 304 form a digital processing circuit 301 that is disposed between the signal conversion circuit 66 and the endpoint circuit 306. Although shown as external to PL3 (e.g., a serial transceiver), endpoint circuitry 306 can be implemented within PL3.

[0041] During operation, the PMC 72 receives information to program the programmable device 1. The PMC 72 loads configuration data for the PS2. The PMC 72 also programs one or more hardening circuits 90 to initialize, select, and otherwise configure functions. As described above, each hardening circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information for programming them may be received and provided by the PMC 72. In contrast to the hardening circuits 90, the PS2 has configurable functions based on configuration data provided by the PMC 72. After programming and configuration, the programmable device 1 implements a digital processing circuit 301 between the signal conversion circuit 66 and the endpoint circuit 306, which includes the hardening circuit 90 and custom logic 304.

[0042] FIG. 8 is a block diagram illustrating an example signal processing circuit 800. The signal processing circuit 800 includes a mix of custom circuitry configured within PL3 and hardening circuits 90. The serial transceiver 67 is coupled to custom frequency domain processing 802 implemented within PL3. The custom frequency domain processing 802 performs some custom processing of the frequency domain information to be transmitted. The custom frequency domain processing 802 is coupled to a hardened inverse fast Fourier transform (iFFT) circuit 804, implemented using one or more hardening circuits 90. The iFFT circuit 804 converts the frequency domain information to time domain information. The iFFT circuit 804 is coupled to custom time domain processing 806 configured within PL3. The custom time domain processing 806 performs some custom processing of the time domain information to be transmitted.

[0043] In the reverse direction, the signal processing circuit 800 includes custom time domain processing 808, hardened FFT 810, and custom frequency domain processing 812. The custom time domain processing 808 performs some processing of the received time domain information and is implemented within PL3. The hardened FFT is implemented using one or more hardening circuits 90 and is configured to convert the time domain information to frequency domain information. The custom frequency domain processing 812 is configured within PL3 and functions to process the frequency domain information. The frequency domain processing 812 is coupled to the serial transceiver 67.

[0044] The output of the custom time domain processing 806 and the input of the custom time domain processing 808 are coupled to a switch 814. The switch 814 can be implemented in PL3 or can be a hardening circuit implemented by one or more hardening circuits 90. The input / output of the switch 814 is coupled to the custom time domain processing 815. The custom time domain processing 815 is configured within PL3 and performs some processing of the transmitted or received time domain information. The custom time domain processing 815 is coupled to a hardening filter 816 implemented using one or more hardening circuits 90. The hardening filter 816 can have a programmable length and programmable coefficients. The hardening filter 816 can perform any type of filtering operation. The hardening filter 816 is coupled to a hardened sample rate converter 818 implemented using one or more hardening circuits 90. The hardened sample rate converter 818 functions to upsample or downsample the time domain information. The hardened sample rate converter 818 is coupled to a hardened mixer and carrier combiner / splitter 820, which is implemented using one or more hardening circuits 90. The hardened sample rate converter 818 may be programmable for varying the sample rate depending on the signal bandwidth. The hardened mixer and carrier combiner / splitter 820 is configured to modulate / demodulate the time-domain information and aggregate or split multiple streams of time-domain signals based on a particular modulation scheme (e.g., orthogonal frequency division multiplexing (OFDM)). The mixer and carrier combiner / splitter 82 0 is coupled to switch 822. Switch 822 may be implemented in PL3 or may be a hardening circuit implemented by one or more hardening circuits 90.

[0045] The output of switch 822 is coupled to a hardening crest factor reduction (CFR) circuit 826, which is implemented using one or more hardening circuits 90. The output of CFR circuit 826 is coupled to a custom DPD circuit 828, implemented in PL3. The output of DPD circuit 828 is coupled to a DAC 830. The input of switch 822 is coupled to the output of ADC 824. ADC 824 and DAC 830 are part of signal conversion circuit 66.

[0046] 8 is one specific example of an alternative processing between the hardening circuit 90 and custom circuitry configured within PL3, performed by specific digital processing circuitry between the signal conversion circuitry and the endpoint circuitry. Those skilled in the art will appreciate that other configurations are possible, including configurations that include all signal processing circuit blocks implemented using the hardening circuit 90.

[0047] While the above is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, which scope is determined by the claims that follow.

Claims

1. a configuration memory configured to store configuration data; programmable logic having configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit; Equipped with a programmable device, wherein the digital processing circuitry includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined function, and a second one or more digital processing functions implemented by the configurable functionality of the programmable logic.

2. 2. The programmable device of claim 1, wherein the first one or more implemented digital processing functions have the hardening circuitry including a digital front end (DFE) function or a conversion function, the DFE function comprising at least one of a filter circuit, a sample rate conversion circuit, and a mixer circuit, and the conversion function comprising at least one of a time-to-frequency domain conversion circuit and a frequency-to-time domain conversion circuit.

3. 10. The programmable device of claim 1, wherein the second one or more digital processing functions implemented by the configurable function of the programmable logic include at least one of a digital pre-distortion (DPD) circuit and a calibration circuit.

4. 2. The programmable device of claim 1, wherein the programmable logic comprises columns of programmable tiles and programmable interconnects, and the hardening circuitry is disposed in at least one column of hardening tiles adjacent to or interspersed within the columns of programmable tiles.

5. 2. The programmable device of claim 1, wherein the first one or more digital processing functions include one or more common functions across multiple applications or one or more common functions used by one or more standards to which the multiple applications comply, and the second one or more digital processing functions include one or more functions that are unique among the multiple applications or one or more functions that do not comply with the one or more standards.

6. Interface circuitry between multiple dies Furthermore, the hardening circuitry within the digital processing circuitry is coupled to the plurality of die-to-die interface circuits; 10. The programmable device of claim 1.

7. a configuration subsystem; at least one programmable subsystem having configurable functionality determined by said configuration subsystem; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit; Equipped with The digital processing circuitry includes at least one conversion circuit or at least one digital front-end (DFE) circuit, each implemented as a hardening circuit having a predetermined function. 、 Programmable devices.

8. 8. The programmable device of claim 1, wherein the signal conversion circuitry comprises at least one analog-to-digital conversion (ADC) circuit, at least one digital-to-analog conversion (DAC) circuit, or at least one ADC and at least one DAC.

9. 8. The programmable device of claim 7, wherein the at least one programmable subsystem comprises at least one of programmable logic, an array of data processing engines (DPEs), and a processing system.

10. 8. The programmable device of claim 7, wherein the at least one DFE circuit includes one or more common functions across multiple applications or used by one or more standards to which the multiple applications comply.

11. 8. The programmable device of claim 7, wherein the at least one DFE circuit comprises at least one of a filter circuit, a sample rate conversion circuit, and a mixer circuit.

12. 8. The programmable device of claim 7, wherein the at least one transform circuit comprises at least one of a time-to-frequency domain transform circuit and a frequency-to-time domain transform circuit.

13. a configuration subsystem; at least one programmable subsystem having configurable functionality determined by said configuration subsystem; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit; Equipped with the digital processing circuitry includes a first one or more digital processing functions implemented as hardening circuits each having a predetermined function, and a second one or more digital processing functions implemented by the configurable functions of the at least one programmable subsystem; Programmable devices.

14. 14. The programmable device of claim 13, wherein the at least one programmable subsystem comprises at least one of programmable logic, an array of data processing engines (DPEs), and a processing system.

15. 14. The programmable device of claim 1 or 13, wherein the first one or more implemented digital processing functions, with the hardening circuitry including a digital front end (DFE) function or a conversion function.

16. 14. The programmable device of claim 1 or 13, wherein the first one or more digital processing functions include one or more common functions across multiple applications or one or more common functions used by one or more standards to which the multiple applications comply.

17. The first one or more digital processing functions are used by one or more common functions across multiple applications or one or more standards to which the multiple applications comply.

14. The programmable device of claim 13, wherein the second one or more digital processing functions include one or more functions that are unique among the multiple applications or that do not conform to the one or more standards.

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