Three-dimensional memory devices and methods for forming the same

Abstract

To relate to a memory device and a method for manufacturing the same.SOLUTION: A three-dimensional (3D) memory device according to a particular embodiment includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with the source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure within the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and costly. As a result, memory densities for planar memory cells approach upper limits.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral circuitry to facilitate operation of the memory array. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment of the present disclosure, a 3D memory device includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure within the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

[0005] Another aspect of the present disclosure is a 3D memory device including a first semiconductor structure having a core region and a non-array region. The first semiconductor structure includes an array of NAND memory strings in a subregion of the core region, a semiconductor layer contacting the source ends of the array of NAND memory strings, an insulating layer in the non-array region, and a plurality of contact structures in the insulating layer and in another subregion of the non-array region. The insulating layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device also includes a second semiconductor structure coupled to the first semiconductor layer. The second semiconductor structure includes a transistor.

[0006] Another aspect of the present disclosure is a method for forming a 3D memory device. The method includes bonding a first semiconductor structure and a second semiconductor structure together, the first semiconductor structure having a core region and a non-array region. The method also includes depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure, removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion, converting a second portion of the doped amorphous silicon layer in the core region to a doped polysilicon layer, forming an insulating layer in the opening, and forming a second contact portion in the insulating layer. The second contact portion is in contact with the first contact portion.

[0007] Another aspect of the present disclosure provides a system. The system includes a memory device configured to store data. The memory device includes a first semiconductor structure having an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and contact structures in the insulating layer, where the insulating layer electrically insulates the contact structures from the semiconductor layer. The memory device also includes a second semiconductor structure coupled to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry. The system also includes a memory controller coupled to the memory device and configured to control the array of NAND memory strings through the peripheral circuitry.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic diagram of a cross section of a 3D memory device according to some embodiments of the present disclosure. [Figure 1B] FIG. 1 illustrates an overview of a 3D memory device according to some aspects of the present disclosure. [Figure 1C] FIG. 1C is a side view of the example 3D memory device of FIGS. 1A and 1B. [Figure 2] 1C is a side view of the example 3D memory device of FIGS. 1A and 1B in accordance with some aspects of the present disclosure. FIG. [Figure 3A] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3B] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3C] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3D] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3E] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3F] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3G] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3H] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3I] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3J] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3K] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3L] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3M] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 3N] 3A-3C illustrate a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 4A] 3A-3C illustrate examples of portions of a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 4B] 3A-3C illustrate examples of portions of a fabrication process for forming the 3D memory device of FIG. 2 in accordance with some aspects of the present disclosure. [Figure 5] 3 illustrates a flowchart of a method for forming the 3D memory device of FIG. 2 according to some aspects of the present disclosure. [Figure 6] FIG. 1 is a block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure. [Figure 7A] 1 is a diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure. [Figure 7B] 1 is a diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present disclosure will now be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features described in the present disclosure can be combined, adjusted, and modified with each other and in ways not specifically shown in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0012] Generally, terminology can be understood, at least in part, from contextual usage. For example, the term "one or more," as used herein, can be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular usage or plural usage, again, depending, at least in part, on the context. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly recited, again, depending, at least in part, on the context.

[0013] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" something, but can also include meaning "on" something with intermediate features or layers between them, and that "above" or "over" can not only mean "above" or "over" something, but can also include meaning it is "above" or "over" something (i.e., directly on) with no intermediate features or layers between them.

[0014] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension that is less than the extension of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes between (or at) the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (with interconnect lines and / or vertical interconnect access (via) contacts formed therein) and one or more dielectric layers.

[0016] In a 3D memory device, the peripheral circuitry and memory cell array of the memory device are arranged in different planes (levels, layers) in the vertical direction, i.e., stacked on top of each other, reducing the planar chip size of the peripheral circuitry and the total chip size of the memory device. In a 3D memory device, memory cells are formed by the intersection of NAND memory strings and word lines. The NAND memory strings are formed extending vertically in a memory stack (e.g., a pair of conductive / dielectric layers), and the source ends of the NAND memory strings are in contact with a semiconductor layer that functions as part of a source contact for applying a source voltage to the NAND memory string. The memory stack and peripheral circuitry are often integrated together through bonding in a 3D NAND flash memory device.

[0017] Through-silicon contacts (TSCs) are often formed to form electrical connections within a 3D memory device (e.g., between a memory cell array and peripheral circuitry) and / or beyond the 3D memory device (e.g., between a 3D NAND flash memory device and external circuitry). To isolate the TSCs from the semiconductor layer, the portion of the semiconductor layer in contact with the NAND memory string is often separated from the portion of the semiconductor layer through which the TSCs extend. An insulating portion is formed between the two portions of the semiconductor layer for isolation. Meanwhile, respective insulating spacers are formed in the semiconductor layer such that the TSCs are each insulated from the semiconductor layer by the respective insulating spacers. The insulating spacers and insulating portions are often formed by patterning the semiconductor layer to form openings and filling the openings with a dielectric material. Due to the small critical dimensions of these openings, deposition of the dielectric material often involves atomic layer deposition (ALD). This fabrication process can be costly due to significant expenses for photolithography, etching, and deposition. On the one hand, the small critical dimension of the opening can cause the etching process for forming the opening to be undesirably complex and can make precise alignment between the opening and the TSC difficult.

[0018] To address one or more of the above-mentioned problems, the present disclosure provides a structure and fabrication method for a 3D memory device, in which the critical dimension of the opening for forming an insulating layer that isolates the TSC and the semiconductor layer is increased, and the etching process for forming the opening is not difficult. The cost and difficulty of isolating different portions of the semiconductor layer may be reduced. A 3D memory device (having a core region and a non-array region) includes multiple NAND memory strings in the core region and one or more TSCs in the non-array region. The semiconductor layer contacts the source ends of the NAND strings in the core region. According to the present disclosure, instead of forming respective insulating spacers to isolate each TSC from the semiconductor layer, a single insulating layer can be formed to isolate multiple TSCs from the semiconductor layer. The lateral width of the insulating layer is large enough to isolate any (e.g., all) TSCs from the semiconductor layer. The insulating layer can be formed in any suitable location where isolation is needed and that is away from the source ends of the NAND memory strings. For example, the insulating layer can be formed in the non-array region. The insulating layer laterally contacts the semiconductor layer and has the same thickness as the semiconductor layer, hi some implementations, the insulating layer includes a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0019] Unlike existing patterning techniques involving photolithography and etching processes, the formation of the openings (in which the insulating layer is formed) in the present disclosure involves a localized heat treatment (e.g., a laser annealing process) and a selective etching process. A doped amorphous silicon layer is first deposited to be in contact with the source end of the NAND memory string, and a portion of the doped amorphous silicon layer is subjected to a localized heat treatment to convert into a doped polysilicon portion. The area of ​​the processed portion of the doped amorphous silicon layer can cover any TSCs to be isolated and does not overlap with the source end of the NAND memory string. In some implementations, a laser annealing process is performed for the conversion. The doped polysilicon portion is selectively etched away to form an opening in the untreated doped amorphous silicon layer. The doped amorphous silicon portion is further converted into a doped polysilicon layer, and an insulating material is deposited into the opening. The insulating layer can be further patterned to allow the TSC to extend through the insulating layer.

[0020] In the fabrication process of the present disclosure, photolithography is not required to form the openings in which the insulating layer is formed. Instead, patterning of the doped amorphous silicon layer involves a laser annealing process and a selective etching process. The critical dimensions of the doped polysilicon portion / insulating layer are desirably large so that the laser beam can be precisely controlled to anneal the desired area of ​​the doped amorphous silicon layer. Compared to existing patterning techniques, the difficulty and cost of patterning can be reduced. The larger critical dimensions of the insulating layer also allow other deposition methods (e.g., chemical vapor deposition (CVD) and / or physical vapor deposition (PVD)) to be used to form the insulating layer, further reducing fabrication costs. Increasing the area of ​​the insulating layer can also reduce the parasitic capacitance of the 3D memory device.

[0021] 1A illustrates a cross-sectional schematic view of a 3D memory device 100 according to some embodiments of the present disclosure. FIG. 1B illustrates an overview of the 3D memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. In some implementations, at least some of the components of the 3D memory device 100 (e.g., the memory cell array and peripheral circuitry) are formed separately in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process").

[0022] It is noted that x-, y-, and z-axes have been added to the figures of the present disclosure to further illustrate the spatial relationships of components of a semiconductor device. A substrate of a semiconductor device (e.g., 3D memory device 100) includes two lateral surfaces (e.g., top and bottom surfaces) extending laterally in the x- and y-directions (lateral or width directions). The x-direction is the word line direction of 3D memory device 100, the y-direction is the bit line direction of 3D memory device 100, and the z-direction is perpendicular to the xy plane. In some implementations, the z-direction is the NAND direction in which NAND memory strings extend vertically. As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device is determined in the z-direction (vertical or thickness direction) relative to the substrate of the semiconductor device when the substrate is positioned within the lowest plane of the semiconductor device in the z-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0023] The 3D memory device 100 can include a first semiconductor structure 102 that includes an array of memory cells (also referred to herein as a “memory cell array”). In some implementations, the memory cell array includes an array of NAND flash memory cells. For ease of explanation, a NAND flash memory cell array can be used as an example to describe memory cell arrays in this disclosure. However, it is understood that the memory cell array is not limited to a NAND flash memory cell array and can include any other suitable type of memory cell array (e.g., a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc., to name a few).

[0024] The first semiconductor structure 102 can be a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages or fingers, which are then organized into blocks, where each NAND memory cell is connected to a separate line called a bit line (BL). All cells having the same vertical position in the NAND memory cell can be connected through their control gates by a word line (WL). In some implementations, a memory plane contains a certain number of blocks connected through the same bit line. The first semiconductor structure 102 can include one or more memory planes, and the peripheral circuitry required to perform all read / program (write) / erase operations can be included in the second semiconductor structure 104.

[0025] In some implementations, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating gate transistor. According to some implementations, the array of 2D NAND memory cells includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells connected in series (similar to a NAND gate) and two select transistors. According to some implementations, each of the 2D NAND memory strings is arranged in the same plane (i.e., this specification refers to a flat two-dimensional (2D) surface, different from the term "memory plane" in this disclosure) above the substrate. In some implementations, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically (in 3D) above the semiconductor layers through a stack structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), the 3D NAND memory string typically includes a certain number of NAND memory cells, each of which includes a floating gate transistor or a charge trap transistor.

[0026] 1A , the 3D memory device 100 may also include a second semiconductor structure 104 having peripheral circuitry for the memory cell array in the first semiconductor structure 102. The peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate operation of the memory cell array. For example, the peripheral circuitry may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an I / O circuit, a charge pump, a voltage supply or generator, a current or voltage reference, any portion (e.g., subcircuit) of the functional circuitry described above, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of a circuit. The peripheral circuitry in the second semiconductor structure 104 may use complementary metal-oxide-semiconductor (CMOS) technology, e.g., it may be implemented by a logic process in any suitable technology node.

[0027] As shown in FIG. 1A , the first and second semiconductor structures 102 and 104 are stacked on top of each other in different planes according to some implementations. As a result, the memory cell array in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 are stacked on top of each other in different planes, allowing the planar size of the 3D memory device 100 to be reduced compared to a memory device in which all peripheral circuitry is disposed in the same plane. As shown in FIG. 1A , in some implementations, the first semiconductor structure 102 is above the second semiconductor structure 104 and includes a pad-out interconnect layer for pad-out purposes. TSVs can be formed extending into the first semiconductor structure 102 to provide electrical connection between components in the memory device 100 (e.g., the peripheral circuitry and / or the memory cell array) and any external circuitry.

[0028] 1A, the 3D memory device 100 further includes a bonding interface 106 between the first semiconductor structure 102 and the second semiconductor structure 104 in the vertical direction. The bonding interface 106 can be an interface between the two semiconductor structures formed by any suitable bonding technique (e.g., hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc., to name a few), as described in detail below. Data transfer between the memory cell array in the first semiconductor structure 102 and the peripheral circuitry in the second semiconductor structure 104 can be performed through interconnects (e.g., bonding contacts) across the bonding interface 106. As shown in FIG. 1A, in some implementations, the memory cell array is above the bonding interface 106 and the peripheral circuitry is below the bonding interface 106 in the z-direction.

[0029] As described in detail below, some of the first and second semiconductor structures 102 and 104 can be fabricated separately (and in some implementations in parallel) by parallel processes, such that the thermal budget for fabricating one of the first and second semiconductor structures 102 and 104 does not limit the process for fabricating another one of the first and second semiconductor structures 102 and 104. Moreover, numerous interconnects (e.g., bonding contacts and / or inter-layer vias (ILVs) / through substrate vias (TSVs)) can be formed across the bonding interface 106 to make direct, short-range (e.g., micron- or submicron-level) electrical connections between adjacent semiconductor structures 102 and 104.

[0030] FIG. 1B illustrates an overview of a memory device 100 according to some embodiments of the present disclosure. Specifically, FIG. 1B illustrates a core region 108 and a non-array region 110 in a first semiconductor structure 102 in the xy plane. In some implementations, a memory cell array is formed in the core region 108, and a TSC is formed in the non-array region 110. In some implementations, the non-array region 110 is positioned on the periphery of the core region 108 or surrounds the core region 108. For example, the non-array region 110 can be a region separate from the memory cell array (e.g., a staircase region). In various implementations, other regions may be included in the non-array region 110 but are not part of the staircase region. In some implementations, the non-array region 110 and the core region 108 do not overlap each other in the xy plane.

[0031] FIG. 1C illustrates a side view of a portion of a 3D memory device 103, which is an example of memory device 100. The 3D memory device includes a first semiconductor structure 105 and a second semiconductor structure 107, which are bonded to each other at a bonding interface 109. The first semiconductor structure 105 is an example of the first semiconductor structure 102, and the second semiconductor structure 107 is an example of the second semiconductor structure 104. The first semiconductor structure 105 includes a plurality of NAND memory strings 117, a plurality of TSCs 115, a semiconductor layer 111, and a plurality of pad-out interconnects 119. The source ends of the NAND memory strings 117 (located in the core region 108) are in contact with a first portion 111-1 of the semiconductor layer. The second portion 111-2 of the semiconductor layer is insulated / separated from the first portion 111-1 of the semiconductor layer by an insulating portion 113 (which includes a dielectric material such as silicon oxide). The TSCs 115 are positioned in the non-array region 110 and can extend through the second portion 111-2 of the semiconductor layer. The pad-out interconnects 119 can be conductively connected to components in the 3D memory device 103 for pad-out purposes. Each TSC 115 resides in (e.g., passes through) a respective insulating spacer 121 in the second portion 111-2 of the semiconductor layer. The insulating spacers 121 include the same material (e.g., silicon oxide) as the insulating portions 113.

[0032] The insulating portions 113 and the insulating spacers 121 are formed by patterning the semiconductor layer 111 to form respective openings and filling the openings with a dielectric material. The patterning process often includes a photolithography process followed by an etching process. The openings for forming the insulating spacers 121 are precisely aligned with, for example, the TSCs 115. Due to the small critical dimensions of the insulating portions 113 and the insulating spacers 121, the dielectric material is often deposited using ALD. Therefore, the fabrication process for forming the 3D memory device 103 can be difficult and costly.

[0033] 2 illustrates a side view of a portion of an exemplary 3D memory device 200 in the xz plane, according to some aspects of the present disclosure. The 3D memory device 200 can be an example of the memory device 100 and, according to some implementations, is a bonded chip including a first semiconductor structure 203 and a second semiconductor structure 207 stacked in different planes in the vertical direction (e.g., the z direction). The first and second semiconductor structures 203 and 207, according to some implementations, are bonded at a bonding interface 209 therebetween. It should be noted that the components illustrated in FIGS. 2, 3A-3N, 4A, and 4B are intended to illustrate relative positions and do not represent actual electrical connections within the 3D memory device 200.

[0034] As shown in FIG. 2 , first and second semiconductor structures 203 and 207 can be bonded to each other in a face-to-face manner at bonding interface 209. Second semiconductor structure 207 can include a substrate 202 and a device layer 204 above and in contact with substrate 202. Substrate 202 can include silicon (e.g., monocrystalline silicon, c-silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some implementations, element 202 represents a semiconductor layer, which can be formed by thinning a substrate. In some implementations, substrate 202 includes monocrystalline silicon. In some implementations, device layer 204 includes peripheral circuitry (details not shown in the figures). The peripheral circuits can include high-voltage (HV) circuits (e.g., driver circuits, etc.) and low-voltage (LV) circuits (e.g., page buffer circuits and logic circuits, etc.). In some implementations, the peripheral circuits include a plurality of transistors in contact with the substrate 202 (or the semiconductor layer 202, if applicable). The transistors can include any transistors disclosed herein (e.g., planar transistors, 3D transistors, etc.).

[0035] In some implementations, the second semiconductor structure 207 further includes an interconnect layer 205 above the device layer 204 to transfer electrical signals to and from peripheral circuitry in the device layer 204. As shown in FIG. 2 , the interconnect layer 205 can be vertically between the bonding interface 209 and the device layer 204 (including transistors of the peripheral circuitry). The interconnect layer 205 can include multiple interconnects (including lateral lines and vias). As used herein, the term “interconnect” can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnects can be coupled to transistors of the peripheral circuitry in the device layer 204. The interconnect layer 205 may further include one or more interlevel dielectric (ILD) layers (also known as “intermetal dielectric (IMD) layers”), and lateral lines and vias may be formed in the one or more interlevel dielectric (ILD) layers. That is, the interconnect layer 205 may include lateral lines and vias in multiple ILD layers. In some implementations, the devices in the device layer 204 are coupled to each other through interconnects in the interconnect layer 205. The interconnects in the interconnect layer 205 may include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The ILD layers in the interconnect layer 205 may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-dielectric constant (low-k) dielectric, or any combination thereof. In some implementations, the interconnects in interconnect layer 205 include W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer detectable features (e.g., voids)) among conductive metal materials.

[0036] 2, the second semiconductor structure 207 may further include a bonding layer 206 in contact with the interconnect layer 205 at a bonding interface 209 and above the interconnect layer 205. The bonding layer 206 may include a plurality of bonding contacts 233 and a dielectric that electrically isolates the bonding contacts 233. The bonding contacts 233 may include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the bonding contacts 233 of the bonding layer 206 include Cu. The remaining areas of the bonding layer 206 may be formed by a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 233 and surrounding dielectric in bonding layer 206 can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) that can simultaneously obtain metal-metal (e.g., Cu-to-Cu) bonding and dielectric-dielectric (e.g., SiO2-to-SiO2) bonding. For example, the bonding interface can be distinguished based on the relative position (e.g., shift) of the bonded contacts 231 and 233.

[0037] As shown in FIG. 2 , the first semiconductor structure 102 may further include a bonding layer 208 at the bonding interface 209 (e.g., on the opposite side of the bonding interface 209 from the bonding layer 206 in the second semiconductor structure 207). The bonding layer 208 may include a plurality of bonding contacts 231 and a dielectric that electrically isolates the bonding contacts 231. The bonding contacts 231 may include a conductive material (e.g., Cu, etc.). The remaining area of ​​the bonding layer 208 may be formed by a dielectric material (e.g., silicon oxide, etc.). The bonding contacts 231 and the surrounding dielectric in the bonding layer 208 may be used for hybrid bonding. In some implementations, the bonding interface 209 is where the bonding layers 208 and 206 meet and bond. In practice, the bonding interface 209 may be a layer having a certain thickness that includes the top surface of the bonding layer 206 and the bottom surface of the bonding layer 208.

[0038] As shown in FIG. 2 , the first semiconductor structure 203 may further include an interconnect layer 210 above and in contact with the bonding layer 208 to transfer electrical signals. The interconnect layer 210 may include multiple interconnects (e.g., MEOL interconnects and BEOL interconnects, etc.). In some implementations, the interconnects in the interconnect layer 210 also include local interconnects (e.g., bit line contacts and word line contacts, etc.). The interconnect layer 210 may further include one or more ILD layers, and lateral lines and vias may be formed in the one or more ILD layers. The interconnects in the interconnect layer 210 may include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The ILD layers in the interconnect layer 210 may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0039] As shown in FIG. 2 , the first semiconductor structure 203 can include a memory cell array, such as an array of NAND memory strings 217 above and in contact with the interconnect layer 210. In some implementations, the interconnect layer 210 is vertically between the NAND memory strings 217 and the bonding interface 209. Each NAND memory string 217, according to some implementations, extends vertically through multiple pairs of gate conductors 239 and dielectric layers 240. The stacked and interleaved gate conductor layers 239 and dielectric layers 240 are also referred to herein as a stack structure (e.g., memory stack 212 (pairs of conductive / dielectric layers)). According to some implementations, the interleaved gate conductor layers 239 and dielectric layers 240 in the memory stack 212 alternate vertically. Each gate conductor layer 239 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material (such as, for example, titanium nitride (TiN)), which may improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the gate conductor layer 239 may extend laterally as a word line and terminate in one or more staircase structures of the memory stack 212. The staircase structures (located in the staircase region that is part of the non-array region 110) may be in contact with a plurality of wordline contacts 237 for applying a voltage to the gate conductor layer 239.

[0040] The number of pairs of gate conductor layers 239 and dielectric layers 240 in the memory stack 212 can be one of the factors that determine the number of memory cells in the memory cell array. The gate conductor layers 239 can include a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductor layer 239 includes a metal layer (e.g., a tungsten layer). In some implementations, each gate conductor layer 239 includes a doped polysilicon layer. Each gate conductor layer 239 can include a control gate surrounding a memory cell.

[0041] As shown in FIG. 2 , each NAND memory string 217 includes a channel structure extending vertically through the memory stack 212. In some implementations, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon (e.g., polysilicon). In some implementations, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also known as a “charge trap / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a pillar shape). According to some implementations, the semiconductor channel, tunneling layer, storage layer, and blocking layer are arranged in this order radially from the center to the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer. The channel structure may further include a channel plug at the drain end of the NAND memory string 217. The channel plug may include polysilicon and may be in contact with the semiconductor channel. In some implementations, each NAND memory string 217 is a “charge trap” type NAND memory. It is understood that the NAND memory string 217 is not limited to a “charge trap” type NAND memory string, and may be a “floating gate” type NAND memory string in other examples.

[0042] According to some implementations, the NAND memory strings 217 lack any semiconductor plugs at their source ends. Instead, the 3D memory device 200 includes a semiconductor layer 211 above and in contact with the memory stacks 212. The semiconductor layer 211 can contact sidewalls of the semiconductor channels of the channel structures at the source ends of each NAND memory string 217. The semiconductor layer 211 can include a semiconductor material (e.g., doped polysilicon, etc.). In some implementations, the semiconductor layer 211 is doped with an N-type dopant, such as phosphorus and / or arsenic. The thickness of the semiconductor layer 211 can range from 100 nm to 600 nm. In some implementations, the semiconductor layer 211 and the source contact in the slit structure (e.g., an array common source or ACS (not shown)) can collectively function as part of a source line (not shown) that is coupled to the source end of the NAND memory string 217, for example, to apply an erase voltage to the source end of the NAND memory string 217 during an erase operation.

[0043] The semiconductor layer 211 includes a first semiconductor layer portion 211-1 and a second semiconductor layer portion 211-2, which are at the same level in the z-direction and separated by an insulating layer 213. The insulating layer 213 may be in laterally contact with each of the first and second semiconductor layer portions 211-1 and 211-2 and may have the same thickness as the semiconductor layer 211. The first and second semiconductor layer portions 211-1 and 211-2 may be separated / insulated from each other by the insulating layer 213. In some implementations, the insulating layer 213 is a single insulating layer comprising a consistent medium / material in the xy plane. That is, the insulating layer 213 may not be separated between any two contact structures 215. The first semiconductor layer portion 211-1 (located partially or entirely within the core region 108) may be above and in contact with the source end of the NAND memory string 217. The area of ​​the first portion 211-1 of the semiconductor layer can be large enough to be in contact with the source ends of all of the NAND memory strings 217 (e.g., can be larger than or equal to the total area in which all of the NAND memory strings 217 are formed (e.g., sub-areas of the core region 108)). The orthogonal projection of the insulating layer 213 in the xy plane can cover multiple (e.g., all) of the contact structures 215. In various implementations, the orthogonal projection of the insulating layer 213 at least partially overlaps the staircase region. In some implementations, the orthogonal projection of the insulating layer 213 does not overlap the core region 108. In various implementations, the second portion 211-2 of the semiconductor layer may or may not be present. In some implementations, the top surface of the insulating layer 213 is coplanar with the top surface of the semiconductor layer 211, and the bottom surface of the insulating layer 213 is coplanar with the bottom surface of the semiconductor layer 211. The insulating layer 213 can include a dielectric material, such as silicon oxide, silicon nitride, and / or silicon oxynitride, etc. In some implementations, the insulating layer 213 includes silicon oxide.

[0044] 2, the first semiconductor structure 203 may further include one or more contact structures 215 extending vertically in (e.g., through) the insulating layer 213. In some implementations, the contact structures 215 couple interconnects in the interconnect layer 210 to pad-out interconnects 219 in the pad-out interconnect layer 216, facilitating electrical connection through the first semiconductor structure 203. The contact structures 215 may include a conductive material including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some implementations, the contact structures 215 include W. In some implementations, the contact structures 215 may each be a TSV having a depth (e.g., length along the z-direction) on the micron or tens of microns level (e.g., between 1 μm and 100 μm).

[0045] 2, the contact structure 215 can be positioned in the non-array region 110 of the first semiconductor structure 203 or can be positioned away from the NAND memory string 217, for example, in the x-y plane. In some implementations, the insulating layer 213 can be partially or completely positioned in the non-array region 110 and provide isolation of the at least one contact structure 215 from the semiconductor layer 211. In some implementations, the insulating layer 213 is positioned in the staircase region of the 3D memory device 200. In some other implementations, the insulating layer 213 is positioned outside the staircase region but in the non-array region 110. In some implementations, the width of the insulating layer 213 in the x-direction and / or y-direction is large enough to surround multiple (e.g., all) contact structures 215 in the non-array region 110 such that all contact structures 215 surrounded by the insulating layer 213 are insulated from the first portion 211-1 of the semiconductor layer. The insulating layer 213 may also insulate the second portion 211-2 of the semiconductor layer (if present) from the first portion 211-1 of the semiconductor layer. In various implementations, the insulating layer 213 may be spaced apart from the source ends of the NAND memory strings 217, and the width and / or area of ​​the insulating layer 213 may desirably be large to isolate a maximum number of contact structures 215. For example, the area of ​​the insulating layer 213 (e.g., a subregion of the non-array region 110) may be greater than or equal to the total area in which the contact structures 215 are located. In some implementations, the insulating layer 213 is located in the non-array region 110.

[0046] 2, the first semiconductor structure 203 may further include a pad-out interconnect layer 216 above and in contact with the semiconductor layer 211. In some implementations, the semiconductor layer 211 is disposed vertically (in the z-direction) between the pad-out interconnect layer 216 and the NAND memory strings 217. The pad-out interconnect layer 216 can include a second insulating layer 214 above and in contact with the semiconductor layer 211 and the insulating layer 213, a plurality of contact portions 241 above and in contact with the first portion 211-1 of the semiconductor layer, a first contact layer 221 above and in contact with the contact structure 215, a second contact layer 223 above and in contact with the contact portion 241, a third insulating layer 227 above and in contact with the first and second contact layers 221 and 223, and a plurality of pad-out interconnects 219 (e.g., contact pads) in the third insulating layer 227. In some implementations, the pad-out interconnects 219 conductively connected to the contact structures 215 are used to drive transistors in peripheral circuits in the device layer 204. In some implementations, pad-out interconnects 219 conductively connected to NAND memory strings 217 are used to provide voltages for memory cell operations (e.g., erasing, writing, and reading).

[0047] The second insulating layer 214 can provide insulation between the contact structures 215 and the contacts 241. The first contact layer 221 (in contact with the contact structures 215 and the respective pad-out interconnects 219) can provide electrical connection between the contact structures 215 and the respective pad-out interconnects 219. The second contact layer 223 (in contact with the contacts 241 and the respective pad-out interconnects 219) can provide electrical connection between the source ends of the NAND memory strings 217 and the respective pad-out interconnects 219. The first and second contact layers 221 and 223 can be insulated from each other, for example, by one or more insulating portions 225. In some implementations, the pad-out interconnects 219 can transfer electrical signals between the 3D memory device 200 and an external device, for example, for pad-out purposes. In some implementations, the second insulating layer 214, the insulating portion 225, and the third insulating layer 227 can each include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any combination thereof. Each of the second insulating layer 214 and the third insulating layer 227 can be a single-layer structure or a multi-layer structure. For example, the third insulating layer 227 can include a silicon nitride layer above a silicon oxide layer. The silicon oxide layer can be in contact with the first and second contact layers 221 and 223, and the silicon nitride layer can cover the silicon oxide layer. The silicon oxide layer can provide balanced stress to the first and second contact layers and the silicon nitride layer. The silicon nitride layer can provide desired insulation against contaminants (e.g., moisture, air, and / or chemicals). The contact structure 215, the contact portion 241, the first and second contact layers 221 and 223, and the pad-out interconnect 219 may each comprise tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.In some implementations, the contact structure 215, the contact 241, and the pad-out interconnect 219 may each comprise tungsten.

[0048] It should be noted that the second insulating layer 214 and the insulating layer 213 can comprise the same material, and although the interface between the second insulating layer 214 and the insulating layer 213 is not visible (e.g., difficult to distinguish), the second insulating layer 214 and the insulating layer 213 can also be defined as two different layers in the present disclosure. For example, if the insulating layer 213 and the second insulating layer 214 comprise the same material, the insulating layer 213 can be the portion of the material that contacts the semiconductor layer 211 laterally (e.g., on a side surface of the semiconductor layer 211), and the second insulating layer 214 can be the portion of the material that contacts the semiconductor layer 211 and the insulating layer 213 vertically (e.g., on the top surfaces of the semiconductor layer 211 and the insulating layer 213). That is, the interface between the semiconductor layer 211 and the insulating layer 213 can extend in the z-direction, and the interface between the semiconductor layer 211 / insulating layer 213 and the second insulating layer 214 can extend in the xy-plane.

[0049] 3A-3N illustrate a fabrication process for forming a 3D memory device 200 according to some embodiments of the present disclosure. FIGS. 4A and 4B illustrate a portion of another fabrication process for forming a 3D memory device 200 according to some embodiments of the present disclosure. FIG. 5 illustrates a flowchart of a method 500 for forming a 3D memory device 200 according to some embodiments of the present disclosure. It is understood that the operations illustrated in method 500 are not exhaustive, and that other operations may similarly be performed before, after, or during any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 5.

[0050] 5, the method 500 begins at operation 502, where a doped amorphous silicon layer is formed over a semiconductor structure having a core region and a step region. Figure 3A illustrates the corresponding structure.

[0051] As shown in FIG. 3A , a doped amorphous silicon layer 320 is formed over a semiconductor structure 350, the semiconductor structure 350 having a core region 108 and a non-array region 110. The semiconductor structure 350 may be an example of a 3D memory device 200. As shown in FIG. 3A , the semiconductor structure 350 may include a portion of a first semiconductor structure coupled to a second semiconductor structure at a bonding interface 309. The second semiconductor structure may include a substrate 302, a device layer 304, an interconnect layer 305, and a bonding layer 306. The portion of the first semiconductor structure may include a bonding layer 308, an interconnect layer 310, and an array stack 312. The array stack 312 may include a plurality of interleaved gate conductor layers 339 and a plurality of dielectric layers 340. The array stack 312 may also include an array of NAND memory strings 317 extending through the interleaved gate conductor layers 339 and dielectric layers 340. The first semiconductor structure may also include one or more first contact portions 315-1, which extend vertically and are coupled to the interconnect layer 310. The first contact portion 315-1 may subsequently form a lower portion of a TSV (e.g., contact structure 215). The NAND memory string 317 may be located in the core region 108, and the first contact portion 315-1 may be located in the non-array region 110. A detailed description of each component may refer to the description of the 3D memory device 200 in FIG. 2 and will not be repeated herein.

[0052] To form the first semiconductor structure, a stack structure (e.g., a memory stack including interleaved gate conductor layers and dielectric layers) is formed on a first substrate to form the array stack 312. In some implementations, the first substrate includes a suitable base material such as silicon. To form the memory stack, in some implementations, a dielectric stack (not shown) including interleaved sacrificial layers (not shown) and dielectric layers is formed on the first substrate. In some implementations, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial layers and dielectric layers can be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The dielectric stack can be repeatedly patterned to form multiple staircases in the non-array region 110. The memory stack can then be formed by a gate exchange process, e.g., by replacing the sacrificial layer with a conductor layer using wet / dry etching of the sacrificial layer selective to the dielectric layer and filling the resulting recess with the conductor layer. In some implementations, each conductor layer includes a metal layer (e.g., a layer of W). It will be appreciated that in some examples, the memory stack can also be formed by alternately depositing conductor layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without the gate exchange process. In some implementations, a pad oxide layer including silicon oxide (e.g., thermally grown local oxidation of silicon (LOCOS)) is formed between the memory stack and the first substrate. A plurality of contact vias can be formed extending vertically and landing on the stair to form electrical connections between the gate conductor layer 339 and the interconnect layer 310 to be formed.

[0053] NAND memory strings 317 can be formed above the first substrate. Each NAND memory string 317 extends vertically through the dielectric stack (or memory stack, depending on the fabrication process) and is in contact with the first substrate. In some implementations, the fabrication process for forming the NAND memory strings 317 includes forming a channel hole through the dielectric stack (or memory stack) into the first substrate using dry etching and / or wet etching (e.g., deep reactive ion etching (DRIE)), followed by filling the channel hole with multiple layers, such as memory films (e.g., tunneling layers, storage layers, and blocking layers) and semiconductor layers, using a thin film deposition process (e.g., ALD, CVD, PVD, or any combination thereof).

[0054] In some implementations, an interconnect layer 310 is formed above the array of NAND memory strings 317 on the first substrate. The interconnect layer 310 can include a first plurality of interconnects in one or more ILD layers. The interconnect layer 310 can include MEOL and / or BEOL interconnects in the multiple ILD layers to provide electrical connection to the NAND memory strings 317. In some implementations, the interconnect layer 310 includes multiple ILD layers formed and interconnects therein in multiple processes. For example, the interconnects in the interconnect layer 310 can include a conductive material deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Additionally, the fabrication process for forming the interconnects can include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layer can include a dielectric material deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The illustrated ILD layer and interconnects can be collectively referred to as interconnect layer 310. In some implementations, the interconnects in interconnect layer 310 include W, which has a relatively high thermal budget among conductive metal materials to sustain subsequent high-temperature processes.

[0055] In some implementations, a bonding layer 308 is formed above the interconnect layer 310. The bonding layer 308 can include a plurality of first bonding contacts 331 surrounded by a dielectric. In some implementations, the dielectric layer is deposited on the top surface of the interconnect layer 310 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The first bonding contacts 331 can then be formed through the dielectric layer in contact with the interconnects in the interconnect layer 310 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0056] To form a second semiconductor structure, a device layer 304 is formed on a substrate 302 (e.g., a second substrate). The device layer 304 can include multiple transistors on the substrate 302. The substrate 302 can be a silicon substrate having single-crystal silicon. The transistors can be formed by multiple processes, including, but not limited to, photolithography, dry / wet etching, thin-film deposition, thermal expansion, implantation, CMP, and any other suitable process. In some implementations, doped regions are formed in the substrate 302 by ion implantation and / or thermal diffusion, which function, for example, as wells and source / drain regions of the transistors. In some implementations, isolation regions (e.g., shallow trench isolation (STI)) are also formed in the substrate 302 by wet / dry etching and thin-film deposition. The transistors can function as part or all of the peripheral circuitry for controlling the NAND memory string 317. It is understood that the details of fabricating the transistors can vary depending on the type of transistor and, therefore, are not detailed for ease of explanation.

[0057] In some implementations, an interconnect layer 305 is formed above the transistors on the substrate 302. The interconnect layer 305 can include multiple interconnects in one or more ILD layers. As shown in FIG. 3 , the interconnect layer 305 can be formed above the transistors in the device layer 304. The interconnect layer 305 can include MEOL and / or BEOL interconnects in multiple ILD layers to provide electrical connection to the transistors. In some implementations, the interconnect layer 305 includes multiple ILD layers and interconnects therein formed in multiple processes. In some implementations, a first contact portion 315-1 can be formed in the non-array region 110, extending into the array stack 312 and coupled to an interconnect in the interconnect layer 305. Formation of the first contact portion 315-1 can include photolithography, etching, and deposition. For example, the first contact portion 315-1 and the interconnects in the interconnect layer 305 can include conductive materials deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer can include dielectric materials deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layer and the interconnects can be collectively referred to as the interconnect layer 305. In some implementations, the interconnects in the interconnect layer 305 include W, which has a relatively high thermal budget among conductive metal materials to sustain subsequent high-temperature processes.

[0058] In some implementations, a bonding layer 306 is formed above the interconnect layer 305. The bonding layer 306 can include a plurality of second bonding contacts 333 surrounded by a dielectric. In some implementations, the dielectric layer is deposited on the upper surface of the interconnect layer 305 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The second bonding contacts 333 can then be formed through the dielectric layer in contact with the interconnects in the interconnect layer 305 by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0059] As shown in FIG. 3A , a first semiconductor structure (e.g., array stack 312 and NAND memory string 317 formed therethrough) is flipped upside down. A downward-facing bonding layer 308 is bonded to an upward-facing bonding layer 306, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 309. That is, first and second bonding contacts in bonding layers 308 and 306 are bonded at bonding interface 309. In some implementations, a treatment process (e.g., plasma treatment, wet treatment, and / or localized heat treatment) is applied to the bonding surfaces before bonding. As a result of bonding (e.g., hybrid bonding), first and second bonding contacts 331 and 333 on opposite sides of bonding interface 309 can be intermixed. According to some implementations, after bonding, the first bonding contact 331 in bonding layer 308 and the second bonding contact 333 in bonding layer 306 are aligned and in contact with each other, such that the array stack 312 and the NAND memory string 317 formed therethrough can be coupled to a transistor through the bonded bonding contacts across the bonding interface 309. The first substrate can then be partially or completely removed to expose the source ends of the NAND memory strings 317. In some implementations, the removal of the first substrate includes an appropriate etching process (e.g., dry etching and / or wet etching) and / or a planarization process (e.g., chemical mechanical polishing or CMP). The bonded chip with the first substrate partially or completely removed can be referred to as semiconductor structure 350.

[0060] A doped amorphous silicon layer 320 may be deposited above the semiconductor structure 350 on the side / surface where the source ends of the NAND memory strings 317 are exposed. The doped amorphous silicon layer 320 may be in contact with at least the source ends of a plurality (e.g., all) of the NAND memory strings 317 in the core region 108. In some implementations, the doped amorphous silicon layer 320 may cover and be in contact with at least one (e.g., all) of the first contact portions 315-1 in the non-array region 110. For example, the doped amorphous silicon layer 320 may cover both the core region 108 and the non-array region 110. In some implementations, the doped amorphous silicon layer 320 is deposited using a low-temperature deposition process (e.g., low-temperature chemical vapor deposition (CVD)). For example, the deposition temperature may be in a range of 400 degrees Celsius to 450 degrees Celsius. Dopants (e.g., phosphorus and / or arsenic) can be doped using an in-situ doping process. In some implementations, the thickness of the doped amorphous silicon layer 320 is in the range of 100 nm to 600 nm. In various implementations, the thickness of the doped amorphous silicon layer 320 is controlled to be in a desired range so that a subsequent localized heat treatment (e.g., a laser annealing process) can fully convert selected areas.

[0061] The method 500 proceeds to operation 504, where a first portion of the doped amorphous silicon layer in the staircase region is converted to a doped polysilicon portion using a localized thermal treatment, while maintaining a second portion of the doped amorphous silicon layer over the core region. Figure 3B illustrates the corresponding structure.

[0062] 3B , the first portion 320a of the doped amorphous silicon layer may be converted to a doped polysilicon portion, and the second portion 320b of the doped amorphous silicon layer may be left. In some implementations, the third portion 320c of the doped amorphous silicon layer in the non-array region 110 may also be left. The first portion 320a of the doped amorphous silicon layer may overlie (e.g., cover) any / all of the first contact portions 315-1 that will be insulated from the NAND memory string 317. In some implementations, the first portion 320a of the doped amorphous silicon layer is partially or completely located in the non-array region 110. The conversion of the doped amorphous silicon to doped polysilicon may include a localized heat treatment (e.g., a laser annealing process, etc.). The localized heat treatment can be limited to a desired, controlled area and will not affect other heat-sensitive structures (e.g., bonding contacts 331 and 333 at bonding interface 209 and other copper structures / interconnects). The first portion 320a of the doped amorphous silicon layer can crystallize during the localized heat treatment to form a doped polysilicon portion. In some implementations, the temperature of the laser annealing process can range from 1300 degrees Celsius to 1700 degrees Celsius. In some implementations, the laser annealing process includes multiple laser pulses, each having a pulse time of 100 ns (i.e., nanoseconds) to 300 ns.

[0063] The localized heat treatment (e.g., a laser annealing process) can be controlled to be performed only on the first portion 320a of the doped amorphous silicon layer. A lateral dimension L1 (e.g., in the x and / or y directions) of the first portion 320a of the doped amorphous silicon layer can be large enough to cover at least a plurality (e.g., all) of the first contact portions 315-1. For example, the lateral dimension L1 can be equal to or smaller than the lateral dimension of the non-array region 110 in the x direction. In some implementations, the lateral dimension L1 can be equal to or smaller than the lateral dimension of the staircase region. In some embodiments, the lateral dimension L1 (e.g., along the x and / or y directions) can be equal to or greater than three times the thickness of the doped amorphous silicon layer 320a in the z direction. In some implementations, the area of ​​the first portion 320a of the amorphous silicon layer may cover the total area of ​​all first contact portions 315-1 in all lateral directions. Meanwhile, the lateral dimension L2 of the second portion 320b of the doped amorphous silicon layer may be greater than or equal to the total lateral dimension of all NAND memory strings 317 in the x-direction. For example, the area of ​​the second portion 320b of the doped amorphous silicon layer may completely cover all NAND memory strings 317 and thus may be equal to or greater than the total area of ​​all NAND memory strings 317. In some implementations, the lateral dimension L2 is equal to or greater than the lateral dimension of the core region 108.

[0064] 5, the method 500 proceeds to operation 506, where the doped polysilicon portion is removed to form a first opening. Figure 3C illustrates the corresponding structure.

[0065] As shown in FIG. 3C , the doped polysilicon layer (converted from the first portion 320a of the doped amorphous silicon layer) can be selectively removed to form a first opening 313a in the doped amorphous silicon layer 320. The first opening 313a can expose the first contact portion 315-1 (e.g., any first contact portion 315-1 covered by the doped polysilicon layer). In some implementations, the aspect ratio (e.g., the ratio of depth to width) of the first opening 313a is less than or equal to 1 / 3. For example, the aspect ratio is less than or equal to 1 / 5. The small aspect ratio can enable a cheaper and easier deposition process of insulating material into the first opening 313a. In some implementations, ALD is not required for the deposition. In some implementations, the first opening 313a is a single opening. The second portion 320b of the doped amorphous silicon layer may be left behind, and in some implementations, the third portion 320c of the doped amorphous silicon layer (if any) may be left behind.

[0066] The doped polysilicon layer can be removed using an etchant that has a higher etch rate for doped polysilicon than for doped amorphous silicon, such that the doped polysilicon layer can be selectively etched away from the doped amorphous silicon layer 320. In some implementations, the etchant includes ammonia.

[0067] 5, the method 500 proceeds to operation 508, where the remaining portion of the doped amorphous silicon layer is converted to a doped polysilicon layer using a localized thermal treatment. Figure 3D illustrates the corresponding structure.

[0068] 3D , the remaining second portion 320b of the doped amorphous silicon layer and any remaining third portion 320c of the doped amorphous silicon layer can be converted to a doped polysilicon layer 311 using a localized thermal treatment (e.g., a laser annealing process) similar or the same as the laser annealing process in operation 504. The doped polysilicon layer 311 can be referred to as a semiconductor layer. The remaining portions of the doped amorphous silicon layer 320 can crystallize during the localized thermal treatment to form a doped polysilicon layer. The crystallization of the doped amorphous silicon can be controlled to be in any suitable area in the doped amorphous silicon layer 320 where an electrical connection needs to be made. In some implementations, the second portion 320b of the doped amorphous silicon layer can be converted to the first portion 311-1 of the doped polysilicon layer, and any third portion 320c of the doped amorphous silicon layer can be converted to the second portion 311-2 of the doped polysilicon layer. In some implementations, the temperature of the laser annealing process can be in the range of 1300 degrees Celsius to 1700 degrees Celsius. In some implementations, the laser annealing process includes multiple laser pulses, each having a pulse time of 100 ns (i.e., nanoseconds) to 300 ns. A localized heat treatment (e.g., laser annealing process) can be controlled to be performed on at least the second portion 320b of the doped amorphous silicon layer. In some implementations, the localized heat treatment is performed only on the remaining second portion 320b of the amorphous silicon layer, but not on the third portion 320c of the amorphous silicon layer. In some implementations, the localized heat treatment is performed only on the remaining second portion 320b of the amorphous silicon layer that is in contact with the NAND memory string 317, but not on the remainder of the second portion 320b of the amorphous silicon layer or the third portion 320c of the amorphous silicon layer.

[0069] 5, the method 500 proceeds to operation 510, where an insulating material is deposited over the polysilicon layer and into the first opening to form a first insulating layer in the first opening, and a second insulating layer over the first insulating layer and the doped polysilicon layer. Figure 3E illustrates the corresponding structure.

[0070] 3E, an insulating material may be deposited over the doped polysilicon layer 311 and into the first opening 313a to form a first insulating layer 313 in the first opening 313a, and a second insulating layer 314 may be formed over the first insulating layer 313 and the doped polysilicon layer 311. The first insulating layer 313 may be formed by filling the first opening 313a with an insulating material and may cover any first contact portion 315-1 exposed in the first opening 313a. The first insulating layer 313 may be in contact with the first portion 311-1 of the doped polysilicon layer and the second portion 311-2 of the doped polysilicon layer (if any). In some implementations, when the doped polysilicon layer 311 does not include the second portion 311-2 of the doped polysilicon layer, the first insulating layer 313 can extend laterally to the periphery of the non-array region 110. The insulating material (e.g., a dielectric material, etc.) can include silicon oxide, silicon nitride, silicon oxynitride, and / or other low-k dielectrics. The insulating material can be deposited using any suitable deposition method (e.g., CVD, PVD, and / or ALD, etc.). In some implementations, the deposition of the insulating material does not include ALD.

[0071] 5, method 500 proceeds to operation 512, where a plurality of second openings are formed through the first and second insulating layers in the staircase region and one or more third openings are formed in the second insulating layer in the core region. Figures 3F and 3G illustrate the corresponding structures.

[0072] 3F , a patterned photoresist layer 352 may be formed on the second insulating layer 314 in the core region 108 and the non-array region 110. The patterned photoresist layer 352 may include one or more openings 354 (in the core region 108) for forming contact portions connecting the first portion 311-1 of the doped polysilicon layer and the pad-out interconnect, and one or more openings 356 for forming contact portions connecting the first contact portion 315-1. The openings 354 and 356 may be in contact with the second insulating layer 314. In some implementations, the openings 356 may be aligned with the respective first contact portions 315-1 in the z-direction. The patterned photoresist layer 352 may be formed by coating a photoresist layer on the second insulating layer 314 and performing a photolithography process to form the openings 354 and 356.

[0073] 3G, a suitable etching process (e.g., dry etching and / or wet etching) can be performed using the patterned photoresist layer 352 as an etching mask to form a plurality of second openings 360 through the first and second insulating layers 313 and 314 and in contact with the respective first contact portions 315-1. In the same etching process, one or more third openings 358 are formed in the second insulating layer 314 in contact with the first portions 311-1 of the doped polysilicon layer. The patterned photoresist layer 352 can then be removed using, for example, an ashing process.

[0074] In some other implementations, the second opening and the third opening can be formed separately, for example, using different etching processes. Figures 4A and 4B illustrate an alternative fabrication process for forming the second opening and the third opening in separate etching processes. As shown in Figure 4A, the second opening 360 can first be formed by patterning the first and second insulating layers 313 and 314 using a first patterned photoresist layer (not shown) that includes openings for forming the second opening 360 (but not for forming any third opening). The first and second insulating layers 313 and 314 can then be etched in the non-array region 110 by a first etching process to form the second openings 360, each aligned with the respective first contact portions 315-1. The first patterned photoresist layer can then be removed. Another layer of photoresist layer may then be spun onto the second insulating layer 314 and fill the second openings 360, forming photoresist portions 408 in each second opening 360. The photoresist layer may be patterned to form a second patterned photoresist layer 404 including openings 406 for forming third openings in the second insulating layer 314. A second etching process may be performed using the second patterned photoresist layer 404 as an etching mask to form third openings 358 in the second insulating layer 314. The second patterned photoresist layer 404 and the photoresist portions 408 may then be removed. In some implementations, the first etching process and the second etching process may include appropriate dry etching and / or wet etching, respectively. In some implementations, the removal of the photoresist may include an ashing process.

[0075] 5, method 500 proceeds to operation 514, where a second contact portion is formed in each second opening and a third contact portion is formed in each third opening. Figure 3H illustrates the corresponding structure.

[0076] 3H , second contact portions 315-2 are formed in respective second openings 360, and third contact portions 341 are formed in respective third openings 358. The second contact portions 315-2 may be in contact with respective first contact portions 315-1. In some implementations, the respective first contact portions 315-1 and the respective second contact portions 315-2 may form a contact structure 315 (e.g., a TSC). The second and third contact portions 315-2 and 341 may each include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, the second and third contact portions 315-2 and 341 can be formed by depositing a layer of conductive material to fill the second and third openings 360 and 358 and performing a recess etch (e.g., a blank etch) to remove any excess conductive material on the second insulating layer 314. In some implementations, the deposition of the conductive material includes CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. The recess etch can include suitable dry and / or wet etching.

[0077] 5, method 500 proceeds to operation 516, where a first contact layer is formed conductively connected to a second contact portion, and a second contact layer is formed conductively connected to a third contact portion. Figures 3I-3K illustrate the corresponding structures.

[0078] 3I, a contact material layer 362 may be formed in contact with the second contact portion 315-2 and the third contact portion 341. The contact material layer 362 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, the contact material layer 362 may be deposited using CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof.

[0079] 3J , a patterned photoresist layer 364 may be formed on the contact material layer 362. The patterned photoresist layer 364 may include one or more openings 366 for patterning the contact material layer 362 to separate a portion of the contact material layer 362 conductively connected to the third contact portion 341 (e.g., the NAND memory string 317) from another portion of the contact material layer 362 conductively connected to the contact structure 315. In some implementations, the opening 366 may be positioned between the third contact portion 341 and the contact structure 315 in the xy plane and may be in contact with the contact material layer 362. The patterned photoresist layer 364 may be formed by spinning a photoresist layer on the contact material layer 362 and patterning the photoresist layer using a photolithography process.

[0080] As shown in FIG. 3K , a first contact layer 321 is formed conductively connected to the second contact portion 315-2 (or contact structure 315), and a second contact layer 323 is formed conductively connected to the third contact portion 341. The first contact layer 321 can be separated from the second contact layer 323 by one or more openings 325 between the first contact layer 321 and the second contact layer 323. The openings 325 can be formed by etching the contact material layer 362 using a patterned photoresist layer 364 as an etching mask. In some implementations, etching the contact material layer 362 includes appropriate dry etching and / or wet etching. The patterned photoresist layer 364 can then be removed using an ashing process.

[0081] 5, method 500 proceeds to operation 518, where the first pad-out interconnect is conductively connected to the first contact layer and the second pad-out interconnect is conductively connected to the second contact layer. Figures 3L-3N illustrate the corresponding structure.

[0082] As shown in FIG. 3L , a dielectric material can be deposited on the first and second contact layers 321 and 323 to form one or more dielectric layers. The dielectric material can fill the opening 325 and provide insulation between the first contact layer 321 and the second contact layer 323. In some implementations, the first dielectric material is deposited in contact with the first and second contact layers 321 and filling the opening 325 to form a first dielectric layer 327. A second dielectric material can be deposited on the first dielectric layer 327 to form a second dielectric layer 329. In some implementations, the first dielectric layer 327 includes silicon oxide, and the second dielectric layer 329 includes silicon nitride. The deposition of the first and second dielectric materials can each include CVD, PVD, ALD, or a combination thereof.

[0083] As shown in FIG. 3M , a patterned photoresist layer 368 may be formed on the second dielectric layer 329. The patterned photoresist layer 368 may include one or more openings 370 for patterning the first and second dielectric layers 327 and 329 and for forming pad-out interconnects. In some implementations, the openings 370 may be positioned over the contact structure 315 and the third contact portion 341, respectively. The patterned photoresist layer 368 may be formed by spinning a photoresist layer on the second dielectric layer 329 and patterning the photoresist layer using a photolithography process. The first and second dielectric layers 327 and 329 may be etched using the patterned photoresist layer 368 as an etch mask to form respective openings (not shown) in the first and second dielectric layers 327 and 329. At least one opening can be in contact with the first contact layer 321 and at least one opening can be in contact with the second contact layer 323. The patterned photoresist layer 368 can be removed using an ashing process.

[0084] 3N, multiple pad-out interconnects 319 are formed in the openings. At least one pad-out interconnect 319 may be in contact with the first contact layer 321, and at least one pad-out interconnect may be in contact with the second contact layer 323. The pad-out interconnects 319 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, the pad-out interconnects 319 may be deposited using CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some implementations, after deposition, a recess etch (e.g., dry etch and / or wet etch) is performed to remove any excess conductive material on the second dielectric layer 329.

[0085] FIG. 6 illustrates a block diagram of a system 600 having a memory device according to some aspects of the present disclosure. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 6 , the system 600 may include a host 608 and a memory system 602, the memory system 602 having one or more memory devices 604 and a memory controller 606. The host 608 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 608 may be configured to transmit data to or receive data from the memory device 604.

[0086] The memory devices 604 can be any memory devices disclosed herein (e.g., 3D memory device 200, etc.). In some implementations, each memory device 604 includes an array of memory cells and peripheral circuitry for the array of memory cells. The array of memory cells and peripheral circuitry are stacked on top of each other in different planes, as described in detail above.

[0087] The memory controller 606 is coupled to the memory device 604 and the host 608 and, according to some implementations, is configured to control the memory device 604. The memory controller 606 can manage data stored in the memory device 604 and communicate with the host 608. In some implementations, the memory controller 606 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 606 is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multimedia card (eMMC) used as data storage and enterprise storage arrays for mobile devices (e.g., smartphones, tablets, laptop computers, etc.). The memory controller 606 can be configured to control operations of the memory device 604 (e.g., read operations, erase operations, and program operations, etc.). In some implementations, memory controller 606 is configured to control the array of memory cells through a first peripheral circuit and a second peripheral circuit. Memory controller 606 can also be configured to manage various functions related to data stored or to be stored in memory device 604 (including, but not limited to, bad block management, garbage collection, logical address-to-physical address translation, wear leveling, etc.). In some implementations, memory controller 606 is further configured to process error correction codes (ECC) on data read from or written to memory device 604. Any other suitable functions can similarly be performed by memory controller 606, for example, forming memory device 604.The memory controller 606 can communicate with an external device (e.g., a host 608) according to a particular communication protocol. For example, the memory controller 606 can communicate with an external device through at least one of a variety of interface protocols (e.g., a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.).

[0088] The memory controller 606 and one or more memory devices 604 can be integrated into various types of storage devices, for example, in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package, etc.). That is, the memory system 602 can be implemented and packaged into different types of end electronics products. In one example, as shown in FIG. 7A , the memory controller 606 and a single memory device 604 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 can further include a memory card connector 704 that couples the memory card 702 with a host (e.g., the host 608 of FIG. 6 ). 7B, the memory controller 606 and the multiple memory devices 604 may be integrated into an SSD 706. The SSD 706 may further include an SSD connector 708 that couples the SSD 706 to a host (e.g., the host 608 in FIG. 6). In some implementations, the storage capacity and / or operating speed of the SSD 706 is greater than that of the memory card 702.

[0089] According to one embodiment of the present disclosure, a 3D memory device includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure within the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

[0090] In some implementations, the first semiconductor structure further includes a second contact structure through the insulating layer, the insulating layer laterally contacting the semiconductor layer and isolating the contact structure and the second contact structure from each other and from the semiconductor layer.

[0091] In some implementations, the semiconductor layer includes a first portion in a core region of the first semiconductor structure and a second portion in a non-array region of the first semiconductor structure, hi some implementations, the insulating layer is positioned in the non-array region of the first semiconductor structure and insulates the first and second portions of the semiconductor layer from each other.

[0092] In some implementations, the semiconductor layer is positioned in a core region of the first semiconductor structure and the insulating layer is positioned in a stair region of the first semiconductor structure.

[0093] In some implementations, the semiconductor layer is positioned in a core region of the first semiconductor structure, and the insulating layer is positioned outside the staircase region of the first semiconductor structure in a non-array region.

[0094] In some implementations, the insulating layer comprises a dielectric material.

[0095] In some implementations, the insulating layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0096] In some implementations, the area of ​​the insulating layer is greater than the area where the contact structures are formed and less than or equal to the non-array area.

[0097] In some implementations, the semiconductor layer and the insulating layer have the same thickness, which is in the range of 100 nm to 600 nm.

[0098] In some implementations, the semiconductor layer includes doped polysilicon.

[0099] In some implementations, the area of ​​the semiconductor layer is greater than or equal to the area in which all of the NAND memory strings are formed.

[0100] In some implementations, the first semiconductor structure further includes a pad-out interconnect layer, and the second semiconductor structure further includes a substrate.

[0101] Another aspect of the present disclosure provides a 3D memory device including a first semiconductor structure having a core region and a non-array region. The first semiconductor structure includes an array of NAND memory strings in a subregion of the core region, a semiconductor layer contacting source ends of the array of NAND memory strings, an insulating layer in the non-array region, and a plurality of contact structures in the insulating layer and in another subregion of the non-array region. The insulating layer electrically insulates the contact structures from the semiconductor layer. The 3D memory device also includes a second semiconductor structure coupled to the first semiconductor layer. The second semiconductor structure includes a transistor.

[0102] In some implementations, the area of ​​the insulating layer is equal to or greater than the area of ​​the other subregions and less than or equal to the area of ​​the non-array regions, and the insulating layer insulates the contact structures from each other.

[0103] In some implementations, the area of ​​the semiconductor layer is equal to or greater than the area of ​​the subregion.

[0104] In some implementations, the insulating layer comprises a dielectric material.

[0105] In some implementations, the insulating layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0106] In some implementations, the semiconductor layer and the insulating layer have the same thickness, which is in the range of 100 nm to 600 nm.

[0107] In some implementations, the semiconductor layer includes doped polysilicon.

[0108] In some implementations, the first semiconductor structure further includes a pad-out interconnect layer, and the second semiconductor structure further includes a substrate.

[0109] Another aspect of the present disclosure provides a method for forming a 3D memory device. The method includes bonding a first semiconductor structure and a second semiconductor structure together, the first semiconductor structure having a core region and a non-array region. The method also includes depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure, removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion, converting a second portion of the doped amorphous silicon layer in the core region to a doped polysilicon layer, forming an insulating layer in the opening, and forming a second contact portion in the insulating layer. The second contact portion is in contact with the first contact portion.

[0110] In some implementations, the method further includes converting the first portion of the doped amorphous silicon layer to a doped polysilicon portion prior to converting the second portion of the doped amorphous silicon layer, and removing the first portion of the doped amorphous silicon layer includes selectively removing the doped polysilicon portion from the doped amorphous silicon layer.

[0111] In some implementations, converting the first portion of the doped amorphous silicon layer includes performing a localized heat treatment on the first portion of the doped amorphous silicon layer.

[0112] In some implementations, converting the second portion of the doped amorphous silicon layer includes performing another localized treatment on the second portion of the doped amorphous silicon layer.

[0113] In some implementations, the localized heat treatment and the other localized heat treatment each include a respective laser annealing process.

[0114] In some implementations, each laser annealing process has an annealing temperature in the range of 1300 degrees Celsius to 1700 degrees Celsius and includes multiple laser pulses each having a pulse duration of 100 ns to 300 ns.

[0115] In some implementations, the etchant for selectively etching the doped polysilicon portions includes ammonia.

[0116] In some implementations, depositing the doped amorphous silicon layer includes a low temperature deposition process and an in-situ doping process.

[0117] In some implementations, the doped amorphous silicon layer is doped with an N-type dopant including at least one of phosphorus or arsenic.

[0118] In some implementations, the insulating layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0119] In some implementations, forming the first semiconductor structure includes forming an array of NAND strings and first contact portions above a substrate and thinning the substrate to expose source ends of the NAND strings.

[0120] In some implementations, a doped amorphous silicon layer is deposited so that it is in contact with the source end of the NAND string.

[0121] In some implementations, the method further includes depositing an insulating material over the doped polysilicon layer to fill the opening, forming an insulating layer in the opening, and forming a second insulating layer over the insulating layer, the second insulating layer being in the core region and the non-array region.

[0122] In some implementations, the method further includes forming a second opening in the insulating layer and the second insulating layer to expose the first contact portion, forming a third opening in the second insulating layer to expose the doped polysilicon layer, and forming a second contact portion in the second opening and a third contact portion in the third opening, wherein the third contact portion is in contact with the doped polysilicon layer.

[0123] In some implementations, the second opening and the third opening are formed in the same patterning process.

[0124] In some implementations, the method further includes forming a first contact layer conductively connected to the second contact portion and a second contact layer conductively connected to the third contact portion on the second insulating layer. The first contact layer and the second contact layer are insulated from each other. The method can further include forming a pad-out interconnect layer on the first and second contact layers. The pad-out interconnect layer includes respective contact structures conductively connected to the first and second contact layers.

[0125] In some implementations, forming the second semiconductor structure includes forming peripheral circuitry on the respective substrates, the peripheral circuitry including a plurality of transistors.

[0126] In some implementations, the aspect ratio of the opening is less than or equal to 1 / 3.

[0127] Another aspect of the present disclosure provides a system. The system includes a memory device configured to store data. The memory device includes a first semiconductor structure having an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and contact structures in the insulating layer, where the insulating layer electrically insulates the contact structures from the semiconductor layer. The memory device also includes a second semiconductor structure coupled to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry. The system also includes a memory controller coupled to the memory device and configured to control the array of NAND memory strings through the peripheral circuitry.

[0128] The foregoing descriptions of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0129] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0130] 100 3D memory devices 102 first semiconductor structure 103 3D Memory Device 104 Second semiconductor structure 105 First semiconductor structure 106 Bonding Interface 107 Second semiconductor structure 108 Core Area 109 Bonding Interface 110 Non-array area 111 Semiconductor layer 111-1 first portion of semiconductor layer 111-2 second portion of the semiconductor layer 113 Insulation part 115 TSC 117 NAND memory strings 119 Pad-out Interconnect 121 Insulating spacer 200 3D memory devices 202 Substrate 203 First semiconductor structure 204 Device Layer 205 Interconnection Layer 206 Bonding Layer 207 Second semiconductor structure 208 Bonding Layer 209 Bonding Interface 210 Interconnection Layer 211 Semiconductor layer 211-1 first portion of semiconductor layer 211-2 second portion of the semiconductor layer 212 Memory Stack 213 Insulating Layer 214 Second insulating layer 215 Contact structure 216 Pad-out Interconnect Layer 217 NAND memory strings 219 Pad-out Interconnect 221 First Contact Layer 223 Second Contact Layer 225 Insulation part 227 Third insulating layer 231 Bonding contact 233 Bonding Contact 237 Word Line Contact 239 Gate conductor layer 240 dielectric layer 241 Contact part 302 Substrate 304 Device Layer 305 Interconnection Layer 306 Bonding Layer 308 Bonding Layer 309 Bonding Interface 310 Interconnection Layer 311 doped polysilicon layer 311-1 first portion of doped polysilicon layer 311-2 second portion of the doped polysilicon layer 312 Array Stack 313 First insulating layer 313a First opening 314 Second insulating layer 315 Contact structure 315-1 First contact part 315-2 Second contact part 317 NAND memory strings 320 doped amorphous silicon layer 320a: first portion of doped amorphous silicon layer 320b second portion of the doped amorphous silicon layer 320c a third portion of the doped amorphous silicon layer 321 First Contact Layer 323 Second Contact Layer 325 Opening 327 First Dielectric Layer 329 Second Dielectric Layer 331 first bonding contact 333 Second bonding contact 339 Gate conductor layer 340 Dielectric Layer 341 Third Contact 350 Semiconductor Structure 352 Patterned photoresist layer 354 Opening 356 Opening 358 Third Opening 360 Second Opening 362 Contact material layer 364 Patterned photoresist layer 366 Opening 368 Patterned photoresist layer 370 Opening 404 Second patterned photoresist layer 406 Opening 408 Photoresist part 600 System 602 Memory System 604 Memory Devices 606 Memory Controller 608 Host 702 Memory Card 704 memory card connector 706 SSD 708 SSD Connector

Claims

1. A first semiconductor structure, an array of NAND memory strings; a semiconductor layer in contact with the source ends of the array of NAND memory strings; an insulating layer in contact with the semiconductor layer; a contact structure in the insulating layer, the insulating layer electrically insulating the contact structure from the semiconductor layer; a first semiconductor structure comprising: a second semiconductor structure coupled to the first semiconductor structure, the second semiconductor structure including a transistor; A three-dimensional (3D) memory device comprising:

2. the first semiconductor structure further includes a second contact structure through the insulating layer; the insulating layer laterally contacts the semiconductor layer and insulates the contact structure and the second contact structure from each other; 10. The 3D memory device of claim 1, wherein the insulating layer insulates the contact structure and the second contact structure from the semiconductor layer.

3. the semiconductor layer includes a first portion in a core region of the first semiconductor structure and a second portion in a non-array region of the first semiconductor structure; 3. The 3D memory device of claim 1, wherein the insulating layer is positioned in the non-array region of the first semiconductor structure and insulates the first and second portions of the semiconductor layer from each other.

4. the semiconductor layer is positioned in a core region of the first semiconductor structure; 4. The 3D memory device of claim 3, wherein the insulating layer is positioned in a staircase region of the first semiconductor structure.

5. the semiconductor layer is positioned in a core region of the first semiconductor structure; 4. The 3D memory device of claim 3, wherein the insulating layer is positioned outside a staircase region of the first semiconductor structure in the non-array area.

6. The 3D memory device of claim 1 , wherein the insulating layer comprises a dielectric material.

7. 7. The 3D memory device of claim 1, wherein the insulating layer comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.

8. 7. The 3D memory device of claim 1, wherein an area of ​​the insulating layer is greater than an area where a plurality of contact structures are formed and less than or equal to an area of ​​the non-array area.

9. 8. The 3D memory device of claim 1, wherein the semiconductor layer and the insulating layer have the same thickness in the range of 100 nm to 600 nm.

10. 9. The 3D memory device of claim 1, wherein the semiconductor layer comprises doped polysilicon.

11. 10. The 3D memory device of claim 1, wherein an area of ​​the semiconductor layer is greater than or equal to an area in which all of the NAND memory strings are formed.

12. the first semiconductor structure further includes a pad-out interconnect layer; 12. The 3D memory device of claim 1, wherein the second semiconductor structure further comprises a substrate.

13. A first semiconductor structure having a core region and a non-array region, an array of NAND memory strings in a sub-area of ​​the core area; a semiconductor layer in contact with the source ends of the array of NAND memory strings; an insulating layer in the non-array region; a plurality of contact structures in the insulating layer and in another subregion of the non-array region, the insulating layer electrically insulating the contact structures from the semiconductor layer; a first semiconductor structure comprising: a second semiconductor structure coupled to the first semiconductor layer, the second semiconductor structure including a transistor; A three-dimensional (3D) memory device comprising:

14. the area of ​​the insulating layer is equal to or greater than the area of ​​the other sub-regions and is less than or equal to the area of ​​the non-array region; 14. The 3D memory device of claim 13, wherein the insulating layer insulates the contact structures from each other.

15. 15. The 3D memory device of claim 13 or 14, wherein an area of ​​the semiconductor layer is equal to or greater than an area of ​​the subregion.

16. 16. The 3D memory device of claim 13, wherein the insulating layer comprises a dielectric material.

17. 17. The 3D memory device of claim 13, wherein the insulating layer comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride.

18. 18. The 3D memory device of claim 13, wherein the semiconductor layer and the insulating layer have the same thickness in the range of 100 nm to 600 nm.

19. 19. The 3D memory device of claim 13, wherein the semiconductor layer comprises doped polysilicon.

20. the first semiconductor structure further includes a pad-out interconnect layer; 20. The 3D memory device of claim 13, wherein the second semiconductor structure further comprises a substrate.

21. bonding a first semiconductor structure and a second semiconductor structure together, the first semiconductor structure including a core region and a non-array region; depositing a doped amorphous silicon layer over the core region and the non-array region of the first semiconductor structure; removing a first portion of the doped amorphous silicon layer in the non-array region to form an opening exposing a first contact portion; converting a second portion of the doped amorphous silicon layer in the core region into a doped polysilicon layer; forming an insulating layer in the opening; forming a second contact portion in the insulating layer, the second contact portion in contact with the first contact portion; 1. A method for forming a three-dimensional (3D) memory device, comprising:

22. The method may further include converting the first portion of the doped amorphous silicon layer into a doped polysilicon portion prior to converting the second portion of the doped amorphous silicon layer, and the step of removing the first portion of the doped amorphous silicon layer includes:

22. The method of claim 21, comprising selectively removing the doped polysilicon portion from the doped amorphous silicon layer.

23. 22. The method of claim 21, wherein converting the first portion of the doped amorphous silicon layer comprises performing a localized heat treatment on the first portion of the doped amorphous silicon layer.

24. 24. The method of any one of claims 21 to 23, wherein converting the second portion of the doped amorphous silicon layer comprises performing another localized treatment on the second portion of the doped amorphous silicon layer.

25. 24. The method of claim 23, wherein the localized heat treatment and the other localized heat treatment each comprise a respective laser annealing process.

26. 26. The method of claim 25, wherein each of the laser annealing processes has an annealing temperature in the range of 1300 degrees Celsius to 1700 degrees Celsius and includes multiple laser pulses each having a pulse time of 100 ns to 300 ns.

27. 24. The method of claim 22 or 23, wherein the etchant for selectively etching the doped polysilicon portion comprises ammonia.

28. 28. The method of any one of claims 21 to 27, wherein the step of depositing the doped amorphous silicon layer comprises a low temperature deposition process and an in-situ doping process.

29. 30. The method of claim 28, wherein the doped amorphous silicon layer is doped with an N-type dopant comprising at least one of phosphorus or arsenic.

30. 30. The method of any one of claims 21 to 29, wherein the insulating layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

31. forming the first semiconductor structure; forming an array of NAND strings and the first contacts above a substrate; thinning the substrate to expose source ends of the NAND strings; 31. The method of any one of claims 21 to 30, comprising:

32. 32. The method of claim 31 , wherein the doped amorphous silicon layer is deposited so as to be in contact with the source ends of the NAND strings.

33. 33. The method of claim 21, further comprising depositing an insulating material to fill the opening and over the doped polysilicon layer to form the insulating layer in the opening, and forming a second insulating layer over the insulating layer, the second insulating layer being in the core region and the non-array region.

34. forming a second opening in the insulating layer and the second insulating layer to expose the first contact portion; forming a third opening in the second insulating layer to expose the doped polysilicon layer; forming the second contact portion in the second opening and a third contact portion in the third opening, the third contact portion contacting the doped polysilicon layer; 34. The method of claim 33, further comprising:

35. 35. The method of claim 34, wherein the second opening and the third opening are formed in the same patterning process.

36. forming a first contact layer conductively connected to the second contact portion and a second contact layer conductively connected to the third contact portion on the second insulating layer, the first contact layer and the second contact layer being insulated from each other; forming a pad-out interconnect layer over the first and second contact layers, the pad-out interconnect layer including respective contact structures conductively connected to the first and second contact layers; 36. The method of claim 34 or 35, further comprising:

37. 37. The method of any one of claims 21 to 36, wherein forming the second semiconductor structure includes forming peripheral circuitry on a respective substrate, the peripheral circuitry including a plurality of transistors.

38. 38. The method of any one of claims 21 to 37, wherein the aspect ratio of the opening is less than or equal to 1 / 3.

39. 1. A memory device configured to store data, comprising: The memory device is A first semiconductor structure, an array of NAND memory strings; a semiconductor layer in contact with the source ends of the array of NAND memory strings; an insulating layer in contact with the semiconductor layer; a first semiconductor structure including a contact structure in the insulating layer, the insulating layer electrically insulating the contact structure from the semiconductor layer; a second semiconductor structure coupled to the first semiconductor structure, the second semiconductor structure including peripheral circuitry; a memory controller coupled to the memory device and configured to control the array of NAND memory strings through the peripheral circuitry; a memory device including Including, the system.

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