Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device improved in electrical characteristic and reliability.SOLUTION: The semiconductor device includes: a bit line extending in a first direction parallel to a substrate; a first channel pattern connected to the bit line and disposed perpendicularly to the substrate; a gate insulating pattern disposed on the first channel pattern; a word line disposed on the gate insulating pattern and extending in a second direction that is parallel to the substrate and perpendicular to the first direction; data storage patterns spaced apart from each other in the first direction and the second direction; storage node contacts each disposed on a data storage pattern; a mold structure extending in the second direction and configured to support the first channel pattern; and a first metal layer disposed in the mold structure.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device with improved electrical characteristics and reliability and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art Semiconductor device manufacturing techniques are being developed in the direction of increasing the degree of integration and improving the operating speed and yield. 2. Description of the Related Art In order to increase the integration density, resistance, current driving capability, etc. of transistors, semiconductor devices including vertical channel transistors (VCTs) have been proposed.

[0003] In a semiconductor device including a vertical channel transistor, a contact is formed to connect a channel pattern to a bit line (BL). Improvement of the electrical characteristics and reliability of such semiconductor devices is a daily challenge. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 11,696,434 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned problems with conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability, and a method for manufacturing the same. [Means for solving the problem]

[0006] In order to achieve the above object, the semiconductor device according to the present invention comprises a bit line (BL) extending in a first direction parallel to a substrate, a first channel pattern (140) connected to the bit line (BL) and arranged perpendicular to the substrate, a gate insulating pattern (150) arranged on the first channel pattern (140), a word line (WL) arranged on the gate insulating pattern (150) and extending in a second direction parallel to the substrate and perpendicular to the first direction, data storage patterns (DSP) arranged to be spaced apart in the first and second directions, a storage node contact (BC) arranged on the data storage pattern (DSP), a mold structure (130) extending in the second direction and supporting the first channel pattern (140), and a first metal layer (134) arranged within the mold structure (130).

[0007] To achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the steps of: preparing a substrate including a storage node contact (BC) connected to a data storage pattern (DSP); forming a mold structure (130) disposed vertically on the substrate and including a first metal layer (134); sequentially forming a first channel pattern (140) and a gate insulating pattern (150) on the mold structure (130); and forming a gate insulating pattern (150) between an upper surface of the first channel pattern (140) and the mold structure (130). The method includes removing an upper surface of the gate insulating pattern (150), forming a word line (WL) on the gate insulating pattern (150), sequentially coating a second insulating layer (160) and a third insulating layer (170) on the word line (WL) and then planarizing the coated layer, exposing upper surfaces of the mold structure (130) and a first channel pattern (140), and depositing a second metal layer (190) on the first channel pattern (140) to form a bit line (BL).

[0008] Furthermore, a semiconductor device according to an embodiment of the present invention includes bit lines extending in a first direction parallel to a substrate, word lines extending in a second direction perpendicular to the first direction, storage node contacts connected to the word lines, data storage patterns connected to lower portions of the storage node contacts, a mold structure extending in the second direction and including a first metal layer, a first channel pattern disposed on the mold structure, and a gate insulating pattern 150 disposed on the first channel pattern, wherein the bit lines are formed of a second metal layer disposed in the first direction. [Effects of the Invention]

[0009] According to the semiconductor device and its manufacturing method of the present invention, in order to solve the problem of minimizing the contact area by replacing a bit line having a wide contact similar to a storage node contact structure with a first channel pattern, a metal layer is formed within a mold structure supporting the first channel pattern, thereby improving electrical characteristics and reliability. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a perspective view showing a schematic configuration of a memory cell array of the semiconductor device of FIG. 1. FIG. [Figure 3] 1 is a cross-sectional view showing a schematic configuration of an example of a semiconductor device according to an embodiment of the present invention. [Figure 4] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 5] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 6] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 7] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 8]4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 9] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 10] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 11A] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 11B] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 11C] 4A to 4C are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 12] FIG. 10 is a cross-sectional view showing a schematic configuration of another example of a semiconductor device according to an embodiment of the present invention. [Figure 13] 13 is a diagram for explaining a method of manufacturing the semiconductor device shown in FIG. 12. [Figure 14] 13 is a diagram for explaining a method of manufacturing the semiconductor device shown in FIG. 12. [Figure 15] FIG. 10 is a cross-sectional view showing a schematic configuration of another example of a semiconductor device according to an embodiment of the present invention. [Figure 16] 16A to 16C are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. [Figure 17] 16A to 16C are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. [Figure 18] 16A to 16C are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. [Figure 19] 16A to 16C are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. [Figure 20] 16A to 16C are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. [Figure 21] FIG. 10 is a cross-sectional view showing a schematic configuration of another example of a semiconductor device according to an embodiment of the present invention. [Figure 22] 22A to 22D are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. 21. [Figure 23] 22A to 22D are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. 21. [Figure 24] 22A to 22D are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. 21. [Figure 25] 22A to 22D are diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. 21. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out the semiconductor device and the manufacturing method thereof according to the present invention will be described with reference to the drawings. In the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the drawing numbers, and redundant description thereof will be omitted.

[0012] The various embodiments and terms used in this specification are not intended to limit the technical features described in the specification to specific embodiments, but should be understood to include various modifications, equivalents, or alternatives to the embodiments. In connection with the description of the drawings, like reference numerals are used for like or related components. The singular form of a noun referring to an item may include one or more of said items unless the relevant context clearly dictates otherwise. As used herein, each phrase such as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C" may include any one of the items listed in the phrase, or all possible combinations thereof. Terms such as "first," "second," "first," or "initial" may be used simply to distinguish a component from other components, and do not limit the component in other respects (e.g., importance or order).

[0013] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. Terms such as commonly used and predefined terms should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be construed as having an ideal or overly formal meaning unless expressly defined herein. Furthermore, in the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the drawing numerals, and redundant description thereof will be omitted. In describing the embodiments, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of the embodiments, the detailed description will be omitted. When a component is described as being "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but that there may also be other components "connected," "coupled," or "connected" between each component.

[0014] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 includes a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5. For example, the semiconductor device 100 may be implemented as a dynamic random access memory (DRAM) device as a semiconductor memory device.

[0015] The memory cell array 1 includes a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. For example, the memory cell array 11 is disposed on one surface of a substrate, and the plane of the memory cell array 11 and the plane of the substrate are parallel to each other. Each of the plurality of memory cells MC is connected to a word line WL and a bit line BL that intersect with each other. Each of the plurality of memory cells MC includes a selection element TR and a data storage element DS. The selection element TR and the data storage element DS are electrically connected to each other. The selection element TR is connected to all of the word lines WL and bit lines BL.

[0016] For example, a selection element TR is provided at a position where a word line WL and a bit line BL cross each other. The selection element TR may include a field effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of a transistor that is a selection element TR is connected to a word line WL, and the source or drain terminal of the transistor is connected to a bit line BL or a data storage element DS. An exemplary connection structure between the selection element TR, the data storage element DS, the word line WL, and the bit line BL of each of the memory cells MC in the memory cell array 1 will be described below with reference to FIG.

[0017] Each selection element TR of the memory cells includes a vertical channel transistor (VCT). The lengthwise direction of the channel of the vertical channel transistor VCT is perpendicular to one surface (eg, the upper surface) of the substrate. Each data storage element DS of a memory cell (MC in FIG. 1) includes a data storage pattern DSP. An exemplary structure of a memory cell MC including a vertical channel transistor VCT is illustrated in FIG. 3 below.

[0018] The row decoder 22 decodes an address input from outside the semiconductor device 100 . The row decoder 22 selects one of the word lines WL of the memory cell array 11 using the address decoding result. The decoding result (eg, decoded address) from the row decoder 2 is provided to a row driver (not shown). The row driver provides a predetermined voltage to the selected word line WL and the unselected word lines WL, respectively, in response to control from the control circuit.

[0019] The sense amplifier 3 senses and amplifies the voltage difference between a selected bit line BL and a reference bit line in response to an address decoded by the column decoder 4, and outputs the amplified voltage difference. The column decoder 4 provides a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 decodes an externally input address and selects one of the bit lines BL.

[0020] The control logic 5 generates a control signal for controlling the write or read operation of data to a corresponding memory cell in the memory cell array 1. For reference, in FIG. 1, the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 are shown around the memory cell array 1, but the present invention is not limited to this. The peripheral circuits including the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 may be arranged on a plane different from the plane on which the memory cell array 1 is arranged. The peripheral circuits are arranged above or below the memory cell array 11 through a COP (Cell Over Peri) structure. For example, a peripheral circuit structure is provided on a substrate, and a memory cell array 1 is provided on the peripheral circuit. As another example, the peripheral circuits are provided on a first substrate, and the memory cell array 1 is provided on a second substrate. The first substrate and the second substrate face each other.

[0021] FIG. 2 is a perspective view showing a schematic configuration of a memory cell array of the semiconductor device of FIG. 2 shows a cross section along the bit line BL direction (for example, the Y-axis direction) of the region including the storage node contacts BC, and line BB' shows a cross section of the region not including the storage node contacts BC. The line CC' is a cross section along the word line WL direction, and shows a region including the mold structure 130 that does not include the word lines WL. The mold structure 130 extends along a second direction (for example, the X-axis direction).

[0022] FIG. 2 is a perspective view showing a schematic configuration of the memory cell array 1 of FIG. 1, showing a state in which a substrate to which storage node contacts BC and data storage patterns DSP are connected is flipped upside down. To improve the integration and performance of semiconductor devices, semiconductor devices are manufactured by fabricating a substrate in a back-end-of-line (BEOL) process, flipping the substrate, and forming a cell array on the storage node contacts BC.

[0023] Referring to FIG. 2, the semiconductor device includes a data storage pattern DSP, storage node contacts BC, word lines (WL1, WL2), and bit lines BL. The bit lines BL extend along a first direction (eg, the Y-axis direction). The word lines (WL1, WL2) are disposed on the storage node contacts BC. The word lines WL1 and WL2 extend along a second direction (eg, the X-axis direction) perpendicular to the first direction. The first direction and the second direction are parallel to the substrate or the plane corresponding to the memory cell array. For example, the substrate has the shape of a plate that extends along a plane defined by a first direction and a second direction. An exemplary embodiment of the present invention forms a mold structure and a channel pattern on top of the storage node contact BC.

[0024] Hereinafter, with reference to FIGS. 3 to 25, the semiconductor device according to the embodiment of the present invention will be described in detail, mainly focusing on the portion 200. FIG. The components of the semiconductor device described below are merely examples for explaining the technical idea of ​​the present invention, and the scope of the present invention is not limited thereto. FIG. 3 is a cross-sectional view showing a schematic configuration of an example of a semiconductor device according to an embodiment of the present invention. FIG. 3 shows a cross section of a memory cell of the semiconductor device taken along line AA' in FIG. 2 in a direction perpendicular to the substrate (for example, a cross section corresponding to the YZ plane). The line A-A' is parallel to the bit line BL.

[0025] The semiconductor device 100 includes a data storage pattern DSP, a storage node contact BC, a lower insulating layer 110, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a mold structure 130, a first channel pattern 140, a gate insulating pattern 150, a second metal layer 190, a BL, and a word line WL1.

[0026] The data storage pattern DSP is disposed on one side (eg, below) of the storage node contact BC. The data storage pattern DSP is electrically connected to the first channel pattern 140 through a storage node contact BC. The data storage patterns DSP are spaced apart in a first direction and a second direction. The data storage patterns DSP are arranged in a matrix shape and completely or partially overlap the storage node contacts BC in one direction (for example, the Z-axis direction). The data storage pattern DSP may be a capacitor. The data storage pattern DSP includes a storage electrode, a plate electrode, and a capacitor dielectric layer interposed between the storage electrode and the plate electrode. In this case, the storage electrode is in contact with the storage node contact BC. The storage electrode can have a variety of shapes, such as circular, elliptical, rectangular, square, rhombic, and hexagonal.

[0027] The lower insulating layer 110 is disposed between the data storage patterns DSP. For example, the lower insulating layer 110 is disposed in the inner region of the data storage pattern DSP when viewed in a direction perpendicular to the substrate. The storage node contacts BC are disposed on the data storage patterns DSP. The storage node contact BC is disposed between the first insulating layers 120 . The storage node contacts BC may have a variety of shapes including thick circles, ellipses, rectangles, squares, rhombuses, hexagons, and polygons. When viewed in a direction perpendicular to the substrate (for example, in the Z-axis direction), an insulating layer is disposed in the inner and outer regions defined by the storage node contacts BC. The storage node contact BC includes a conductive material. For example, the conductive material may include at least one of doped polysilicon, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, two-dimensional materials, metals, and metal alloys. A landing pad is disposed on each storage node contact BC.

[0028] The first insulating layer 120 is disposed between the storage node contacts BC. For example, the first insulating layer 120 is disposed in the inner region of the storage node contact BC when viewed in a direction perpendicular to the substrate (for example, the Z-axis direction). For example, if the storage node contact BC is formed in a circular donut shape, the first insulating layer 120 is provided in an inner region including the center point of the donut shape. The first insulating layer 120 is also provided between the storage node contact BC and the landing pad. The first insulating layer 120 includes an insulating material.

[0029] The first channel pattern 140 is connected to the bit line BL and is disposed perpendicular to the substrate. For example, the first channel pattern 140 extends on the outer surface of the mold structure 130 in a third direction (eg, Z-axis direction) perpendicular to the storage node contacts BC. The gate insulating pattern 150 is disposed on the first channel pattern 140 . The gate insulating pattern 150 includes an insulating material. The word line WL1 is disposed on the gate insulating pattern 150 and extends in a second direction (eg, the X-axis direction). According to one embodiment, the upper end of the word line WL1 is located at a level higher than the lower end of the first metal layer 134. The second insulating layer 160 is disposed on the outer surfaces of the gate insulating pattern 150 and the word line WL1 and may be silicon nitride. The third insulating layer 170 is contained within the inner space surrounded by the second insulating layer 160 and may be silicon oxide.

[0030] The mold structure 130 protrudes in a third direction (eg, Z-axis direction) perpendicular to one surface (eg, upper surface) of the first insulating layer 120. The third direction is a direction perpendicular to the first direction and the second direction. The mold structure 130 is provided on the first insulating layer 120 corresponding to the portions between the storage node contacts BC. The mold structure 130 extends in a second direction (eg, the X-axis direction) and supports the first channel pattern 140 . The mold structure 130 includes a first silicon nitride 131, a silicon oxide 132, a second silicon nitride 133, and a first metal layer 134.

[0031] A silicon oxide 132 is disposed between the first silicon nitride 131 and the second silicon nitride 133, and a first metal layer 134 is disposed on the second silicon nitride 133 to form a mold structure 130. For example, a first silicon nitride 131, a silicon oxide 132, a second silicon nitride 133, and a first metal layer 134 are sequentially disposed from the bottom. The lower end of the first metal layer 134 is located at a level lower than the upper end of the word line WL. For reference, the plurality of mold structures 130 are arranged in a first direction (for example, the Y-axis direction). For example, as shown in FIG. 11A, a plurality of mold structures 130 are arranged so as to be spaced apart from each other in a first direction (eg, the Y-axis direction).

[0032] A first metal layer 134 is disposed within the mold structure 130 . The first metal layer 134 contacts the first channel pattern 140 in a vertical direction that is parallel to the mold structure 130 . The first metal layer 134 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The first metal layer 134 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0033] The second metal layer 190 is disposed on the first metal layer 134 , the first channel pattern 140 , and the third insulating layer 170 . The second metal layer 190 is the bit line BL. The second metal layer 190 extends in a first direction parallel to the substrate. The second metal layer 190 comprises doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The second metal layer 190 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0034] According to one embodiment, the first channel pattern 140 has multiple surfaces, the first metal layer 134 contacts a first surface of the multiple surfaces, and the second metal layer 190 contacts a second surface of the multiple surfaces that is different from the first surface. According to one embodiment, the first metal layer 134 and the second metal layer 190 may comprise the same or different types of conductive materials. The contact area between the first channel pattern 140 and the metal layer ( 134 , 190 ) exceeds the thickness of the first channel pattern 140 . According to one embodiment, the bit line BL is formed by a second metal layer 190 located on the first channel pattern 140 . For example, the second metal layer 190 is a bit line BL formed on the first metal layer 134 . The bit lines BL extend in a first direction parallel to the substrate. The bit lines BL are formed on the first channel patterns 140 along a direction (eg, a first direction) perpendicular to the word lines WL1.

[0035] 4 to 12 are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. Referring to FIG. 4, a substrate including storage node contacts BC connected to data storage patterns DSP is prepared, and a first insulating layer 120 is disposed between the storage node contacts BC. The data storage pattern DSP is connected to the storage node contact BC, and the substrate prepared through a back-end-of-line (BEOL) process is flipped so that the data storage pattern DSP faces downward. An insulating film IF is coated on the storage node contact BC and the first insulating layer 120, and the top surface of the first insulating layer 120 is exposed through an etching process.

[0036] Referring to FIG. 5, a mold structure 130 is formed in a direction perpendicular to one surface (eg, upper surface) of the exposed first insulating layer 120 . The mold structure 130 includes an insulating layer formed by a CVD (Chemical Vapor Deposition) process. The mold structure 130 includes an insulating layer on which a first silicon nitride 131, a silicon oxide 132, a second silicon nitride 133, and a first metal layer 134 are stacked. The first and second silicon nitrides (131, 133) may be at least one of SiCN, SiCON, and SiN. The silicon oxide 133 may include any one of hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO). The first metal layer 134 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

[0037] Referring to FIG. 6, a first channel pattern 140 and a gate insulating pattern 150 are formed by a PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition) process. The first channel pattern 140 is formed on the mold structure 130, the first insulating layer 120 between the mold structure 130, and the storage node contact BC. A gate insulating pattern 150 is formed on the first channel pattern 140 . For example, a first channel pattern 140 and a gate insulating pattern 150 are sequentially formed on the mold structure 130 .

[0038] Referring to FIG. 7, the top surface of the first channel pattern 140 is opened through an etch-back process to form a node. The upper surface of the gate insulating pattern 150 located between the mold structures 130 is removed by etching.

[0039] Referring to FIG. 8, the gate insulating pattern 150 is re-deposited to form word lines WL on the gate insulating pattern 150 . The mold structure 130 includes the first metal layer 134, which increases the level of the mold structure 130, and accordingly increases the level of the word lines WL. The word lines WL include a conductive material. The word lines WL are chamfered through a wet etching process.

[0040] Referring to FIG. 9, a second insulating layer 160 is deposited on the word lines WL, and a third insulating layer 170 is implanted on the second insulating layer 160. The second insulating layer 160 may be silicon nitride and the third insulating layer 170 may be silicon oxide. After forming the second insulating layer 160 and the third insulating layer 170, the entire upper surface is planarized by a chemical mechanical polishing (CMP) process to expose the upper surfaces of the mold structure 130 and the first channel pattern 140.

[0041] Referring to FIG. 10, the second insulating layer 160, the third insulating layer 170, and the upper portion of the first channel pattern 140 are opened by an etch-back process to form a node. After node isolation, oxide deposition and CMP (Chemical Mechanical Polishing) processes are carried out.

[0042] Referring to FIG. 11A, a second metal layer 190 is deposited on the first channel pattern 140 . The second metal layer 190 is the bit line BL. The second metal layer 190 may be the same as the first metal layer 134 or may be a different conductive material. 11B is a cross-sectional view showing a part of a cross section taken along line BB' in FIG. The upper end of the word line WL is disposed at a level higher than the lower end of the second silicon nitride 133 . 11C is a cross-sectional view showing a part of a cross section taken along line CC' in FIG. The first metal layer 134 and the second metal layer 190 are disposed on the second silicon nitride 133 in a protruding form.

[0043] FIG. 12 is a cross-sectional view showing a schematic configuration of an example of a semiconductor device according to an embodiment of the present invention. FIG. 12 shows a cross section of a memory cell of a semiconductor device taken along line AA' in FIG. 2 in a direction perpendicular to the substrate (for example, a cross section corresponding to the YZ plane). The semiconductor device 100 includes a data storage pattern DSP, a storage node contact BC, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a mold structure 130, a first channel pattern 140, a gate insulating pattern 150, a first metal layer 134, a second metal layer 190, a word line WL1, a bit line BL, and a second channel pattern 180.

[0044] The second channel pattern 180 is disposed to extend from one end of the first channel pattern 140 in a first direction. According to an embodiment, the first channel pattern 140 and the second channel pattern 180 may be the same as each other or may comprise different types of semiconductor oxides. The semiconductor oxide may include, but is not limited to, any one of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO or a combination thereof. For example, the first channel pattern 140 may be made of IGZO (Indium Gallium Zinc Oxide), and the second channel pattern 180 may be made of ITO (Indium Tin Oxide). The semiconductor oxide may contain a high proportion of some elements contained in the oxide, for example, IGZO (Indium Gallium Zinc Oxide) is gallium-rich IGZO (Ga-rich IGZO), and any one or more of the first channel pattern 140 and the second channel pattern 180 may contain gallium-rich IGZO (Ga-rich IGZO).

[0045] According to one embodiment, the first metal layer 134 and the second metal layer 190 may comprise the same or different types of conductive materials. According to one embodiment, the bit lines BL are formed by a second metal layer 190 . For example, the second metal layer 190 includes a conductive material and is formed on the first metal layer 134 .

[0046] 13 and 14 are diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. 4 to 9 are similarly applied to the method of manufacturing a semiconductor device for the embodiment of FIG.

[0047] Referring to FIG. 13, the second insulating layer 160, the third insulating layer 170, and the upper portion of the first channel pattern 140 are opened by an etch-back process to form a node. After node isolation, oxide deposition and CMP (Chemical Mechanical Polishing) processes are carried out. A second channel pattern 180 is deposited on the surface opened by an etch-back process, and the second channel pattern 180 on the top surface of the first metal layer 134 is removed by cutting. The upper portion of the second channel pattern 180 protrudes above the first metal layer 134 .

[0048] Referring to FIG. 14, a second metal layer 190 is formed on the first channel pattern 140 in the direction of the bit line BL. The second metal layer 190 is the bit line BL. The second metal layer 190 may be the same as the first metal layer 134 or may be a different conductive material. The second channel pattern 180 is disposed to extend from one end of the first channel pattern 140 in a first direction. According to an embodiment, the first channel pattern 140 and the second channel pattern 180 may be the same as each other or may comprise different types of semiconductor oxides.

[0049] FIG. 15 is a cross-sectional view showing a schematic configuration of an example of a semiconductor device according to an embodiment of the present invention. FIG. 15 shows a cross section of a memory cell of a semiconductor device taken along line AA' in FIG. 2 in a direction perpendicular to the substrate (for example, a cross section corresponding to the YZ plane). The semiconductor device 100 includes a data storage pattern DSP, a storage node contact BC, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a mold structure 130, a first channel pattern 140, a gate insulating pattern 150, a first metal layer 134, a second metal layer 190, a word line WL1, a bit line BL, and an oxide layer Ox.

[0050] The oxide layer Ox may include an oxide of at least one selected from nickel (Ni), titanium (TiO), vanadium (V), iron (Fe), chromium (Cr), cobalt (Co), hafnium (Hf), and tantalum (Ta). The oxide layer Ox is disposed at the lower end of the word line WL and contacts one side of each of the gate insulating pattern 150 and the second insulating layer 160. An oxide layer Ox is included between the lower end of the word line WL and the storage node contact BC to enhance the reliability of the semiconductor device. According to an embodiment, the second channel pattern 180 extends from one end of the first channel pattern 140 in a first direction. According to an embodiment, the first channel pattern 140 and the second channel pattern 180 may be the same as each other or may comprise different types of semiconductor oxides.

[0051] The semiconductor oxide may include, but is not limited to, any one of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO, or a combination thereof. For example, the first channel pattern 140 may include IGZO (Indium Gallium Zinc Oxide), and the second channel pattern 180 may include ITO (Indium Tin Oxide). Semiconductor oxides contain a high proportion of some elements contained in the oxide, for example, IGZO (Indium Gallium Zinc Oxide) is gallium-rich IGZO (Ga-rich IGZO), and any one or more of the first channel pattern 140 and the second channel pattern 180 may contain gallium-rich IGZO (Ga-rich IGZO).

[0052] 16 to 20 are diagrams for explaining a method for manufacturing a semiconductor device according to the embodiment of FIG. 4 to 7 are similarly applied to the method of manufacturing a semiconductor device for the embodiment of FIG.

[0053] Referring to FIG. 16, an oxide layer Ox is formed on the gate insulating pattern 150 between the mold structures 130. An oxide layer Ox is included at the bottom end of the word line WL before the word line WL is formed. The oxide layer Ox may include at least one oxide selected from nickel (Ni), titanium (TiO), vanadium (V), iron (Fe), chromium (Cr), cobalt (Co), hafnium (Hf), and tantalum (Ta), and is formed by an ALD (Atomic Layer Deposition) process.

[0054] Referring to FIG. 17, word lines WL are formed on the oxide layer Ox. The word lines WL include a conductive material. The word lines WL1 and WL2 are chamfered through a wet etching process.

[0055] Referring to FIG. 18, a second insulating layer 160 is deposited on the word lines WL, and a third insulating layer 170 is implanted on the second insulating layer 160. The second insulating layer 160 may be silicon nitride and the third insulating layer 170 may be silicon oxide. After forming the second insulating layer 160 and the third insulating layer 170, the entire upper surface is planarized by a chemical mechanical polishing (CMP) process to expose the upper surfaces of the mold structure 130 and the first channel pattern 140.

[0056] Referring to FIG. 19, the second insulating layer 160, the third insulating layer 170, and the upper portion of the first channel pattern 140 are opened by an etch-back process to form a node. After node isolation, oxide deposition and CMP (Chemical Mechanical Polishing) processes are carried out.

[0057] Referring to FIG. 20, a second metal layer 190 is deposited on the first channel pattern 140 . The second metal layer 190 is the bit line BL. The second metal layer 190 may be the same as the first metal layer 134 or may be a different conductive material. The region 300 in FIG. 20 indicates a structure in which an oxide layer Ox is deposited on the lower end of the word line WL.

[0058] FIG. 21 is a cross-sectional view showing a schematic configuration of another example of a semiconductor device according to an embodiment of the present invention. FIG. 21 shows a cross section of a memory cell of a semiconductor device taken along line AA' in FIG. 2 in a direction perpendicular to the substrate (for example, a cross section corresponding to the YZ plane).

[0059] Referring to FIG. 21, the lower end of the first metal layer 134 is located at a level higher than the upper end of the word line WL1. The word line WL1 is positioned at a level lower than the bottom end of the first metal layer 134, so that the bit line BL and the word line WL1 form an underlap structure. If a high voltage is continuously applied, there is a risk of TDDB (Time Dependent Dielectric Breakdown) occurring when the semiconductor device is driven. Therefore, the word line WL1 is lowered to form an underlap structure. According to an embodiment, the second channel pattern 180 is disposed extending from one end of the first channel pattern 140 in a first direction.

[0060] According to an embodiment, the first channel pattern 140 and the second channel pattern 180 may be the same as each other or may comprise different types of semiconductor oxides. The semiconductor oxide may include, but is not limited to, any one of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO or a combination thereof. For example, the first channel pattern 140 may include IGZO (Indium Gallium Zinc Oxide), and the second channel pattern 180 may include ITO (Indium Tin Oxide). Semiconductor oxides contain a high proportion of some elements contained in the oxide, for example, IGZO (Indium Gallium Zinc Oxide) is gallium-rich IGZO (Ga-rich IGZO), and any one or more of the first channel pattern 140 and the second channel pattern 180 may contain gallium-rich IGZO (Ga-rich IGZO).

[0061] According to one embodiment, the first channel pattern 140 has multiple surfaces, the first metal layer 134 contacts a first surface of the multiple surfaces, and the second metal layer 190 contacts a second surface of the multiple surfaces that is different from the first surface. According to one embodiment, the first metal layer 134 and the second metal layer 190 may comprise the same or different types of conductive materials. The contact area between the first channel pattern 140 and the metal layer ( 134 , 190 ) exceeds the thickness of the first channel pattern 140 . According to one embodiment, the bit lines BL are formed by a second metal layer 190 . For example, the second metal layer 190 includes a conductive material and is formed on the first metal layer 134 . According to one embodiment, an oxide layer Ox is disposed at the lower end of the word line WL1.

[0062] 22 to 25 are diagrams for explaining a method for manufacturing a semiconductor device according to the embodiment of FIG. 4 to 7 are similarly applied to the method of manufacturing a semiconductor device for the embodiment of FIG.

[0063] Referring to FIG. 22, the gate insulating pattern 150 is re-deposited to form word lines WL on the gate insulating pattern 150. After the word lines WL are formed, a chamfering process is performed to lower the level of the word lines. The word lines WL include a conductive material. The word lines WL are chamfered through a wet etching process.

[0064] Referring to FIG. 23, a second insulating layer 160 is deposited on the word lines WL, and a third insulating layer 170 is implanted on the second insulating layer 160. The second insulating layer 160 may be silicon nitride and the third insulating layer 170 may be silicon oxide. After forming the second insulating layer 160 and the third insulating layer 170, the entire upper surface is planarized by a chemical mechanical polishing (CMP) process to expose the upper surfaces of the mold structure 130 and the first channel pattern 140.

[0065] Referring to FIG. 24, the second insulating layer 160, the third insulating layer 170, and the upper portion of the first channel pattern 140 are opened by an etch-back process to form a node. After node isolation, oxide deposition and CMP (Chemical Mechanical Polishing) processes are carried out.

[0066] Referring to FIG. 25, a second metal layer 190 is deposited on the first channel pattern 140 in the direction of the bit line BL. The second metal layer 190 is the bit line BL. The second metal layer 190 may comprise the same or a different conductive material as the first metal layer 134 . The region 400 in FIG. 25 indicates that the lower end of the first metal layer 134 is located at a level higher than the upper end of the word line WL.

[0067] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0068] 1. Memory cell array 2 Low Decoder 3 Sense Amplifier 4 Column Decoder 5 Control Logic 100 Semiconductor device 110 Lower insulating layer 120 First insulating layer 130 Mold structure 131 First Silicon Nitride 132 Silicon oxide 133 Secondary Silicon Nitride 134 1st metal layer 140 1st channel pattern 150 Gate insulation pattern 160 Second insulating layer 170 Third insulating layer 190 2nd metal layer BC Storage Node Contact DSP Data Storage Pattern WL1, WL2 word lines

Claims

1. a bit line (BL) extending in a first direction parallel to the substrate; a first channel pattern 140 connected to the bit line BL and disposed perpendicular to the substrate; a gate insulating pattern 150 disposed on the first channel pattern 140; a word line (WL) disposed on the gate insulating pattern (150) and extending in a second direction parallel to the substrate and perpendicular to the first direction; data storage patterns (DSPs) spaced apart in the first and second directions; a storage node contact (BC) disposed on the data storage pattern (DSP); a mold structure (130) extending in the second direction and supporting the first channel pattern (140); a first metal layer (134) disposed within the mold structure (130).

2. 2. The semiconductor device of claim 1, wherein the bit line (BL) is formed by a second metal layer (190) located on the first channel pattern (140).

3. 2. The semiconductor device according to claim 1, wherein an upper end of the word line (WL) is located at a level higher than a lower end of the first metal layer (134).

4. The first channel pattern (140) has a plurality of faces; the first metal layer (134) contacts a first surface of the plurality of surfaces; 3. The semiconductor device according to claim 2, wherein the second metal layer (190) contacts a second surface of the plurality of surfaces that is different from the first surface.

5. 5. The semiconductor device of claim 4, wherein the first metal layer (134) and the second metal layer (190) comprise the same or different types of conductive materials.

6. 2. The semiconductor device of claim 1, further comprising a second channel pattern extending in a first direction from one end of the first channel pattern.

7. 7. The semiconductor device of claim 6, wherein the second channel pattern (180) comprises the same or a different type of semiconductor oxide as the first channel pattern (140).

8. 2. The semiconductor device according to claim 1, further comprising an oxide layer (Ox) interposed at a lower end of the word line (WL).

9. 2. The semiconductor device according to claim 1, wherein an upper end of the word line (WL) is located at a level lower than a lower end of the first metal layer (134).

10. providing a substrate including a storage node contact (BC) connected to a data storage pattern (DSP); forming a mold structure (130) disposed perpendicular to the substrate and including a first metal layer (134); sequentially forming a first channel pattern 140 and a gate insulating pattern 150 on the mold structure 130; removing an upper surface of the gate insulating pattern 150 located between an upper surface of the first channel pattern 140 and the mold structure 130; forming a word line (WL) on the gate insulating pattern (150); a second insulating layer 160 and a third insulating layer 170 are sequentially coated on the word line WL, and then planarized; exposing the upper surfaces of the mold structure (130) and the first channel pattern (140); and depositing a second metal layer on the first channel pattern to form a bit line.

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