Manufacturing method of wiring board
By using a glass substrate of specific thickness and direct imaging exposure, the method addresses warping issues in wiring board manufacturing, ensuring high yield and precise conductor patterns.
JP2025185631APending Publication Date: 2025-12-22IBIDEN CO LTD
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Patent Information
- Application Number
- JP2024093989
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-10
- Publication Date
- 2025-12-22
AI Technical Summary
Technical Problem
The existing method for manufacturing wiring boards is prone to warping of the support substrate, insulating resin, and wiring layer during lamination, leading to defects in the wiring layer pattern and reduced yield.
Method used
A method involving the use of a glass substrate with a thickness of 0.5 mm to 2.0 mm, forming a build-up portion with alternately stacked conductor and insulating layers, and employing direct imaging exposure to create a resist pattern with precise conductor patterns, minimizing warpage and ensuring high yield.
Benefits of technology
The method effectively suppresses warpage and enables efficient manufacturing of wiring boards with high yield and accurate fine wiring patterns.
✦ Generated by Eureka AI based on patent content.
Abstract
To improve yield in manufacturing of a wiring board.SOLUTION: A manufacturing method of a wiring board according to an embodiment includes steps of: preparing a glass substrate having one or a plurality of product areas; and forming a build-up portion by laminating a conductor layer 12 and an insulating layer 11 over the product areas. The thickness of the glass substrate is 0.5 mm or more and 2.0 mm or less, and includes alternately laminating three or more conductor layers 12 and three or more insulating layers 11. The shape of each product area is rectangular in which a dimension of each side is 80 mm or more and 240 mm or less, and laminating the conductor layer 12 includes forming a resist layer having a resist pattern, forming a minimum value of the width of the wiring included in a conductor pattern to 2 μm or less, and forming a minimum value of an interval of a wiring to 2 μm or less, and forming a resist layer includes exposing the resist layer by a direct imaging exposure.SELECTED DRAWING: Figure 3J
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