Support for mixed reads in non-volatile memory controllers

Abstract

To provide an apparatus and a method for avoiding read data conflicts in a memory system that supports different read modes with varying read latency.SOLUTION: A memory controller includes separate queues for high-speed reading commands and low-speed reading commands, enabling the coordination of the issuance of these two types of commands. A mixed read coordinator tracks issued low-speed reading commands and determines whether a high-speed reading command is issued. The issued commands are sequenced to ensure they are correctly associated with the read data returned from memory cells.SELECTED DRAWING: Figure 35A

Description

[Technical Field]

[0001] Memories are widely used in various electronic devices, such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0002] The memory cells may reside in a cross-point memory array. In a memory array having a cross-point architecture, a first set of conductive lines extends across a surface of a substrate, and a second set of conductive lines is formed above the first set of conductive lines and extends across the substrate in a direction perpendicular to the first set of conductive lines. The memory cells are located at the cross-point junctions of the two sets of conductive lines.

[0003] Reversible resistive cells are formed from materials with programmable resistance. In a binary approach, the memory cell at each cross point can be programmed to one of two resistance states: high and low. In some approaches, more than two resistance states may be used. One type of reversible resistive cell is a Magnetoresistive Random Access Memory (MRAM) cell. MRAM cells use magnetization to represent stored data, as opposed to some other memory technologies that use electronic charge to store data. Bits of data are written to an MRAM cell by changing the magnetization direction of a magnetic element (the "free layer") within the MRAM cell, and the bits are read by measuring the resistance of the MRAM cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit).

[0004] Challenges exist when reading reversible resistive memory cells, including but not limited to MRAM cells. One technique for reading reversible resistive cells is a reference read, in which the state of the memory cell is compared to a reference signal, such as a reference voltage. To determine the state of the memory cell, a signal is applied to the memory cell. For example, a voltage can be applied across the memory cell to obtain a current having a magnitude representative of the resistance of the memory cell. The current may be converted to a sample voltage that is compared to the reference voltage. The state of the memory cell is determined based on whether the sample voltage is higher or lower than the reference voltage.

[0005] Another technique for reading reversibly resistive cells is self-referenced read (SRR). One SSR technique involves a first read, a write to a known state, and a second read. One technique for the first read is to apply a read voltage across the memory cell, resulting in a current having a magnitude representative of the resistance of the memory cell and stored. The stored voltage may be adjusted (e.g., to 150 mV) for comparison with a later read. One technique for the second read is to apply a read voltage across the memory cell, resulting in a current having a magnitude representative of the resistance of the memory cell. A voltage sample from the first read is stored and compared with a voltage sample from the second read. Determining the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage after the destructive write to a known state. If the bit state remains unchanged in the second read, it was in the destructive write state before the destructive write. If the bit state changes, the destructive write changed the bit state from a different state to the state to which the destructive write drove the bit. [Brief explanation of the drawings]

[0006] Similar numbered elements refer to common components in different figures. [Figure 1] FIG. 1 is a block diagram of one embodiment of a non-volatile memory system connected to a host. [Figure 2]1 is a block diagram of one embodiment of a front-end processor circuit, in some embodiments the front-end processor circuit is part of a memory controller. [Figure 3] 1 is a block diagram of one embodiment of a back-end processor circuit, in some embodiments the back-end processor circuit is part of a memory controller. [Figure 4] FIG. 1 is a block diagram of one embodiment of a memory package. [Figure 5A] FIG. 2 is a block diagram of one embodiment of a memory die. [Figure 5B] FIG. 1 is a block diagram of one embodiment of an integrated memory assembly including a control die and a memory structure die. [Figure 6A] 1 illustrates a side view of an embodiment of an integrated memory assembly stacked on a substrate. [Figure 6B] 1 illustrates a side view of an embodiment of an integrated memory assembly stacked on a substrate. [Figure 7A] 1 illustrates a perspective view of one embodiment of a portion of a memory array forming a cross-point architecture. [Figure 7B] 7B presents a side view and a top view, respectively, of the crosspoint architecture of FIG. 7A. [Figure 7C] 7B presents a side view and a top view, respectively, of the crosspoint architecture of FIG. 7A. [Figure 7D] 1 illustrates a perspective view of an embodiment of a portion of a two-level memory array forming a cross-point architecture. [Figure 8] 1 illustrates an embodiment of an MRAM memory cell structure, where, for example, a selected cell is driven by a current source to read or write. [Figure 9] 1 illustrates in more detail an embodiment of an MRAM memory cell design implemented in a cross-point array. [Figure 10A] 1 illustrates writing an MRAM memory cell by passing a current that generates spin torque transfer (STT). [Figure 10B]1 illustrates writing an MRAM memory cell by passing a current that generates spin torque transfer (STT). [Figure 11A] 1 illustrates an embodiment for incorporating a threshold switching selector into an MRAM memory array having a cross-point architecture. [Figure 11B] 1 illustrates an embodiment for incorporating a threshold switching selector into an MRAM memory array having a cross-point architecture. [Figure 12] 1 illustrates an embodiment of a memory array having a cross-point architecture. [Figure 13] 10 is a flow chart of one embodiment of a process for mixed forced current readout. [Figure 14] 10 is a flow chart of one embodiment of a process for a mixed forced current read in which an ECC engine is used to test whether the forced current referenced read was successful. [Figure 15A] 10 is a flow chart of one embodiment of a process for a mixed forced current read in which memory cells are tested for whether they are within a zone of uncertainty. [Figure 15B] 1 shows two resistance distributions of a memory cell with an uncertainty zone between the two resistance distributions. [Figure 15C] The concept of uncertainty zone is shown, with the horizontal axis being voltage. [Figure 15D] 1 illustrates a circuit that may be used to determine whether a memory cell is in the uncertainty zone. [Figure 16] 10 is a flow chart illustrating one embodiment of a process for forced current referenced readout. [Figure 17] 1 is a flow chart illustrating one embodiment of a process for forced current SRR. [Figure 18A] 10 shows current versus time for accessed bit current driven through a selected word line during a forced current SRR embodiment. [Figure 18B]18 shows voltage versus time for the voltage across a selected MRAM cell during an embodiment of a forced current, where the dashed line is for a bit already in the AP state and the solid line is for a bit in the P state that is written to the AP state during the 1822 waveform. [Figure 19] 10 is a flow chart illustrating one embodiment of a process by which values ​​from a forced current referenced readout are stored and used in a forced current SRR. [Figure 20] FIG. 1 is a block diagram of components for forcing current through a word line. [Figure 21] FIG. 10 is a schematic diagram of one embodiment of a current generator that reduces variations in inter-tile current despite variations in distance from a reference voltage source and power source. [Figure 22] 10 is a flow chart of an embodiment of a process for deterministic return time when using a mixed forced current readout scheme. [Figure 23] 10 shows an interface timing diagram for a mixed forced current readout embodiment. [Figure 24] 10 shows an interface timing diagram for a mixed forced current readout embodiment. [Figure 25] 10 is a flow chart of one embodiment of a process for communicating that a read retry should be performed in a mixed forced current read scheme. [Figure 26] 1 shows read command and read data waveforms for a device such as a DDR (Dual Data Rate) memory that only supports a single read type. [Figure 27] FIG. 1 is a block diagram of some exemplary hardware for the implementation of a single read type architecture. [Figure 28] 28 illustrates an embodiment of a workflow for issuing a read command to the architecture of FIG. 27. [Figure 29] 28 is an embodiment of a read data processing workflow for the architecture of FIG. 27. [Figure 30]This illustrates the need to support mixed read types for embodiments such as MRAM, which have both higher and lower latency reads. [Figure 31] 1 illustrates data output conflicts that can occur with multiple read types having different timings. [Figure 32] Consider when issuing a fast read after a slow read can cause data output timing conflicts. [Figure 33] The elements of Figure 32 are repeated, but now marked to indicate the number of contention cycles to be tracked. [Figure 34] Considerations are taken to avoid read data being out of order when a slow read is issued before a fast read. [Figure 35A] 1 illustrates an embodiment of a circuit architecture that supports mixed readout. [Figure 35B] 1 illustrates an embodiment of a circuit architecture that supports mixed readout. [Figure 36] 1 is a flow chart of an embodiment for issuing read commands in a mixed read command architecture. [Figure 37] 10 is a flow chart of an embodiment for updating a mixed read coordinator. [Figure 38] 10 is a flowchart of an embodiment of slow read ordering performed by a mixed read coordinator. [Figure 39] 35B. FIG. 35C is a flowchart of an embodiment of a mixed readout mode based on the embodiment of FIGS. 35A and 35B. DETAILED DESCRIPTION OF THE INVENTION

[0007] Disclosed herein are techniques for reading reversibly resistive cells in a memory array when using forced current reading. Forced current reading involves forcing a current through a memory cell and measuring the resulting voltage appearing across the cell and selection circuitry. The measured voltage represents the resistance of the memory cell. The memory cells may be in a cross-point memory array. In embodiments, each memory cell has a resistive random access memory element in series with a two-terminal selector element. The two-terminal selector element may be a threshold-switching selector, such as an Ovonic Threshold Switch (OTS). In embodiments, the resistive random access memory element comprises a magnetoresistive random access memory (MRAM) element.

[0008] In embodiments, the memory cell is first read using a forced current referenced read. If the forced current referenced read is successful, the forced current referenced read result is returned. If the forced current referenced read fails, a forced current self-referenced read (SRR) is performed and the forced current SRR result is returned. The forced current referenced read provides a faster read of the memory cell and can be successful in most cases. The forced current SRR provides a more accurate (higher margin) read when the forced current referenced read is unsuccessful. Furthermore, the forced current referenced read may use less power than the forced current SRR. In some embodiments, the forced current referenced read is successful most of the time (e.g., about 99 percent of the time). Thus, most of the time, the read is accomplished using a low-power forced current referenced read. Thus, significant power and latency are saved compared to always performing an SRR.

[0009] When a memory system supports different read modes with different read latencies, such as reference-based reads and self-referenced reads, read data conflicts may occur for data returned from memory cells in response to issued read commands. To support such mixed read modes, memory controller embodiments may include separate queues for fast read commands and slow read commands and coordinate the issuance of the two command types. A mixed read coordinator may track issued slow read commands and determine whether a fast read command can be issued. Issued commands are ordered to be correctly associated with the read data returned from the memory cells.

[0010] As mentioned above, the read may be a forced current read. In a forced current read embodiment, a memory cell is accessed by forcing a current through a selected word line while applying a select voltage to the selected bit line. The access current flows through a portion of the selected word line, through the selected memory cell, and through a portion of the selected bit line through each of the respective composite circuits. In response to the access current, a voltage develops across the selected memory cell. The voltage across the selected memory cell depends on the magnitude of the access current and the resistance of the memory cell. Thus, the voltage across the selected memory cell represents the resistance of the memory cell.

[0011] In some embodiments, the memory cells in the cross-point array are magnetoresistive random access memory (MRAM) cells. MRAM cells use magnetization to represent stored data, as opposed to some other memory technologies that use electronic charge to store data. Bits of data are written to an MRAM cell by changing the magnetization direction of a magnetic element (the "free layer") in the MRAM cell, and the bits are read by measuring the resistance of the MRAM cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction established by another element (the "reference layer") in the MRAM. In some embodiments, low resistance is referred to as the parallel state or P state, and high resistance is referred to as the antiparallel state or AP state. MRAM can change the direction of magnetization from the P state to the AP state, and vice versa, using the spin-transfer torque effect; writing typically requires a bipolar (bidirectional write) operation.

[0012] One conventional approach reads reversible resistive memory cells, such as MRAM cells, by forcing a voltage through the memory cell and sampling the resulting memory cell current. In some embodiments, the MRAM cell has a threshold selector in series with a programmable resistance element. An example of a threshold selector is an Ovonic Threshold Switch (OTS). There can be significant variation in the OTS electrical characteristics from one memory cell to the next, which can reduce read margins. Using such a voltage-force approach to read an MRAM cell in series with a threshold selector can be problematic. One problem is that voltage-force reading techniques do not compensate for variations in the voltage drop across the threshold selector when the threshold selector is in the on state. The on-state voltage drop is also referred to as the “offset voltage.” A forced current approach can compensate for the offset voltage variation of such threshold selectors. A forced current approach can also compensate for issues such as voltage drop across selected word lines and selected bit lines due to variations in the resistance of the word lines and bit lines depending on their combined position in the array.

[0013] As mentioned above, issues such as variations in OTS (electrical characteristics) can reduce read margins. One way to address this issue is to use a larger signal to read the memory cell. For example, to successfully read an MRAM cell, a sufficiently large current must be forced across the memory cell. Alternatively, to successfully read an MRAM cell, a sufficiently large voltage must be forced across the memory cell. Both forced current and forced voltage techniques result in a voltage across the memory cell, which is referred to herein as the cell voltage. If the cell voltage is not large enough, the bit error rate may exceed the range that can be corrected by the error correction circuitry. However, for example, if the cell voltage is too high, the reversible resistive memory cell may be overstressed, reducing its endurance. In some embodiments, forced current reading limits the voltage that can appear across the MRAM cell by clamping the voltage that can appear across the memory cell.

[0014] As used herein, the terms "top" and "bottom," "upper" and "lower," and "vertical" and "horizontal," and their configurations, are exemplary and illustrative only and are not intended to limit the description of the present technology, insofar as references may be interchanged in location and orientation. Also, as used herein, the terms "substantially" and / or "about" mean that a specified dimension or parameter may vary within acceptable tolerances for a given application.

[0015] 1 is a block diagram of one embodiment of a non-volatile memory system (or more simply, "memory system") 100 connected to a host system 120. The memory system 100 can implement the techniques presented herein for a mixed forced current read scheme. Many different types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include Dual In-line Memory Modules (DIMMs), solid state drives ("SSDs"), memory cards, and embedded memory devices. However, other types of memory systems can also be used.

[0016] The memory system 100 of FIG. 1 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory 106 (e.g., MRAM / ReRAM / DRAM). In one embodiment, the memory controller 102 provides access to memory cells in a cross-point array in the local memory 106. For example, the memory controller 102 may provide access to a cross-point array of MRAM cells in the local memory 106. In another embodiment, the controller 102 or the interface 126, or both, are eliminated, and the memory package is directly connected to the host 120 through a bus such as DDRn. The local memory 106 may be referred to as a memory system. The combination of the memory controller 102 and the local memory 106 may be referred to herein as a memory system. In some embodiments, the resistive random access memory elements in the local memory 106 are read using a mixed forced current read, which includes performing a forced current referenced read followed by a forced current SRR if the forced current referenced read fails.

[0017] The memory controller 102 includes a Front-End Processor (FEP) circuit 110 and one or more Back-End Processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In another embodiment, an integrated controller ASIC can combine both front-end and back-end functions. In another embodiment, the FEP and BEP are eliminated in favor of directional control by the host 120, and any functionality required for memory, such as ECC and wear leveling, is generated on the memory chip. Further details of on-chip memory maintenance are described in U.S. Pat. No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Pat. No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entireties. The memory is synchronous if the time allowed to read the memory is consistently the same (thus allowing for both the first read / sample / store / and SRR). If handshaking is used, the memory is asynchronous and requires handshaking so that the improved latency of forced current referenced read can be signaled for reduced latency. In another embodiment, forced current referenced read is always used without an SRR cycle, so the chip can be used synchronously with this faster latency in a direct replacement for DRAM in a DDRn interface connected directly to the host, and the BER should be low enough so that all errors are within the correction capability of the ECC engine.

[0018] The ASICs for each of the BEP circuit 112 and the FEP circuit 110 are implemented on the same semiconductor, such that the memory controller 102 is fabricated as a system on a chip ("SoC"). Alternatively, such circuitry can be located on each memory chip, avoiding the overhead space and expense of adding an external controller and / or BEP or FEP. Both the FEP circuit 110 and the BEP circuit 112 include their own processors. In one embodiment, the FEP circuit 110 and the BEP circuit 112 function in a master-slave configuration, with the FEP circuit 110 being the master and each BEP circuit 112 being the slave. For example, the FEP circuit 110 implements a Media Management Layer (MML), which performs memory management (e.g., garbage collection, wear leveling, etc.), logical-to-physical address translation, communication with the host, management of the local memory 106, and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuitry 112 manages memory operations within the memory package / die upon request of the FEP circuitry 110. For example, the BEP circuitry 112 may perform read, erase, and programming processes. Additionally, the BEP circuitry 112 may perform buffer management, setting specific voltage levels required by the FEP circuitry 110, error correction (ECC), control of toggle mode interfaces to the memory packages, etc. In one embodiment, each BEP circuitry 112 is responsible for its own set of memory packages.

[0019] In one embodiment, non-volatile memory 104 includes multiple memory packages. Each memory package includes one or more memory dies. Accordingly, memory controller 102 is connected to one or more non-volatile memory dies. In one embodiment, the memory packages may include types of memory such as storage class memory (SCM) based on resistive random access memory (e.g., ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, memory controller 102 provides access to memory cells in a cross-point array within memory packages 104.

[0020] The memory controller 102 communicates with the host system 120 via an interface 130 that implements a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be eliminated and the memory package placed directly on a host bus, e.g., DDRn. To cooperate with the memory system 100, the host system 120 includes a host processor 122, a host memory 124, and an interface 126, connected along a bus 128. The host memory 124 is the host's physical memory and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In embodiments, the host memory 124 includes a cross-point array of non-volatile memory cells, each having a resistive random access memory element and a two-terminal selector element in series with the memory element. In some embodiments, the resistive random access memory elements in the host memory 124 are read using a mixed forced current read, which includes performing a forced current SRR after the forced current referenced read if the forced current referenced read fails.

[0021] Host system 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host system 120. Host memory 124 may be referred to herein as a memory system. The combination of host processor 122 and host memory 124 may be referred to herein as a memory system. In one embodiment, such host memory may be a cross-point memory using MRAM.

[0022] FIG. 2 is a block diagram of one embodiment of the FEP circuit 110. It shows an interface 150 that communicates with the host system 120 and a host processor 152 that communicates with the interface. The interface 150 may be, for example, CXL, DDR, or PCIe. The host processor 152 may be any type of processor known in the art that is suitable for implementation. The host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit, typically between cores within an SoC. NOCs can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, providing significant improvements over traditional bus and crossbar interconnects. NOCs improve SoC scalability and power efficiency for complex SoCs compared to other designs. NOC wires and links are shared by many signals. A high level of parallelism is achieved because all links within a NOC can operate on different data packets simultaneously. Thus, as the complexity of integrated subsystems continues to increase, the NOC provides improved performance (e.g., throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Memory processor 156, SRAM 160, and local memory controller 162 are connected to and communicate with NOC 154. Local memory controller 162 is used to operate and communicate with local memory 106 (e.g., local memory 106 in FIG. 1). In one embodiment, local memory controller 162 is an MRAM controller for operating and communicating with MRAM in local memory 106. In one embodiment, local memory controller 162 is a ReRAM controller for operating and communicating with ReRAM in local memory 106. SRAM 160 is local RAM memory used by memory processor 156.The memory processor 156 is used to operate the FEP circuitry and perform various memory operations. Also in communication with the NOC are two interfaces 164 and 166, which may be, for example, CXL, DDR, or PCIe. In the embodiment of FIG. 2, the SSD controller includes two BEP circuits 112. Thus, there are two interfaces 164 / 166. Each interface 164 / 166 communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112. Thus, there may be three or more interfaces 164 / 166.

[0023] The FEP circuit 110 may also include a media management layer (MML) 158 that performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logical-to-physical address translation, communication with the host, management of DRAM (local volatile memory), and overall operation of the SSD (or other non-volatile storage system). The media management layer MML 158 may be integrated as part of the memory management that can handle memory errors and interface with the host. Specifically, the MML may be a module within the FEP circuit 110 and may be responsible for the internals of memory management. Specifically, the MML 158 may include algorithms within the memory device firmware that translate writes from the host into writes to the die's memory structures (e.g., 502 in FIGS. 5A and 5B below). The MML 158 may be required because 1) memory endurance may be limited, 2) memory structures can only be written in multiples of pages, and / or 3) memory structures cannot be written unless erased as a block. The MML 158 understands these potential constraints of the memory structure that may not be visible to the host, and therefore attempts to translate writes from the host into writes into the memory structure.

[0024] FIG. 3 is a block diagram of one embodiment of the BEP circuit 112. FIG. 3 shows an interface 200 (which may be, for example, CXL, DDR, or PCIe) for communicating with the FEP circuit 110 (e.g., for communicating with one of the interfaces 164 and 166 of FIG. 2). The interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs may be combined into one larger NOC. Each NOC (202 / 204) is connected to the SRAMs (230 / 260), buffers (232 / 262), processors (220 / 250), and data path controllers (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engines 226 / 256 are used to perform error correction. The XOR engines 224 / 254 are used to XOR data, so that the data can be combined and stored in a manner that can be restored in the event of a programming error. The data path controller 222 is connected to an interface module for communicating with memory packages via four channels. Thus, the upper NOC 202 is associated with an interface 228 for four channels for communicating with memory packages, and the lower NOC 204 is associated with an interface 258 for four additional channels for communicating with memory packages. Each interface 228 / 258 includes four toggle mode interfaces (TM interfaces), four buffers, and four schedulers. There is one scheduler, buffer, and TM interface for each channel. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. The XOR engines 224 / 254 and the ECC engines 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, the XOR engine 224 / 254 and the ECC engine 226 / 256 may be implemented in software.The scheduler, buffers, and TM interface are hardware circuits. In another embodiment, such circuits and software, or portions thereof, are located on-chip within each memory.

[0025] 4 is a block diagram of one embodiment of a memory package 104 including multiple memory dies 292 connected to a memory bus (data lines and chip enable lines) 294. The memory bus 294 connects to a toggle mode interface 296 for communicating with a TM interface of the BEP circuit 112 (see, for example, FIG. 3). In some embodiments, the memory package may include a controller connected to the memory bus and the TM interface. A memory package may have one or more memory dies. In one embodiment, each memory package includes 8 or 16 memory dies, although other numbers of memory dies may also be implemented. The technology described herein is not limited to a particular number of memory dies.

[0026] FIG. 5A is a block diagram illustrating an example of a memory die 292 in which the techniques described herein can be implemented. In one embodiment, the memory die 292 is included in the local memory 106. In one embodiment, the memory die 292 is included in the host memory 124. The memory die 292 includes a memory array 502 that can include any of the memory cells described below. The array demarcation lines of the memory array 502 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented. The memory die 292 includes a row control circuit 520, whose output 508 is connected to each word line of the memory array 502. The row control circuit 520 receives a group of M row address signals and one or more various control signals from the system control logic circuit 560 and can typically include circuits such as a row decoder 522, a row driver 524, and a block select circuit 526 for both read and write operations. The row control circuit 520 may also include read / write circuitry. In an embodiment, row decode and control circuitry 520 includes sense amplifiers 528, each including circuitry for sensing the state (e.g., voltage) of a word line of memory array 502. In one embodiment, sensing the word line voltage determines the state of memory cells in the cross-point array. Memory die 292 also includes column decode and control circuitry 510, whose inputs / outputs 506 are connected to respective bit lines of memory array 502. While only a single block is shown for array 502, a memory die may include multiple arrays or "tiles" that can be individually accessed. Column control circuitry 510 receives a group of N column address signals and one or more various control signals from system control logic 560 and typically includes circuits such as a column decoder 512, a column decoder or driver 514, a block select circuit 516, and read / write circuits and I / O multiplexers.

[0027] System control logic 560 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. In other embodiments, these data and commands are sent and received directly from the memory package to the host without a separate controller, with any required controllers being within each die or additional dies in a multi-chip memory package. In some embodiments, system control logic 560 may include a state machine 562 that provides die-level control of memory operations. In one embodiment, state machine 562 is programmable by software. In other embodiments, state machine 562 is implemented entirely in hardware (e.g., electrical circuitry) without the use of software. In another embodiment, state machine 562 is replaced by a microcontroller or microprocessor. System control logic 560 may also include a power control module 564 that controls the power and voltage supplied to the rows and columns of memory 502 during memory operations and may include charge pump and regulator circuits for generating regulated voltages. System control logic 560 includes storage 566 that can be used to store parameters for operating memory array 502. Such system control logic may be instructed by host 120 or memory controller 102 to refresh logic 572, which may load on-chip stored row and column addresses (pointers) that may be incremented after a refresh. Such address bits may simply be selected (to refresh the OTS). Alternatively, such addresses may be read, corrected by steering through ECC engine 569, and then stored in a "spare" location that is also incremented (thus, all codewords are periodically read, corrected, and relocated across the chip).Such operations may be controlled more directly by an external controller, for example a host PCIe or CXL controller.

[0028] Commands and data are transferred between the memory controller 102 and the memory die 292 via a memory controller interface 568 (also referred to as a "communications interface"). Such an interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 568 is an electrical interface for communicating with the memory controller 102. An example of the memory controller interface 568 includes a toggle mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 568 may implement a toggle mode interface that connects to a toggle mode interface of the memory interface 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 568 includes a set of input and / or output (I / O) pins that connect to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn, such as DDR5 or LPDDR5, or a subset thereof with smaller pages and / or relaxed timing.

[0029] The system control logic 560, located in an external controller on a memory die within the memory package, may include an error correction code (ECC) engine 569. The ECC engine 569 may be referred to as an on-die ECC engine because it is on the same semiconductor die as the memory cells. That is, the on-die ECC engine 569 may be used to encode data to be stored in the memory array 502, decode the decoded data, and correct errors. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 569 may be used to execute a decoding algorithm and perform error correction. Thus, the ECC engine 569 may decode the ECC codeword. In embodiments, the ECC engine 569 can decode data very quickly, which facilitates mixed forced current reads of MRAM and other memory element technologies using two-terminal selectors such as OTS.

[0030] Having the ECC engine 569 on the same die as the memory cells allows for very fast decoding, which facilitates mixed forced current read embodiments. The ECC engine 569 can use a wide variety of decoding algorithms, including, but not limited to, Reed-Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC). In embodiments, the ECC engine 569 can determine or estimate the number of bit errors in a codeword before decoding the codeword. In embodiments, the ECC engine 569 calculates a syndrome for the codeword to estimate the number of bit errors in the codeword. In embodiments, the syndrome is based on the number of parity check equations that are not satisfied. In embodiments, the ECC engine 569 can decode a codeword if the codeword has no more than a certain number of erroneous bits.

[0031] In some embodiments, all of the elements of memory die 292, including system control logic 560, may be formed as part of a single die. In other embodiments, some or all of system control logic 560 may be formed on a different die.

[0032] In one embodiment, memory structure 502 comprises a three-dimensional memory array of non-volatile memory cells, with multiple memory levels formed on a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active areas disposed on a silicon (or other type) substrate. In another embodiment, memory structure 502 comprises a two-dimensional memory array of non-volatile memory cells.

[0033] The exact types of memory array architectures or memory cells included in memory structure 502 are not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. No particular non-volatile memory technology is required for the purposes of the newly claimed embodiments presented herein. Other examples of technologies suitable for memory cells of memory structure 502 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of technologies suitable for memory cell architectures of memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0034] An example of a ReRAM or MRAM cross-point memory includes a reversible resistance-switching element and an OTS selector arranged in series in a cross-point array accessed by X- and Y-lines (e.g., word lines and bit lines). Another embodiment of the cross-point is a PCM in series with an OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state-change element based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes with a thin solid electrolyte film between them, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper). As temperature increases, the mobility of ions also increases, lowering the programming threshold of the conductive bridge memory cell. Therefore, a conductive bridge memory element may have a wide range of programming thresholds over temperature.

[0035] Magnetoresistive random access memory (MRAM) stores data using magnetic memory elements. The elements are formed from two ferromagnetic layers, each capable of retaining magnetization, separated by a thin insulating layer. In field-controlled MRAM, one of the two layers is a permanent magnet set to a specific polarity. The magnetization of the other layer can be changed to match that of an external field to store memory. Other types of MRAM cells are possible. A memory device can be constructed from a grid of MRAM cells. In one embodiment for programming, each memory cell is located between a pair of write lines positioned perpendicular to each other and parallel to the cell, one above the cell and one below the cell. In some MRAM cells, an induced magnetic field is generated when a current is passed through them. MRAM-based memory embodiments are discussed in more detail below.

[0036] Phase change memory (PCM) exploits the unique behavior of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of germanium atoms with a laser pulse (or light pulse from another light source). Memory cells are programmed with current pulses that can change the coordination of the PCM material or switch it between amorphous and crystalline states. The use of "pulse" herein does not require a square pulse, but includes vibrations or bursts of sound (continuous or non-continuous), current, voltage, light, or other waves. Additionally, the current forced for writing can be rapidly driven to a peak value and then linearly ramped down, for example, with an edge rate of 500 ns. Forcing such peak currents can be limited by zoned voltage standards that vary depending on the memory cell's location along the word line or bit line.

[0037] Those skilled in the art will appreciate that the technology described herein is not limited to a single particular memory structure, memory architecture, or material composition, but rather covers many related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0038] The elements in FIG. 5A can be grouped into two parts: the memory structure 502 and the peripheral circuitry, which includes all of the other elements. A key characteristic of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die 292 devoted to the memory structure 502. However, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose very severe limitations on these peripheral elements. For example, the need to fit sense amplifier circuitry within the available area can place significant constraints on the sense amplifier design architecture. With respect to the system control logic 560, reduced area availability can limit the available functionality that can be implemented on-chip. As a result, the amount of area devoted to the memory structure 502 and the amount of area devoted to the peripheral circuitry are fundamental trade-offs in the design of the memory die 292. Such trade-offs can result in more IR drop by using a larger xy array of memory between the driver circuits on the word lines and bit lines, which can benefit more from the use of voltage limits and voltage-compliant zoning by memory cell location along the word lines and bit lines.

[0039] Another area where memory structures 502 and peripheral circuits often conflict is in the processes involved in forming these regions, as these regions often involve different process technologies and the trade-offs of having different technologies on a single die. For example, such sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 560 often use PMOS devices. In some cases, memory structures will be based on CMOS devices. Process operations for fabricating CMOS dies differ in many aspects from process operations optimized for NMOS technology.

[0040] To ameliorate these limitations, the embodiments described below can separate the elements of FIG. 5A onto separately formed dies, which are then bonded together. FIG. 5B shows an integrated memory assembly 570 having a memory structure die 580 and a control die 590. The memory structure 502 is formed on the memory structure die 580, and some or all of the peripheral circuit elements, including one or more control circuits, are formed on the control die 590. For example, the memory structure die 580 can be formed solely of memory elements, such as an array of memory cells of MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuitry, even if it includes elements such as decoders and sense amplifiers, can then be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows more space for peripheral elements, which can incorporate additional functionality that could not easily be incorporated if the die were limited by the margins of the same die holding the memory cell array. The two dies can then be bonded together in a bonded multi-die integrated memory assembly, with the array on one die connected to the peripheral elements on the other die. The following focuses on an integrated memory assembly of one memory die and one control die, although other embodiments may use additional dies, such as two memory dies and one control die.

[0041] 5A, memory die 580 of FIG. 5B can include multiple independently accessible arrays or "tiles." System control logic 560, row control circuitry 520, and column control circuitry 510 are located within control die 590. In some embodiments, all or a portion of column control circuitry 510 and all or a portion of row control circuitry 520 are located on memory structures die 580. In some embodiments, some of the circuitry within system control logic 560 is located on memory structures die 580.

[0042] 5B shows column control circuitry 510 on control die 590 coupled to memory structures 502 on memory structure die 580 through electrical paths 592. For example, electrical paths 592 may provide electrical connections between column decoder 512, column driver circuitry 514, and block select 516 and the bit lines of memory structure 502. The electrical paths may extend from column control circuitry 510 in control die 590 through pads on control die 590 that are bonded to corresponding pads on memory structure die 580 that are connected to the bit lines of memory structure 502. Each bit line of memory structure 502 may have a corresponding electrical path within electrical paths 592 that includes a pair of bond pads that connect to column control circuitry 510. Similarly, row control circuitry 520, including row decoder 522, row driver 524, block select 526, and sense amplifier 528, is coupled to memory structure 502 through electrical paths 594. Each of electrical paths 594 may correspond to a word line, for example. Additionally, additional electrical paths may be provided between the control die 590 and the memory die 580 .

[0043] For purposes of this specification, the phrase "control circuitry" may include one or more of the memory controller 102, system control logic 560, column control circuitry 510, row control circuitry 520, a microcontroller, a state machine, host processor 122, and / or other control circuitry or similar circuitry used to control non-volatile memory. A control circuitry may include hardware alone or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuitry. A control circuitry may include a processor, FPGA, ASIC, integrated circuit, or other type of circuitry. Such control circuitry may include a driver, such as a direct drive by connecting a node through a transistor (gate to power supply) that drives to a certain voltage, such as a power supply. Such control circuitry may also include a current source driver.

[0044] For purposes of this specification, the term "device" may include, but is not limited to, one or more of host system 120, a combination of host processor 122 and host memory 124, host memory 124, memory system 100, memory controller 102, local memory 106, a combination of memory controller 102 and local memory 106, memory package 104, memory die 292, integrated memory assembly 570, and / or control die 590.

[0045] In the following description, the memory array 502 of FIGS. 5A and 5B will be discussed in the context of a cross-point architecture. A cross-point architecture includes a first set of conductive lines or wires, such as word lines, that run in a first direction relative to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, that run in a second direction relative to the underlying substrate. Memory cells are located at the cross points of the word lines and bit lines. The memory cells at these cross points can be formed according to any of several techniques, including those described above. The following description focuses primarily on embodiments based on a cross-point architecture using MRAM memory cells, each arranged in series with a two-terminal selector, such as an ovonic threshold switch (OTS), to form a selectable memory bit. Thus, embodiments include a mixed forced current read scheme in a cross-point architecture with MRAM cells each having a series OTS selector. However, embodiments of the mixed forced current read scheme are not limited to cross-point architectures with MRAM cells each having a series OTS selector.

[0046] In some embodiments, there are two or more control dies 590 and two or more memory structure dies 580 in the integrated memory assembly 570. In some embodiments, the integrated memory assembly 570 includes a stack of multiple control dies 590 and multiple memory structure dies 580. Figure 6A shows a side view of an embodiment of an integrated memory assembly 570 (e.g., a stack with control dies 590 and memory structure dies 580) stacked on a substrate 602. The integrated memory assembly 570 has three control dies 590 and three memory structure dies 580. In some embodiments, there are four or more memory structure dies 580 and four or more control dies 590.

[0047] Each control die 590 may be affixed (e.g., bonded) to at least one of the memory structure dies 580. Each control die 590 has several bond pads 674 on its major surface. Each memory structure die 580 has several bond pads 670 on its major surface. Note that there are bond pad pairs 670 / 674. In one embodiment, the pattern of bond pads 670 matches the pattern of bond pads 674. In some embodiments, bond pads 670 and / or 674 are flip-chip bond pads. Thus, bond pads 670, 674 electrically and physically couple memory die 580 to control die 590. Bond pads 670, 674 also enable internal signal transfer between memory die 580 and control die 590. Thus, memory die 580 and control die 590 are bonded together by bond pads.

[0048] The bond pads 670, 674 may be formed, for example, from copper, aluminum, and alloys thereof. A liner 648 may be present between the bond pads 670, 674 and the major surface. The liner may be formed, for example, from a titanium / titanium nitride stack. The bond pads 670, 674 and the liner may be applied by evaporation and / or plating techniques. The bond pads and liner may have a combined thickness of 720 nm, although in further embodiments, this thickness may be greater or less.

[0049] Bond pads enable internal signal transfer. As used herein, "internal signal transfer" means signal transfer between the control die 590 and the memory die 580. Internal signal transfer enables the circuits on the control die 590 to control memory operations within the memory die 580. Accordingly, bond pads 670, 674 can be used for memory operation signal transfer. As used herein, "memory operation signal transfer" refers to any signal related to a memory operation within the memory die 580. Memory operation signal transfer can include, but is not limited to, providing a voltage, providing a current, receiving a voltage, receiving a current, sensing a voltage, and / or sensing a current.

[0050] There can be more bond pads than shown in FIG. 6A. The space between the two dies 580, 590 joined together can be filled with a solid layer 648 formed from an epoxy or other resin or polymer. This fixing layer 648 protects the electrical connections between the dies 580, 590 and further fixes the dies together. Various materials can be used as the fixing layer 648, but in an embodiment, it can be a Hysol epoxy resin from Henkel Corp. which has an office in California, USA.

[0051] The integrated memory assembly 570 can be stacked, for example, with a step offset, and the bond pads at each level are not covered and are accessible from above. Wire bonds 606 connected to the bond pads connect the control die 590 to the substrate 602. Some of these wire bonds can be formed across the full width of each control die 590 (i.e., within the page of FIG. 6A).

[0052] Signals may be routed through the memory structure die 580 using memory through silicon vias (TSVs) 612. Signals may be routed through the control die 590 using control through silicon vias (TSVs) 614. The TSVs 612, 614 may be formed before, during, or after the formation of the integrated circuits in the semiconductor dies 580, 590. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to metal diffusion. The barrier layer may then be lined with a seed layer, which may be plated with a conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0053] Solder balls 608 may optionally be affixed to contact pads 610 on the underside of substrate 602. Solder balls 608 may be used to electrically and mechanically couple integrated memory assembly 570 to a host device, such as a printed circuit board. If integrated memory assembly 570 is used as an LGA package, solder balls 608 may be omitted. Solder balls 608 may form part of an interface between integrated memory assembly 570 and memory controller 102.

[0054] 6B shows a side view of an embodiment of an integrated memory assembly 570 stacked on a substrate 602. The integrated memory assembly 570 has three control dies 590 and three memory structure dies 580. In some embodiments, there are four or more memory structure dies 580 and four or more control dies 590. In this example, each control die 590 is bonded to at least one memory structure die 580. Optionally, a control die 590 may be bonded to two memory structure dies 580.

[0055] Some of the bond pads 670, 674 are shown. Many more bond pads may be present. The space between the two die 580, 590 bonded together is filled with a solid layer 648, which may be formed from epoxy or other resin or polymer. In contrast to the embodiment of FIG. 6A, the integrated memory assembly 570 of FIG. 6B does not have a step offset. Memory structure die through silicon vias (TSVs) 612 may be used to route signals through the memory structure die 580. Control die through silicon vias (TSVs) 614 may be used to route signals through the control die 590.

[0056] Solder balls 608 may optionally be attached to contact pads 610 on the underside of substrate 602. Solder balls 608 may be used to electrically and mechanically couple integrated memory assembly 570 to a host device, such as a printed circuit board. If integrated memory assembly 570 is used as an LGA package, solder balls 608 may be omitted.

[0057] As briefly discussed above, the control die 590 and the memory structure die 580 may be bonded together. Bond pads on each die 580, 590 can be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other in a so-called Cu-to-Cu bonding process, without solder or other additional materials. In a Cu-to-Cu bonding process, the bond pads are formed in a highly controlled environment where they are controlled to be highly flat and free of surrounding particulates, which could otherwise settle on the bond pads and prevent a tight bond. Under these well-controlled conditions, the bond pads are aligned and pressed together to form an interconnect bond based on surface tension. Such bonds can be formed at room temperature, although heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads can be approximately 6 μm square and spaced apart from each other at a pitch of 6 μm to 6 μm. This process is referred to herein as Cu-Cu bonding, although the term may also be applied when the bond pads are formed of materials other than Cu.

[0058] Bonding semiconductor dies together can be difficult when the bond pads have small areas. The size of the bond pads and the pitch between them can be further reduced by providing a film layer on the surface of the semiconductor die that includes the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads can bond to each other, and the film layers on each die can bond to each other. Such bonding techniques are sometimes referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads can be approximately 6 μm square and spaced apart at a pitch of 1 μm to 6 μm. Bonding techniques that provide bond pads with even smaller sizes and pitches can also be used.

[0059] Some embodiments may include a film on the surfaces of the dies 580, 590. If such a film is not initially provided, the space between the dies may be underfilled with an epoxy or other resin or polymer. The underfill material may be applied as a liquid, which then hardens into a solid layer. This underfill step protects the electrical connection between the dies 580, 590 and also secures the dies together. While various materials may be used as the underfill material, in embodiments, it may be Hysol epoxy resin from Henkel Corp., with offices in California, USA.

[0060] FIG. 7A shows a perspective view of one embodiment of a portion of a memory array forming a cross-point architecture. The memory array 502 of FIG. 7A is one example of an implementation of the memory array 502 of FIG. 5A or 5B, and the memory die 292 or memory structure die 580 can include multiple such array structures. The memory array 502 can be included in the local memory 106 or the host memory 124. The bit lines BL1-BL5 are arranged in a first direction (represented as extending into a page) relative to a substrate (not shown) underlying the die, and the word lines WL1-WL5 are arranged in a second direction perpendicular to the first direction. FIG. 7A illustrates an embodiment in which the word lines WL1-WL5 and BL1-BL5 both extend horizontally relative to the substrate, while the memory cells, two of which are shown at 701, are arranged in a direction perpendicular to the substrate, such that the current (I cell 7D. In a memory array having additional layers of memory cells, such as those described below with respect to FIG. 7D, there are corresponding additional layers of bit lines and word lines.

[0061] As shown in FIG. 7A, the memory array 502 includes a plurality of memory cells 701. The memory cells 701 may include rewriteable memory elements, such as those that may be implemented using ReRAM, MRAM, PCM, or other materials with programmable resistance. Memory cells that include MRAM memory elements will be referred to simply as MRAM memory cells. The memory cells 701 may also include selector elements, such as those that may be implemented using ovonic threshold switches (OTS), volatile conductive bridges (VCB), metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current on select voltage. The following discussion focuses on memory cells comprised of MRAM memory elements combined in series with ovonic threshold switches, although much of the discussion is more generally applicable. Current flow in memory cells of the first memory level is indicated by arrow I cell Although shown as flowing upward as indicated by , current can flow in either direction, as will be explained in more detail below.

[0062] 7B and 7C present side and top views, respectively, of the cross-point architecture of FIG. 7A. The side view of FIG. 7B shows one bottom wire, i.e., word line WL1, and top wires, i.e., bit lines BL1-BL2. n 7C shows the M bottom wires WL1-WL2. At the cross-point between each top wire and bottom wire is an MRAM memory cell 701, although PCM, ReRAM, FeRAM, or other technologies can also be used as memory elements. M and N upper wires BL1 to BL N 12B is a top view showing the cross-point structure of a binary MRAM memory cell. In a binary embodiment, the MRAM cell at each cross-point can be programmed to one of two resistance states: high and low. MRAM memory cell design embodiments and techniques for reading them are described in more detail below. In some embodiments, these sets of wires are arranged consecutively as "tiles," and such tiles can be paired adjacently in the word line (WL) direction and orthogonally in the bit line direction to create a module. Such modules can be "center-driven" by combining 2x2 tiles to form four tiles, with the WL drivers between tiles running consecutively across the driver approximately in the middle of the line. Similarly, a BL driver may be located between a pair of center-driven tiles paired in the BL direction, so that the driver and its area are shared between the pair of tiles. One embodiment of a module with four tiles is shown in FIG. 12B and described below.

[0063] The cross-point array of Figure 7A shows an embodiment with one layer of word lines and bit lines, with MRAM or other memory cells located at the intersections of two sets of conductive lines. To increase the storage density of a memory die, multiple layers of such memory cells and conductive lines can be formed. A two-layer example is shown in Figure 7D.

[0064] 7D shows a perspective view of an embodiment of a portion of a two-level memory array forming a cross-point architecture. Similar to FIG. 7A, FIG. 7D shows word lines WL 1、1 ~WL 1、4 1 shows a first layer 718 of memory cells 701 of array 502 connected at the cross points of the first layer of bit lines BL1-BL5. A second layer of memory cells 720 is shown above bit lines BL1-BL5 and connected between these bit lines and word lines WL 2、1 ~WL 2、4 , and a second set of memory cells. While FIG. 7D shows two layers 718 and 720 of memory cells, this structure can be extended upward through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array of FIG. 7D can be biased for a read or program operation so that current in each layer flows from the word line layer to the bit line layer, or vice versa. The two layers can be configured with driver selections in either the positive or negative direction to have current flow in the same direction in each layer for a given operation, or to have current flow in opposite directions.

[0065] The use of a cross-point architecture enables a small-footprint array, and several such arrays can be formed on a single die. The memory cells formed at each cross-point may be resistive memory cells, with data values ​​encoded as different resistance levels. Depending on the embodiment, the memory cells may be binary-valued, having either a low-resistance state or a high-resistance state, or may be multi-level cells (MLC) that can have additional resistances intermediate the low-resistance state and the high-resistance state. The cross-point arrays described herein may be used in the memory die 292 of FIG. 4, the local memory 106 of FIG. 1, and / or the host memory 124 of FIG. 1. Resistive memory cells may be formed according to many of the technologies described above, such as ReRAM, PCM, FeRAM, or MRAM. The following description is presented primarily in the context of a memory array using a cross-point architecture with binary-valued MRAM memory cells, although much of the description may be more generally applicable.

[0066] 8 shows an embodiment of the structure of an MRAM cell. The MRAM cell includes a bottom electrode 801, a spacer 812, a threshold switching selector 802, a spacer 814, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separation or tunnel layer, in this example, magnesium oxide (MgO) 805, and a top electrode 811 separated from the free layer 807 by a spacer 809. In another embodiment, the locations of the reference layer 803 and the free layer 807 are switched, with the reference layer 803 above the MgO 805 and the free layer 807 below the MgO 805. In another embodiment, the location of the threshold switching selector 802 is between the free layer 807 and the top electrode 811.

[0067] In some embodiments, the bottom electrode 801 is referred to as a word line and the top electrode 811 is referred to as a bit line. In other embodiments, the bottom electrode 801 is referred to as a bit line and the top electrode 811 is referred to as a word line. The state of the memory cell is based on the relative orientations of the magnetizations of the reference layer 803 and the free layer 807: when the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low resistance state (LRS); when the two layers have opposite orientations, the memory cell is in an anti-parallel (AP) high resistance state (HRS). MLC embodiments include additional intermediate states. The orientation of the reference layer 803 is fixed, oriented upward in the example of FIG. 8. The reference layer 803 is also known as a fixed layer or pinned layer. The reference layer 803 can be composed of multiple ferromagnetic layers antiferromagnetically coupled in a structure commonly referred to as a synthetic antiferromagnet, or SAF for short.

[0068] Data is written to an MRAM memory cell by programming the free layer 807 to either the same or opposite orientation. An array of MRAM memory cells can be placed in an initial or erased state by setting all of their free layers to a low-resistance state with the same magnetic orientation as their reference layers. Each memory cell is then selectively programmed (also referred to as "written") by reversing the magnetic field to the opposite side of the reference layer 803, placing its free layer 807 in a high-resistance state. The reference layer 803 is formed to maintain its orientation when programming the free layer 807. The reference layer 803 can have a more complex design, including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, the diagram and description omit these additional layers and focus only on the fixed magnetic layer, which is primarily responsible for tunneling magnetoresistance in the cell.

[0069] The threshold switching selector 802 has a high resistance (off or non-conducting state) until it is biased to a voltage above its threshold voltage or a current above its threshold current, and until its voltage bias falls below Vhold (“Voffset”) or the current falls below Ithreshold. After Vt is exceeded and while Vhold is exceeded across the switching selector, the switching selector has a low resistance (on or conducting state). The threshold switching selector remains on until its current is reduced to Ihold, which is less than the holding current, or the voltage is reduced to Vhold, which is less than the holding voltage. When this occurs, the threshold switching selector returns to its off (high) resistance state. Thus, to program a memory cell at a crosspoint, a voltage sufficient to turn on the associated threshold switching selector and set or reset the memory cell is applied, and to read the memory cell, the threshold switching selector must also be activated by being turned on before the resistance state of the memory cell can be determined. One example of a threshold switching selector is the Ovonic threshold switching material of an Ovonic Threshold Switch (OTS). Exemplary threshold-switching materials include Ge—Se, Ge—Se—N, Ge—Se—As, Ge—Se—Sb—N, Ge58Se42, GeTe6, Si—Te, Zn—Te, C—Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with atomic percentages ranging from a few percent to over 90 percent for each element. In one embodiment, the threshold-switching selector 802 is a two-terminal device. The threshold-switching selector 802 may also include an additional conductive layer on its interface with the reference layer 803. For example, a spacer 814 is shown between the switching selector 802 and the reference layer 803. The spacer layer 814 on its interface with the reference layer 803 may be a single conductive layer or may be composed of multiple conductive layers. The threshold-switching selector 802 may also include an additional conductive layer on its interface with the bottom electrode 801. For example, a spacer 812 is shown between the switch selector 802 and the reference layer 803. The spacer layer 812 on the interface with the bottom electrode 801 may be a single conductive layer or may be composed of multiple conductive layers.Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbon, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, etc. A threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes substantially from insulating or semi-insulating to conductive.

[0070] In the embodiment of FIG. 8, a forced current approach is used to access the MRAM cells. The forced current approach can be used to read or write the MRAM cells. In the forced current approach, an access current (e.g., I read or I write ) is driven through electrode 801 by current source 813, which is part of the row driver circuitry for electrode 801. select ) is supplied to electrode 811. An access current is driven through a portion of a first conductive line (e.g., a word line), through the selected memory cell, and through a portion of a second conductive line (e.g., a bit line). As used herein, a "read current" (I read ) and "write current" (I write The term ) is used in reference to the access current driven through an MRAM cell. A write current will change the state of the MRAM cell. As an example, a write current of about 30 uA for 50 ns will result in an RA of 10 Ωμm. 2 The critical dimension (CD) of the MRAM cell may be about 20 nanometers. The read current can be about half the write current for a limited time, such as less than 20 ns. A write current flowing in one direction through the MRAM cell changes an MRAM cell in the AP state from the AP state to the P state. A write current flowing in the opposite direction through the MRAM cell changes an MRAM cell in the P state from the P state to the AP state. In general, it is preferable that the read current be low enough and the read time be short enough so as not to change the state of the MRAM cell from the P state to the AP state or from the AP state to the P state.

[0071] As discussed in more detail below in connection with FIG. 10B , in some embodiments, the read current can be applied in the P2AP direction or, alternatively, in the AP2P direction. In some embodiments, the MRAM cell is read by performing a self-referenced read (SRR). The SRR operation can include two read and two write operations that allow for a direct comparison of the initial bit state resistance with the resistance of the bit in a known programmed state, followed by a rewrite to restore the initial bit state if it differs from the initial state after the first write. In one embodiment, the SRR includes a first read (Read 1 in the P2AP direction), a first write (Write 1 to the AP state), and a second read (Read 2 in the P2AP direction), followed by an optional second write (Write 2 to the P state for a bit initially in the P state). The voltage level of the memory cell from Read 1 in the P2AP direction is stored by converting it to a digital bit, for example, on a capacitor or by an analog-to-digital converter, and the bit is stored in a memory, such as an SRAM, until used in Read 2. The state stored in the capacitor can be adjusted to be 150mV positive or negative by forcing a voltage across one terminal of the capacitor connected to the storage capacitor. Alternatively, the digital storage level can be adjusted by digitally adding or subtracting 150mV to the storage bit.

[0072] Next, the memory cell is written to the AP state (Write 1). The sensed voltage level resulting from Read 2 in the P2AP direction (after Write 1) is compared to the stored and adjusted voltage level from Read 1, with both Read 1 and Read 2 being performed in the P2AP direction. A sufficient change in voltage level between Read 2 and Read 1, for example a change of 150 mV or more, indicates that the MRAM cell was originally in the P state. If the voltage change is less than 150 mV, the MRAM cell was originally in the AP state (the write indicated the bit state). An optional Write 2 of the bit AP2P is performed if the bit was initially in the P state and was switched to the AP state by Write 1. Alternatively, SRR has a first read (Read 1 in the AP2P direction), a first Write 1 to the P state, and a second read (Read 2 in the AP2P direction). The voltage level of the memory cell from Read 1 in the AP2P direction is stored and adjusted, for example, at −150 mv. The memory cell is then written to the P state (Write 1). The voltage level resulting from Read 2 in the AP2P direction is compared to the adjusted voltage level resulting from Read 1 in the AP2P direction. A sufficient change in voltage level indicates the MRAM cell was originally in the AP state. If the bit was originally in the AP state and was switched to the P state by Write 1, an optional Write 2 is performed. In some embodiments, the same polarity is used for Read 1, Write 1, and Read 2 to avoid switching a selector between Read 1 and Read 2. In some embodiments, Write 2 is delayed and performed only after other operations have been performed. In some embodiments, Write 1 is performed by extending the duration of the read current applied during Read 1.

[0073] In one embodiment, the MRAM cell is read by applying, for example, 0V to electrode 811 while driving, for example, 15 microamperes (μA) of current through electrode 801. This read current flows from electrode 801 to electrode 811. Note that this read can be Read1 or Read2 in a P2AP direction. P2AP means that the current flows in a direction that writes a bit from P to AP or from AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to electrode 811 while driving, for example, a write current of −30 μA through electrode 801. This write current flows from one electrode 811 to the other electrode 801. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to one electrode 811 while driving, for example, a 30 μA current through the other electrode 801. This write current flows from electrode 801 to electrode 811 .

[0074] 8, a select voltage can be applied to electrode 801 and an access current can be applied through electrode 811. In one such embodiment, the MRAM cell is read by applying, for example, 3V to one electrode 801 while driving, for example, a read current of −15 μA to the other electrode 811. This read current flows from electrode 801 to top electrode 811.

[0075] In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, −3 V to the bottom electrode 801 while driving, for example, a 30 μA write current through the top electrode 811. This electron current flows from the bottom electrode 801 to the top electrode 811. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0 V to the bottom electrode 801 while driving, for example, a −30 μA current through the top electrode 811. The electron current flows from the top electrode 811 to the bottom electrode 801. The duration for which the read current is applied can be substantially different from the duration for which the write current is applied. For example, the read current can be applied for 20 ns while the write current can be applied for 50 ns, after which the current through the cell is reduced to zero or to an amount that has a negligible chance of disturbing the cell during the duration for which it is applied. The durations of the write current and the read current can also be the same or substantially similar, for example, 20 ns. Each read can be performed with significantly less applied current than the write, such as 10 ua and 40 ua, respectively. It is also understood in this description that the direction of the current polarity to switch the magnetization of the bit to the P or AP state can vary based on the reference layer design and the location of the reference layer relative to the free layer.

[0076] FIG. 9 shows in more detail an embodiment of an MRAM memory cell design that can be implemented in a cross-point array. When placed in a cross-point array, the top and bottom electrodes of the MRAM memory cell are the top and bottom wires of the array. In the embodiment shown herein, the bottom electrode is the word line 901 and the top electrode is the bit line 911 of the memory cell, although in other embodiments, this can be reversed. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are also separated by an MgO barrier 905. In the embodiment shown in FIG. 9, an MgO cap 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. The threshold switch selector 802 can be between the reference layer 903 and the conductive spacer 902. On either side of the memory cell structure are liners 921 and 923, which may be part of the same structure but appear separate in the cross section of Figure 9. On either side of liners 921, 923 are shown portions of fill material 925, 927 used to fill otherwise empty areas of the cross point structure.

[0077] Regarding the free layer design 907, embodiments include a CoFe or CoFeB alloy having a thickness on the order of about 1-2 nm. An Ir layer can be interspersed within the free layer near the MgO barrier 905, and the free layer 907 can be doped or interspersed with Ta, W, or Mo. Embodiments of the reference layer 903 can include a bilayer of CoFeB and Co / Pt multilayers combined with an Ir or Ru spacer or a combination of both or an alloy 902. The MgO cap 908 is optional but can be used to increase the anisotropy and reduce the critical switching current of the free layer 907. The conductive spacer can be a conductive metal such as Ta, W, Ru, CN, TiN, and TaN, among others. The free layer can also be a composite free layer composed of multiple free layers with conductive layers such as W, Ta, or W between them, or multiple free layers with tunneling layers such as MgO between them.

[0078] The following description is primarily in terms of perpendicular spin-transfer torque MRAM memory cells, where the free layer 807 / 907 in FIGS. 8 and 9 includes a switchable magnetization direction perpendicular to the plane of the free layer. Spin transfer torque (STT) is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction (MJT) can be changed using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum inherent to the carrier. The current is generally unpolarized (e.g., consisting of 50% spin-up electrons and 50% spin-down electrons). A spin-polarized current is one in which electrons of one spin are more prevalent (e.g., majority spin-up electrons or majority spin-down electrons). A spin-polarized current can be generated by passing a current through a thick magnetic layer (commonly called a reference layer). When this spin-polarized current is injected into the second magnetic layer (free layer), angular momentum is transferred to the second magnetic layer, changing the magnetization direction of the second magnetic layer. This is called spin transfer torque. Figures 10A and 10B illustrate the use of spin transfer torque to program or write to MRAM memory. Spin transfer torque magnetic random access memory (STT MRAM) has the advantages of lower power consumption and better scalability than other MRAM variants. Compared to other MRAM implementations, such as toggle MRAM, STT switching technology requires relatively low power, virtually eliminates the problem of neighboring bit disturbance, and has better scaling for higher memory cell densities (reduced MRAM cell size). The latter issue also favors STT MRAM, in which the free and reference layer magnetizations are oriented perpendicular to the film plane rather than in-plane.

[0079] 10A and 10B and their explanations are given in terms of electron current, where the direction of the write current is defined as the direction of electron flow. Accordingly, with reference to FIGS. 10A and 10B, the term "write current" refers to electron current. Because electrons are negatively charged, the electron current is opposite to the conventionally defined current; the electron current flows from a lower voltage level to a higher voltage level, rather than from a higher voltage level to a lower voltage level as in conventional current flow.

[0080] 10A and 10B illustrate writing an MRAM memory cell via the STT mechanism, showing a simplified schematic diagram of an example of an STT-switched MRAM memory cell 1000 in which the magnetizations of both the reference and free layers are perpendicular. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 including an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is a free layer FL, whose magnetization direction is switchable. The lower ferromagnetic layer 1012 is a reference (or fixed) layer RL, whose magnetization direction is not switchable. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. The data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000, such as by forcing a current through it, using electrical conductors 1006 / 1008 attached to the memory cell 1000 to read the MRAM data. By design, both the parallel and antiparallel configurations remain stable (at sufficiently low read currents) during quiescent conditions and / or read operations.

[0081] For both the reference layer RL1012 and the free layer FL1010, the magnetization directions are in the perpendicular direction (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figures 10A and 10B show the magnetization direction of the reference layer RL1012 as upward and the magnetization direction of the free layer FL1010 as switchable between upward and downward, which is perpendicular to the plane.

[0082] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO), although other materials can also be used. The free layer 1010 is a ferromagnetic metal and possesses the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be many different types of materials, including, but not limited to, multiple layers of cobalt and platinum, and / or alloys of cobalt and iron.

[0083] As depicted in FIG. 10A , to “set” an MRAM memory cell bit value (i.e., select the magnetization direction of the free layer), an electron current 1050 is applied from conductor 1008 to conductor 1006 (so that the current flows in the opposite direction). Due to the negative charge of the electrons, the top conductor 1006 is placed at a higher voltage level than the bottom conductor 1008 to generate the electron current 1050. The electrons in the electron current 1050 are spin-polarized as they pass through the reference layer 1012 because the reference layer 1012 is a ferromagnetic metal. As the spin-polarized electrons tunnel across the tunnel barrier 1014, conservation of angular momentum can result in a spin-transfer torque on both the free layer 1010 and the reference layer 1012, but this torque is insufficient (by design) to affect the magnetization direction of the reference layer 1012. In contrast, if the initial magnetization orientation of the free layer 1010 is antiparallel (AP) to the reference layer 1012, this spin-transfer torque is sufficient (by design) to switch the magnetization orientation in the free layer 1010 to be parallel (P) to the magnetization orientation of the reference layer 1012, which is called antiparallel-to-parallel (AP2P) writing. The parallel magnetization then remains stable before and after such electronic current is turned off.

[0084] In contrast, if the free layer 1010 magnetization and the reference layer 1012 magnetization are initially parallel, the magnetization direction of the free layer 1010 can be switched to antiparallel with respect to the reference layer 1012 by applying an electron current in the opposite direction to that previously described. For example, electron current 1052 is applied from conductor 1006 to conductor 1008 by placing a higher voltage level on the bottom conductor 1008, as shown in FIG. 10B. This writes the P-state free layer 1010 to the AP state, and is called parallel-to-antiparallel (P2AP) writing. Thus, with the same STT physics, the magnetization direction of the free layer 1010 can be deterministically set to one of two stable orientations by judicious selection of the electron current direction (polarity).

[0085] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. A low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit, although an alternating pattern may occur. A read current can be applied across the memory cell (e.g., across MJT 1002) by applying an electron current flowing from conductor 1008 to conductor 1006 as shown at 1050 in FIG. 10A (the "AP2P direction"); alternatively, an electron current can be applied from conductor 1006 to conductor 1008 as shown at 1052 in FIG. 10B (the "P2AP direction"). For better understanding, the electron current flows in the opposite direction to the conventionally defined current. During a read operation, if the electron current is too high, it may disturb the data stored in the memory cell and change its state. For example, if the electron current Read1 uses the P2AP direction of FIG. 10B, too high a current or voltage level may switch any memory cells in the low-resistance P state to the high-resistance AP state before the bit voltage at Read1 is stored. As a result, although MRAM memory cells can be read in either direction, in various embodiments, the directionality of the write operation may favor one read direction over the other. For example, for a given read current, performing SRR in the P2AP direction may result in a lower error rate.

[0086] While the discussion of Figures 10A and 10B was in the context of electron currents for read and write currents, the discussion below is in the context of conventional currents unless otherwise specified.

[0087] Whether reading or writing a selected memory cell in the array structure of Figures 7A-7D, the bit line and word line corresponding to the selected memory cell are biased to apply a voltage or current across the selected memory cell to induce electron flow, as shown with respect to Figures 10A or 10B. As used herein, a "selected memory cell" means that the memory cell is selected for access (e.g., read access, write access). An "unselected memory cell" means that the memory cell is not selected for access by placing either its WL or BL, or both, at a voltage approximately halfway between the maximum positive and minimum negative voltages across the memory cell. For a given process, forward versus reverse programming of an MRAM may result in approximately the same write current, and programming from the low resistance state (LRS) to the high resistance state (HRS) may result in a write current of approximately 20 nm and RA 10 Ωμm. 2 For CDs, 20% more current may be required.

[0088] Some biasing techniques apply a voltage across unselected memory cells of the array, potentially inducing current through the unselected memory cells. While this wasted power consumption can be mitigated to some extent by designing memory cells to have relatively high resistance levels for both high and low resistance states, this still results in increased current and power consumption and imposes additional design constraints on the design of the memory cells and arrays. One approach to addressing this undesirable current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a select transistor can be placed in series with each resistive memory cell element of FIGS. 7A-7D, such that memory cell 701 is now a composite of a select transistor and a programmable resistor. However, the use of a select transistor requires the introduction of additional control lines and cell area that can turn on the corresponding transistor of a selected memory cell. Additionally, transistors often do not scale in the same way as resistive memory elements, so that as memory arrays scale to smaller sizes, the use of transistor-based selectors can become a limiting factor, for example, in cost reduction. An alternative approach to transistor selection is the use of a threshold selector in series with a programmable resistance element, such as threshold selector 802. A two-terminal threshold selector does not require the additional control lines and cell area described above to enable turning on the corresponding select transistor of the selected memory cell.

[0089] 11A and 11B illustrate an embodiment for incorporating a threshold switching selector into an MRAM memory array with a cross-point architecture. The example of FIG. 11A and FIG. 11B shows, in side view, two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer cross-point array as shown in FIG. 7D. FIG. 11A and FIG. 11B show a bottom first conductive line, which is word line 1 1100, a top first conductive line, which is word line 2 1120, and a middle second conductive line, which is bit line 1110. In these figures, for ease of presentation, all of these lines are shown extending from left to right across the page, but in a cross-point arrangement, they are more accurately represented in the perspective view of FIG. 7D, with the word line or first conductive line or wire extending in one direction parallel to the surface of the underlying substrate and the bit line or second conductive line or wire extending in a second direction parallel to the surface of the substrate that is approximately perpendicular to the first direction. The MRAM memory cell is also represented in a simplified form showing only the reference layer, the free layer, and the intermediate tunnel barrier, but in actual implementations will typically include additional structures as described above with respect to FIG.

[0090] An MRAM element 1102, including a free layer 1101, a tunnel barrier 1103, and a reference layer 1105, is formed over a threshold switching selector 1109, and this series combination of MRAM element 1102 and threshold switching selector 1109 together form a layer 1 cell between bit line 1110 and word line 1 1100. The series combination of MRAM element 1102 and threshold switching selector 1109 operates primarily as described above with respect to Figures 10A and 10B when threshold switching selector 1109 is turned on. However, initially, threshold switching selector 1109 is turned on by switching on the threshold voltage V of threshold switching selector 1109. th The bias current or voltage must then be kept sufficiently higher than the holding current or voltage of the threshold switch selector 1109 so that it turns on during subsequent read or write operations.

[0091] In the second layer, MRAM elements 1112 include a free layer 1111, a tunnel barrier 1113, and a reference layer 1115 formed above a threshold switching selector 1119, with the series coupling of the MRAM elements 1112 and the threshold switching selector 1119 forming a layer 2 cell between a bit line 1110 and a word line 2 1120. The layer 2 cells operate as for the layer 1 cells, but the bottom conductor now corresponds to the bit line 1110 and the top conductor now is the word line, word line 2 1120. Additional pairs of layers may have a pattern of WL1, BL1, WL2, WL3, BL2, WL4 and similarly share another bit line between them, or have separate bit lines in the pattern WL1, BL1, WL2, BL2, etc.

[0092] In the embodiment of FIG. 11A , threshold switching selectors 1109 / 1119 are formed below MRAM elements 1102 / 1112, but in alternative embodiments, threshold switching selectors may be formed above MRAM elements in one or both layers. As discussed with respect to FIGS. 10A and 10B , MRAM memory cells are directional. In FIG. 11A , MRAM elements 1102 and 1112 have the same orientation, with free layers 1101 / 1111 above reference layers 1105 / 1115 (relative to the substrate, not shown). Forming layers between conductive lines with the same structure can have several advantages in terms of processing, particularly because each of the two layers, as well as subsequent layers in embodiments with more layers, can be formed according to the same process sequence.

[0093] Figure 11B shows an alternative embodiment arranged similarly to Figure 11A, except that in the layer 2 cell, the locations of the reference and free layers are reversed. More specifically, between word line 1 1150 and bit line 1160 as in Figure 11A, layer cell 1 includes an MRAM element 1 having a free layer 1151 formed on a tunnel barrier 1153, which is formed on a reference layer 1155, and an MRAM element 1152 formed on a threshold switch selector 1159. The second layer of the Figure 11B embodiment also includes an MRAM element 1162 formed on a threshold switch selector 1169 between bit line 1160 and word line 2 1170, but compared to Figure 11A, the MRAM element 1162 is inverted, now with the reference layer 1161 formed on the tunnel barrier 1163 and the free layer 1165 now formed below the tunnel barrier 1163. Alternatively, the configuration of MRAM cell 1162 may be used for layer 1 cells and the configuration of MRAM cell 1152 may be used for layer 2 cells.

[0094] While the embodiment of Figure 11B requires a different process sequence for forming the layers, it can have advantages in some embodiments. Specifically, the directionality of the MRAM structure can make the embodiment of Figure 11B attractive because when writing or reading in the same direction (with respect to the reference and free layers), the bit line is biased the same relative to both the bottom and top layers, and both word lines are biased the same. For example, if both the layer 1 and layer 2 memory cells are sensed in the P2AP direction (with respect to the reference and free layers), then the bit line layer 1160 is biased in the P2AP direction, etc., and the bit line 1160 is biased low (e.g., 0V) relative to both the top and bottom cells, and word line 1 1150 and word line 2 1170 are both biased to a higher voltage level. Similarly, for writing, to write to a high-resistance AP state, bit line 1160 is biased low (e.g., 0V) relative to both the top and bottom cells, and word line 1 1150 and word line 2 1170 are both biased to a higher voltage level; to write to a low-resistance P state, bit line 1160 is biased to a high voltage level, and word line 1 1150 and word line 2 1170 are both biased to a low voltage level. In contrast, in the embodiment of FIG. 11A, to perform either of these operations at the top level relative to the bottom level, the bit line and word line must reverse their bias levels. Note that in one embodiment of the forced current approach, the word line is biased to a target voltage by driving a current through the word line.

[0095] Reading or writing data from an MRAM memory cell involves passing a current through the memory cell. In embodiments where a threshold switching selector is placed in series with the MRAM element, the threshold switching selector must be turned on by applying sufficient voltage and current across the series combination of the threshold switching selector and MRAM element before current can be passed through the MRAM element.

[0096] 12 illustrates an embodiment of a memory array 502 having a cross-point architecture. The array 502 includes a set of first conductive lines 1206a-1206h and a set of second conductive lines 1208a-1208d. In one embodiment, the set of first conductive lines 1206a-1206h are word lines, and the set of second conductive lines 1208a-1208b are bit lines. For ease of explanation, the set of first conductive lines 1206a-1206h may be referred to as word lines, and the set of second conductive lines 1208a-1208b may be referred to as bit lines. However, the set of first conductive lines 1206a-1206h may also be bit lines, and the set of second conductive lines 1208a-1208b may also be word lines.

[0097] The array 502 includes several memory cells 701. Each memory cell 701 is connected between one of the first conductive lines 1206 and one of the second conductive lines 1208. Each memory cell 701 includes a magnetoresistive random access memory (MRAM) element 1202 in series with a threshold switching selector element 1204. Thus, each memory cell (bit) 701 may be referred to as an MRAM cell or bit. The threshold switching selector 1204 is configured to become conductive with a lower resistance in response to application of a voltage level above a threshold voltage of the threshold switching selector 1204, and remain conductive with a lower resistance until the current through the switching selector 1204 is reduced below a selector hold current Ihold. The threshold switching selector element 1204 is a two-terminal device. In an embodiment, the threshold switching selector element 1204 includes an OTS.

[0098] Each first conductive line 1206 can be driven by one of WL drivers 1210a-1210h. For example, first conductive line 1206a can be driven by WL driver 1210a, first conductive line 1206b can be driven by WL driver 1210b, etc. Each second conductive line 1208 can be driven by one of BL drivers 1212a-1212d. For example, second conductive line 1208a can be driven by BL driver 1212a, second conductive line 1208b can be driven by BL driver 1212b, etc. In one embodiment, word lines and bit lines are driven from one end of the word line or bit line. FIG. 12A shows such an embodiment in which word lines and bit lines are driven from one end. In an alternative embodiment, bit lines and / or word lines are driven from midpoints. Driving the wordline or bitline from a midpoint reduces the worst case IR drop.

[0099] Although a separate driver 1210 is shown connected to each word line 1206, it is not necessary to have a separate driver 1210 for each word line. In one embodiment, the same driver can be used to provide access current to any currently selected word line. This driver can be connected to the word line selected by a decoding circuit that selects the WL 1206 to be driven. The driver and decoding circuit can be connected to a "global node" (see global node VX in FIG. 20). However, the location of the WL drivers 1210a-1210h in FIG. 12A can still indicate the location (e.g., end) of the driven word line.

[0100] For the purposes of discussion, memory cell 701a is selected for access. This can be a read or write access. The selected memory cell 701a is at the cross point of the selected word line 1206g and the selected bit line 1208b. The other memory cells are not selected for access (i.e., are unselected memory cells). All other word lines and all other bit lines are unselected by forcing them to an unselected voltage of about half the drive reference voltage, e.g., about 1 / 2 of 3.3V, e.g., Vmid of 1.65V. To select memory cell 701, a select voltage (V select_BL ) is applied to drive (or force) an access current through a selected word line (e.g., word line 1206g). The access current may flow between portions of the selected word line, through selected memory cells, and through portions of selected bit lines. An unselected voltage (V unsel_BL In one embodiment, V select_BL has a magnitude such that the threshold switching selector 1204 in the selected memory cell is turned on, and is, for example, approximately V select_BL may be approximately 0V. unsel_BL has a magnitude such that the threshold switching selector 1204 in the unselected memory cells is not turned on, for example, V select_BL may be approximately 1.65V. The word line driver 1210g drives an access current (I access ) which may also flow through the selected memory cell 701a to a portion of the selected bit line 1208b. Such a selected WL may be driven high, for example, by 15 ua for a read or 30 ua for a write, by a current source with a nominal voltage of, for example, 3.3V.

[0101] The WL driver 1210 is configured to either source or sink a current. accesscan flow in either direction through the selected word line (and selected bit line). By convention used herein, when current driver 1210 is used as a current source, the magnitude of the access current is positive. By convention used herein, when current driver 1210 is used as a current sink, the magnitude of the access current is negative. Whether current driver 1210 sources or sinks current, this is referred to herein as forcing a current through the selected word line. In one embodiment, no current other than leakage is forced through unselected word lines (e.g., 1206a, 1206b, 1206c, 1206d, 1206e, 1206f, and 1206h). Note that, as used herein, a "selected word line" means that a current is forced through that word line at 15 ua when reading or 30 ua when writing, with a voltage reference of approximately 3.3 V for a 20 nm CD, for example, and that the word line is connected to a selected memory cell, which is further determined by being connected to a "selected" bit line at approximately 0 V. To write the opposite polarity, the selected word line is forced, for example, at -15 uA. The selected word line can also be connected to unselected memory cells if the other cell terminal is connected to an unselected bit line at Vmid, such as 1.65 V. An "unselected word line" means that the word line is connected only to unselected memory cells. In other words, all memory cells connected to an unselected word line are unselected memory cells, such as when an unselected WL is forced to conduct current at Vmid 1.65 V, or when an unselected BL is forced to conduct current at Vmid 1.65 V. As used herein, a "selected bit line" means that a bit line near 0 V, for example, when reading or writing P2AP, or near Vp (approximately 3.3 V), is connected to at least one selected memory cell. An "unselected bit line" means that the bit line is connected only to unselected memory cells.In other words, all memory cells connected to unselected bit lines are unselected memory cells. As mentioned above, a selected memory cell is a memory cell selected for access. A selected memory cell is connected between a selected word line and a selected bit line.

[0102] In one embodiment, the selected word line voltage is clamped to a voltage limit (voltage compliance) while driving an access current (current force) through a portion of the selected word line and through a portion of the selected bit line to the selected memory cell. In other words, the voltage can be clamped so that it is not allowed to exceed a certain magnitude. Clamping the selected word line voltage when using forced current read can result in a lower bit error rate while reducing stress on the memory cell.

[0103] In the example of FIG. 12, there are more word lines than bit lines in the cross-point array. In one embodiment, there are more bit lines than word lines in the cross-point array. In one embodiment, the number of bit lines is equal to the number of word lines in the cross-point array. In the example of FIG. 12, there are twice as many word lines as bit lines in the cross-point array, but different ratios can be used, allowing for different tile sizes. For example, a tile can have 1024 BLs by 2048 WLs, which can be configured into a module of 2048 by 4096 cells by centrally driving the WLs and BLs between four tiles.

[0104] In an embodiment of the mixed read scheme, a forced current technique is used to access memory cells in a cross-point memory array. The forced current technique helps automatically compensate for IR drops due to varying word line resistances and / or varying bit line resistances. A threshold switching selector may be used in series with the memory cell. The threshold switching selector is connected in series with the memory element between the word line and the bit line. Therefore, any voltage across the switching selector reduces the voltage across the memory element. Typically, there is some variation in offset voltage between the switching selectors. The forced current technique helps to mitigate the variation in offset voltage between the threshold switching selectors.

[0105] 13 is a flow chart of one embodiment of a process 1300 for mixed forced current reading. Process 1300 can be used on nonvolatile memory cells, each having a resistive random access memory element and a two-terminal selector element in series with the memory element. The nonvolatile memory cells may be in a cross-point array. In one embodiment, the memory cells are MRAM cells. In an embodiment, the selector is an OTS.

[0106] Step 1302 involves reading a group of memory cells using a forced current referenced read. In a forced current referenced read of a particular memory cell, a current is forced through the memory cell being read. The voltage that appears across the cell as a result of forcing current through the cell is sensed. This voltage is compared to a reference voltage. Note that step 1302 is performed for a group of memory cells that may be in different tiles of a memory array. Collectively, the memory cells may store an ECC codeword. Further details of one embodiment of a forced current referenced read are described below in connection with FIG. 16.

[0107] Step 1304 includes determining whether a condition is met for a forced current referenced read. In one embodiment, the condition is whether the data read from the memory cells was successfully decoded by an ECC engine. In an embodiment, the ECC engine is on the same semiconductor die as the memory cells, which facilitates a quick determination of whether the data was successfully decoded. Further details of an embodiment in which the condition is whether the data read from the memory cells was successfully decoded by an ECC engine are described below in conjunction with FIG. 14. In one embodiment, the condition is based on how many of the memory cells in a group have resistances that fall into the uncertainty zone. Further details of an embodiment in which the condition is based on how many memory cells in a group have resistances that fall into the uncertainty zone are described below in conjunction with FIG. 15A.

[0108] If the condition is not met, step 1306 is performed. Step 1306 includes returning data based on the forced current referenced read. In an embodiment, step 1306 is performed if the data read from the group is successfully decoded. Thus, step 1306 may include returning the successfully decoded data.

[0109] If the condition is met, step 1308 is performed. Step 1308 includes reading the group of memory cells using forced current SRR. Further details of one embodiment of forced current SRR are discussed below in connection with FIG. 17.

[0110] Step 1310 includes returning the data read using the forced current SRR. An ECC engine may be used to decode and correct the data read using the forced current SRR. Thus, the data returned in step 1310 may be the decoded and corrected data. Given that the forced current SRR may be substantially more accurate and error-free than a forced current referenced read before applying the ECC engine, the ECC engine should be able to successfully decode the data in almost all cases. In the very rare occasion that the data is not successfully decoded, an error message may be returned.

[0111] FIG. 14 is a flowchart of one embodiment of a process 1400 for a mixed forced current read in which an ECC engine is used. Process 1400 provides further details about one embodiment of process 1300. Step 1402 includes reading a group of memory cells using a forced current referenced read. Step 1402 is similar to step 1302 and will not be described in detail. Step 1404 is running an ECC algorithm on the data sensed using the forced current referenced read. Step 1406 is determining whether decoding is successful. If decoding passes, the decoded data is returned in step 1408. If decoding fails, the group of memory cells is read using a forced current SRR in step 1410. Step 1410 is similar to step 1308 and will not be described in detail. Step 1412 includes running an ECC algorithm on the data to decode and correct the data. Step 1414 includes returning the data read using the forced current SRR. As described above, the data may be decoded and corrected by an ECC engine.

[0112] As an alternative to step 1404, in one embodiment, the ECC engine is used to determine or estimate the number of bit errors in the codeword before decoding it. In an embodiment, the ECC engine 569 calculates a syndrome for the codeword to estimate the number of bit errors in the codeword. In an embodiment, the syndrome is based on the number of unsatisfied parity check equations. In an embodiment, the ECC engine 569 can decode the codeword if the number of erroneous bits in the codeword is less than or equal to a certain number. In step 1406, a decision is made as to whether to attempt to decode the codeword or proceed to step 1410. This decision may be based on whether successful decoding of the codeword is likely. For example, if the estimate of the number of bit errors in the codeword is less than or equal to the number of bits that can be corrected by the ECC engine 569, the codeword is decoded and corrected. If the estimate of the number of bit errors in the codeword is greater than the number of correctable bits, a forced current SRR is performed, and the resulting read data may then be decoded, corrected, and returned.

[0113] 15A is a flow chart of one embodiment of a process 1500 for a mixed forced current read in which memory cells are tested for whether they are within the uncertainty zone. Process 1500 provides further details for one embodiment of process 1300. Step 1502 includes reading a group of memory cells using a forced current referenced read. Step 1502 is similar to step 1302 and will not be described in detail.

[0114] Step 1504 is determining how many memory cells have a resistance within the uncertainty zone. FIG. 15B shows two resistance distributions of memory cells with an uncertainty zone between them. FIG. 15B shows a low resistance distribution 1540 and a high resistance distribution 1542. In an embodiment, distribution 1540 corresponds to memory cells programmed to a 0, and distribution 1542 corresponds to memory cells programmed to a 1. Memory cells with a resistance less than R_demarcation are considered to store a "1." Memory cells with a resistance greater than R_demarcation are considered to store a "0." While FIG. 15B shows a clear gap between the two distributions, in reality, some memory cells may have a resistance within the uncertainty zone. FIG. 15C illustrates the concept of an uncertainty zone, but the horizontal axis is the voltage sensed across the memory cell when reading the cell, as opposed to the cell's resistance. Thus, there is a lower voltage distribution 1550 and an upper voltage distribution 1552. In a forced current read embodiment, a higher sensed voltage corresponds to a higher cell resistance. Memory cells sensed at a voltage below V_demarcation are considered to store a "1." Memory cells sensed at a voltage above V_demarcation are considered to store a "0." The voltage Vref_low corresponds to R1, and the voltage Vref_hi corresponds to R2. Thus, in one embodiment, to determine how many memory cells have a resistance within the uncertainty zone, the system determines how many memory cells have a sensed voltage between Vref_low and Vref_high. Such sensed voltages may vary with, for example, variations in position along the CD or word or bit lines of the MRAM.

[0115] 15D shows a circuit that can be used to determine whether a memory cell is in the uncertainty zone. This circuit includes a first sense amplifier 1562, a second sense amplifier 1564, and XOR logic 1566. The first sense amplifier 1562 inputs Vref_hi, which is compared to Vrd (the voltage sampled from the memory cell). The second sense amplifier 1562 inputs Vref_low, which is also compared to Vrd. The output of each respective sense amplifier is input to XOR logic 1566. If the output of XOR logic 1566 is true (e.g., "1"), this indicates that the memory cell falls within the uncertainty zone.

[0116] Returning again to FIG. 15A , step 1506 involves determining whether the number of memory cells is greater than a permitted number. In an embodiment, the permitted number is predetermined. In one embodiment, the permitted number corresponds to the number of bits that can be corrected by the ECC engine 569. For example, the ECC engine may be capable of correcting up to 9 bit errors in a codeword. If the number is less than or equal to the permitted number, step 1508 is executed. Step 1508 involves using the ECC engine to decode the data and return the decoded and corrected data. Note that step 1508 can be executed even if some memory cells are within the uncertainty zone, as long as the number is within the permitted number. This allows process 1500 to be completed based on a forced current referenced read without having to perform a forced current SRR, which has added latency. Thus, significant time and power are saved. Note also that in some very high rate cases, the decoding of the data in step 1508 may fail, in which case the process may proceed to step 1510.

[0117] If the number from step 1504 is greater than the allowed number, step 1510 is performed. Step 1510 is to read the group of memory cells using the forced current SRR. Step 1512 is to return the (decoded and corrected) data from the forced current SRR. Steps 1510 and 1512 may be similar to steps 1308 and 1310, respectively.

[0118] FIG. 16 is a flow chart illustrating one embodiment of a process 1600 for forced current referenced reading. Process 1600 can be used in steps 1302, 1402, or 1502. Process 1600 describes reading one memory cell. The process may be performed in parallel on different memory cells within a group. The group may store an ECC codeword. Step 1602 includes applying a select voltage to a selected second conductive line. Referring to FIG. 12A, Vselect is provided to the selected bit line 1208b. An unselected voltage is provided to the unselected bit lines.

[0119] Step 1604 includes driving a read current to the selected word line to force a read current through the selected memory cell. access is driven onto the selected word line 1206g. No access current is provided to unselected word lines. The access current may flow through a portion of the selected word line, through the selected memory cell, and through a portion of the selected bit line. In particular, the access current may flow through the portion of the selected word line from where the word line is driven (by a current driver) to the selected memory cell. Also, the access current may flow through the portion of the selected bit line from where the selected memory cell is driven by a voltage driver to where the bit line is driven.

[0120] Step 1606 includes sensing the voltage generated by the selected memory cell. In an embodiment, the voltage between the selected word line and the selected bit line of the selected bit is sensed directly or on a global node that includes a driver circuit. The sensed voltage is between ground and a current source that drives current into the array decoding circuitry.

[0121] Step 1608 includes comparing the sensed voltage to a reference voltage to determine the state of the memory cell. The reference voltage may be, for example, V_demarcation shown in FIG. 15C. The magnitude of the reference voltage is independent of the physical state (e.g., resistance) of the memory cell. A common reference voltage may be used for different memory cells in the array. However, in some embodiments, the magnitude of the reference voltage may be based on factors such as the location of the memory cell in the array. Thus, the reference voltage need not have the same magnitude for all memory cells in the array.

[0122] FIG. 17 is a flowchart illustrating one embodiment of a process 1700 for forced current SRR. SRR may also be referred to as destructive SRR, meaning that the original state of the memory cell may be altered during SRR. Process 1700 may be used in steps 1308, 1410, or 1510. Process 1700 describes reading a single memory cell and may be performed in parallel for memory cells in a codeword group (which may be in different tiles or groups of tiles). In one embodiment, process 1700 is performed by control circuitry within memory die 292. In one embodiment, process 1700 is performed by control circuitry within control die 590. In one embodiment, process 1700 is performed by control circuitry within host 122 (e.g., host processor 122). Process 1700 is described with reference to FIGS. 18A and 18B. FIG. 18A illustrates current versus time for an access current driven through a selected word line during a forced current embodiment. FIG. 18B illustrates voltage versus time for the voltage across a selected MRAM cell during a forced current embodiment.

[0123] Step 1702 includes driving a first read current through a selected word line to drive a first access current through a selected MRAM cell while applying a select voltage to a selected bit line. Referring to FIG. 12, I is driven by a current driver 1210g through a selected first conductive line 1206g. access is driven, for example, using a current of 15 uA, through memory cell 701a. access Referring to FIG. 12, a voltage driver 1212b drives V select_BL In one embodiment, for example, I access is 15μA, and V select_BL is 0V. In another embodiment, for a 20 nm CD MRAM with RA10, which may have a low resistance state of about 25K ohms and a high resistance state of about 50K ohms, the current is −15 ua and V select_BL is 3.3V.

[0124] 18A and 18B will now be described with respect to one MRAM cell 701 to further detail step 1702. Referring to FIG. 18A, the current I read and increases to t3. read 18B, the voltage across memory cell 701 increases from t1 to t2. Threshold selector 1204 is off between t1 and t2. Between t1 and t2, a current flows through the word line voltage. This current also supports any leakage in the path. Once the voltage across threshold selector 1204 reaches the threshold voltage V of threshold selector 1204, th , the switching threshold selector turns on and switches to a low resistance state (at t2). Thus, the voltage across the series combination of the switching threshold selector 1204 and the resistive MRAM element 1202 rises when the switching threshold selector is in the off state.

[0125] When the threshold switching selector 1204 is turned on (at t2), I readA current flows through the selected memory cell 701a. The access current is I read When held fixed at 1000 ohms, the voltage across the memory cell drops to a level that depends on the series resistance of the MRAM element 1202 and the on-state resistance of the threshold switching selector 1204. In a binary embodiment where the memory cell stores only two states, the memory cell has a high resistance AP state, e.g., 50K ohms, and a low resistance P state, e.g., 25K ohms. The I for the high resistance state (HRS) and low resistance state (LRS) are read The resulting voltages across the series-connected MRAM elements 1202 and threshold switching selector 1204 in response to the current are shown as lines 1810 and 1812, respectively. While the description herein relates to an MRAM-based memory cell arranged in series with a threshold switching selector, the read technique is equally applicable to other programmable resistive memory cells, such as PCM or ReRAM devices.

[0126] 17, step 1704 includes sensing the voltage across the selected memory cell. Step 1704 may also include storing the sensed voltage, for example, on a capacitor. Step 1705 includes adjusting the stored voltage by adding (Deck 1) or subtracting (Deck 2) a 150 mV voltage.

[0127] Step 1706 includes driving a write current through the selected word line to drive a write current through the selected MRAM cell while applying a select voltage to the selected bit line. Referring to FIG. 12, I is driven by a current driver 1210g through a selected first conductive line 1206g. access is driven and I access Referring to FIG. 12, a voltage driver 1212b applies V to the second conductive line 1208b. select_BL In one embodiment, I for writing access is 30μA, and V select_BL is 0V. In another embodiment, I accessis -30μA, and V select_BL is 3.3V

[0128] 18A and 18B will now be described with respect to one MRAM cell 701 to further detail step 1706. Referring to FIG. 18A, the access current is I write Increases to t5. write 18B, at t3, the voltage across MRAM cell 701 increases. If MRAM cell 701 was in HRS (line 1810), the voltage across the MRAM cell rises to the level shown by line 1820 at t3 and remains there until t5. Recall that HRS is the AP state. Therefore, this MRAM cell remains in the AP state.

[0129] If MRAM cell 701 was in the LRS (line 1812), the voltage across the MRAM cell rises to the level shown by line 1822 at t3. Recall that LRS is the P state. If MRAM cell 701 was in the P state, it switches to the AP state. Figure 18B shows that line 1822 rises and intersects with line 1820 at t4. This represents the MRAM cell switching from the P state (LRS) to the AP state (HRS).

[0130] 17, step 1708 includes driving a second read current through the selected word line while applying a select voltage to the selected bit line to force a second access current through the selected MRAM cell. In one embodiment, the second access current has the same direction and substantially the same magnitude as the first access current. Referring back to FIG. 12, I is driven by current driver 1210g through the selected first conductive line 1206g. access is driven and I access Referring to FIG. 12, a voltage driver 1212b applies V to the second conductive line 1208b. select In one embodiment, I access is 15μA, and Vselect is 0V.

[0131] 18A and 18B will now be described with respect to one MRAM cell 701 to further detail step 1708. Referring to FIG. 18A, the access current is I write From I read until t6. read 18B, the voltage across memory cell 701 is reduced to a level indicated by 1830 at t5 and held at that level until t6. Note that line 1830 is the HRS level. Recall also that regardless of the initial state of the MRAM cell, the MRAM cell was placed in the HRS state (AP state) in step 1708.

[0132] 17, step 1710 includes sensing the voltage across the selected memory cell. Step 1710 also includes comparing the voltage sensed in step 1710 to the voltage stored in step 1704.

[0133] Step 1712 includes determining a pre-read state of the selected MRAM cell based on a comparison of the stored voltage from driving a first read current through the selected memory cell and the voltage from forcing a second read current through the selected memory cell. After step 1712, the data from each memory cell in the group being read may be provided to an ECC engine, and the ECC engine may begin decoding the data. In some embodiments, the ECC engine 569 is on the same semiconductor die as the memory cells, which provides faster decoding by reducing data transfer time.

[0134] 18A and 18B will now be described with respect to one MRAM cell 701 to further detail step 1712. The first voltage on the selected word line after applying the first read current will be a voltage between t2 and t3. Therefore, the first voltage is either the HRS level 1810 or the LRS level 1812. This first voltage may be stored in step 1704, for example, by charging a sense capacitor using the word line voltage. The second voltage on the selected word line after applying the second read current will be a voltage between t5 and t6. This second voltage is typically about the HRS level 1810. However, the second voltage may be slightly different from the HRS level 1810. Therefore, comparing the first voltage to the second voltage can be used to determine whether the MRAM cell was at the HRS level 1810 or the LRS level 1812 between t2 and t3. For ease of comparison, the level produced by the Read 1 current to the AP state may be stored and bumped positive by approximately half the voltage difference between the HRS and LRS, e.g., 150 mV. Alternatively, if the Read 1 current is in the P state, the level may be bumped negative. These choices may be reversed depending on the orientation of the MRAM cell, as will be apparent to those skilled in the art.

[0135] Returning again to FIG. 17 , after step 1712, a determination is made whether a writeback is required (step 1714). As described above, process 1700 is a destructive SRR in which the original state of the memory cells may be lost during step 1706. Writeback is used to restore the original state of the memory cells, if necessary. Thus, step 1716 is performed if a writeback is required. Step 1716 includes driving a write current through the selected word line to write back the original state of the memory cells, if necessary. Recall that step 1706 placed all MRAM cells in the AP state. Thus, in step 1716, all MRAM cells that were originally in the P state are written back to the P state. All MRAM cells that were originally in the AP state remain in the AP state in step 1716. Note that, as described above, the ECC engine can begin decoding and correcting data in step 1712. Thus, data can be decoded, corrected, and provided to the requestor before the writeback is terminated in step 1716.

[0136] In some embodiments, the forced current SRR is shortened by saving the value from the forced current referenced readout and using this value, thereby eliminating the need for the first readout in the forced current SRR. Figure 19 is a flow chart illustrating one embodiment of a process 1900 in which the value from the forced current referenced readout is saved and used in the forced current SRR. Step 1902 includes saving the value from the forced current referenced readout. In one embodiment, the voltage is stored on a capacitor. Process 1902 may be performed in step 1502 of Figure 15.

[0137] Step 1904 includes changing the stored voltage by, for example, 150 mV. Note, however, that the first read of the forced current SRR can be skipped. With reference to process 1700 of FIG. 17, steps 1702 and 1704 can be skipped. Step 1906 includes writing the MRAM cell to a known state. With reference to process 1700 of FIG. 17, step 1706 can be performed. Step 1908 includes a forced current read of the MRAM cell. With reference to process 1700 of FIG. 17, steps 1708 and 1710 can be performed. Step 1910 includes determining the pre-read state of the MRAM cell based on a comparison of the stored voltage (from the current forced reference read) and the voltage from the forced current read in the SRR (e.g., the sampled voltage from step 1908). Thus, process 1900 saves time and / or power by mitigating the need for an initial read in the SRR.

[0138] FIG. 20 is a block diagram of components for driving current into a word line to force a current through a memory cell. A current source generator 2010 generates and outputs a current control signal that is provided to a current source 2020. In one embodiment, the current control signal is a precision voltage. The current source 2020 outputs a constant magnitude current in response to the current control signal. The current source 2020 can be used to generate a read current or a write current, which can be referred to as an access current. The access current is provided to a selected word line by a row decode and drive circuit 2040. The row decode and drive circuit 2040 inputs a WL address and provides the access current to the selected word line. A state machine 562 can provide the WL address to the row decode and drive circuit 2040. In one embodiment, there are separate current sources 2020 for generating the read current and the write current, and selection logic selects the appropriate current source for the memory operation. In one embodiment, there is a first current source for generating a positive write current and a second current source for generating a negative write current. Not shown in FIG. 20 are bit line drivers that can provide a select voltage to a selected bit line. An access current can flow through a portion of a selected word line, through a selected memory cell, and through a portion of a selected bit line. In one embodiment, the voltage at node VX is clamped to not exceed a certain magnitude. Clamping the voltage at node VX clamps the voltage on the word line, which reduces stress on memory cells (e.g., MRAM cells) while maintaining a low bit error rate by selecting a clamp voltage that is high enough not to reduce read margins, but low enough to reduce stress on some of the smaller CD MRAM bits.

[0139] 21 is a schematic diagram of one embodiment of a current source generator 2010. The current source generator 2010 outputs a voltage Read_1G (between transistors 2120 and 2130) that is provided to a current source 2020. In some embodiments, Read_1G may be provided to multiple types of current sources, such as a read current source, a positive current write source, and a negative current write source.

[0140] The gates of transistors 2130 and 2122 are provided with voltages by resistors 2112 and 2114, respectively. These resistor voltages are generated by a left-hand circuit including current source 2102, transistor 2104, transistor 2106, transistor 2108, and transistor 2110, and capacitors 2116 and 2118. Current source 2102 may be approximately 5 microamps. The right-hand circuit includes transistors 2120, 2130, 2122, 2124, 2126, and 2128. In some embodiments, the left-hand circuit is used for the entire bank, and a different version of the right-hand circuit is used for each tile. Current source 2102, e.g., 5 uA, may generate a voltage of approximately 2 Vt above ground on the drain of transistor 2104 that is distributed to the tile. V_PA to the gate of transistor 2110 may be high (e.g., V_P) to activate the circuit, or may open the circuit when the gate of transistor 2110 is grounded so that current is eliminated when the circuit is not in use. The gate of transistor 2104 is distributed across the tiles, and by driving only the transistor gate and not the source or drain, the drop across the tiles is eliminated, allowing the currents across the tiles to be relatively the same. Two distributed voltages, approximately 1.5V and 0V, are then connected to the right generator in each tile. That is, the gate of transistor 2130 is approximately 1.5V, and the gate of transistor 2122 is approximately 0V. These mirror circuits can then be turned on by either Step1T, Read1T, or Read1T_NX going high on V_P. As a result, the current of current source 2102 is driven into the drain of transistor 2120, and the gate of transistor 2120 will be at V_P-Vt, or approximately 2.5V if V_P is 3.3V.

[0141] One challenge of a mixed forced current read scheme is the interface timing between the memory device and the requestor of data, such as a memory controller. For example, a forced current SRR may take longer than a forced current referenced read, so from the perspective of the memory controller, data may be returned in a non-deterministic time after the memory controller issues a read request. In embodiments, data is returned to the memory controller in a deterministic time after the memory controller issues a read request, regardless of whether a forced current referenced read or a forced current SRR is used to read the data. Furthermore, memory protocols such as the DDR protocol have very strict timing. Therefore, having a mixed forced current read scheme for MRAM that operates within the DDR protocol is a challenge and is not very effective at reducing latency.

[0142] 22 is a flowchart of an embodiment of a process 2200 for deterministic return time when using a mixed forced current read scheme. Process 2200 involves a communication interface between a memory controller and a memory device. In one embodiment, the communication interface is a DDR interface. Step 2202 includes the memory controller issuing a read request to the memory device. In one embodiment, the memory controller 102 issues the read request to the local memory 106. In one embodiment, the memory controller 102 issues the read request to the memory package 104. In one embodiment, the host processor 122 issues the read request to the host memory 124.

[0143] Step 2204 includes the memory device performing a forced current referenced read (CFRR). In one embodiment, process 1600 is performed. Step 2206 includes determining whether the CFRR was successful. In one embodiment, in step 2206, an ECC algorithm is performed on the data. In one embodiment, the CFRR is successful if the data is successfully decoded and corrected. If the CFRR is successful, the memory device returns the corrected data to the memory controller in step 2208. In step 2210, the memory device indicates to the memory controller that there is no need to retry the read command.

[0144] If the CFRR is not successful, then in step 2212, the memory device indicates to the memory controller that a read retry is required. In one embodiment, the memory device sends a signal having a value of either 0 or 1. The signal may be sent on a communication line between the memory device and the memory controller. In one embodiment, a new communication line (or pin) is added to the interface (e.g., a DDR interface). However, no new line needs to be added, as existing lines can be used for the retry signal. Further details are described in conjunction with Figures 23 and 24. In one embodiment, the memory device sends a cyclic redundancy check (CRC) that is the opposite of what the CRC should be to signal a retry. Further details are described in conjunction with Figure 25.

[0145] In step 2214, the memory device performs a forced current SRR to read data from the group of memory cells. In one embodiment, process 1700 is performed. In one embodiment, some steps of process 1700 (e.g., steps 1702, 1704, 1706) may be skipped due to the read performed in step 2204. In other words, the voltage from the read in step 2204 may be preserved, as described in process 1900.

[0146] In step 2216, the memory controller waits a predetermined amount of time after receiving the indication that a read retry is required and then reissues the read request. The predetermined amount of time is based on how long it takes the memory device to perform the force current SRR. In one embodiment, the memory device informs the memory controller how long the predetermined amount of time should be. This can be done once, as the predetermined amount can be fixed.

[0147] In step 2218, the memory device returns the data to the memory controller, i.e., the memory device decodes the data from the forced current SRR and returns the decoded data to the memory controller.

[0148] In step 2220, the memory device indicates to the memory controller that no read retry is required.

[0149] 23 and 24 show interface timing diagrams for an embodiment of a mixed forced current read. FIG. 23 illustrates the case where only a forced current referenced read is required. FIG. 24 illustrates the case where the memory device performs both forced current referenced and forced current SRR. In FIG. 23, data is available after the first read request, while in FIG. 24, data is available only after the second read request is issued. However, in each case, data is returned to the memory controller within tRL, the time it takes for the memory device to successfully respond to the read request. Thus, the time to return data is deterministic. The various commands (activate, read, PRE) may be DDR commands. Similarly, the various timings (tRCD, tRTP, tRP, tRL) may be DDR timings. The actual values ​​of the various timings (tRCD, tRTP, tRP, tRL) depend on the protocol in use. FIGS. 23 and 24 provide further details about an embodiment of process 2200.

[0150] Referring now to FIG. 23, the memory controller issues an activate command to the memory device. As described above, this may be a DDR activate command. Next, the memory controller issues a read command to the memory device. This may be a DDR read command. The timing tRCD (Row Column Delay) refers to the delay from the row address to the column address. Following the read command, the memory controller issues a PRE command to the memory device. The PRE command refers to a "precharge command," which may be used in RAMs such as DDR. The timing tRTP refers to the delay between the read command and the PRE command. The timing tRL is the read command latency (or data output delay) and is widely used in RAMs such as DDR. In other words, tRL is the time from the read command to the data being provided by the memory device. Importantly, in FIG. 23, the memory device provides data to the memory controller within tRL from the time the read command is received. The memory device also indicates to the memory controller that it does not need to retry the read command by sending a value (e.g., 0) on the retry line. The retry line may be any communication line between the memory device and the memory controller that is not currently in use. The retry signal is used in one embodiment of step 2210 of Figure 22. In an alternative embodiment, the retry is encoded into a CRC that is appended to the data.

[0151] Referring now to FIG. 24, the memory controller issues an activate command and a read command in a manner similar to that described in connection with FIG. 23. However, in this example, the memory device does not return valid data. This corresponds to a forced current referenced read failure. The memory device sends a "1" on the retry line to indicate to the memory controller that the read command should be retried. The PRE after the first read command is depicted in a dashed box to indicate that a PRE command does not need to be issued by the memory controller. The memory controller waits a predetermined time (tDelay) after receiving the retry signal to reissue the read command. Note that the activate command does not need to be reissued.

[0152] However, it should be noted that the memory device may initiate the forced current SRR as soon as it determines that the forced current referenced read was not successful. Therefore, the memory device does not need to wait for the memory controller to reissue the read command. Importantly, the memory device returns data to the memory controller within tRL from the time the memory controller reissued the read command. Therefore, for both the read command of FIG. 23 and the reissued read command of FIG. 24, the memory device returns data within tRL. Therefore, the time to return valid data is deterministic, significantly simplifying the logic of the memory controller. Therefore, embodiments of the mixed forced current read of MRAM may be integrated with a DDR controller. In other words, embodiments of the mixed forced current read of MRAM may be integrated with a DDR protocol. Finally, it should be noted that after the reissued read command, the memory controller may proceed with the next read command in a manner similar to the example of FIG. 23.

[0153] FIG. 25 is a flowchart of one embodiment of a process 2500 for communicating that a read retry should be performed in a mixed forced current read scheme. This process is an alternative to sending a retry signal (e.g., a 1 or 0) as shown in FIGS. 23 and 24. Process 2500 begins in response to the memory controller determining that the forced current referenced read failed. Step 2502 includes the memory device calculating a cyclic redundancy check (CRC) on the data pattern, which can be any data pattern. Step 2504 includes the memory controller inverting the CRC. Inverting the CRC means changing every 1 to a 0 and every 0 to a 1. Step 2506 includes the memory device sending the data pattern and the inverted CRC to the memory controller. In one embodiment, the timing diagram of FIG. 24 is modified following the first read by having the memory device send the data pattern on the DQ lines and the inverted CRC instead of a retry signal of 1.

[0154] Step 2508 includes the memory controller calculating a CRC for the received data pattern. Step 2510 includes the memory controller comparing the calculated CRC with the CRC received from the memory device. The memory controller determines that the calculated CRC is inverted from the received CRC. Accordingly, step 2512 includes the memory controller determining that the read command should be reissued.

[0155] The embodiments presented above for MRAM memory presented a mixed read scheme with faster, less accurate reads (reference-based reads) and slower, more accurate reads (self-referenced reads). The following presents embodiments of a memory controller that can provide timing accuracy in a mixed read scheme using fewer resources for MRAM as well as other memory types (e.g., ReRAM, FeRAM, RRAM, or PCM) that have multiple read modes with different latencies.

[0156] By way of background, Figure 26 shows command and read data waveforms for a device such as a DDR (Dual Data Rate) memory that supports only a single read type. At the top, Figure 26 shows read commands (here, read commands Rd0, Rd1, ...) as issued by a memory controller to one or more memory banks or arrays. While these commands may be issued to a single bank or array of memory cells, these commands are typically distributed across multiple arrays that can be accessed independently; thus, one array can execute one command in a sequence, and the controller issues the next command to another array. In memory products such as DDR memory that support only a single read type, all read data is returned to the controller after the same Read_Latency after issuing the command. Under this configuration, the read data appears back to the memory controller in the same order in which the read commands were issued (i.e., the read data is in order).

[0157] FIG. 27 is a block diagram of some of the typical hardware for implementing a single read-type architecture. With respect to the memory controller, FIG. 27 includes a command scheduler 2701 and a media interface 2703. The memory medium 2707 can be one or more banks or arrays of DRAM memory or non-volatile memory such as MRAM or PCM. The command scheduler 2701 maintains a queue of N read commands (READ CMD 0, ..., READ CMD N-1) that are issued sequentially to the media interface 2703, which then issues them along with addresses to the memory medium 2707 (for purposes of this discussion). The top waveform of FIG. 26 illustrates the sequence of such commands to one or more banks of the memory medium 2707. In the media interface 2703, as read commands are input, they are also input into an in-flight command read FIFO 2705. After reading the data specified by the command from the memory medium 2707, the read data is received at the controller's media interface 2703 after a read latency, as shown in the bottom waveform of FIG. 26. The read data from the memory media is then associated with a corresponding read command from the in-flight read command FIFO 2705 to provide the read data of the read command to the memory controller. In current state-of-the-art memory products (such as single read type DRAM) with timing as shown in Figure 26, the read data is in sequence with the issued read command.

[0158] Figure 28 is an embodiment of a workflow for issuing a read command to the architecture of Figure 27. In step 2801, command scheduler 2701 selects a read command that meets timing requirements, and the command is issued to memory media 2707 along with an address in step 2803. Once the read command is issued, in step 2805 the read command is pushed into in-flight read command FIFO 2705.

[0159] Figure 29 is an embodiment of a workflow for processing read data for the architecture of Figure 27. When read data is received, the memory controller needs to get the read data's corresponding read command. Step 2901 gets the read command at the head of the in-flight read command FIFO 2705, and in step 2903 the head entry is popped from the in-flight read command FIFO 2705. In step 2905, the read data is returned along with the associated read command.

[0160] FIG. 30 illustrates the need to support mixed read types for embodiments such as MRAM having both higher and lower latency reads. FIG. 30 is laid out similarly to FIG. 26, but illustrates a fast read (i.e., shorter latency, typically lower accuracy) followed by a slow read (i.e., longer latency, typically higher accuracy). As discussed above, mixed read MRAM embodiments use two different read types (i.e., fast reference read and slow self-reference read) to improve memory performance, reliability, and cost. As shown in FIG. 30, the fast read command and the slow read command have different read latencies (i.e., Fast_Read_Latency and Slow_Read_Latency, respectively). If different read types with different latencies exist, this can lead to timing conflicts, as illustrated with respect to FIG. 31.

[0161] FIG. 31 illustrates a data output conflict that can occur with multiple read types with different timing. In FIG. 31, a slow read latency command is issued some time before issuing a fast read latency read command; in this example, these two commands are offset by an amount such that the ends of the latency periods align. As shown in FIG. 31, both the slow read command and the fast read command expect data to return from the memory bank in the same cycle, resulting in a timing conflict error. Without extra support in the memory controller, a conflict case occurs on the read data bus. The following embodiments address this issue. FIGS. 32-34 further consider this issue.

[0162] Figure 32 shows how issuing a fast read after a slow read can cause a data output timing conflict. In Figure 32 and other similar command / read data diagrams, an example value of two cycles is used for the read command, and the time for the read data to return, i.e., t_Data_Burst, is four cycles. The top pair of command / read data waveforms shows the case where a slow read command is issued before a fast read command, and the time is not long enough to avoid a data timing conflict. When a slow read is issued, the slow read data arrives on the read data bus after the Slow_Read_Latency time and lasts for the duration of t_Data_Burst. Similarly, after issuing a slow read, the fast read data arrives on the read data bus after the Fast_Read_Latency time and lasts for the duration of t_Data_Burst. If the fast read command is issued more than (Slow_Read_Latency-Fast_Read_Latency+t_Data_Burst) cycles later, there is no conflict and the slow read data arrives before the fast read data; however, if it is issued earlier, such as (Slow_Read_Latency-Fast_Read_Latency+t_Data_Burst-1) cycles as shown, there is a conflict when the data reads overlap, a 1 cycle conflict (in this example).

[0163] The bottom pair of command / read data waveforms in Figure 32 illustrates the case where a slow read command is again issued before a fast read command, but is issued earlier than the top pair of command / read data waveforms, with a time that is not short enough to avoid data timing conflicts. After issuing a slow read, the slow read data arrives on the read data bus after the Slow_Read_Latency time and lasts for the duration of t_Data_Burst. Similarly, after issuing a slow read, the fast read data arrives on the read data bus after the Fast_Read_Latency time and lasts for the duration of t_Data_Burst. In the timing situation of the bottom pair of command / read data waveforms in Figure 32, the slow read command is followed shortly and early enough by the fast read command so that the fast read data starts arriving first. If the fast read command is issued less than or equal to (Slow_Read_Latency-Fast_Read_Latency-t_Data_Burst) cycles later, there is no conflict, but the data for the later issued fast read command will appear out of order before the slow read data. However, if it is issued later, such as the (Slow_Read_Latency-Fast_Read_Latency-t_Data_Burst+1) cycles shown, there will be a conflict when the data reads overlap, resulting in a one cycle conflict (in this example).

[0164] As a result, as can be seen in FIG. 32, there is a Fast_Read_Conflict_Range 3201 with a number of cycles given by: After a slow read command is issued, [Earliest_Fast_Read_Conflict_Cycle,Latest_Fast_Read_Conflict_Cycle] As shown in Figure 32, Earliest_Fast_Read_Conflict_Cycle= Slow_Read_Latency-Fast_Read_Latency-t_Data_burst+1 and Latest_Fast_Read_Conflict_Cycle= Slow_Read_Latency-Fast_Read_Latency+t_Data_burst-1.

[0165] This range covers (Latest_Fast_Read_Conflict_Cycle-Earliest_Fast_Read_Conflict_Cycle+1) cycles and can be labeled as Fast_Read_Conflict_Cycles. Fast_Read_Conflict_Cycles= Latest_Fast_Read_Conflict_Cycle-Earliest_Fast_Read_Conflict_Cycle+1= 2 * t_Data_burst-1.

[0166] FIG. 33 considers the number of cycles that should be tracked after issuing a slow read to avoid such conflicts.

[0167] Figure 33 repeats the elements of Figure 32, but now is marked to indicate the number of conflict cycles to be tracked. With respect to Figure 32, Fast_Read_Conflict_Range 3201 has been removed and the number of cycles in Conflict_Tracking_Cycles 3301 has been included. As shown in the figure and described above, the number of Conflict_Tracking_Cycles 3301 needed to keep track of to avoid the latest possible data conflict is Conflict_Tracking_Cycles = (Slow_Read_Latency - Fast_Read_Latency + t_Data_burst).

[0168] FIG. 34 considers the order of read data when a slow read is issued before a fast read. As discussed above with respect to the command / read data pair at the bottom of the waveform in FIG. 32, if a fast read immediately follows a slow read, the fast read data may begin to arrive before the slow read data. Regarding determining when the read order of fast and slow reads is determined, as shown in FIG. 34, when a fast read command is issued after Fast_Read_Conflict_Range 3401, the fast read data comes after the slow read data in the same order as the issued command. As a result, when a slow read enters Fast_Read_Conflict_Range 3401, the newly issued fast read command will not have data that appears before the slow read data. As a result, any cycle within Fast_Read_Conflict_Range 3401 can be considered a data ordering point for the slow read.

[0169] Figures 35A and 35B show embodiments of a circuit architecture that supports mixed reads. Similar to Figure 27, Figure 35A also includes a memory controller command scheduler 3501 and a media interface 3503 connected to a memory media 3507 via a bus structure. With reference to Figure 27, the command scheduler 3501 now needs to maintain separate queues for fast read commands and slow read commands and track the timing of these two groups of read commands. The command scheduler 3501 also receives a fast read enable input control signal from the media interface 3503 that indicates whether a fast read can be issued in the current clock cycle. In addition to the in-flight read command FIFO 3505, the media interface 3503 also includes a pre-ordering slow read command FIFO 3513, whose data output order to the in-flight read command FIFO 3505 has not yet been finally determined. Here, the media interface 3503 also includes a mixed read coordinator 3511, which is updated via issued read commands. When read commands are received at the mixed read coordinator, slow read commands are sent to the pre-ordering slow read command FIFO 3513 and fast read commands are sent directly to the in-flight read command FIFO 3505. The mixed read coordinator 3511 also generates fast read enable signals for the command scheduler 3501 and controls the push / pop operations of the pre-ordering slow read command FIFO 3513 and the push operation of the in-flight read command FIFO 3505. Figure 35B provides further details regarding the mixed read coordinator 3511.

[0170] Figure 35B presents the in-flight read command FIFO 3505 and pre-ordered slow read command FIFO 3513 of interface 3503, along with further details regarding an embodiment of mixed read coordinator 3511. Issued read commands are demultiplexed in MUX 3519 as issued slow read commands, which go to pre-ordered slow read command FIFO 3513, and as issued fast read commands, which go to in-flight read command FIFO 3505. The issued slow read commands are then connected to a conflict tracking register 3515 and pre-ordered slow read command FIFO 3513. The conflict tracking register 3515 maintains a Conflict_Tracking_Cycles bit set. The last Fast_Read_Conflict_Cycles bit of the conflict tracking register 3515 is a conflict check bit, which is connected to NOR gate 3517 to generate the fast read enable signal. The conflict tracking register 3515 has a slow read insertion point bit. In the exemplary embodiment implementation, the slow read insertion point is bit ([0]). The conflict tracking register 3515 also has a slow read ordering point bit, which can be any bit of the conflict check bits. The slow read ordering point bit is connected to the pre-ordered slow read command FIFO 3513 as a FIFO pop enable signal. In some embodiments, the size of the conflict tracking register 3515 and the number of its bits that are conflict check bits that serve as input to the NOR gate 3517 may be configurable to account for different latency and t_Data_Burst values. The embodiments described herein are for read commands with two different latency values, but can be extended to a larger number of latency values ​​where conflicts can be managed between different pairs of latency values.

[0171] Figure 36 is a flow chart of an embodiment for issuing read commands in a mixed read command architecture. First, for each clock cycle, in step 3601, a determination is made as to whether there have been no slow read commands issued during the last t_Data_Burst number of cycles. If so, in step 3603, a determination is made as to whether at least one pending slow read command meets all timing requirements; if so, flow proceeds to step 3605, where command scheduler 3501 issues a slow read command that meets all timing requirements. This is followed by step 3607, where mixed read coordinator 3511 updates conflict tracking register 3515 under the condition that there has been an issued slow read. In step 3609, the slow read command is pushed into pre-ordered slow read command FIFO 3513. If the determination is NO in either step 3601 or 3603, flow proceeds to step 3611.

[0172] In step 3611, it is determined whether a fast read is allowed by the mixed read coordinator 3511, and if so, flow proceeds to step 3613, where it is determined whether a fast read has not been issued within the last t_Data_Burst number of cycles, and if so, flow proceeds to step 3615. Step 3615 determines whether at least one pending fast read command meets all timing requirements, and if so, flow proceeds to step 3617. In step 3617, command scheduler 3501 has received the fast read grant signal and issues a fast read command that meets the timing requirements. Then, in step 3619, the fast read command is pushed into in-flight read command FIFO 3505. If the response in any of 3611, 3613, or 3615 is No, flow proceeds instead to step 3621, where nothing is done.

[0173] 37 is a flowchart of an embodiment for updating the mixed read coordinator 3511. Starting at step 3701, for all bits [n] in the conflict tracking register 3515 other than the start bit, the bit value is shifted left one bit from bit [n] to bit [n-1]. Next, step 3703 determines whether a slow read command has been issued and demultiplexed in MUX 3519. If so, a new slow read command is tracked in step 3705 by entering a value for a single bit of "1" (i.e., 1 bit or 1'b1 in 1'b format) at the slow read insertion point of bit [0], and this "1" is propagated through the conflict tracking register 3515 as each cycle passes. Alternatively, if no slow read command was issued during the clock cycle, a "0" is entered at the insertion point in step 3707.

[0174] Figure 38 is a flow chart of an embodiment of slow read ordering performed by mixed read coordinator 3511 to avoid read conflicts and maintain data read order assignments. Starting at step 3801, every clock cycle, conflict tracking register 3515 is checked to determine if the bit in the slow read ordering point is "1". As shown in Figure 35B, the first bit of the Fast_Read_Conflict_Cycles conflict check bits is used, although either of these bits can be used, serving as input to NOR gate 3517. If the bit in the slow read ordering point is not "1", flow proceeds to step 3803 and nothing is done. If instead the bit in the slow read ordering point is "1", then in step 3805 the slow read at the head of the pre-ordered slow read command FIFO 3513 (indicated by the arrow from conflict tracking register 3515) is popped and mixed read coordinator 3511 can obtain a new slow read command for pre-ordered slow read command FIFO 3513. In step 3807, the popped slow read command of step 3805 is pushed into in-flight read command FIFO 3505 and issued as it works its way through in-flight read command FIFO 3505.

[0175] Figure 39 is a flow chart of an embodiment of a mixed read mode based on the embodiment of Figures 35A and 35B. Starting at step 3901, command scheduler 3501 maintains separate queues for fast latency read commands and slow latency read commands. In step 3903, commands are issued from the fast queue and the slow queue to memory media 3507. In the primary example here, the fast and slow latency reads are reference-based and self-referenced reads of MRAM-based memory cells, respectively, but the technique may be more generally applicable to other memory technologies and other read types. When issuing a slow read command, in step 3905, a slow read indication is recorded relative to its timing (e.g., clock cycles) at the slow read insertion point in conflict tracking register 3515. Before a fast read can be issued, step 3907 determines whether a fast read is permitted based on the output of NOR gate 3517, as described in more detail with respect to Figures 36-38, where steps 3905 and 3907 may have an either-or relationship.

[0176] In step 3909, read data responsive to the issued command is returned from memory media 3507 to the memory controller and, in step 3911, associated with the corresponding issued command from in-flight read command FIFO 3505. Associating the returned data with the issued read command includes entering the issued fast read command into in-flight read command FIFO 3505 in step 3913 and first entering the issued slow read command into pre-ordered slow read command FIFO in step 3915. In step 3917, the issued slow read command is transferred from the pre-ordered slow read command FIFO to in-flight read command FIFO 3505 based on the slow read ordering point bit value of conflict tracking register 3515. Then, in step 3919, the in-flight read command FIFO 3505 is used to assign the issued read command to the returned read data.

[0177] In view of the above, according to a first aspect, it can be seen that an apparatus includes one or more memory arrays, each including a plurality of non-volatile memory cells and a control circuit. The control circuit is configured to read selected memory cells of the memory array using a first read mode and to read selected memory cells of the memory array using a second read mode, the second read mode having a higher read latency than the first read mode, to maintain read commands using the first read mode in a first read command queue and to maintain read commands using the second read mode in a second read command queue, and to issue first read mode commands from the first read command queue and second read mode commands from the second read command queue to the memory array. To issue the first read mode commands, the control circuit is configured to determine where a timing conflict exists between a current first read mode command and a previously issued second read mode command, and to avoid issuing the first read command during a timing conflict with one of the second read commands. The control circuitry is also configured to associate read data returned from the memory array in response to the issued command with the corresponding issued command; to associate read data returned from the memory array in response to the issued command with the corresponding issued command, the control circuitry is configured to input the issued first read mode command into the first issued command queue, input the issued second read mode command into the second issued command queue, and in response to issuing the second read mode command, transfer the issued second read mode command from the second issued command queue to the first issued command queue, and associate read data returned from the memory array with the command from the first issued command queue.

[0178] A further aspect includes a method of operating a memory, the method including maintaining, in a memory controller, a first queue that stores read commands having a first read latency value and a second queue that stores read commands having a second read latency value greater than the first read latency value, and issuing read commands from the first queue and the second queue to a memory medium having one or more arrays of non-volatile memory cells. Issuing the read commands includes, if issuing a read command from the second queue, recording a clock cycle of the memory controller on which the read command from the second queue was issued, and determining, prior to issuing the read command from the first queue, that a read command from the second queue was not recorded as having been issued within a first range of the preceding clock cycle. The method also includes, for each issued read command, receiving from the memory media corresponding read data returned to the memory controller in response to the issued read command; associating by the memory controller the returned read data with the corresponding issued read command, including inputting the issued read command from a first queue into a first-in-first-out (FIFO); inputting the issued read command from a second queue into a second FIFO; and, in response to the command from the second queue being issued a first number of clock cycles prior, transferring the issued read command from the second FIFO to the first FIFO; and assigning the issued read command from the first FIFO to the returned read data.

[0179] A further aspect includes a memory system including a non-volatile memory controller including a command scheduler and a media interface. The command scheduler is configured to maintain a first queue that stores read commands having a first read latency value and a second queue that stores read commands having a second read latency value greater than the first read latency value, and to issue read commands from the first queue and the second queue to one or more arrays of non-volatile memory cells. The media interface is configured such that the command scheduler determines whether a command can be issued from the first queue without causing a read data conflict with a previously issued command from the second queue, receives corresponding read data returned from the array for each issued read command, orders the issued read commands in the order in which the corresponding returned read data is received from the array, and assigns the returned read data to the corresponding issued read commands based on the ordering.

[0180] For purposes of this specification, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different or the same embodiment.

[0181] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that they can exchange electronic signals between each other.

[0182] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0183] For purposes of this specification, the use of numerical terms such as "first," "second," and "third" objects without additional context does not imply an ordering of the objects, but instead may be used for identification purposes to distinguish between different objects.

[0184] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling those skilled in the art to best utilize this technology in various embodiments, with various modifications as appropriate for the particular uses contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. 1. An apparatus comprising: one or more memory arrays each including a plurality of non-volatile memory cells; A system comprising a control circuit, the control circuit comprising: reading selected memory cells of the memory array using a first read mode; reading selected memory cells of the memory array using a second read mode, the second read mode having a higher read latency than the first read mode; maintaining read commands using the first read mode in a first read command queue; maintaining read commands using the second read mode in a second read command queue; configured to issue the first read mode command from the first read command queue and the second read mode command from the second read command queue to the memory array, wherein to issue the first read mode command, the control circuitry determining where there is a timing conflict between the current first read mode command and the previously issued second read mode command; not issuing the first read command during a timing conflict with one of the second read commands; configured to associate read data returned from the memory array in response to the issued command with the corresponding issued command, wherein the control circuitry, for associating the read data returned from the memory array in response to the issued command with the corresponding issued command, inputting the first issued read mode command into a first issued command queue; inputting the issued second read mode command into a second issued command queue; in response to issuance of a second read mode command, transferring the issued second read mode command from the second issued command queue to the first issued command queue; An apparatus configured to associate the read data returned from the memory array with a command from the first issued command queue.

2. 10. The device of claim 1, wherein each of the non-volatile memory cells comprises a resistive random access memory element and a two-terminal selector element in series with the memory element.

3. 3. The apparatus of claim 2, wherein the first read mode is a forced current referenced read and the second read mode is a forced current self-referenced read.

4. The device of claim 3 , wherein the resistive random access memory element comprises a magnetoresistive random access memory (MRAM) element.

5. The device of claim 3 , wherein the resistive random access memory element comprises a phase change memory element.

6. The apparatus of claim 2 , wherein the two-terminal selector element comprises an Ovonic Threshold (OTS).

7. 2. The apparatus of claim 1, wherein the first issued command queue is a first first-in-first-out (FIFO) and the second issued command queue is a second FIFO.

8. To determine whether there is a timing conflict between the current first read mode command and the previously issued second read mode command, the control circuitry: maintaining a conflict register having a plurality of register bits; inputting, at each clock cycle of the control circuit, a register bit value indicating whether a second read mode was issued during the clock cycle; propagating the input register bit through the conflict register by one bit place each clock cycle; 2. The apparatus of claim 1, further configured to determine whether the timing conflict exists between the current first read mode command and the previously-issued second read mode command based on whether the subset of register bits indicates that a second read mode command was previously issued.

9. 9. The apparatus of claim 8, wherein the number of register bits in the subset depends on the number of clock cycles used by read data returned in response to the corresponding issued read command.

10. 9. The apparatus of claim 8, wherein the number of register bits in the subset depends on a relative amount of read latency between the first read mode command and the second read mode command.

11. 1. A method comprising: maintaining, in a memory controller, a first queue for storing read commands having a first read latency value and a second queue for storing read commands having a second read latency value greater than the first read latency value; issuing read commands from the first queue and the second queue to a memory medium having one or more arrays of non-volatile memory cells; When issuing a read command from the second queue, recording the clock cycle of the memory controller on which the read command from the second queue was issued; determining that a read command from the second queue is not recorded as having been issued within a first range of preceding clock cycles before issuing the read command from the first queue; for each of the issued read commands, receiving from the memory medium the corresponding read data returned to the memory controller in response to the issued read command; associating, by the memory controller, the returned read data with the corresponding issued read command; inputting issued read commands from the first queue into a first first-in-first-out (FIFO); inputting the issued read command from the second queue into a second FIFO; transferring an issued read command from the second FIFO to the first FIFO in response to a command from the second queue being issued a first number of clock cycles prior; and associating issued read commands from the first FIFO with returned read data.

12. each of the nonvolatile memory cells includes a resistive random access memory element and a two-terminal selector element in series with the memory element; 12. The method of claim 11, wherein the read command having the first read latency value is a forced current referenced read and the read command having the second read latency value is a forced current self-referenced read.

13. The method of claim 12 , wherein the resistive random access memory elements comprise magnetoresistive random access memory (MRAM) elements.

14. 12. The method of claim 11, wherein the number of cycles in the first range of preceding clock cycles and the first number of clock cycles depend on the number of clock cycles used by read data returned in response to the corresponding issued read command.

15. 12. The method of claim 11, wherein the first range of preceding clock cycles and the first number of clock cycles depend on a relative amount of read latency between the first read latency value and the second read latency value.

16. 1. A memory system comprising:

1. A non-volatile memory controller, comprising: A command scheduler, maintaining a first queue that stores read commands having a first read latency value; maintaining a second queue for storing read commands having a second read latency value, the second read latency value being greater than the first read latency value; a command scheduler configured to issue read commands from the first queue and the second queue to one or more arrays of non-volatile memory cells; A media interface, determining whether the command scheduler can issue a command from the first queue without causing a read data conflict with a previously issued command from the second queue; receiving corresponding read data returned from the array for each of the issued read commands; ordering the issued read commands in the order in which the corresponding returned read data is received from the array; and a media interface configured to allocate returned read data with the corresponding issued read commands based on their ordering.

17. further comprising one or more memory dies including said one or more arrays of non-volatile memory cells; each of the nonvolatile memory cells includes a resistive random access memory element and a two-terminal selector element in series with the resistive random access memory element; the read command having a first read latency value is a forced current referenced read; 17. The memory system of claim 16, wherein the read command having the second read latency value is a forced current self-referencing read.

18. 20. The memory system of claim 17, wherein the resistive random access memory elements are magnetoresistive random access memory (MRAM) elements.

19. to determine whether the command scheduler can issue the command from the first queue without causing the read data conflict with a previously issued command from the second queue, the media interface: When a read command is issued from the second queue, recording the clock cycle in which the read command is issued from the second queue; 17. The memory system of claim 16, configured to disallow issuance of a read command from the first queue if a read command from the second queue is recorded as having been issued within a first range of a preceding clock cycle.

20. the media interface to order the issued read commands in the order in which the returned corresponding read data is received from the array; inputting issued read commands from the first queue into a first first-in-first-out (FIFO); inputting the issued read command from the second queue into a second FIFO; 17. The memory system of claim 16, further configured to: transfer an issued read command from the second FIFO to the first FIFO in response to a command from the second queue being issued a first number of clock cycles ago.

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