Light emitting diode and light emitting device

Abstract

To provide a light emitting diode.SOLUTION: A light emitting diode includes: an n-type semiconductor layer; a mesa disposed atop the n-type semiconductor layer and exposing a portion thereof, and including an active layer and a p-type semiconductor layer; a transparent electrode in electrical contact with the p-type semiconductor layer; a first bonding pad in electrical contact with the n-type semiconductor layer; a second bonding pad in electrical contact with the p-type semiconductor layer; a current blocking layer disposed under the first bonding pad and separated from the transparent electrode; a first insulation layer partially disposed on the n-type semiconductor layer exposed by the mesa; and a first extension extending from the first bonding pad and partially disposed on the first insulation layer. The first insulation layer and the current blocking layer are separated. The first insulation layer comprises a plurality of islands disposed along the first extension. The first extension is electrically connected to the n-type semiconductor layer between the islands.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a light emitting diode and a light emitting element having the same, and more particularly to a light emitting diode and a light emitting element having high optical output and excellent reliability under high humidity conditions. [Background technology]

[0002] Inorganic light-emitting diodes using semiconductors are used in a variety of fields such as lighting, displays, and automobile headlamps, and their application fields are continuously increasing.

[0003] The light-emitting diode has a structure in which a p-type semiconductor layer and an n-type semiconductor layer are arranged opposite each other with an active layer sandwiched therebetween. Furthermore, electrodes are formed on the n-type semiconductor layer and the p-type semiconductor layer, respectively, and power is supplied from the outside via these electrodes, causing the light-emitting diode to generate light.

[0004] Light emitting diodes are used in a variety of environments and must be able to operate stably even under adverse conditions. In particular, light emitting diodes are vulnerable to moisture, so they must pass accelerated tests under high temperature and humidity conditions.

[0005] On the other hand, a protective film has generally been used to protect light-emitting diodes from moisture. The protective film covers the light-emitting diode and prevents the semiconductor layers and transparent electrodes from being exposed to the outside. This protects the light-emitting diode from being damaged by external factors such as moisture.

[0006] However, since the protective film is placed on the path of light emitted from the light-emitting diode, it absorbs part of the light, resulting in a decrease in the light output of the light-emitting diode. For example, when no protective film is used, the light output is about 5% to 10% higher than when a transparent protective film such as SiO2 is used.

[0007] Therefore, there is a demand for light emitting diodes and light emitting elements that are highly reliable under high humidity conditions and have high light output. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Korean Patent Publication No. 10-2012-0053990 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the present invention is to provide a light emitting diode that is highly reliable even under high humidity conditions while preventing a decrease in light output due to a protective film, and a light emitting device having the same. [Means for solving the problem]

[0010] A light-emitting diode according to one embodiment of the present invention includes an n-type semiconductor layer; a mesa located on the n-type semiconductor layer to partially expose an upper surface of the n-type semiconductor layer, the mesa including an active layer and a p-type semiconductor layer located on the active layer; a first bonding pad electrically connected to the n-type semiconductor layer; a second bonding pad electrically connected to the p-type semiconductor layer; and a first insulating layer at least a portion of which is disposed between the second bonding pad and an exposed region of the n-type semiconductor layer exposed by the mesa. The first insulating layer covers a portion of the p-type semiconductor layer region between the exposed region of the n-type semiconductor layer closest to the second bonding pad and the second bonding pad, and the first insulating layer is disposed along an edge of the p-type semiconductor layer adjacent to the exposed n-type semiconductor layer.

[0011] A light emitting device according to another embodiment of the present invention includes an n-type semiconductor layer; a mesa located on the n-type semiconductor layer to partially expose an upper surface of the n-type semiconductor layer, the mesa including an active layer and a p-type semiconductor layer located on the active layer; a first bonding pad electrically connected to the n-type semiconductor layer; a second bonding pad electrically connected to the p-type semiconductor layer; a bonding wire bonded to the second bonding pad; and a metal migration prevention layer disposed between the exposed n-type semiconductor layer and the second bonding pad; the metal migration prevention layer is formed opposite the first bonding pad and spaced apart from the second bonding pad, and is disposed along an edge of the p-type semiconductor layer adjacent to the bonding wire.

[0012] A light emitting device according to yet another embodiment of the present invention includes a base; first and second leads disposed adjacent to the base; the above-mentioned light emitting diode mounted on the base; bonding wires electrically connecting the light emitting diode to the first and second leads; and a molding portion covering the light emitting diode and the bonding wires. The light emitting diode includes a transparent electrode disposed on a p-type semiconductor layer, and the bonding wires are bonded to a first and second bonding pad, respectively. The molding portion contacts the first and second bonding pads of the light emitting diode, the transparent electrode, and the first insulating layer, and also partially contacts the n-type semiconductor layer exposed by the mesa. [Effects of the Invention]

[0013] According to each embodiment of the present invention, a light emitting diode with improved reliability under high humidity conditions can be provided by removing the protective film, increasing light output, and partially disposing a first insulating layer around the second bonding pad.

[0014] Other features and advantages of the present invention will be described in or will be apparent from the following detailed description. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic plan view illustrating a light emitting diode according to an embodiment of the present invention; [Figure 2a] FIG. 2 is a cross-sectional view taken along line AA' in FIG. [Figure 2b] FIG. 2 is a cross-sectional view taken along line BB' in FIG. [Figure 2c] FIG. 2 is a cross-sectional view taken along line CC' in FIG. [Figure 3] FIG. 10 is a schematic cross-sectional view illustrating a modified example of a light-emitting diode according to an embodiment of the present invention. [Figure 4] FIG. 10 is a schematic cross-sectional view illustrating another modified example of a light-emitting diode according to an embodiment of the present invention. [Figure 5] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 6] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 7a] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 7b] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 7c] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 8] FIG. 10 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention. [Figure 9] 10 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention; FIG. [Figure 10a] FIG. 10 is a schematic cross-sectional view taken along line DD' in FIG. 9. [Figure 10b]FIG. 10 is a schematic cross-sectional view taken along line EE' in FIG. 9. [Figure 11] 10 is a schematic plan view illustrating a light emitting diode according to still another embodiment of the present invention. FIG. [Figure 12a] FIG. 12 is a schematic cross-sectional view taken along line FF' in FIG. [Figure 12b] FIG. 12 is a schematic cross-sectional view taken along line GG' in FIG. [Figure 13] 1 is a schematic cross-sectional view illustrating a light emitting device according to an embodiment of the present invention. [Figure 14a] 10 is a SEM image of a light emitting element according to a comparative example after a high-temperature, high-humidity reliability test. [Figure 14b] 10 is an optical image of a light emitting device according to an embodiment of the present invention after a high temperature and high humidity reliability test. [Figure 15a] 10 is a graph showing a change in forward voltage depending on the time of a high-temperature, high-humidity reliability test of light emitting devices according to a comparative example and an embodiment; [Figure 15b] 10 is a graph showing changes in light output with time during high-temperature, high-humidity reliability testing of light emitting devices according to a comparative example and an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to fully convey the concept of the present invention to those skilled in the art. Therefore, the present invention is not limited to the following embodiments and may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Furthermore, when a component is described as being "on top of" or "on" another component, this includes not only the case where each component is "directly above" or "directly on" the other component, but also the case where another component is interposed between the other component and the other component. The same reference numerals refer to the same components throughout the specification.

[0017] A light-emitting diode according to one embodiment of the present invention includes an n-type semiconductor layer; a mesa located on the n-type semiconductor layer to partially expose an upper surface of the n-type semiconductor layer, the mesa including an active layer and a p-type semiconductor layer located on the active layer; a first bonding pad electrically connecting to the n-type semiconductor layer; a second bonding pad electrically connecting to the p-type semiconductor layer; and a first insulating layer at least a portion of which is disposed between an exposed region of the n-type semiconductor layer exposed by the mesa and the second bonding pad; wherein the first insulating layer covers a portion of the p-type semiconductor layer region between the second bonding pad and an exposed region of the n-type semiconductor layer exposed by the mesa that is closest to the second bonding pad, and the first insulating layer is disposed along an edge of the p-type semiconductor layer adjacent to the exposed n-type semiconductor layer.

[0018] By using the first insulating layer, the protective film that covers most of the mesa area can be removed, improving the optical output while preventing defects caused by metal migration under high humidity conditions, thereby improving reliability.

[0019] The first insulating layer may be disposed closer to the exposed n-type semiconductor layer than the second bonding pad. Also, the first insulating layer may partially cover the exposed n-type semiconductor layer. May be covered.

[0020] Meanwhile, the first insulating layer may have a length longer than the width of the second bonding pad. Furthermore, the first insulating layer may have a shape that surrounds three sides of the second bonding pad.

[0021] In one embodiment, the mesa may have an elongated shape, the second bonding pad may be disposed on the mesa opposite the first bonding pad near an edge of one side end in the length direction of the mesa, and the first insulating layer may cover a portion of the p-type semiconductor layer region between the second bonding pad and the edge of the one side end.

[0022] The first insulating layer may cover a side surface of the mesa near an edge of the one side end and the exposed n-type semiconductor layer.

[0023] Furthermore, the first insulating layer may extend lengthwise along the edge of the mesa near the edge of the one side end. The length of the first insulating layer portion disposed along the length of the mesa may be greater than the width of the second bonding pad and less than half the maximum length of the mesa. This reduces optical loss due to the first insulating layer and ensures reliability under high humidity conditions.

[0024] In another embodiment, the mesa may include a groove exposing the n-type semiconductor layer through the p-type semiconductor layer and the active layer, and the first insulating layer may cover a portion of the p-type semiconductor layer region located between the groove and the second bonding pad.

[0025] In yet another embodiment, the light-emitting diode may further include an additional insulating layer spaced apart from the first insulating layer, the mesa may include a groove exposing the n-type semiconductor layer through the p-type semiconductor layer and the active layer, and the additional insulating layer may cover a portion of the p-type semiconductor layer region located between the groove and the second bonding pad.

[0026] The additional insulating layer may also cover part of the sidewalls of the groove.

[0027] The light emitting diode may further include a transparent electrode in ohmic contact with the p-type semiconductor layer, and the second bonding pad may be located on the transparent electrode and electrically connected to the transparent electrode.

[0028] In one embodiment, the transparent electrode may cover a portion of the first insulating layer.

[0029] Furthermore, the transparent electrode and the first insulating layer may overlap by a first width w1, and the transparent electrode may be spaced apart from the edge of the p-type semiconductor layer by a second width w2, and the first width w1 may be greater than the second width w2 and may be 10 μm or less. For example, the first width w1 may be 5 μm, and the second width w2 may be 4 μm.

[0030] The semiconductor device may further include a first extension extending from the first bonding pad. The first extension may be electrically connected to the n-type semiconductor layer. The first extension may be electrically connected to the n-type semiconductor layer through holes formed in the first insulating layer. Alternatively, the first insulating layer may include a plurality of islands spaced apart from one another, and the first extension may be electrically connected to the n-type semiconductor layer in regions between the islands.

[0031] In another embodiment, a portion of the first insulating layer may cover the transparent electrode. In yet another embodiment, a side surface of the first insulating layer and a side surface of the transparent electrode may be disposed to face each other.

[0032] A light emitting device according to yet another embodiment of the present invention includes an n-type semiconductor layer; a mesa located on the n-type semiconductor layer to partially expose an upper surface of the n-type semiconductor layer, the mesa including an active layer and a p-type semiconductor layer located on the active layer; a first bonding pad electrically connected to the n-type semiconductor layer; a second bonding pad electrically connected to the p-type semiconductor layer; a bonding wire bonded to the second bonding pad; and a metal migration prevention layer disposed between the exposed n-type semiconductor layer and the second bonding pad; the metal migration prevention layer is formed opposite the first bonding pad and spaced apart from the second bonding pad, and is disposed along an edge of the p-type semiconductor layer adjacent to the bonding wire.

[0033] The length of the metal migration prevention layer may be less than half the total length of the edge of the mesa.

[0034] Under high humidity conditions, metal ions can migrate from the metal wire located on the anode electrode side to the cathode electrode side, which can cause leakage current and lead to defects due to short circuits. However, by providing a metal migration prevention layer, migration of metal ions can be prevented, thereby preventing defects due to short circuits under high humidity conditions.

[0035] In one embodiment, the bonding wire may be a silver (Ag) wire.

[0036] A light emitting device according to yet another embodiment of the present invention includes a base; first and second leads disposed adjacent to the base; the above-mentioned light emitting diode mounted on the base; bonding wires electrically connecting the light emitting diode to the first and second leads; and a molding portion covering the light emitting diode and the bonding wires. The light emitting diode includes a transparent electrode disposed on a p-type semiconductor layer, and the bonding wires are bonded to a first and second bonding pad, respectively. The molding portion contacts the first and second bonding pads of the light emitting diode, the transparent electrode, and the first insulating layer, and also partially contacts the n-type semiconductor layer exposed by the mesa.

[0037] Furthermore, the area where the molding part and the transparent electrode contact each other may be larger than the area where the molding part and other components of the light emitting diode contact each other.

[0038] FIG. 1 is a schematic plan view illustrating a light-emitting diode 100 according to one embodiment of the present invention, and FIGS. 2a, 2b, and 2c are cross-sectional views taken along lines A-A', B-B', and C-C' in FIG. 1, respectively.

[0039] 1, 2a, 2b, and 2c, the light emitting diode 100 may include a substrate 21, a light emitting structure 30 including a mesa M, a current barrier layer 29a, a current blocking layer 29b, a first insulating layer 31, a transparent electrode 33, a first bonding pad 35, a first extension 35a, a second bonding pad 37, and a second extension 37a.

[0040] The substrate 21 may be an insulating or conductive substrate. The substrate 21 may also be a growth substrate for growing the light emitting structure 30, such as a sapphire substrate or a silicon carbide substrate. The substrate 21 may include a plate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, etc. For example, the substrate 21 may be a sapphire substrate, and in particular, a patterned sapphire substrate (PSS). In this case, the substrate 21 may include a plurality of protrusions on its upper surface. The substrate 21 may also have a generally elongated rectangular shape, although the present invention is not limited thereto.

[0041] A light emitting structure 30 including a mesa M is disposed on the substrate 21. The light emitting structure 30 may include an n-type semiconductor layer 23, a p-type semiconductor layer 27 located on the n-type semiconductor layer 23, and an active layer 25 located between the n-type semiconductor layer 23 and the p-type semiconductor layer 27. Meanwhile, the mesa M includes the p-type semiconductor layer 27 and the active layer 25.

[0042] The n-type semiconductor layer 23, the active layer 25, and the p-type semiconductor layer 27 are grown by molecular beam epitaxy (MBE). The n-type semiconductor layer 23 may be grown on the substrate 21 in a chamber using a known method such as MBE (metal organic chemical vapor deposition) or MOCVD (metal organic chemical vapor deposition). The n-type semiconductor layer 23 may have the same planar shape as the substrate 21 by being diced together with the substrate 21. However, the present invention is not necessarily limited to this, and the n-type semiconductor layer 23 may be located within a partial region of the substrate 21.

[0043] Meanwhile, the n-type semiconductor layer 23, the active layer 25, and the p-type semiconductor layer 27 may include a III-V series nitride-based semiconductor, for example, a nitride-based semiconductor such as (Al, Ga, In)N. The n-type semiconductor layer 23 may include n-type impurities (e.g., Si, Ge, Sn), and the p-type semiconductor layer 27 may include p-type impurities (e.g., Mg, Sr, Ba). The active layer 25 may include a single quantum well structure or a multiple quantum well (MQW) structure, and the composition ratio of the nitride-based semiconductors can be adjusted to emit light of a desired wavelength.

[0044] The mesa M is located on a portion of the n-type semiconductor layer 23, thereby exposing the top surface of the n-type semiconductor layer 23 in the region where the mesa M is not formed. The mesa M may be formed by growing the n-type semiconductor layer 23, the active layer 25, and the p-type semiconductor layer 27 on the substrate 21 and then partially etching the p-type semiconductor layer 27 and the active layer 25. The shape of the mesa M is not limited, but may generally have a shape similar to that of the substrate 21. That is, as shown in FIG. 1 , the mesa M may have a generally rectangular shape or a shape that is elongated in one direction (length direction). The mesa M may also have an inclined side surface, but is not limited thereto, and may also have a side surface that is perpendicular to the top surface of the n-type semiconductor layer 23. In this embodiment, the mesa M may include a recessed portion recessed inward on one side surface to accommodate a first extension portion 35a, which will be described later.

[0045] The mesa M may further include a concave-convex pattern (not shown) formed on its side surface. The concave-convex pattern may be formed by a patterning method such as dry etching and / or wet etching. The concave-convex pattern improves the extraction efficiency of light generated in the active layer 25.

[0046] The transparent electrode 33 may be located on the p-type semiconductor layer 27 and may be in ohmic contact with the p-type semiconductor layer 27. The transparent electrode 33 may include a material that is optically transparent and electrically conductive, such as a conductive oxide or a light-transmitting metal layer. For example, the transparent electrode 33 may be made of ITO (Indium Tin Oxide), ZnO (Zinc Oxide), ZITO (Zinc Indium Tin Oxide), ZIO (Zinc Indium Oxide), ZTO (Zinc Tin Oxide), GITO (Gallium Indium Tin Oxide), GIO (Gallium Indium Oxide), or GZO The insulating layer may include at least one of gallium zinc oxide (AZO), aluminum doped zinc oxide (AZO), fluorine tin oxide (FTO), or a Ni / Au stacked structure.

[0047] The first bonding pad 35 may be disposed on the mesa M. The first bonding pad 35 is electrically insulated from the p-type semiconductor layer 27, and for this purpose, a current blocking layer 29b may be disposed between the first bonding pad 35 and the p-type semiconductor layer 27. The current blocking layer 29b may also partially cover the side surface of the mesa M and the n-type semiconductor layer 23 that are exposed around the first bonding pad 35. The current blocking layer 29b insulates the first bonding pad 35 from the p-type semiconductor layer 27 and prevents a bonding wire disposed on the first bonding pad 35 from shorting to the transparent electrode 33 or the p-type semiconductor layer 27.

[0048] Meanwhile, a first extension 35a may extend from the first bonding pad 35. The first extension 35a may extend onto the exposed n-type semiconductor layer 23 and contact the n-type semiconductor layer 23. The first extension 35a may be formed in the same process and using the same material as the first bonding pad 35. The first extension 35a contacts the n-type semiconductor layer 23 over a wide area to promote current spreading.

[0049] The second bonding pad 37 may be disposed on the mesa M. As shown, the second bonding pad 37 may be disposed near the edge of one longitudinal end of the mesa M, facing the first bonding pad 35. The second bonding pad 37 is spaced apart from the edge of the mesa M, so that a portion of the mesa M is disposed between the second bonding pad 37 and the n-type semiconductor layer 23 exposed around the mesa M.

[0050] Meanwhile, the second extension 37a extends from the second bonding pad 37 toward the first bonding pad 35. The second extension 37a may be formed of the same material and in the same process as the second bonding pad 37. However, the second bonding pad 37 is a pad for bonding a wire and has a relatively wider width than the second extension 37a so that a wire ball can be formed.

[0051] The second bonding pad 37 may include a metal material such as Ti, Pt, Au, Cr, Ni, or Al, and may have a single-layer or multi-layer structure. For example, the second bonding pad 37 may include at least one of a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, a Cr / Pt / Au layer, a Ni / Au layer, a Ni / Pt / Au layer, and a Cr / Al / Cr / Ni / Au layer. The second bonding pad 37 may also be formed of the same material as the first bonding pad 35.

[0052] The current barrier layer 29a may be disposed under the second bonding pad 37 and the second extension 37a. In particular, the current barrier layer 29a may be disposed between the p-type semiconductor layer 27 and the transparent electrode 33. The current barrier layer 29a prevents current supplied through the second bonding pad 37 from concentrating around the second bonding pad 37 or the second extension 37a. Therefore, the current barrier layer 29a may include an insulating material and may be formed as a single layer or multiple layers. For example, the current barrier layer 29a may include SiOx or SiNx, and may include a distributed Bragg reflector in which insulating material layers with different refractive indices are stacked. The current barrier layer 29a may be optically transparent, optically reflective, or selectively reflective.

[0053] The current barrier layer 29a is formed so that the second bonding pad 37 and the second extension 37a are located exclusively on the current barrier layer 29a. It may have an area larger than 37a.

[0054] On the other hand, as shown in FIG. 2a, the transparent electrode 33 may have an opening that exposes the current barrier layer 29a below the second bonding pad 37, so that the second bonding pad 37 can contact the current barrier layer 29a.

[0055] Meanwhile, the first insulating layer 31 covers a portion of the region of the p-type semiconductor layer 27 between the second bonding pad 37 and the n-type semiconductor layer 23 exposed around the mesa M. The first insulating layer 31 is partially disposed along the edge of the mesa M. In particular, the first insulating layer 31 may be disposed in an elongated shape along the edge of the p-type semiconductor layer 27, covering a portion of the region of the p-type semiconductor layer 27 between the second bonding pad 37 and an exposed region of the n-type semiconductor layer 23 exposed by the mesa M that is closest to the second bonding pad 37. Furthermore, as shown in FIG. 1, the first insulating layer 31 may be disposed so as to surround three sides of the second bonding pad 37 (surrounding the second bonding pad 37 from three directions). Furthermore, the first insulating layer 31 may partially cover the side surfaces of the mesa M and the exposed region of the n-type semiconductor layer 23, as shown in FIGS. 1 and 2a. Generally, the first insulating layer 31 may be formed opposite the first bonding pad 35 and spaced apart from the second bonding pad 37 , that is, on the opposite side of the first bonding pad 35 .

[0056] The first insulating layer 31 is disposed to prevent metal ions from migrating from the bonding wire formed on the second bonding pad 37 due to an electric field. Therefore, the first insulating layer 31 may be referred to as a metal migration prevention layer. Under high humidity conditions, a moisture layer forms on the transparent electrode 33, and metal ions can migrate from the second bonding pad 37 to the n-type semiconductor layer 23 through this moisture layer. The closer the distance between the second bonding pad 37 and the exposed n-type semiconductor layer 23, the stronger the electric field. Therefore, the first insulating layer 31 must be disposed in a location closest to the metal ion migration path. Furthermore, by disposing the first insulating layer 31 in a relatively long shape so as to adequately block the path through which metal ions can migrate, electrical short circuits caused by metal ions can be prevented. For this reason, the first insulating layer 31 is preferably formed to be wider than the width of the second bonding pad 37.

[0057] On the other hand, the first insulating layer 31 is limited to a certain region because it may reduce optical output. In particular, the overall length of the first insulating layer 31 may be less than half, or even less than one-quarter, of the overall length of the edge of the mesa M. By controlling the overall length of the first insulating layer 31, optical loss due to the first insulating layer 31 can be reduced. However, the present invention is not limited thereto, and the first insulating layer 31 may cover most of the edge of the mesa M or may be connected to the current blocking layer 29b.

[0058] As shown in FIG. 2A, the transparent electrode 33 may cover a portion of the first insulating layer 31. That is, the first insulating layer 31 may be disposed below the transparent electrode 33. As shown in the partially enlarged cross-sectional view of FIG. 2A, the first insulating layer 31 and the transparent electrode 33 may overlap by a first width w1. Meanwhile, the transparent electrode 33 is spaced from the edge of the p-type semiconductor layer 27 by a second width w2. Typically, the transparent electrode 33 is spaced from the edge of the p-type semiconductor layer 27, and the second width w2 may be, for example, about 4 μm. Meanwhile, to efficiently prevent metal ions from migrating to the bottom of the first insulating layer 31, the transparent electrode 33 and the first insulating layer 31 must overlap sufficiently. Therefore, the first width w1 may be larger than the second width w2, for example, about 5 μm or more. Meanwhile, the upper limit of the second width w2 may be limited so as to allow current to be dispersed near the edge of the p-type semiconductor layer 27. For example, the second width w2 may be less than 10 μm.

[0059] On the other hand, the first insulating layer 31 may be formed together with the current barrier layer 29a and the current blocking layer 29b before the formation of the transparent electrode 33. However, the present invention is not limited to this. The edge layer 31 may be formed of a material different from that of the current barrier layer 29a and the current blocking layer 29b. The first insulating layer 31 may be formed of, for example, silicon oxide or silicon nitride.

[0060] In this embodiment, the insulating layers disposed on the p-type semiconductor layer 27 may be limited to the current barrier layer 29a, the current blocking layer 29b, and the first insulating layer 31. This means that most of the p-type semiconductor layer 27 is not covered with material layers other than the transparent electrode 33, thereby reducing light loss due to the insulating layers.

[0061] Furthermore, while the protective film according to the prior art covers the transparent electrode 33, in this embodiment, no insulating layer is disposed on the transparent electrode 33. However, the present invention is not limited to this, and a portion of the first insulating layer 31 may cover the transparent electrode 33, as will be described later.

[0062] 3 to 8 are schematic cross-sectional views illustrating various modified examples of the light emitting diode 100 according to one embodiment of the present invention.

[0063] 3, in the above-described light-emitting diode 100, the first insulating layer 31 extends to the edge of the n-type semiconductor layer 23 exposed around the mesa M, but in this modification, the first insulating layer 31 partially covers the exposed n-type semiconductor layer 23, exposing a region near the edge of the n-type semiconductor layer 23. Because the first insulating layer 31 is spaced apart from the edge of the n-type semiconductor layer 23, it is possible to prevent the first insulating layer 31 from being damaged during the dicing process when the light-emitting diode is divided by the dicing process.

[0064] 4, in this modification, a portion of the first insulating layer 31 covers the transparent electrode 33. Therefore, the first insulating layer 31 may be formed after the transparent electrode 33 is formed. Because the first insulating layer 31 covers the transparent electrode 33, it is possible to more reliably block metal ions from migrating from the second bonding pad 37 side to the n-type semiconductor layer 23 side.

[0065] 5, in this modification, the first insulating layer 31 is disposed so that its side surface faces the side surface of the transparent electrode 33. Therefore, the first insulating layer 31 and the transparent electrode 33 do not overlap each other. The side surface of the first insulating layer 31 may contact the side surface of the transparent electrode 33, but is not limited to this, and the first insulating layer 31 may be spaced apart from the transparent electrode 33.

[0066] 6, in this modification, the first insulating layer 31 is disposed only on the p-type semiconductor layer 27, and does not cover the side surface of the mesa M or the exposed n-type semiconductor layer 23. Although the first insulating layer 31 is shown disposed so as not to overlap with the transparent electrode 33, this is not limitative, and at least a portion of the first insulating layer 31 may be disposed below or above the transparent electrode 33.

[0067] 7a, 7b, and 7c are schematic plan views illustrating still another modified example of a light-emitting diode according to an embodiment of the present invention.

[0068] Referring to FIG. 7a, the light-emitting diode 100a according to this embodiment is generally similar to the light-emitting diode of FIG. 1, except that the first insulating layer 31 extends further along the edge of the mesa M.

[0069] The first insulating layer 31 may extend along both side edges of the mesa M, or may extend up to the vicinity of the current blocking layer 29b. The width w1 by which the first insulating layer 31 overlaps the transparent electrode 33 may be generally constant and may be 5 μm to 10 μm, more specifically, about 5 μm. The first insulating layer 31 may also be spaced apart from the current blocking layer 29b by about 2 μm to 5 μm.

[0070] In this embodiment, the current blocking layer 29b is separated from the transparent electrode 33. However, the present invention is not limited to this, and the current blocking layer 29b may overlap the transparent electrode 33.

[0071] Meanwhile, the first insulating layer 31 covers the n-type semiconductor layer 23 exposed near the mesa M, and therefore the first extension 35a passes through the top of the first insulating layer 31. As shown, the first insulating layer 31 may have a plurality of openings 31a exposing the n-type semiconductor layer 23, and the first extension 35a may be electrically connected to the n-type semiconductor layer 23 through the plurality of openings 31a. The plurality of openings 31a may be arranged at regular intervals, but are not limited thereto, and may be arranged at different intervals. For example, the openings 31a may be arranged so that the intervals between them become narrower as they are farther from the first bonding pad 35, thereby enabling more uniform distribution of current.

[0072] 7b, a light emitting diode 100b according to this embodiment is generally similar to the light emitting diode 100a of FIG. 7a, but differs in that it further includes a protrusion protruding toward the current blocking layer 29b at the left end of the first insulating layer 31. This maximizes the overlapping area between the transparent electrode 33 and the first insulating layer 31.

[0073] 7c, a light-emitting diode 100c according to this embodiment is generally similar to the light-emitting diode 100a described with reference to FIG. 7a, but differs in that the first insulating layer 31 extends to the current-blocking layer 29b and is connected to it. The first insulating layer 31 and the current-blocking layer 29b may be formed from the same material in the same process, and connecting them to each other can simplify the process.

[0074] FIG. 8 is a schematic cross-sectional view illustrating yet another modified example of the light-emitting diode according to one embodiment of the present invention.

[0075] Referring to Figure 8, the light-emitting diode 100d of this embodiment is generally similar to the light-emitting diode 100c of Figure 7c, except that instead of each opening 31a being formed in the first insulating layer 31, the first insulating layer 31 is patterned into a plurality of islands 31b.

[0076] Each island 31b is disposed along and below the first extension 35a, so that the first extension 35a can be electrically connected to the n-type semiconductor layer 23 exposed between the islands 31b.

[0077] Similarly to the first insulating layer 31, each island 31b may overlap the transparent electrode 33 by a first width w1. Each island 31b may have various shapes, and in particular, may have a shape with an inclined side surface. This prevents the first extension 35a from being disconnected at the side surface of each island 31b.

[0078] Also, while Figure 8 shows a state in which the left end of the first insulating layer 31 is connected to the current blocking layer 29b, the left end of the first insulating layer 31 may be spaced apart by approximately 2 μm to 5 μm, as in the modified examples of Figures 7a and 7b.

[0079] Meanwhile, the modifications of Figures 3 to 5 described above can also be applied to the modifications of Figures 7a, 7b, 7c, and 8. In addition, the modifications described with reference to Figures 3 to 8 can be similarly applied to various embodiments described later. Figure 9 is a schematic plan view illustrating a light emitting diode 200 according to another embodiment of the present invention, and Figures 10a and 10b are schematic cross-sectional views taken along lines D-D' and E-E' of Figure 9, respectively.

[0080] Referring to FIGS. 9, 10a and 10b, the light emitting diode 200 according to this embodiment is Although the light emitting diode 200 is generally similar to the light emitting diode 100 described above, the light emitting diode 200 has a relatively larger light emitting area and therefore more extensions 35a and 37b. Also, while the light emitting diode 100 described above includes a first bonding pad 35 disposed on the p-type semiconductor layer 27, the light emitting diode according to this embodiment includes a first bonding pad 35 disposed in a groove 30a formed in the mesa M.

[0081] First, the mesa M is disposed on a partial region of the n-type semiconductor layer 23 so as to expose the top surface of the n-type semiconductor layer 23 along its periphery. The mesa M may have a long rectangular shape, and as shown in the figure, may have an uneven pattern on its side surface.

[0082] Meanwhile, the mesa M may include grooves 30a and 30b exposing the n-type semiconductor layer 23, and the first bonding pad 35 may be disposed in the groove 30a. The first extension 35a extends from the first bonding pad 35 toward the second bonding pad 37.

[0083] The second bonding pad 37 is disposed opposite the first bonding pad 35 near an edge of one longitudinal end of the mesa M (one edge perpendicular to the longitudinal direction). In this embodiment, the region of the exposed n-type semiconductor layer 23 closest to the second bonding pad 37 may be located near the edge of the one longitudinal end of the mesa M.

[0084] The first insulating layer 31 covers a portion of the p-type semiconductor layer 27 between the second bonding pad 37 and the exposed n-type semiconductor layer 23. In particular, the first insulating layer 31 covers a portion of the p-type semiconductor layer between the second bonding pad 37 and the exposed n-type semiconductor layer 23 closest to the second bonding pad 37, and may extend along the edge of the mesa M. The length of the first insulating layer 31 is greater than the width of the second bonding pad 37. Alternatively, the first insulating layer 31 may extend toward the edges parallel to the length direction, thereby surrounding three sides of the second bonding pad 37 (surrounding the second bonding pad 37 from three directions). However, the present invention is not limited to this, and the edges parallel to the length direction may not be covered at all by the first insulating layer 31. For example, if the edges parallel to the length direction of the mesa M are relatively far from the second bonding pad 37, electrical shorts do not easily occur even if the first insulating layer 31 is omitted. Therefore, in this case, the first insulating layer 31 can be disposed only near one side edge perpendicular to the length direction.

[0085] Meanwhile, the n-type semiconductor layer 23 is exposed through the groove 30b for forming the first extension 35a, and a relatively large electric field may also be formed between the n-type semiconductor layer 23 exposed by the groove 30b and the second bonding pad 37. Therefore, the first insulating layer 31 may cover a portion of the region of the p-type semiconductor layer 27 located between the groove 30b and the second bonding pad 37. When the second bonding pad 37 is disposed relatively closer to the groove 30b than the n-type semiconductor layer 23 exposed along the periphery of the mesa M, the first insulating layer 31 disposed near the edge of the mesa M may be omitted, and the first insulating layer 31 may be disposed only near the groove 30b.

[0086] Meanwhile, a current barrier layer 129a may be disposed below the second bonding pad 37 and the second extension portion 37a, and the current barrier layer 129a may be disposed below the transparent electrode 33, similar to the above-mentioned current barrier layer 29a.

[0087] In addition, a current barrier layer 129b may be partially disposed in the lower region of the first bonding pad 35, and a current blocking layer 129c may cover the sidewall of the groove 30a around the first bonding pad 35.

[0088] In this embodiment, the first insulating layer 31 is disposed below the transparent electrode 33 and extends to the edge of the exposed n-type semiconductor layer 23, but various modifications are possible as described with reference to Figures 3 to 6.

[0089] FIG. 11 is a schematic plan view illustrating a light-emitting diode 300 according to yet another embodiment of the present invention, and FIGS. 12a and 12b are schematic cross-sectional views taken along lines F-F' and G-G' in FIG. 11, respectively.

[0090] 11, 12a and 12b, the light emitting diode 300 is generally similar to the light emitting diode 200 described with reference to Fig. 9, but differs in that a plurality of light emitting cells R1C1 to R2C3 are disposed on a substrate 21 and these light emitting cells are electrically connected to each other. In the following, to avoid duplication, only the details that are distinguished from the above will be described.

[0091] The substrate 21 may have a rectangular or square outer shape, as shown in the plan view of Fig. 11. While the substrate 21 in each of the above-described embodiments has a generally elongated shape, the substrate 21 in this embodiment has a shape that is generally close to a square. However, this embodiment is not necessarily limited to this, and the size and shape of the substrate 21 can be selected in a variety of ways.

[0092] A plurality of light emitting cells R1C1 to R2C3 are disposed on a substrate 21. Each light emitting cell includes an n-type semiconductor layer 23 and a mesa M disposed on the n-type semiconductor layer 23. As described above, the mesa M includes the active layer 25 and the p-type semiconductor layer 27, and has an area smaller than that of the n-type semiconductor layer 23.

[0093] The light emitting cells R1C1 to R2C3 may be arranged in a matrix structure by the mesa etching region and the cell isolation region ISO. Although the drawing shows a case where the light emitting cells are arranged in a 2x3 matrix, the arrangement is not limited thereto and the light emitting cells may be arranged in various matrices of 2x2 or more.

[0094] On the other hand, the light emitting cells arranged in the same row may share the n-type semiconductor layer 23. For example, the light emitting cells R1C1, R1C2, and R1C3 arranged in the first row may share the n-type semiconductor layer, and the light emitting cells R2C1, R2C2, and R2C3 arranged in the second row may share the n-type semiconductor layer.

[0095] Meanwhile, the light emitting cells arranged in the same column may have mutually separated n-type semiconductor layers 23. For example, the n-type semiconductor layers 23 of the light emitting cells R1C1, R2C1 arranged in the first column are separated from each other by a cell isolation region ISO, the n-type semiconductor layers 23 of the light emitting cells R1C2, R2C2 arranged in the second column are also separated from each other by a cell isolation region ISO, and the n-type semiconductor layers 23 of the light emitting cells R1C3, R2C3 arranged in the third column are also separated from each other by a cell isolation region ISO.

[0096] In this embodiment, current concentration along a specific column can be prevented by the light emitting cells arranged in the same row sharing the n-type semiconductor layer 23. That is, even if current is concentrated through a specific light emitting cell in one row, the current can be dispersed again through the shared n-type semiconductor layer 23. Therefore, the current can be uniformly dispersed and supplied to each light emitting cell in the next row.

[0097] However, the present invention is not limited thereto, and each light emitting cell in the same row may be separated from each other by a cell separating region.

[0098] Each transparent electrode 33 is disposed on each light emitting cell. The transparent electrodes 33 generally have the same shape as the p-type semiconductor layer 27. However, the transparent electrodes 33 may have a smaller area than the p-type semiconductor layer 27.

[0099] Meanwhile, each light emitting cell may include a groove 130a penetrating the p-type semiconductor layer 27 and the active layer 25 to expose the n-type semiconductor layer 23. The groove 130a is surrounded by the transparent electrode 33, the p-type semiconductor layer 27, and the active layer 25. As shown in the figure, the groove 130a may have an elongated shape extending from one edge of the light emitting cell to the other edge. For example, as shown in FIG. 11, each groove 130a may have an elongated shape extending in a direction perpendicular to the cell isolation region ISO.

[0100] The grooves 130a formed in each light emitting cell generally have the same size. Therefore, the exposed areas of the n-type semiconductor layers 23 exposed by the grooves 130a also generally have the same size. Furthermore, the light emitting cells R1C1 to R2C3 generally have the same size, so that the active layers 25 may have the same light-generating areas. That is, the active layers 25 may have the same outer shape, and grooves 130a of the same size penetrate the active layers 25. Because the light-generating areas of the active layers 25 are the same, current can be uniformly distributed to the light emitting cells. However, the present invention is not limited thereto, and the area of ​​each light emitting cell may be adjusted to generate light uniformly. For example, the light emitting cells R1C2 and R2C2 arranged in the second column may have a larger area than the light emitting cells R1C1, R2C1, R1C3, and R2C3 arranged in the first and third columns.

[0101] 11, the grooves 130a may be formed at roughly the same positions in the active layers 25, but in the case of the light emitting cell R1C2 in which the second bonding pad 37 is formed, the position of the groove 130a may be slightly deformed due to the second bonding pad 37. That is, to ensure a sufficient separation distance from the second bonding pad 37, the groove 130a formed in the light emitting cell R1C2 may be slightly shorter than the grooves 130a formed in the other light emitting cells, as shown in FIG.

[0102] The first bonding pad 35 and the second bonding pad 37 may be disposed in different light emitting cell regions, as shown in Fig. 11. For example, the first bonding pad 35 may be disposed in the light emitting cell R2C2 region, and the second bonding pad 37 may be disposed on the light emitting cell R1C2.

[0103] 9, the current barrier layer 129b is partially disposed in the lower region of the first bonding pad 35, and the current blocking layer 129c covers the mesa sidewall around the first bonding pad 35. Furthermore, the current barrier layer 129a may be disposed under the second bonding pad 37 and each extension 37a. The current barrier layer 129a may be disposed between the transparent electrode 33 and the p-type semiconductor layer 27, as described in the above-mentioned embodiments.

[0104] Meanwhile, each first extension 35a extends from the first bonding pad 35, and each extension 35a contacts each n-type semiconductor layer 23 in each groove 130a. Also, each current barrier layer 129d may be arranged in an island shape below each first extension 35a.

[0105] Each first electrode connector 37b electrically connects the second extensions 37a on the adjacent light emitting cells, and each second electrode connector 36 electrically connects the adjacent first extensions 35a and second extensions 37a. To prevent electrical shorts due to each second electrode connector 36, each current blocking layer 129e may be disposed below each second electrode connector 36. Each first electrode The connecting parts 37b are insulated from the n-type semiconductor layer 23, and therefore, a current blocking layer may also be disposed below each of the first electrode connecting parts 37b. In the present embodiment, the first insulating layer 31 is disposed below each of the first electrode connecting parts 37b, but this is not necessarily limited to this, and another current blocking layer spaced apart from the first insulating layer 31 may also be disposed.

[0106] Meanwhile, in this embodiment, the first insulating layer 31 may be disposed around the light emitting cell R1C2 as described with reference to FIG. 9. That is, the first insulating layer 31 covers a portion of the p-type semiconductor layer 27 region between the n-type semiconductor layer 23 exposed by the mesa M on the light emitting cell R1C2 and the second bonding pad 37. The first insulating layer 31 may extend from the edge of the mesa M adjacent to the second bonding pad 37 to the region between the light emitting cells, as shown in FIG. 11. The first insulating layer 31 may be disposed to surround three sides of the second bonding pad 37 (surrounding the second bonding pad 37 from three directions), or may partially cover the side surfaces of the mesa M and the exposed n-type semiconductor layer 23. The first insulating layer 31 may also be modified as described with reference to FIGS. 3 to 6.

[0107] Furthermore, the first insulating layer 31 may additionally cover a portion of the region of the p-type semiconductor layer 27 between the second bonding pad 37 and the groove 130a.

[0108] FIG. 13 is a schematic cross-sectional view illustrating a light emitting device according to one embodiment of the present invention.

[0109] Referring to FIG. 13, the light emitting device may include a base 210 , a first lead 221 and a second lead 223 , bonding wires 231 and 233 , a reflector 211 , a light emitting diode 100 , and a molding part 240 .

[0110] The base 210 may be formed from a variety of materials, such as plastic or ceramic, and may be a printed circuit board or a molded lead frame.

[0111] The first lead 221 and the second lead 223 are attached to the base 210. The first lead 221 and the second lead 223 may be printed circuits printed on the base 210, or may be leads provided from a lead frame.

[0112] The light emitting diode 100 may be mounted on the base 210. As shown, the light emitting diode 100 may be mounted on the second lead 223, but is not limited to this. The light emitting diode 100 may be mounted on the first lead 221, or may be mounted on the base 210 apart from the first lead 221 and the second lead 223.

[0113] Bonding wire 231 is bonded to first bonding pad 35 of light emitting diode 100, and bonding wire 233 is bonded to second bonding pad 37. As shown in Fig. 13, bonding wire 233 may include a ball portion disposed on second bonding pad 37 and a wire portion extending therefrom. Also, first bonding wire 231 may include a ball portion disposed on first bonding pad 35 and a wire portion extending therefrom.

[0114] The ball portion of the bonding wire 233 is positioned exclusively within the upper region of the second bonding pad 37, but is not necessarily limited to this, and at least a portion of it may extend to the side of the second bonding pad 37.

[0115] The bonding wires 231 and 233 may be made of copper or silver. Copper or silver wires are more economical than gold wires, which can reduce the manufacturing cost of the light emitting device. .

[0116] The metal migration prevention layer 31 (the first insulating layer 31 described above) of the light-emitting diode 100 may be disposed at least along the edge of the p-type semiconductor layer 27 adjacent to the bonding wire 233, and can block metal from migrating along the short distance between the bonding wire 233 and the n-type semiconductor layer 23.

[0117] The reflector 211 may be disposed on the base 210 and surround the light emitting diode 100. The reflector 211 may have an inclined surface, which may reflect the light emitted from the light emitting diode 100 and improve the light emitting efficiency of the light emitting element.

[0118] The molding portion 240 may include a wavelength converting material and mold the area surrounded by the reflector 211. Therefore, the molding portion 240 may cover the bonding wires 231 and 233 and contact the first bonding pad 35 and the second bonding pad 37. The molding portion 240 also contacts the first extension portion 35a extending from the first bonding pad 35 and the second extension portion 37a extending from the second bonding pad 37. The molding portion 240 may also contact the first insulating layer 31, the transparent electrode 33, and the current blocking layer 29b. In some embodiments, the molding portion 240 may also partially contact the n-type semiconductor layer 23 exposed around the mesa M. In this embodiment, the molding portion 240 contacts various components of the light-emitting diode 100, but the largest area of ​​the molding portion 240 is in contact with the transparent electrode 33. Therefore, the light emitted from the light emitting diode 100 can be directly incident on the molding part 240 mainly through the transparent electrode 33. This improves the light efficiency of the light emitting device.

[0119] In this embodiment, a case where the light emitting diode 100 is disposed on the base 210 will be described, but the light emitting diode is not limited to the light emitting diode 100, and the light emitting diodes 100a, 100b, 200, or 300 may be disposed, or modified light emitting diodes may be disposed. In addition, the light emitting device is not limited to the specific package type described here, and may be embodied in various packages or light emitting modules using bonding wires.

[0120] Furthermore, the light emitting device can be mounted and used in various products such as lighting fixtures, displays, and automobile headlamps.

[0121] (Experimental example)

[0122] A large number of light-emitting elements (Examples) were fabricated using light-emitting diodes with the same structure as the light-emitting diode of Figure 1, in which the first insulating layer 31 was formed so as to surround three sides of the second bonding pad 37, and reliability tests were conducted using these at 60°C and a relative humidity of 90%. Meanwhile, a large number of light-emitting elements (Comparative Examples) were fabricated using light-emitting diodes in which the first insulating layer 31 was omitted from the light-emitting diode of Figure 1, and reliability tests were conducted using these under the same conditions as the Examples. In both the Comparative Examples and Examples, silver wire was used as the bonding wire.

[0123] In the light emitting devices according to the comparative examples, leakage current tended to occur in many samples as the test proceeded for a long time, resulting in many defective devices, whereas in the light emitting devices according to the examples, leakage current did not occur and no defects occurred.

[0124] FIG. 14a is an SEM image of the vicinity of the second bonding pad 37 of the light emitting diode taken from the light emitting device that has developed a defect after the high-temperature and high-humidity reliability test of the light emitting device according to the comparative example. FIG. 14b is an optical image of the periphery of the second bonding pad 37 after the high temperature and high humidity reliability test of the light emitting device according to the embodiment of the present invention.

[0125] Referring to Figure 14a, it can be seen that silver agglomerates were formed in each of the box-treated areas labeled P1, P2, and P3. Each silver agglomerate was concentrated near the edge of the mesa close to the wire ball. On the other hand, as shown in Figure 14b, no silver agglomerates were observed in the example in which the first insulating layer 31 was disposed around the second bonding pad 37 where the wire was bonded.

[0126] 15a is a graph showing the change in forward voltage of the light emitting devices according to the comparative example and the example as a function of time during a high-temperature, high-humidity reliability test. The forward voltage of the light emitting device according to the comparative example increased significantly with the passage of time during the reliability test compared to the light emitting device according to the example. While it is difficult to clearly explain the cause of the increase in forward voltage, it is believed to be due to metal migration making the electrical characteristics of the light emitting diode unstable under high-temperature, high-humidity conditions.

[0127] 15b is a graph showing the change in light output of the light emitting devices according to the comparative example and the example with respect to the time of the high temperature and high humidity reliability test. The light output of the light emitting device according to the comparative example decreased relatively faster with the time of the reliability test than that of the example.

[0128] Although various embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and the matters and elements described in one embodiment may be applied to other embodiments without departing from the technical spirit of the present invention.

Claims

1. an n-type semiconductor layer; a mesa disposed on the n-type semiconductor layer so as to expose a portion of an upper surface of the n-type semiconductor layer, the mesa including an active layer and a p-type semiconductor layer disposed on the active layer; a transparent electrode disposed on the p-type semiconductor layer and configured to be in electrical contact with the p-type semiconductor layer; a first bonding pad electrically connected to the n-type semiconductor layer; a second bonding pad electrically connected to the p-type semiconductor layer; a current blocking layer disposed under the first bonding pad and spaced apart from the transparent electrode; a first insulating layer disposed at least partially on an exposed region of the n-type semiconductor layer exposed by the mesa; a first extension extending from the first bonding pad and disposed at least partially on the first insulating layer; Equipped with the first insulating layer and the current blocking layer are spaced apart, the first insulating layer has a plurality of islands disposed along and below the first extension; The first extension is electrically connected to the n-type semiconductor layer exposed between the islands.

2. The light-emitting diode according to claim 1 , wherein the side surface of the island has an inclined surface.

3. 2. The light emitting diode of claim 1, wherein the first insulating layer is spaced from the current blocking layer by a distance of 2 μm to 5 μm.

4. The light-emitting diode according to claim 1 , wherein the first insulating layer partially covers the exposed n-type semiconductor layer.

5. 5. The light emitting diode of claim 4, wherein the first insulating layer extends along an edge of the mesa.

6. a base including a first lead and a second lead; A light-emitting diode according to any one of claims 1 to 5 mounted on the base; a plurality of bonding wires electrically connecting the light emitting diode to the first lead and the second lead.

7. The light emitting device of claim 6 , further comprising a molding portion covering the light emitting diode and the plurality of bonding wires.

8. the plurality of bonding wires are connected to the first bonding pad and the second bonding pad, respectively; The light emitting device of claim 7 , wherein the molding portion contacts the first bonding pad and the second bonding pad of the light emitting diode.

9. the plurality of bonding wires include a first bonding wire connected to the first bonding pad and a second bonding wire connected to the second bonding pad; 9. The light emitting device of claim 8, wherein the second bonding wire includes a ball portion disposed on the second bonding pad and a wire portion extending from the ball portion.

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