Processing device

Abstract

To provide a technique capable of accurately specifying a reception time even when a process of specifying a reception time is activated in response to a time measurement value exceeding a measurement range.SOLUTION: A processing device includes a timer, a storage unit, a data number counting unit, a counter, and a processing unit. In response to a time measurement value of the timer exceeding a measurement range, the processing unit acquires a count value of the reception data held in the data number counting unit at the time when the time measurement value exceeds the measurement range, sequentially reads the reception data and time information from the storage unit in the order of reception to the storage unit, and corrects the time information stored in association with the reception data using the count value and the value recorded in the counter. The present invention provides a technique configured to store modified time information together with the corresponding received data in a pre-reserved first buffer and to add a value of the counter.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a processing device, and is a technology that is effective when applied to a processing device as a gateway electronic control unit (GWECU) for an in-vehicle network. [Background technology]

[0002] Patent Document 1 (paragraphs 0079-81) describes a technique for monitoring the time at which data is received using a timestamp, with the aim of preventing unauthorized access to an in-vehicle communication device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-41200 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the timer is configured to reset the time measurement value to its initial value each time it exceeds the measurement range and to start a process to determine the reception time when the time measurement value exceeds the measurement range, if no action is taken with respect to data received between the time measurement value exceeding the measurement range and the time when the process is actually started, the data may be mistakenly recognized as data received before the time measurement value exceeded the measurement range, and the accurate reception time may not be determined.

[0005] The present disclosure aims to provide a technology that can accurately identify the reception time, even when the time measurement value is configured to return to an initial value each time the time measurement value exceeds the measurement range and to start a process to identify the reception time in response to the time measurement value exceeding the measurement range.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows. According to one embodiment, a) a timer that measures time and returns to an initial value when the measured time value exceeds the measurement range; b) a storage unit that stores received data from the network in the order of reception together with time information indicated by the timer at the time of reception of the received data; c) a data number counting unit that holds a count value indicating the number of pieces of received data stored in the storage unit; d) a counter that records the number of times the time measurement value of the timer exceeds the measurement range; e) A technology is provided which has a processing unit configured to, in response to the time measurement value of the timer exceeding the measurement range, obtain the count value of the received data held in the data counting unit at the time the measurement range is exceeded, sequentially read out the received data and time information from the storage unit in the order in which they were received in the storage unit, correct the time information stored in association with the received data using the count value and the value recorded in the counter, store the corrected time information together with the corresponding received data in a first buffer secured in advance, and increment the value of the counter. [Effects of the Invention]

[0008] According to the above embodiment, it is possible to provide a technology that can accurately identify the reception time, even if the configuration is such that a process for identifying the reception time is initiated in response to the time measurement value exceeding the measurement range. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a conceptual configuration example of a processing device according to an embodiment. [Figure 2] FIG. 2 is a timing chart illustrating a process of identifying a reception time according to an embodiment. [Figure 3] FIG. 3 is a flowchart illustrating the operation of the process of identifying the reception time according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, examples will be described with reference to the drawings. However, in the following description, the same components will be assigned the same reference numerals, and repeated explanations may be omitted. Note that the drawings may be more schematic than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention. [Example]

[0011] 1 is a block diagram showing a conceptual configuration example of a processing device according to an embodiment. The processing device 1 is a gateway electronic control unit (GWECU) connected to an in-vehicle network 2 such as a CAN (Controller Area Network) or an in-vehicle LAN (Local Area Network).

[0012] The processing device 1 includes a timer 11, a memory unit 12, a data number counting unit 13, a counter 14, a first buffer 15, a second buffer 16, a DMA (Direct Memory Access) transfer processing unit 17, and a processing unit 18. The memory unit 12 includes a first-in, first-out (FIFO) type memory (hereinafter simply referred to as FIFO). The memory unit 12 may also be simply referred to as FIFO.

[0013] The timer 11 measures time, and when the measured time value exceeds the measurement range, it returns to the initial value and continues measuring time. The timer 11 includes, for example, a clock counter that counts clocks (counting: time measurement), a data register that stores a desired count value related to a desired time (measurement range) to be measured, and a comparison circuit that compares the counter value (measured time value) of the clock counter with the desired count value of the data register. When the counter value of the clock counter matches the desired count value of the data register, the comparator outputs an overflow signal. At this time, the counter value is reset to the initial value and the clock counting operation is performed again. For example, if the clock counter is an up-counter, the initial value is zero (0). For example, if the clock counter is a down-counter, the initial value is set to the desired count value, and when the counter value of the clock counter reaches zero (0), the comparator outputs an underflow signal.

[0014] The storage unit 12 stores multiple pieces of received data received from the network 2, which is a communication path, in the order in which they are received. The storage unit 12 can be regarded as, for example, a received data buffer provided in a CAN module. The storage unit 12 has a FIFO memory structure, and is configured to store received data in the order in which it is received, and to read out the received data in the order in which it is received. By configuring the storage unit 12 as a FIFO memory structure, it is possible to easily read out data in the order in which it is received.

[0015] The storage unit 12 is electrically coupled to the timer 11 and is configured to be able to acquire time information (reception time information: timestamp) at the time of reception indicated by the timer 11 when the received data is received. The reception time information corresponds to the clock counter value (time measurement value) at the time of reception. Each piece of received data is configured to be stored in the storage unit 12 together with the reception time information acquired when the corresponding received data was received.

[0016] The data number counter 13 holds a count value indicating the number of received data stored in the memory unit 12. The data number counter 13 has a received data number counter electrically coupled to the memory unit 12. The received data number counter counts the number of received data stored in the memory unit 12 and stores the count value. The count value of the data number counter 13 can be regarded as the number J stored in the memory unit 12 (the number J stored in the FIFO).

[0017] The counter (CT) 14 records the number of times the time measurement value of the timer 11 exceeds the measurement range. When the counter (CT) 14 counts the number of overflow signals, it can be called an overflow counter. When the counter (CT) 14 counts the number of underflow signals, it can be called an underflow counter. In this specification, the counter (CT) 14 will be described as an overflow counter CT.

[0018] DMA transfer processing unit 17 is started when timer 11 exceeds its measurement range. In other words, DMA transfer processing unit 17 is started based on an overflow signal generated when timer 11 exceeds its measurement range. At the time of starting, DMA transfer processing unit 17 reads count value J held in data number counter 13 and transfers and stores count value J in second buffer 16. The value stored in second buffer 16 can be considered to be the number K of FIFO data held at the time of timer 11 overflow. By using DMA transfer processing unit 17, the number of data (count value J) when timer 11 exceeds its measurement range can be reliably stored in second buffer 16 regardless of the processing priority in processing unit 18 or the load on processing unit 18.

[0019] When the time measurement value of timer 11 exceeds the measurement range, processing unit 18 acquires the count value of the received data held in data number counter 13 at the time the measurement range is exceeded. Processing unit 18 then sequentially reads out the received data and time information (timestamp) from memory unit 12 in the order in which they were received in memory unit 12, and corrects the time information (timestamp) stored accompanying the received data using count value J of data number counter 13 and the value recorded in counter 14 (correction of time information). Processing unit 18 corrects the time information for the number of received data pieces indicated by count value J. Here, the value recorded in counter 14 is the numerical value of the number of overflow signals.

[0020] The processing unit 18 then stores the corrected time information together with the corresponding received data in the first buffer 15. The processing unit 18 is also configured to have an arithmetic function of adding "1" to the value of the counter 14 when correcting the time information.

[0021] The time information correction performed by the processing unit 18 can be configured to be initiated by an interrupt that occurs when the timer 11 exceeds the measurement range, allowing the processing unit 18 to perform time correction processing at the appropriate time.

[0022] Furthermore, the adjustment of the time information performed by processing unit 18 can be configured to start upon completion of the transfer and storage of count value J to second buffer 16 by DMA transfer processing unit 17, i.e., upon an interrupt that occurs upon completion of the DMA transfer process. Since the time adjustment process is performed after count value K is acquired in second buffer 16, processing unit 18 can perform the time adjustment process reliably.

[0023] The processing unit 18 uses the count value K transferred to the second buffer 16 as the count value J used to correct the time information.

[0024] When correcting the time information, if the number (J) of received data stored in the memory unit 12 is greater than the count value K transferred to the second buffer 16, the processing unit 18 uses the updated value obtained by adding "1" to the value of the counter 14 when correcting the time information accompanying the received data read out from the memory unit 12 in excess of the count value K.

[0025] FIG. 2 is a timing chart illustrating a process of identifying a reception time according to an embodiment.

[0026] The timer 11 measures time by counting clocks, and when the measured time value exceeds the upper limit value C1 of the measurement range, it returns to the initial value C0 and continues measuring time. For example, the timer 11 can measure a time of 6.5535 ms by counting clocks from the initial value C0 to the upper limit value C1.

[0027] In this example, the storage unit 12, which is a FIFO of a CAN module, receives the first receive data A0 from the network 2 at time t1, and receives the second receive data B0 at time t4.

[0028] The reception time information tA0 of the received data A0 received at time t1 is the timestamp when the received data A0 was received, and the reception time information tB0 of the received data B0 received at time t4 is the timestamp when the received data B0 was received. The memory unit 12 first stores the received data A0 and the reception time information tA0, and then stores the received data B0 and the reception time information tB0.

[0029] At time t1, when memory unit 12 stores received data A0 and received time information tA0, the count value (J) of data number counter 13, which is the number of data stored in memory unit 12 (number of data stored in FIFO J), changes from zero (0) to "1." Received data A0 is a signal received before timer 11 overflows at time t2.

[0030] At time t2, when the count value of timer 11 exceeds the upper limit value C1 of the measurement range, an overflow state occurs, and timer 11 generates an overflow signal. DMA transfer by DMA transfer processing unit 17 is initiated based on the overflow signal. This DMA transfer reads out count value J (here, "1"), which is the number of received data currently stored in the FIFO of the CAN module, held in data number counter 13, and transfers count value J to second buffer 16, where it is stored as the number K of data stored in the FIFO at the time of overflow. As a result, the number K of data stored in the FIFO at the time of overflow becomes "1." Storing this count value J in second buffer 16 is completed at time t4.

[0031] At time t3, the completion of the DMA transfer at time t2 triggers the DMA transfer processing unit 17 to request the processing unit 18 to activate an overflow interrupt.

[0032] At time t4, the received data B0 is received, and the received data B0 and the received time information tB0 are stored in the memory unit 12. As a result, the count value (J) of the data number counter 13 changes from "1" to "2." The received data B0 is a signal received after the timer 11 overflowed at time t2.

[0033] At time t5, the overflow interrupt process started at time t3 is executed by the processing unit 18 after a start delay time has elapsed. The start delay time is shown as an interrupt start delay in FIG.

[0034] At time t6, the processing unit 18 determines the value CT(A0) of the overflow counter CT (counter 14) when the received data A0 was received. The received data A0 is the first data stored in the memory unit 12 from the beginning, and since it is within K=1 data from the beginning of the memory unit 12, it can be determined that it is received data that was stored in the memory unit 12 before overflow. Therefore, the value CT(A0) of the overflow counter CT when the received data A0 was received is determined to be the current value of the overflow counter CT, "1".

[0035] At time t7, processing unit 18 determines the value CT(B0) of overflow counter CT at the time of receiving received data B0. Since received data B0 is the second line of received data stored in memory unit 12 from the beginning and is K=1 or later lines of received data from the beginning of memory unit 12, it can be determined that it is received data stored in memory unit 12 after overflow. Therefore, the value CT(B0) of overflow counter CT at the time of receiving received data B0 is determined to be the value obtained by adding "1" to the current value "1" of overflow counter CT, i.e., "2".

[0036] At time t8, when all of the received data A0 and B0 stored in the storage unit 12 have been received and processed, the value of the overflow counter CT is incremented by "1" to become "2".

[0037] Through the above processing, the processing unit 18 corrects the time information at the time of reception (reception time: timestamp) by the following calculation.

[0038] 1) Reception time of received data A0 = (6.5536 [ms] x value of overflow counter CT CT(A0)) + timestamp tA0 [ms] 2) Reception time of received data B0 = (6.5536 [ms] x value of overflow counter CT CT(B0)) + timestamp tB0 [ms] In this way, the process of identifying the reception time (overflow interrupt process) is triggered by the count value of timer 11 reaching the upper limit value C1 of the measurement range (overflow). In this case, data (received data B0) received during the period from when the count value of timer 11 reaches the measurement range until the process of identifying the reception time actually starts (during the interrupt start delay time) is determined to be data received after the count value of timer 11 reaches the measurement range. This makes it possible to identify the correct reception time of received data B0.

[0039] Fig. 3 is a flowchart illustrating the operation of the process of identifying the reception time according to the embodiment. Fig. 3 shows a flowchart illustrating the operation of the processing device when the count value of the timer 11 reaches the upper limit value C1 of the measurement range. Steps 30-42 of the operation of the process of identifying the reception time of the processing device 1 will be described below.

[0040] Step 30 The count value of the timer 11 reaches the measurement range (upper limit C1).

[0041] Step 31 When the count value of timer 11 reaches upper limit C1 of the measurement range (overflow), DMA transfer processing unit 17 performs DMA transfer. In DMA transfer, count value J (here, "1"), which is the number of received data stored in memory unit 12 (current FIFO of the CAN module) held in data number counter 13, is read out, and count value J is transferred to second buffer 16, where it is stored and held as the number of data stored in FIFO at the time of overflow K.

[0042] Step 32 When the DMA transfer is completed, the DMA transfer processing unit 17 requests the processing unit 18 to activate an overflow interrupt.

[0043] Step 33 The processing unit 18 starts an overflow interrupt process.

[0044] Step 34 The processing unit 18 starts the execution of the reception process of all signals stored in the storage unit 12 by the overflow interrupt process. First, the processing unit 18 acquires the first piece of reception data (for example, reception data A0 and reception timestamp tA0) from the storage unit 12.

[0045] Step 35 In the reception process, the processing unit 18 checks whether the processing order is greater than the number of data stored in the memory unit (FIFO) 12 (count value K). The processing order is the order in which the received data stored in the memory unit (FIFO) 12 is processed. The first processing order is "1". For example, in FIG. 2, the processing order of the first received data A0 is "1", the processing order of the second received data B0 is "2", and the count value K is "1". If the processing order is greater than the count value K (YES), the process proceeds to step 36. If the processing order is not greater than the count value K (NO), the process proceeds to step 37.

[0046] Step 36 The processing unit 18 adds "1" to the current value of the overflow counter (CT) 14 and uses the result as the calculation value.

[0047] Step 37 The processing unit 18 uses the current value of the overflow counter (CT) 14 as the calculation value.

[0048] Step 38 The processing unit 18 uses the calculated value of the overflow counter obtained in step 37 or step 38 to calculate the reception time information of the reception data being processed based on the following formula.

[0049] Received time = (6.5536 ms x overflow counter value for calculation (calculated value)) + received timestamp Here, the reception timestamps are tA0 and tB0.

[0050] Step 39 The processing unit 18 adds "1" to the processing order.

[0051] Step 40 The processing unit 18 checks whether all the received data in the storage unit (FIFO) 12 has been processed. If all the received data has been processed (YES), the process proceeds to step 40. If not all the received data has been processed (NO), the process proceeds to step 34, where unprocessed received data is processed.

[0052] Step 41 The processing unit 18 adds "1" to the value of the overflow counter (CT) 14. Then, the process of identifying the reception time is completed.

[0053] According to the embodiment, a technology can be provided that can accurately identify the reception time even if the configuration is such that a process for identifying the reception time is initiated when the time measurement value exceeds the measurement range.

[0054] (Variation) In the above embodiment, an example was described in which the overflow counter CT is incremented by +1 at time t8. In a modified example, consider a case in which the overflow counter CT is incremented by +1 not at time t8 but at time t5 (when an interrupt is activated) in FIG. 2. In this case, the correction method for the overflow counter CT in the reception process is changed to decrement by 1. This provides the same effect as the above embodiment, making it possible to accurately identify the reception time.

[0055] The invention made by the inventor has been specifically described above based on examples, but it goes without saying that the present invention is not limited to the above-described embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0056] 1: Processing equipment 2: Network 11: Timer 12: Storage section (FIFO) 13: Data counting section 14: Counter (overflow counter) 15: First buffer 16: Second buffer 17: DMA transfer processing section 18: Processing section.

Claims

1. a) a timer that measures time and returns to an initial value when the measured time value exceeds a measurement range; b) a storage unit that stores received data received from the network in the order of reception together with time information indicated by the timer at the time of reception of the received data; c) a data number counting unit that holds a count value indicating the number of pieces of received data stored in the storage unit; d) a counter that records the number of times the time measurement value of the timer exceeds the measurement range; e) a processing unit configured to, in response to the time measurement value of the timer exceeding the measurement range, obtain the count value of the received data stored in the data counting unit at the time the measurement range is exceeded, sequentially read out the received data and the time information from the storage unit in the order of reception into the storage unit, correct the time information stored in association with the received data using the count value and the value recorded in the counter, store the corrected time information together with the corresponding received data in a first buffer secured in advance, and increment the value of the counter; A processing device comprising:

2. a DMA transfer processing unit that is activated when the timer exceeds the measurement range, reads out the count value held in the data number counter at the time of activation, and transfers the count value to a second buffer; 2. The processing device according to claim 1, wherein the processing unit uses the count value transferred to the second buffer as the count value used in the correction.

3. 3. The processing device according to claim 1, wherein the storage unit has a FIFO structure in which the received data is read in the order in which it is received.

4. The processing device described in claim 2, characterized in that when the number of received data stored in the memory unit at the time of the correction is greater than the count value transferred to the second buffer, the processing unit uses the value of the counter after the addition when correcting the time information accompanying the received data read from the memory unit in excess of the count value.

5. 2. The processing device according to claim 1, wherein the processing unit performs the correction on the number of the received data pieces indicated by the count value.

6. 2. The processing device according to claim 1, wherein the correction of the time information is initiated in response to an interrupt that occurs when the timer exceeds the measurement range.

7. 3. The processing device according to claim 2, wherein the correction of the time information is initiated in response to an interrupt that occurs upon completion of a DMA transfer process.

8. The processing device described in claim 2, characterized in that when the number of received data stored in the memory unit at the time of the correction is less than the count value transferred to the second buffer, the processing unit uses the value of the counter minus one when correcting the time information accompanying the received data read from the memory unit in excess of the count value.

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