Processor, information processing apparatus, and information processing method

Abstract

To provide a processor, an information processing apparatus, and an information processing method which improve processing performance.SOLUTION: A lower control unit of a processor 1 determines whether or not data read in accordance with a load instruction is present in an L2 cache 151 or an LL cache 152 and processes the load instruction through data response using data stored in the L2 cache 151 or the LL cache 152, or a memory 2 on the basis of the determination result. A linkage list structure detection unit detects a first load instruction setting data having a linkage list structure as a read target. A preceding acquisition control unit predicts that the first data read in accordance with the first load instruction is not present in the L2 cache 151 or the LL cache 152 and makes the lower control unit read out the first data from the memory 2 before the processing of the first load instruction and process the first load instruction using the first data read out in advance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processor, an information processing device, and an information processing method. [Background technology]

[0002] Computers have multiple levels of cache memory between the CPU (Central Processing Unit) core and the main memory to conceal access latency to the main memory and lower-level cache memory and improve throughput insufficiency.Furthermore, as CPU cores have become faster and more many-core in recent years, it has become important to improve the cache memory hit rate and conceal cache miss latency.

[0003] The prefetching technique is being introduced as one of the methods to improve the cache memory hit rate and hide cache miss latency. The prefetching technique is a technology that reduces the occurrence of cache misses by loading data that is predicted to be used in the near future into the cache memory in cache line units in advance. There are two methods for implementing prefetching: a software method called software prefetching and a hardware method called hardware prefetching.

[0004] Hardware prefetching is a data address prediction method, such as stream prefetching or stride prefetching, and is mostly used for data arrays arranged at regular addresses. If there is a regularity in the data addresses, it is easy to determine the address to be prefetched by following the rule, and in the case of data address prediction methods, hardware prefetching can be expected to improve processing performance.

[0005] Furthermore, a prefetching technique has been proposed in which the order of memory addresses accessed during program execution is stored, and data that should be obtained in advance is fetched from memory to a cache based on the stored order, and the program is executed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-191824 Summary of the Invention [Problem to be solved by the invention]

[0007] However, there are many different types of data structures, and not all of them have a regularity in addresses. In some cases, a linked list structure is used, in which each element has reference information for the next element. In a linked list structure, there is no regularity in addresses, and the next address cannot be determined until the end of the list structure is loaded, making address prediction, such as with data address prediction, difficult. Because address prediction, such as data address prediction, is difficult in a linked list structure, improving performance through hardware prefetching has been difficult.

[0008] Furthermore, since there is a very high possibility of a cache miss when accessing memory for data with a linked list structure, a method is used to reduce latency by reading directly from memory without checking the caches at each level. However, this only addresses the problem of frequent cache misses, and it is difficult to improve the processing performance of the arithmetic unit.

[0009] Furthermore, with technology that prefetches data based on the order of accessed memory addresses, it is difficult to determine whether the data has a linked list structure, and if the data has regularity in the addresses, there is a risk that the processing performance of the arithmetic unit will decrease.

[0010] The disclosed technology has been made in view of the above, and aims to provide a processor, an information processing device, and an information processing method that improve processing performance. [Means for solving the problem]

[0011] In one aspect of the processor, information processing device, and information processing method disclosed herein, the processor includes a cache and the following units. The control unit determines whether data to be read by a load instruction exists in the cache, and processes the load instruction by performing a data response using data stored in the cache or memory based on the determination result. The linked list structure detection unit detects a first load instruction that is to read data having a linked list structure. The advance fetch control unit predicts that first data to be read by the first load instruction detected by the linked list structure detection unit does not exist in the cache, and causes the control unit to read the first data from the memory prior to processing the first load instruction, and processes the first load instruction using the first data read in advance. [Effects of the Invention]

[0012] In one aspect, the present invention can improve processing performance. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram of a processor according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a program including a load instruction that targets data having a linked list structure. [Figure 3] FIG. 3 is a diagram illustrating an example of the linked list structure detection table. [Figure 4] FIG. 4 is a diagram illustrating an example of the advance acquisition queue according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing the flow of data acquisition from memory when advance acquisition processing is not performed. [Figure 6] FIG. 6 is a diagram showing the flow of data acquisition from memory when advance acquisition processing is performed. [Figure 7]FIG. 7 is a flowchart of a linked list structure detection process performed by the processor according to the first embodiment. [Figure 8] FIG. 8 is a flowchart of a data advance acquisition process performed by the processor according to the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the advance acquisition queue according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating the hardware configuration of the information processing device. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of a processor, an information processing device, and an information processing method disclosed in the present application will be described in detail with reference to the accompanying drawings. Note that the processor, the information processing device, and the information processing method disclosed in the present application are not limited to the following embodiments. [Example]

[0015] 1 is a block diagram of a processor according to an embodiment. The processor 1 is connected to a memory 2. The processor 1 executes a given instruction using the memory 2. For example, in the case of a load instruction, the processor 1 reads data stored in the memory 2 from the memory 2 or an L1 cache 14. In addition, in the case of a write instruction, the processor 1 writes data to the memory 2. As shown in FIG. 1, the processor 1 includes an instruction control unit 11, a linked list structure detection unit 12, an L1 cache control unit 13, an L1 cache 14, a lower hierarchy 15, and a prefetch control unit 16.

[0016] 2 is a diagram showing an example of a program including a load instruction that targets data having a linked list structure. Here, a program including a load instruction that targets data having a linked list structure will be described with reference to FIG. 2.

[0017] Column 101 in Figure 2 represents the program counter (PC), and column 102 represents the execution instruction. The program counter indicates the address where the next instruction to be executed is located based on the value it holds. For example, at address 1000 indicated by the program counter, there is the execution instruction "LD x1,(x0)" (the parentheses have been changed for clarity).

[0018] Here, the execution instruction expressed as "LD xb,(xa)" (a and b are arbitrary numbers) is a load instruction that stores data stored at the location indicated by the address stored in the register with register number xa in the location indicated by the address stored in the register with register number xb. The data source xa is called the source operand, and the data destination xb is called the destination operand.

[0019] Here, we have explained the load instruction, but a source operand and a destination operand are also specified in the write instruction. Below, the address indicated by the value of the program counter will be called the address indicated by the program counter. Also, the instruction at the address indicated by the program counter will be called the instruction at that address. For example, if the program counter indicates address 1000, the instruction at address 1000 will be called the instruction at 1000.

[0020] 2 is a load instruction that stores data stored at the location indicated by the address stored in the register with register number x0 into the location indicated by the address stored in the register with register number x1. Also, instruction 1020 is a load instruction that stores the data stored in the register with register number x1 by the load instruction 1000 into the register with register number x2.

[0021] In this way, in the program shown in Figure 2, the register pointed to by the pointer of the load instruction No. 1000 is the register from which data is read in the load instruction No. 1020. In other words, the destination operand of the load instruction No. 1000 is the source operand of the load instruction No. 1020. In other words, the program shown in Figure 2 includes a load instruction that targets data having a linked list structure.

[0022] Returning to Figure 1, the explanation will continue. The instruction control unit 11 starts executing a given program and acquires an execution instruction specified in the program. The instruction control unit 11 then determines whether the acquired execution instruction is a memory access instruction. If the execution instruction is not a memory access instruction, the instruction control unit 11 executes the arithmetic processing, etc. specified in the execution instruction.

[0023] On the other hand, if the execution instruction is a memory access instruction, the instruction control unit 11 executes the following memory access process: The instruction control unit 11 notifies the linked list structure detection unit 12 of instruction information including the register numbers of the destination operand and source operand specified in the execution instruction, which is a memory access instruction, and the instruction type.

[0024] Thereafter, if the execution instruction that is a memory access instruction is a load instruction, the instruction control unit 11 receives load instruction overlap information indicating whether the instruction that updated the register of the source operand of the load instruction is a load instruction from the linked list structure detection unit 12. Next, the instruction control unit 11 issues the load instruction to the L1 cache control unit 13. In addition, the instruction control unit 11 outputs the load instruction overlap information and the program counter value of the load instruction to the L1 cache control unit 13. Thereafter, the instruction control unit 11 obtains data that is the target of reading the load instruction from the L1 cache 14.

[0025] On the other hand, if the execution instruction, which is a memory access instruction, is a write instruction rather than a load instruction, the instruction control unit 11 writes the data designated by the write instruction into the memory 2.

[0026] The linked list structure detection unit 12 has a linked list structure detection table 120. FIG. 3 is a diagram showing an example of the linked list structure detection table. As shown in FIG. 3, the linked list structure detection table 120 is a table in which register numbers and load instruction update flags corresponding to each register number are registered. The load instruction update flag is information indicating whether or not the register of the corresponding register number is set as the destination operand of another load instruction. Here, if the load instruction update flag has a value of 1, it indicates that the corresponding register number is set as the destination operand of another load instruction. Here, in FIG. 3, load instruction update flags that do not have a value of 1 are shown as blank, but for example, the linked list structure detection unit 12 may initialize the value of the load instruction update flag to 0.

[0027] Linked list structure detection unit 12 receives instruction information including the register numbers of the destination operand and source operand of the execution instruction, and the instruction type, from instruction control unit 11. Next, linked list structure detection unit 12 determines whether the execution instruction is a load instruction or not from the instruction type.

[0028] If the executable instruction is a load instruction, linked list structure detection unit 12 searches linked list structure detection table 120 to identify an entry corresponding to the register number of the destination operand of the executable instruction. Linked list structure detection unit 12 then updates the value of the load instruction update flag of the entry corresponding to the register number of the destination operand of the executable instruction to 1.

[0029] Next, linked list structure detection unit 12 searches linked list structure detection table 120 using the register number of the source operand of the executable instruction, and checks the value of the load instruction update flag of the entry corresponding to the register number of the source operand of the executable instruction. If the value of the load instruction update flag is 1, linked list structure detection unit 12 notifies instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction is a load instruction.

[0030] On the other hand, if the value of the load instruction update flag is other than 1, the linked list structure detection unit 12 notifies the instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction was not a load instruction.

[0031] On the other hand, if the execution instruction is not a load instruction, linked list structure detection unit 12 searches linked list structure detection table 120 to identify an entry corresponding to the register number of the destination operand of the execution instruction. Then, linked list structure detection unit 12 updates the value of the load instruction update flag of the entry corresponding to the register number of the destination operand of the execution instruction to 0. Thereafter, if the value of the load instruction update flag is other than 1, linked list structure detection unit 12 notifies instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction was not a load instruction.

[0032] For example, when linked list structure detection table 120 is in the state shown in FIG. 3 and load instruction 1020 in FIG. 2 is executed, linked list structure detection unit 12 sets the value of the load instruction update flag for the entry with register number x2 to 1. Next, linked list structure detection unit 12 checks the load instruction update flag for the entry with register number x1. Because the value of the load instruction update flag for the entry with register number x1 is 1, linked list structure detection unit 12 notifies instruction control unit 11 of load instruction overlay information indicating that the instruction that updated the register of the source operand of the load instruction is a load instruction.

[0033] In this way, linked list structure detection unit 12 detects a first load instruction that reads data having a linked list structure. In other words, a load instruction that linked list structure detection unit 12 determines to be a load instruction that reads data having a linked list structure is an example of a "first load instruction." For example, if the data read by a specific load instruction is data that was stored by another load instruction that was executed earlier, linked list structure detection unit 12 detects the specific load instruction as a first load instruction.

[0034] 1, the explanation will be continued. The L1 cache control unit 13 receives an input of a load instruction issued by the instruction control unit 11. The L1 cache control unit 13 also receives an input of load instruction overlap information and the program counter value of the load instruction from the instruction control unit 11.

[0035] Next, the L1 cache control unit 13 performs an L1 cache miss determination for the data to be loaded specified by the load instruction. If the corresponding data exists in the L1 cache 14, the L1 cache control unit 13 determines it as a cache hit. Then, the L1 cache control unit 13 transmits the data to be loaded specified by the load instruction from the L1 cache 14 to the instruction control unit 11 as a data response.

[0036] On the other hand, if the corresponding data does not exist in the L1 cache 14, the L1 cache control unit 13 determines that a cache miss has occurred. Then, the L1 cache control unit 13 makes a data request for the data to be loaded specified by the load instruction to the lower hierarchical level 15. Furthermore, the L1 cache control unit 13 refers to the load instruction overlap information to confirm whether the instruction that updated the register of the source operand of the load instruction to be processed is a load instruction.

[0037] If the instruction that updated the register of the source operand of the load instruction being processed is not a load instruction, the L1 cache control unit 13 determines that the data targeted by the load instruction does not have a linked list structure.Then, the L1 cache control unit 13 makes a request to the lower hierarchical level 15 to acquire the data specified in the load instruction, without issuing an instruction to perform a pre-fetch process of the specified data from the memory 2, and waits for a data response from the lower hierarchical level 15.

[0038] Thereafter, upon receiving a data response from the lower hierarchy 15, the L1 cache control unit 13 transmits the data to be read in response to the load command from the L1 cache 14 to the instruction control unit 11, thereby making the data response.

[0039] On the other hand, if the instruction that updated the register of the source operand of the load instruction to be processed is a load instruction, the L1 cache control unit 13 determines that the data to be read by the load instruction has a linked list structure. Next, the L1 cache control unit 13 sends the value of the program counter of the load instruction to the prefetch control unit 16 and instructs the prefetch control unit 16 to perform data prefetch processing. Then, the L1 cache control unit 13 requests the lower hierarchical level 15 to acquire the data to be read by the load instruction, and waits for a data response from the lower hierarchical level 15. Thereafter, upon receiving the data response from the lower hierarchical level 15, the L1 cache control unit 13 sends the data to be read by the load instruction from the L1 cache 14 to the instruction control unit 11 to perform the data response.

[0040] The advance acquisition control unit 16 includes an advance acquisition queue control unit 161 , an advance acquisition queue 162 , and an advance acquisition request generation unit 163 .

[0041] 4 is a diagram illustrating an example of the advance acquisition queue according to the embodiment 1. The advance acquisition queue 162 has a plurality of entries in which a program counter and a cache miss flag can be registered, as shown in FIG.

[0042] The pre-fetch queue control unit 161 receives an instruction for pre-fetching data together with the program counter value of the load command from the L1 cache control unit 13. Next, the pre-fetch queue control unit 161 searches the pre-fetch queue 162 using the notified program counter value.

[0043] If an entry for the notified program counter value does not exist in the pre-fetch queue 162, the pre-fetch queue control unit 161 waits until an L2 cache miss determination and an LL cache miss determination are made in the lower hierarchical level 15. Then, the pre-fetch queue control unit 161 receives, from the lower hierarchical level 15, input of cache miss information indicating whether a cache miss has occurred in both the L2 cache 151 and the LL cache 152 in the lower hierarchical level 15. Hereinafter, a cache miss in both the L2 cache 151 and the LL cache 152 in the lower hierarchical level 15 is referred to as a "lower hierarchical cache miss."

[0044] When cache miss information indicating the occurrence of a lower-level cache miss is acquired, the pre-fetch queue control unit 161 determines that the load instruction indicated by the program counter is the load instruction that caused the lower-level cache miss. That is, the pre-fetch queue control unit 161 can determine that the load instruction indicated by the program counter is the load instruction that targets data having a linked list structure and that caused the lower-level cache miss.

[0045] In this case, the pre-fetch queue control unit 161 registers the notified program counter value in a new entry of the pre-fetch queue 162, and sets the cache miss flag to 1. This allows the pre-fetch queue control unit 161 to use the program counter value to learn about load instructions that target data having a linked list structure and that cause a lower-level cache miss.

[0046] In this embodiment, when cache miss information is sent from the lower hierarchical layer 15, the pre-fetch queue control unit 161 registers the notified program counter value in a new entry, but other procedures may be used to register the program counter value in the pre-fetch queue 162. For example, when an entry for the notified program counter value does not exist in the pre-fetch queue 162, the pre-fetch queue control unit 161 registers the program counter value in a new entry and sets the cache miss flag to 0. Then, when cache miss information indicating a lower hierarchical layer cache miss is notified in the data response, the pre-fetch queue control unit 161 may update the cache miss flag of the entry for that program counter value to 1.

[0047] When the pre-fetch queue control unit 161 receives cache miss information indicating that a lower-level cache miss has not occurred, the pre-fetch queue control unit 161 determines that the load instruction indicated by the program counter is a load instruction for which a lower-level cache miss has not occurred. The pre-fetch queue control unit 161 then registers the notified program counter value in a new entry in the pre-fetch queue 162, and updates the cache miss flag to 0.

[0048] On the other hand, if an entry for the notified program counter value exists in the pre-fetch queue 162, the pre-fetch queue control unit 161 checks the cache miss flag of that entry. If the cache miss flag is 1, the pre-fetch queue control unit 161 determines that the load instruction targets data having a linked list structure and is an instruction that will cause a lower-level cache miss. Then, the pre-fetch queue control unit 161 notifies the pre-fetch request generation unit 163 of the notified program counter value and instructs the pre-fetch request generation unit 163 to execute the pre-fetch request. On the other hand, if the cache miss flag is 0, the pre-fetch queue control unit 161 ends the data pre-fetch processing.

[0049] Thereafter, the pre-fetch queue control unit 161 waits until a data response from the lower hierarchical layer 15 is sent to the L1 cache control unit 13. Then, the pre-fetch queue control unit 161 receives input of cache miss information from the lower hierarchical layer 15. Thereafter, the pre-fetch queue control unit 161 updates the cache miss flag of the entry in the pre-fetch queue 162 corresponding to the notified program counter value.

[0050] The advance acquisition request generation unit 163 receives an instruction to execute the advance acquisition request from the advance acquisition queue control unit 161. Next, the advance acquisition request generation unit 163 generates an advance acquisition request to acquire the data to be read by the load instruction at the notified program counter address from the memory 2. Then, the advance acquisition request generation unit 163 outputs the generated advance acquisition request to the lower hierarchical level 15.

[0051] In this way, the prefetch control unit 16 predicts that the first data to be read by the first load instruction detected by the linked list structure detection unit 12 does not exist in the L2 cache 151 or the LL cache 152. Then, the prefetch control unit 16 causes the lower-level control unit 150 to read the first data from the memory 2 prior to processing the first load instruction, and causes the lower-level control unit 150 to process the first load instruction using the first data that has been read in advance. Also, the cache miss flag in the prefetch queue 162 is an example of information indicating the "detection result notified from the lower-level control unit 150." That is, the prefetch control unit 16 predicts that the first data does not exist in the L2 cache 151 or the LL cache 152 based on the detection result notified from the lower-level control unit 150.

[0052] In this embodiment, the lower hierarchy 15 includes a lower level control unit 150, an L (layer) 2 cache 151, and an LL (Last Level) cache 152. However, the cache hierarchy of the lower hierarchy 15 is not limited to this.

[0053] The L2 cache 151 is a cache at the next level after the L1 cache 14. The LL cache 152 is a cache at the next level after the L2 cache 151 and is the final cache. The LL cache 152 has an area for caching data as well as a temporary save area 153 for temporarily storing data. The L2 cache 151 and the LL cache 152 are examples of a "cache."

[0054] The lower level control unit 150 controls reading of data from the L2 cache 151 and the LL cache 152 and writing of data to the L2 cache 151 and the LL cache 152 .

[0055] The lower control unit 150 receives the advance acquisition request from the advance acquisition request generation unit 163. Next, the lower control unit 150 issues an acquisition request for the data specified in the advance acquisition request to the memory 2. Thereafter, the lower control unit 150 acquires the data specified in the advance acquisition request from the memory 2. Then, the lower control unit 150 stores the advance acquired data in the temporary save area 153 of the LL cache 152.

[0056] Furthermore, the lower-level control unit 150 receives a request to acquire data that is the read target of the load instruction from the L1 cache control unit 13. Next, the lower-level control unit 150 executes an L2 cache miss determination for the data that is the load target specified by the load instruction.

[0057] If the corresponding data exists in the L2 cache 151, the lower-level control unit 150 determines that there is a cache hit. Then, the lower-level control unit 150 outputs cache miss information indicating a cache hit in the lower tier 15 to the pre-acquisition queue control unit 161. Next, the lower-level control unit 150 transmits the load target data that is the read target of the load instruction that exists in the L2 cache 151 to the L1 cache 14, and makes a data response to the L1 cache control unit 13 notifying that the corresponding data has been stored in the L1 cache 14.

[0058] On the other hand, if the corresponding data does not exist in the L2 cache 151, the lower level control unit 150 determines that there is a cache miss. Next, the lower level control unit 150 executes an LL cache miss determination for the data that is the read target of the load instruction.

[0059] If the corresponding data exists in the LL cache 152, the lower-level control unit 150 determines that there is a cache hit. Then, the lower-level control unit 150 outputs cache miss information indicating a cache hit in the lower tier 15 to the pre-acquisition queue control unit 161. Next, the lower-level control unit 150 transmits the data to be read by the load instruction existing in the LL cache 152 to the L1 cache 14 via the L2 cache 151. Then, the lower-level control unit 150 sends a data response to the L1 cache control unit 13 notifying that the corresponding data has been stored in the L1 cache 14.

[0060] On the other hand, if the corresponding data does not exist in the LL cache 152, the lower level control unit 150 determines that there is a cache miss. Then, the lower level control unit 150 outputs cache miss information indicating the occurrence of a lower level cache miss to the advance acquisition queue control unit 161.

[0061] Next, the lower-level control unit 150 determines whether or not the data to be read by the load command is stored in the temporary save area 153 of the LL cache 152. Here, if the load command targets data having a linked list structure and a cache miss has occurred in the lower tier 15, the data specified by the load command is stored in the temporary save area 153.

[0062] If the data to be read by the load command is stored in the temporary save area 153 of the LL cache 152, the lower-level control unit 150 acquires the corresponding data from the temporary save area 153 and transmits it to the L1 cache 14 via the LL cache 152 and the L2 cache 151. The lower-level control unit 150 then sends a data response to the L1 cache control unit 13 notifying that the corresponding data has been stored in the L1 cache 14.

[0063] On the other hand, if the data to be read by the load command is not stored in the temporary save area 153 of the LL cache 152, the lower-level control unit 150 requests the memory 2 to acquire the data to be read by the load command. After that, the lower-level control unit 150 acquires the data to be read by the load command from the memory 2. Next, the lower-level control unit 150 transmits the data acquired from the memory 2 to the L1 cache 14 via the LL cache 152 and the L2 cache 151, and sends a data response to the L1 cache control unit 13.

[0064] The lower-level control unit 150 is an example of a "control unit." That is, the lower-level control unit 150 determines whether data to be read by a load command is present in either the L2 cache 151 or the LL cache 152, and processes the load command by issuing a data response using data stored in the L2 cache 151 or the LL cache 152, or the memory 2, based on the determination result. The lower-level control unit 150 also detects in advance that the first data is not present in either the L2 cache 151 or the LL cache 152 by transmitting cache miss information to the prefetch control unit 16, and notifies the prefetch control unit 16 of the detection result.

[0065] In this embodiment, the pre-acquired data is stored in the temporary save area 153 and used for processing the subsequent load command, but the lower-level control unit 150 can also directly store the pre-acquired data from the memory 2 in the LL cache 152 without temporarily saving it. In this case, it is preferable that the lower-level control unit 150 perform control so as to maintain cache coherence in the LL cache 152.

[0066] When the memory 2 receives a data write command from the command control unit 11, it writes the data to a specified address. When the memory 2 receives a data acquisition request from the lower-level control unit 150, it reads out the specified data and outputs it to the lower-level control unit 150.

[0067] 5 is a diagram showing the flow of data acquisition from memory when advance acquisition processing is not performed. The flow of data acquisition from memory 2 when advance acquisition processing is not performed will be described with reference to FIG.

[0068] The instruction control unit 11 issues a data request in accordance with the load instruction (step S1).

[0069] Next, the L1 cache control unit 13 determines whether or not there is an L1 cache miss, and if the relevant data does not exist in the L1 cache 14, a data request is sent to the lower hierarchy 15 (step S2).

[0070] Next, the lower level control unit 150 determines whether there is an L2 cache miss, and if the relevant data does not exist in the L2 cache 151, it makes a data request to the LL cache 152 (step S3).

[0071] Next, the lower level control unit 150 performs an LL cache miss determination, and if the relevant data does not exist in the LL cache 152, a data acquisition request is made to the memory 2 (step S4).

[0072] In response to the data acquisition request, the memory 2 reads out the corresponding data and transmits it to the LL cache 152 (step S5).

[0073] The data sent from the memory 2 is stored in the LL cache 152, and then the data is sent to the L2 cache 151 (step S6).

[0074] Next, the data sent from the LL cache 152 is stored in the L2 cache 151, and then the data is sent to the L1 cache 14 (step S7).

[0075] Next, the data sent from the L2 cache 151 is stored in the L1 cache 14, and then the L1 cache control unit 13 sends a data response to transmit the data to the instruction control unit 11 (step S8).

[0076] The instruction control unit 11 acquires the data sent from the L1 cache 14 and completes the execution of the load instruction (step S9).

[0077] Here, if the advance acquisition process is not performed, the time required from the issuance of the load command by the command control unit 11 to the completion of the execution of the load command is time T1.

[0078] 6 is a diagram showing the flow of data acquisition from memory when advance acquisition processing is performed. The flow of data acquisition from memory 2 when advance acquisition processing is performed will be described with reference to FIG.

[0079] The instruction control unit 11 issues a data request in accordance with the load instruction (step S11).

[0080] Next, the L1 cache control unit 13 determines whether or not there is an L1 cache miss, and if the relevant data does not exist in the L1 cache 14, a data request is sent to the lower hierarchy 15 (step S12).

[0081] At this time, if a cache miss occurs in the L1 cache 14 and the target data of the load command has a linked list structure, the prefetch control unit 16 receives an instruction for prefetch processing from the L1 cache control unit 13. Then, if the cache miss flag of the entry for the program counter value indicating the load command in the prefetch queue 162 is 1, the prefetch control unit 16 makes a request to the memory 2 to acquire the corresponding data (step S13).

[0082] The memory 2 reads out the corresponding data in response to the data acquisition request from the advance acquisition control unit 16 and transmits it to the lower layer 15. The data transmitted from the memory 2 is stored in the temporary save area 153 (step S14).

[0083] In parallel with the advance acquisition process by the advance acquisition control unit 16, the lower control unit 150 performs an L2 cache miss determination, and if the corresponding data does not exist in the L2 cache 151, a data request is made to the LL cache 152 (step S15).

[0084] Next, the lower level control unit 150 performs an LL cache miss determination, and if the corresponding data does not exist in the LL cache 152, reads the corresponding data stored in the temporary save area 153 (step S16).

[0085] Next, the data read from the temporary save area 153 is stored in the LL cache 152, and then the corresponding data is sent to the L2 cache 151 (step S17).

[0086] Next, the data sent from the LL cache 152 is stored in the L2 cache 151, and then the corresponding data is sent to the L1 cache 14 (step S18).

[0087] Next, the data sent from the L2 cache 151 is stored in the L1 cache 14, and then the L1 cache control unit 13 sends a data response to the instruction control unit 11 to transmit the corresponding data (step S19).

[0088] The instruction control unit 11 acquires the data sent from the L1 cache 14 and completes the execution of the load instruction (step S20).

[0089] Here, when performing pre-fetch processing, the time it takes from when instruction control unit 11 issues a load command to when the load command is completed is time T2. That is, the processing time for a load command for data having a linked list structure can be reduced by time T3, which is the difference between time T1 and time T2. Time T3 is roughly the time it takes for lower hierarchical level 15 to fetch data from memory 2, and by performing pre-fetch processing, it is possible to hide the time it takes for lower hierarchical level 15 to fetch data from memory 2.

[0090] 7 is a flowchart of the linked list structure detection process by the processor according to the embodiment 1. Next, the flow of the linked list structure detection process by the processor 1 according to the embodiment will be described with reference to FIG.

[0091] The instruction control unit 11 starts execution of a given program and acquires an execution instruction specified in the program. If the execution instruction is a memory access instruction, the instruction control unit 11 notifies the linked list structure detection unit 12 of instruction information including the register numbers of the destination operand and source operand, and the instruction type (step S101).

[0092] Linked list structure detection unit 12 receives the input of instruction information from instruction control unit 11. Next, linked list structure detection unit 12 determines whether the execution instruction is a load instruction or not based on the instruction type included in the instruction information (step S102).

[0093] If the execution instruction is a load instruction (step S102: Yes), linked list structure detection unit 12 searches linked list structure detection table 120 to identify an entry corresponding to the register number of the destination operand of the execution instruction. Then, linked list structure detection unit 12 updates the value of the load instruction update flag of the entry corresponding to the register number of the destination operand of the execution instruction to 1 (step S103).

[0094] Next, the linked list structure detection unit 12 searches the linked list structure detection table 120 using the register number of the source operand of the execution instruction (step S104).

[0095] Then, the linked list structure detection unit 12 determines whether the value of the load instruction update flag of the entry corresponding to the register number of the source operand of the execution instruction is 1 or not (step S105).

[0096] If the value of the load instruction update flag is 1 (step S105: Yes), the linked list structure detection unit 12 notifies the instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction is a load instruction (step S106).

[0097] On the other hand, if the value of the load instruction update flag is 0 (step S105: No), the linked list structure detection unit 12 notifies the instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction was not a load instruction (step S108).

[0098] On the other hand, if the executable instruction is not a load instruction (step S102: No), linked list structure detection unit 12 searches linked list structure detection table 120 to identify an entry corresponding to the register number of the destination operand of the executable instruction. Then, linked list structure detection unit 12 updates the value of the load instruction update flag of the entry corresponding to the register number of the destination operand of the executable instruction to 0 (step S107).

[0099] Thereafter, the linked list structure detection unit 12 notifies the instruction control unit 11 of load instruction overlap information indicating that the instruction that updated the register of the source operand of the load instruction was not a load instruction (step S108).

[0100] 8 is a flowchart of the data advance acquisition process by the processor according to the embodiment 1. Next, the flow of the data advance acquisition process by the processor 1 according to the embodiment will be described with reference to FIG.

[0101] The instruction control unit 11 receives the load instruction overlap information from the linked list structure detection unit 12. Next, the instruction control unit 11 issues a memory access instruction, which is a load instruction, to the L1 cache control unit 13 (step S111). In addition, the instruction control unit 11 outputs the load instruction overlap information and the program counter value of the load instruction to the L1 cache control unit 13.

[0102] The L1 cache control unit 13 receives an input of a load command issued by the instruction control unit 11. The L1 cache control unit 13 also receives an input of load command overlap information from the instruction control unit 11. Next, the L1 cache control unit 13 determines whether a cache miss has occurred in the L1 cache 14 for the data that is the read target of the load command (step S112). If a cache hit has occurred (step S112: No), the data advance acquisition process proceeds to step S128.

[0103] On the other hand, if a cache miss occurs (step S112: Yes), the L1 cache control unit 13 makes a data request to the lower hierarchical level 15 for the data that is the read target of the load command (step S113).

[0104] Furthermore, the L1 cache control unit 13 refers to the load instruction overlap information and determines whether or not a linked list structure has been detected as the data structure of the data targeted by the load instruction (step S114).

[0105] If a linked list structure is not detected (step S114: No), the data advance acquisition process proceeds to step S127.

[0106] On the other hand, if a linked list structure is detected (step S114: Yes), the L1 cache control unit 13 transmits the program counter value of the load instruction to the advance acquisition queue control unit 161 and instructs the advance acquisition queue control unit 161 to execute advance acquisition processing of the data. The advance acquisition queue control unit 161 searches the advance acquisition queue 162 using the notified program counter value and determines whether or not there is a hit (step S115).

[0107] If the search result is a hit (step S115: Yes), the advance acquisition queue control unit 161 notifies the notified program counter value and instructs the advance acquisition request generation unit 163 to execute an advance acquisition request. The advance acquisition request generation unit 163 generates an advance acquisition request to acquire from the memory 2 the data that is the read target of the load instruction at the notified program counter address, and outputs the request to the lower layer 15 to execute an advance acquisition request for the data (step S116).

[0108] The lower-level control unit 150 receives the advance acquisition request from the advance acquisition request generation unit 163, reads the data specified in the advance acquisition request from the memory 2, and temporarily saves the advance acquired data in the temporary save area 153 of the LL cache 152 (step S117).

[0109] In parallel with the advance acquisition request, the lower-level control unit 150 receives an acquisition request for the data to be read by the load instruction from the L1 cache control unit 13. Then, the lower-level control unit 150 sequentially determines whether the relevant data is a hit in the L2 cache 151 or a hit in the LL cache 152, and determines whether a lower-level cache miss has occurred in response to the load instruction (step S118).

[0110] If a lower-level cache miss does not occur (step S118: No), the lower-level control unit 150 sends a data response to the L1 cache control unit 13 using the data that has been hit in the L2 cache 151 or the LL cache 152 (step S119).

[0111] On the other hand, if a lower-level cache miss occurs (step S118: Yes), the lower-level control unit 150 responds to the load command by sending a data response to the L1 cache control unit 13 using the data temporarily saved in the temporary save area 153 (step S120).

[0112] Furthermore, the lower level control unit 150 responds with cache miss information to the advance acquisition queue control unit 161 (step S121).

[0113] The advance acquisition queue control unit 161 checks the cache miss information, which is a response from the lower control unit 150, and determines whether a lower hierarchical cache miss has occurred (step S122). If a lower hierarchical cache miss has occurred (step S122: Yes), the data advance acquisition process proceeds to step S128.

[0114] On the other hand, if a lower-level cache miss has not occurred (step S122: No), the pre-fetch queue control unit 161 deletes the entry of the program counter value indicating the load command from the pre-fetch queue 162 (step S123). Thereafter, the data pre-fetch process proceeds to step S128.

[0115] On the other hand, if the search result does not yield a hit (step S115: No), the pre-acquisition queue control unit 161 receives a response containing cache miss information from the lower level control unit 150 (step S124).

[0116] Then, the pre-acquisition queue control unit 161 checks the cache miss information, which is a response from the lower control unit 150, and determines whether a lower hierarchical cache miss has occurred (step S125). If a lower hierarchical cache miss has not occurred (step S125: No), the data pre-acquisition process proceeds to step S127.

[0117] On the other hand, if a lower-level cache miss has occurred (step S125: Yes), the pre-fetch queue control unit 161 registers an entry of the program counter value indicating the load command in the pre-fetch queue 162 (step S126). At this time, the pre-fetch queue control unit 161 sets the cache miss flag to 1. Thereafter, the data pre-fetch processing proceeds to step S127.

[0118] The lower-level control unit 150 acquires the data to be read by the load command in accordance with the normal procedure using the L2 cache 151, the LL cache 152, and the memory 2, and sends a data response to the L1 cache control unit 13 using the acquired data (step S127). Thereafter, the data advance acquisition process proceeds to step S128.

[0119] Thereafter, the L1 cache control unit 13 transmits the data to be read by the load instruction from the L1 cache 14 to the instruction control unit 11 as a data response (step S128).

[0120] As described above, when a load instruction is issued, the processor according to this embodiment uses the linked list structure detection table to determine whether the load instruction targets data having a linked list structure. Furthermore, if the load instruction targets data having a linked list structure, the processor according to this embodiment uses the prefetch queue to determine whether the load instruction has caused a lower-level cache miss. If the load instruction targets data having a linked list structure and has caused a lower-level cache miss, the processor according to this embodiment prefetches the data from memory. Then, when processing the load instruction, the processor according to this embodiment performs a data response using the data read by the prefetch.

[0121] This reduces latency when a load command is issued to data with a linked list structure, which is highly likely to result in a cache miss, because the data is read directly from memory without checking the lower-level cache, thereby improving the processing performance of data with a linked list structure.

[0122] The data pre-fetching process described in the embodiment is more effective the deeper the cache hierarchy, but it can also be applied to a shallower cache hierarchy. For example, it can be applied even when there is only one cache hierarchy. [Example]

[0123] Next, a second embodiment will be described. The processor according to this embodiment controls to execute data pre-fetch processing preferentially for load instructions with a high probability of a lower-level cache miss. The processor according to this embodiment is also represented by the block diagram of FIG. 1. In the following explanation, explanations of the operations of the same parts as those in the first embodiment will be omitted.

[0124] 9 is a diagram illustrating an example of the advance acquisition queue according to the second embodiment. Each entry of the advance acquisition queue 162 according to the second embodiment can register a program counter, a cache miss flag, and a reliability counter. The reliability counter registers the number of responses of cache miss information indicating that a lower-level cache miss has occurred.

[0125] The pre-fetch queue control unit 161 receives an instruction for pre-fetching data together with the program counter value of the load command from the L1 cache control unit 13. Next, the pre-fetch queue control unit 161 searches the pre-fetch queue 162 using the notified program counter value.

[0126] If an entry for the notified program counter value does not exist in the pre-fetch queue 162, the pre-fetch queue control unit 161 waits until an L2 cache miss determination and an LL cache miss determination are made in the lower hierarchical layer 15. Then, the pre-fetch queue control unit 161 receives input of cache miss information from the lower hierarchical layer 15.

[0127] When cache miss information indicating the occurrence of a lower-level cache miss is acquired, the advance acquisition queue control unit 161 registers the notified program counter value in a new entry in the advance acquisition queue 162 and updates the cache miss flag to 1. Furthermore, the advance acquisition queue control unit 161 sets 1 to the reliability counter.

[0128] In addition, when cache miss information indicating that no lower-level cache miss occurred is acquired, the advance acquisition queue control unit 161 registers the notified program counter value in a new entry in the advance acquisition queue 162 and sets the cache miss flag to 0.

[0129] On the other hand, if an entry for the notified program counter value exists in the pre-fetch queue 162, the pre-fetch queue control unit 161 checks the cache miss flag of that entry. If the cache miss flag is 1, the pre-fetch queue control unit 161 notifies the pre-fetch request generation unit 163 of the notified program counter value and instructs the pre-fetch request generation unit 163 to execute the pre-fetch request. On the other hand, if the cache miss flag is 0, the pre-fetch queue control unit 161 ends the data pre-fetch process.

[0130] Thereafter, the advance acquisition queue control unit 161 waits until cache miss information is sent from the lower hierarchical layer 15. Then, the advance acquisition queue control unit 161 receives input of the cache miss information from the lower hierarchical layer 15. If the cache miss information indicates that a lower hierarchical cache miss has occurred, the advance acquisition queue control unit 161 increments by one the reliability counter of the entry in the advance acquisition queue 162 corresponding to the notified program counter value.

[0131] On the other hand, if the cache miss information indicates that a lower-tier cache miss has not occurred, the pre-fetch queue control unit 161 acquires the reliability counter of the entry of the notified program counter value in the pre-fetch queue 162. Then, the pre-fetch queue control unit 161 compares the value of the reliability counter with a predetermined threshold value.

[0132] If the value of the reliability counter is equal to or greater than the threshold, the pre-acquisition queue control unit 161 leaves the entry in the pre-acquisition queue 162. On the other hand, if the value of the reliability counter is less than the threshold, the pre-acquisition queue control unit 161 deletes the entry from the pre-acquisition queue 162.

[0133] In this way, the advance acquisition control unit 16 detects as the first load instruction a load instruction whose probability of not being present in either the L2 cache 151 or the LL cache 152 is greater than or equal to the threshold by leaving entries whose reliability counter value is greater than or equal to the threshold in the advance acquisition queue 162.

[0134] As described above, the pre-fetch queue control unit according to this embodiment increments the reliability counter in response to the occurrence of a lower-tier cache miss, and deletes entries whose reliability counters are less than the threshold from the pre-fetch queue if a lower-tier cache miss does not occur. This leaves entries related to load instructions with a high probability of cache misses in the pre-fetch queue, making it possible to execute data pre-fetch processing for load instructions with a high probability of cache misses. This allows for efficient data pre-fetch processing, thereby improving the processing performance of data having a linked list structure.

[0135] (Hardware configuration) 10 is a hardware configuration diagram of an information processing device 10. A processor 1 according to the embodiment is mounted on, for example, an information processing device 10 shown in FIG.

[0136] The information processing device 10 includes a processor 1, a memory 2, a hard disk 3, and a network interface 4. The processor 1 is connected to the memory 2, the hard disk 3, and the network interface 4 via a bus.

[0137] The hard disk 3 is an auxiliary storage device that stores various programs including an OS (Operating System), etc. The network interface 4 is a communication interface between the information processing device 10 and external devices.

[0138] The processor 1 reads a program from the hard disk 3, expands it in the memory 2, and executes it. When executing the program read from the hard disk 3, the processor 1 realizes the functions of an instruction control unit 11, a linked list structure detection unit 12, an L1 cache control unit 13, an L1 cache 14, a lower hierarchy 15, and a prefetch control unit 16. [Explanation of symbols]

[0139] 1 processor 2. Memory 11 Command control section 12 Linked list structure detection unit 13 L1 cache control unit 14 L1 cache 15 Lower Hierarchy 16 Advance acquisition control unit 120 Linked List Structure Detection Table 150 Lower control section 151 L2 cache 152 LL Cache 153 Temporary Evacuation Area 161 Advance acquisition queue control unit 162 Pre-fetch queue 163 Advance acquisition request generation unit

Claims

1. Cache and a control unit that determines whether data to be read by a load command exists in the cache, and processes the load command by performing a data response using data stored in the cache or memory based on the result of the determination; a linked list structure detection unit that detects a first load instruction that reads data having a linked list structure; an advance fetch control unit that predicts that first data to be read by the first load instruction detected by the linked list structure detection unit does not exist in the cache, and causes the control unit to read the first data from the memory prior to processing the first load instruction, and to process the first load instruction using the first data that has been read in advance; A processor comprising:

2. 2. The processor according to claim 1, wherein the linked list structure detection unit detects a specific load instruction as the first load instruction when data read by the specific load instruction is data stored by another load instruction that was executed earlier.

3. the control unit detects in advance that the first data does not exist in the previous cache and notifies the advance acquisition control unit of the detection result; The advance acquisition control unit predicts that the first data does not exist in the cache based on the detection result notified from the control unit. The processor of claim 1 .

4. 2. The processor according to claim 1, wherein the prefetch control unit detects, as the first load instruction, a load instruction whose probability of not being present in the cache is equal to or greater than a threshold value.

5. An information processing device having a processor and a memory, The processor: Cache and a control unit that determines whether data to be read by a load command exists in the cache, and processes the load command by performing a data response using data stored in the cache or the memory based on the result of the determination; a linked list structure detection unit that detects a first load instruction that reads data having a linked list structure; a prefetch control unit that predicts that first data to be read by the first load instruction detected by the linked list structure detection unit does not exist in the cache, and causes the control unit to read the first data from the memory prior to processing the first load instruction, and to process the first load instruction using the first data that has been prefetched.

1. An information processing device comprising:

6. A processor with a cache Issue a load instruction, determining whether or not data to be read by the issued load command exists in the cache, and based on the result of the determination, performing a data response using data stored in the cache or memory to process the load command; Detecting a first load instruction from the issued load instructions that is to read data having a linked list structure; predicting that first data to be read by the detected first load instruction does not exist in the cache; reading the first data from the memory prior to processing the first load instruction; The first load instruction is processed using the first data previously read. An information processing method characterized by executing processing.

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