Semiconductor wafer manufacturing method

Abstract

To provide a technology that enables good peeling after laser irradiation in laser slicing of a semiconductor single crystal.SOLUTION: A peeling processing target (3) is prepared, which includes a columnar or plate-shaped semiconductor single crystal (1, 2) having a pair of front and back main surfaces, with a peeling layer (31) provided along the main surfaces. A tensile stress is applied to the peeling processing target in a manner that separates one main surface from the other main surface, forming a stress concentration region in the peeling layer inside the outer edge (13, 23) in a radial direction centered on a central axis (CL) perpendicular to the main surfaces of the single crystal, and causing a crack to propagate from the stress concentration region, thereby peeling one side from the other side of the peeling layer in an axial direction parallel to the central axis.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor wafer manufacturing methods. [Background technology]

[0002] The wafer production method described in Patent Document 1 includes forming a separation origin and peeling a wafer. In forming the separation origin, a laser beam with a wavelength that is transparent to an ingot fixed to a support table is focused at a depth from the surface corresponding to the thickness of the wafer to be produced, and the focus and the ingot are moved relative to each other to irradiate the surface with the laser beam. This forms a modified layer and a crack that propagates from this modified layer along the c-plane. In peeling the wafer, an external force is applied to separate a plate-like object corresponding to the thickness of the wafer to be produced from the ingot, starting from the separation origin consisting of the modified layer and the crack.

[0003] Specifically, in Patent Document 1, wafer separation is performed by a pressing mechanism. The pressing mechanism includes a head that is moved up and down by a moving mechanism, and a pressing member that is rotated relative to the head. The pressing mechanism is positioned above an ingot fixed to a support table, and the head is lowered until the pressing member presses against the surface of the ingot. When the pressing member is rotated while pressed against the surface of the ingot, torsional stress is generated in the ingot, causing the ingot to fracture from the separation starting point where a modified layer and a crack have formed, allowing the wafer to be separated from the ingot. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-111143 Summary of the Invention [Problem to be solved by the invention]

[0005] Since the outer periphery of the ingot has sagging and chipping due to grinding and polishing, stress may be concentrated there, causing cracks to form from the outer periphery at positions different from the originally intended separation starting point, which may result in a deterioration in material yield. The present disclosure has been made in consideration of the above-mentioned circumstances. That is, the present disclosure provides a technology that enables good separation after laser irradiation, for example, in so-called laser slicing of a semiconductor single crystal body. [Means for solving the problem]

[0006] In one aspect of the present disclosure, a semiconductor wafer manufacturing method includes: A peeling processing target (30) is prepared, which includes a columnar or plate-shaped semiconductor single crystal (1, 2) having a pair of front and back main surfaces, and a peeling layer (31) formed by laser irradiation marks is provided along the main surface; A tensile stress is applied to the object to be peeled in a manner that separates one of the main surfaces from the other of the main surfaces, thereby forming a stress concentration region in the peeling layer inside the outer edge (13, 23) in the radial direction centered on a central axis (CL) perpendicular to the main surfaces of the single crystal body, and causing a crack to propagate from the stress concentration region, thereby peeling one side from the other side of the peeling layer in the axial direction parallel to the central axis.

[0007] In addition, in each section of the application documents, each element may be assigned a reference symbol in parentheses. In this case, the reference symbol merely indicates an example of the correspondence between the element and the specific configuration described in the embodiment described below. Therefore, the present disclosure is not limited in any way by the description of the reference symbol. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a conceptual diagram showing an outline of a semiconductor wafer manufacturing method according to a first embodiment of the present disclosure. [Figure 2] 2 is a side view showing a schematic configuration of a peeling jig used in a peeling process performed in the semiconductor wafer manufacturing method shown in FIG. 1. [Figure 3]3 is a partial cross-sectional side view showing an example of the configuration of the upper jig shown in FIG. 2. FIG. [Figure 4] FIG. 4 is a diagram showing the stress distribution inside the ingot when the upper jig shown in FIG. 3 is used. [Figure 5] 3 is a partial cross-sectional side view showing another example of the configuration of the upper jig shown in FIG. 2. FIG. [Figure 6] FIG. 6 is a diagram showing the stress distribution inside the ingot when the upper jig shown in FIG. 5 is used. [Figure 7] FIG. 10 is a conceptual diagram illustrating an outline of a semiconductor wafer manufacturing method according to a second embodiment of the present disclosure. [Figure 8] FIG. 8 is a plan view of the ingot shown in FIG. 7. [Figure 9] FIG. 10 is a side view showing a structure of a target to be subjected to peeling processing in a semiconductor wafer manufacturing method according to a third embodiment of the present disclosure. [Figure 10] FIG. 10 is a partial cross-sectional side view showing the structure of a target to be peeled in a semiconductor wafer manufacturing method according to a fourth embodiment of the present disclosure. [Figure 11] FIG. 11 is a partial cross-sectional side view showing the structure of a target to be subjected to peeling processing in a semiconductor wafer manufacturing method according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Embodiment) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following descriptions of the embodiments and their variations in the specification and the drawings are schematic or simplified for the purpose of concisely explaining the contents of the present disclosure, and are not intended to limit the contents of the present disclosure in any way. Therefore, it goes without saying that the descriptions in the drawings in this application do not necessarily coincide with the specific configurations of actual products manufactured and sold by implementing the present disclosure. In other words, unless expressly limited by the applicant in the prosecution history of this application, it goes without saying that the present disclosure should not be interpreted as being limited by the descriptions in the drawings and the corresponding descriptions of the configurations, functions, or operations of each element described below.

[0010] (First embodiment) 1, the semiconductor wafer manufacturing method according to this embodiment is a method for obtaining a semiconductor wafer 1 by using a so-called laser slicing technique to slice a semiconductor wafer 1 from a semiconductor ingot 2, which is a columnar or plate-shaped semiconductor single crystal. In this embodiment, the semiconductor wafer 1 and the semiconductor ingot 2 are SiC single crystals. Note that in this specification and the corresponding drawings, orientation flats and notches that are typically provided on the semiconductor wafer 1 and the semiconductor ingot 2 are not shown or described in order to simplify the illustrations and explanations.

[0011] The semiconductor wafer 1 is formed in the shape of a thin plate of approximately uniform thickness, having a pair of main surfaces aligned in the thickness direction, namely, a wafer front surface 11 and a wafer back surface 12. The "main surface" is the surface that is approximately perpendicular to the thickness direction of a plate-like object such as the semiconductor wafer 1, or the surface that is approximately perpendicular to the height direction of a columnar object such as the semiconductor ingot 2, and may also be referred to as the "upper surface," "lower surface," "top surface," "bottom surface," or "plate surface."

[0012] The semiconductor wafer 1 also has a wafer outer edge 13 formed of a cylindrical end face having a central axis CL parallel to the thickness direction. That is, the semiconductor wafer 1 is formed so that the wafer outer edge 13, which is the outer edge in the radial direction, is circular in a planar view parallel to the central axis CL. The terms "cylindrical" and "circular" are not strictly defined and, as mentioned above, include cases where an orientation flat or notch is present. The "radial direction" refers to a direction extending radially from the central axis CL in a plane perpendicular to the central axis CL. In other words, the "radial direction" refers to a direction in which the radius of a virtual circle extends from the center of a virtual plane whose normal is the central axis CL and whose center is the intersection of the virtual plane and the central axis CL. The "radial direction" also corresponds to the "in-plane direction." The "in-plane direction" refers to any direction perpendicular to the central axis CL. That is, the in-plane direction refers to a direction along the wafer front surface 11 or the wafer back surface 12.

[0013] In Fig. 1, for the sake of simplicity of illustration and explanation, the semiconductor wafer 1 and the semiconductor ingot 2 are shown in a side view, arranged coaxially with a common central axis CL. Furthermore, in Fig. 1, the radial direction of the semiconductor ingot 2 is indicated by a dashed arrow. The in-plane direction of the semiconductor ingot 2 is the direction along the first ingot main surface 21, the second ingot main surface 22, and the peeling layer 31 described below. Furthermore, the direction parallel to the central axis CL is referred to as the "axial direction."

[0014] The semiconductor ingot 2 is formed in a generally cylindrical shape centered on the central axis CL. The semiconductor ingot 2 has a pair of main surfaces, a first ingot main surface 21 and a second ingot main surface 22, aligned in the thickness direction or height direction, and an ingot outer edge 23 consisting of a cylindrical side surface centered on the central axis CL.

[0015] In the semiconductor wafer manufacturing method according to this embodiment, first, a semiconductor ingot 2 having a delamination layer 31 is prepared as a delamination processing target 30. The delamination layer 31 is a portion that is more susceptible to fracture than other portions, and serves as the starting point for brittle fracture due to crack propagation along the in-plane direction when an external force is applied. When provided inside the semiconductor ingot 2, the delamination layer 31 is a portion that has a lower fracture stress than other portions of the semiconductor ingot 2. The fracture stress is typically, for example, tensile fracture stress. Because the delamination layer 31 forms the main surface after delamination, it is ideally formed as a planar delamination surface along the in-plane direction (i.e., approximately parallel to the in-plane direction). However, in reality, the delamination layer 31 is formed as a thin layer extending along the in-plane direction due to variations in the depth direction during formation. The delamination layer 31 may also be referred to as a "delamination surface," "separation surface," or "separation layer."

[0016] Specifically, for example, the focal point of a laser beam having a wavelength that is transparent to the semiconductor ingot 2 is positioned at a predetermined depth from the second ingot main surface 22, and the focal point and the ingot are moved relative to each other in the in-plane direction while the laser beam is irradiated onto the second ingot main surface 22. The "predetermined depth" is a depth equivalent to the thickness of the semiconductor wafer 1 that is ultimately desired to be obtained plus a thickness equivalent to the processing allowance due to grinding and polishing after separation.

[0017] As a result, a delamination layer 31 having numerous laser irradiation marks formed in the in-plane direction is provided along the second ingot main surface 22, which is the laser irradiated surface. The laser irradiation marks consist of a modified layer formed by separation of SiC into silicon and carbon by laser beam irradiation, and cracks propagating from this modified layer along the c-plane. Note that the method of forming the delamination layer 31 on the semiconductor ingot 2 using laser irradiation was already publicly known or well known at the time of filing this application (see, for example, JP 2018-93046 A), and therefore further detailed explanation will be omitted in this specification.

[0018] The manufacturing method according to this embodiment applies a tensile stress to the separation processing target 30 in a manner that separates the first ingot main surface 21 and the second ingot main surface 22 from each other in the axial direction, causing cracks to propagate in the in-plane direction in the separation layer 31. This makes it possible to separate the separation target layer 32, which will become the source of the semiconductor wafer 1, from the semiconductor ingot 2. The separation target layer 32 is a portion on one side of the separation layer 31 in the axial direction, i.e., on the second ingot main surface 22 side, specifically, a portion between the separation layer 31 and the second ingot main surface 22, and has a predetermined thickness corresponding to the above-mentioned predetermined depth.

[0019] Here, the cylindrical side surface of the semiconductor ingot 2, i.e., the outer peripheral surface, which constitutes the ingot outer edge 23, may have geometric defects such as sagging or chipping caused by grinding and polishing when forming the outer shape of the semiconductor ingot 2 into a cylindrical shape. If stress concentrates in such geometric defects, cracks may occur from the outer peripheral surface at a different axial position from the peeling layer 31, which is the originally intended separation starting point, thereby potentially reducing material yield. Furthermore, the transmittance of the outer peripheral portion of the semiconductor ingot 2 is unstable. Therefore, if separation is attempted starting from the radial outer edge of the peeling layer 31, i.e., the ingot outer edge 23, the external stress required for separation becomes unstable.

[0020] Therefore, in this embodiment, the delamination starting point is located inside the in-plane direction, i.e., the radial direction, of the ingot outer edge 23, thereby enabling the delamination process to be performed more effectively than in the past. Specifically, in this embodiment, a stress concentration region is formed in the delamination layer 31 inside the radial direction of the ingot outer edge 23, and a crack is propagated starting from the stress concentration region, thereby delaminating, i.e., cleaving, the delamination target layer 32 from the semiconductor ingot 2.

[0021] 2 shows a state in which a semiconductor ingot 2 is attached to a peeling jig 100 for performing peeling by forming a stress concentration region in the peeling layer 31 radially inward of the outer edge 23 of the ingot. In this embodiment, peeling is performed using this peeling jig 100. The configuration and function of this peeling jig 100 will be described below.

[0022] The peeling jig 100 includes a lower jig 101 and an upper jig 102. The semiconductor ingot 2 as the peeling processing target 30 is sandwiched between the lower jig 101 and the upper jig 102 with the second ingot main surface 22 facing the lower jig 101 and the first ingot main surface 21 facing the upper jig 102. Note that in FIG. 2, for the sake of simplicity of illustration and description, the axial direction in which the lower jig 101, the semiconductor ingot 2, and the upper jig 102 are arranged, i.e., the direction along which the central axis CL extends, is defined as the up-down direction in the figure. However, the present disclosure is not limited to this configuration. In other words, the up-down direction in the figure is not necessarily parallel to the direction of gravity. The concepts of up-down in the terms "lower jig 101" and "upper jig 102" are used for convenience in light of the relationship shown in FIG. 2, and they may also be referred to as "first jig" and "second jig."

[0023] The lower jig 101 has a lower jig tension joint 111 and a lower jig main body 112. The lower jig tension joint 111, which serves as a first tension joint in the present disclosure, is connected to the lower jig main body 112 at a lower jig connection portion 113. The lower jig tension joint 111 is formed in the shape of a cylinder, an elliptical cylinder, or a polygonal cylinder, and is provided so as to protrude downward in the figure from the lower jig main body 112 along the central axis CL. The lower jig tension joint 111 is adapted to be connected to a tension breaking device (not shown).

[0024] The lower jig body 112, which serves as the first jig body in the present disclosure, is configured to hold the separation processing target 30, i.e., the semiconductor ingot 2, on the second ingot main surface 22 side. The lower jig body 112 has a lower jig front surface 114, which is the surface facing the separation processing target 30, and a lower jig back surface 115, which is the surface facing the lower jig connection portion 113. The lower jig front surface 114 and the lower jig back surface 115 are formed as flat planes perpendicular to the central axis CL. The separation processing target 30 may be fixed to the lower jig front surface 114 using a bonding material such as adhesive or double-sided tape, or may be suction-bonded by negative air pressure. Such fixing methods are already publicly known or well-known at the time of filing of the present application, and therefore will not be illustrated or described in further detail.

[0025] The upper jig 102 has an upper jig tension joint 121 and an upper jig main body 122. The upper jig tension joint 121, which serves as a second tension joint in the present disclosure, is connected to the upper jig main body 122 at an upper jig connection portion 123. The upper jig tension joint 121 is formed in the shape of a cylinder, an elliptical cylinder, or a polygonal cylinder, and is provided so as to protrude upward in the figure from the upper jig main body 122 along the central axis CL. The upper jig tension joint 121 is adapted to be connected to a tension breaking device (not shown).

[0026] The upper jig body 122, which serves as the second jig body in the present disclosure, is configured to hold the separation processing target 30, i.e., the semiconductor ingot 2, on the side of the first ingot main surface 21. The upper jig body 122 has an upper jig front surface 124, which is the surface facing the separation processing target 30, and an upper jig back surface 125, which is the surface facing the upper jig connection portion 123. The upper jig front surface 124 and the upper jig back surface 125 are formed as flat planes perpendicular to the central axis CL. The upper jig front surface 124 is formed in the same shape as the lower jig front surface 114. Similarly, the upper jig back surface 125 is formed in the same shape as the lower jig back surface 115. The separation processing target 30 may be fixed to the upper jig front surface 124 using a bonding material such as an adhesive or double-sided tape, or may be suction-bonded by negative air pressure.

[0027] In the peeling jig 100, with the peeling processing target 30 sandwiched between the lower jig 101 and the upper jig 102, the lower jig tensile joint 111 and the upper jig tensile joint 121 are arranged coaxially about an axis parallel to the central axis CL. In this embodiment, the lower jig tensile joint 111 and the upper jig tensile joint 121, i.e., the lower jig connecting portion 113 and the upper jig connecting portion 123, are disposed radially inward of the ingot outer edge 23. Specifically, in the configuration example of FIG. 2, the lower jig tensile joint 111 and the upper jig tensile joint 121 are arranged coaxially with the central axis CL. The lower jig 101 and the upper jig 102 are formed symmetrically across the abutment surface when the upper jig surface 124 and the lower jig surface 114, which have identical shapes, are abutted against each other without misalignment.

[0028] In this embodiment, an external force is applied to the lower fixture tensile joint 111 and the upper fixture tensile joint 121 using a tensile cleaving device (not shown) in a manner that separates the lower fixture tensile joint 111 and the upper fixture tensile joint 121 from the semiconductor ingot 2. Specifically, the tensile cleaving device applies an external force in a manner that separates the lower fixture tensile joint 111 and the upper fixture tensile joint 121 in the axial direction. For example, the tensile cleaving device holds one of the lower fixture tensile joint 111 and the upper fixture tensile joint 121 fixedly and separates the other from the other (i.e., "pulls"). This makes it possible to generate peeling in the peeling layer 31, starting from positions corresponding to the lower fixture tensile joint 111 and the upper fixture tensile joint 121 in the in-plane direction.

[0029] FIG. 3 shows an example configuration of the upper jig 102. As shown in FIG. 3, the upper jig tension joint 121 and the upper jig main body 122 can be configured to be joined together after being formed as separate parts or components. In the example configuration shown in FIG. 3, an engagement hole 126 that opens in the axial direction is formed on the rear surface 125 of the upper jig. Specifically, the engagement hole 126 is formed as a threaded hole. Meanwhile, the upper jig tension joint 121 is provided with an engagement portion 127 that is inserted into and engages with the engagement hole 126. Specifically, the engagement portion 127 is configured as a cylindrical screw portion that is screwed into the threaded engagement hole 126.

[0030] A semiconductor ingot 2 as a separation processing target 30 is sandwiched between an upper jig 102 having the configuration shown in FIG. 3 and a lower jig 101 having the same configuration as the upper jig 102. An external force is then applied in a manner that separates the lower jig tensile joint 111 and the upper jig tensile joint 121. The distribution of axial stress in the in-plane direction inside the semiconductor ingot 2 in this case is shown in FIG. 4. In FIG. 4, the density of the hatching represents the magnitude of the stress. In this case, as shown in FIG. 4, a ring-shaped stress concentration portion is generated that corresponds to the diameter of the upper jig connection portion 123 centered on the central axis CL, i.e., the diameter of the threaded portion between the engagement hole 126 and the engagement portion 127.

[0031] Fig. 5 shows another example configuration of the upper jig 102. As shown in Fig. 5, the upper jig tension joint 121 and the upper jig main body 122 are integrally formed. Specifically, for example, the upper jig tension joint 121 and the upper jig main body 122 can be seamlessly formed integrally from the same material.

[0032] A semiconductor ingot 2 as a separation processing target 30 is sandwiched between an upper jig 102 having the configuration shown in FIG. 5 and a lower jig 101 having the same configuration as the upper jig 102. An external force is then applied in a manner that separates the lower jig tensile joint 111 and the upper jig tensile joint 121. The distribution of axial stress in the in-plane direction inside the semiconductor ingot 2 in this case is shown in FIG. 6. In FIG. 6, the intensity of the hatching also represents the magnitude of the stress. In this case, as shown in FIG. 6, the tensile stress is large in the region inside the circle corresponding to the outer diameter of the upper jig connection portion 123, centered on the central axis CL. In other words, a stress concentration portion occurs in this region.

[0033] 2, these configuration examples enable a stress concentration region to be formed in the central portion in the in-plane direction of the peeling layer 31, and a crack to propagate from the stress concentration region as a starting point. Therefore, good peeling, i.e., cleaving, of the peeling layer 31 can be easily and stably performed using the peeling jig 100 having a simple configuration.

[0034] Second Embodiment A second embodiment of the present disclosure will be described below. Note that in the following description of the second embodiment, differences from the first embodiment will be mainly described. In addition, identical or equivalent parts in the first and second embodiments are assigned the same reference numerals. Therefore, in the following description of the second embodiment, for components having the same reference numerals as those in the first embodiment, the description of the first embodiment may be appropriately cited unless there is a technical contradiction or a special additional explanation. The same applies to the third to fifth embodiments and modified examples described below.

[0035] As shown in Figures 7 and 8, a facet region RF may be formed in a semiconductor wafer 1 or a semiconductor ingot 2. It is known that the facet region RF has a lower transmittance for the laser beam used for laser slicing than the non-facet region RN outside it. For this reason, depending on the laser irradiation method, cracks tend to propagate in the facet region RF, and the external stress required for cleaving is low. Therefore, by using the facet region RF as the cleaving starting point, it is possible to perform good cleaving while reducing the cleaving stress.

[0036] 2, in this embodiment, the peeling jig 100 is configured so that the in-plane positions of the lower jig tensile joint 111 and the upper jig tensile joint 121 are variable. The peeling jig 100 is configured so that the stress concentration position during cutting, i.e., peeling, can be set to any position by changing the in-plane positions of the lower jig tensile joint 111 and the upper jig tensile joint 121.

[0037] Specifically, for example, the upper jig 102 may have a configuration in which the upper jig tension joint 121 and the upper jig main body 122 can be attached and detached by magnetic force. Alternatively, for example, the upper jig 102 may be formed with a plurality of engagement holes 126 shown in Fig. 3. In this case, each of the plurality of engagement holes 126 is provided at a different position in the in-plane direction. The same applies to the lower jig 101.

[0038] According to this embodiment, it is possible to set a stress concentration position in a local region where the cleaving stress is low in the in-plane direction of the peeling layer 31. Therefore, according to this embodiment, it is possible to achieve good cleaving while reducing the cleaving stress with a simple device configuration.

[0039] (Third embodiment) A third embodiment of the present disclosure will be described below. In this embodiment, as shown in Fig. 9, the delamination processing object 30 is a bonded body of a semiconductor ingot 2, which is a single crystal body, and a support substrate 201. The support substrate 201 is bonded to the second ingot main surface 22, which is the main surface of the semiconductor ingot 2 on the side closer to the delamination layer 31. The support substrate 201 may be formed of, for example, a silicon semiconductor. The present disclosure can also be suitably applied to such an embodiment of the delamination processing object 30.

[0040] Specifically, for example, a portion where the direct bonding between the second ingot main surface 22 and the support substrate 201 is incomplete may occur in a region near the ingot outer edge 23. If such a portion occurs, when an attempt is made to fracture the ingot starting from the ingot outer edge 23, a wafer crack may occur starting from the boundary between the completely bonded portion and the incompletely bonded portion on the second ingot main surface 22.

[0041] In this regard, according to the present embodiment, even if such an imperfectly bonded portion occurs, a stress concentration region can be formed in the peeling layer 31 radially inward of the ingot outer edge 23, and cracks can propagate from the stress concentration region. This makes it possible to effectively suppress the occurrence of wafer cracks as described above. Note that this embodiment can be applied in combination with the first and second embodiments. That is, the position of the stress concentration portion in the in-plane direction may be fixed or may be arbitrarily set.

[0042] (Fourth embodiment) A fourth embodiment of the present disclosure will now be described. In this embodiment, as shown in Fig. 10 , a delamination processing target 30 is a bonded body of a semiconductor wafer 1, which is a single crystal body, a support substrate 201, and a device protection layer 202.

[0043] The semiconductor wafer 1 has a surface device D, which is a semiconductor device such as a MOS transistor or a light-emitting diode, formed on the wafer surface 11. A release layer 31 is formed inside the semiconductor wafer 1, i.e., between the wafer surface 11 and the wafer back surface 12, on the wafer back surface 12 side. That is, the release layer 31 is provided along the wafer back surface 12. A release target layer 32 is formed between the wafer back surface 12 and the release layer 31. A support substrate 201 is bonded to the wafer back surface 12. A device protection layer 202 is a glass substrate or the like, and is bonded to the wafer surface 11 via a bonding layer 203 so as to protect the surface device D.

[0044] The present disclosure can also be suitably applied to such a peeling processing target 30. That is, in this embodiment, a stress concentration region is formed in the peeling layer 31 radially inward of the wafer outer edge 13, and cracks can propagate starting from the stress concentration region. This makes it possible to effectively suppress the occurrence of wafer cracks as described above. Note that this embodiment can be applied in combination with the first and second embodiments. That is, the position of the stress concentration point in the in-plane direction may be fixed or may be arbitrarily set. The same applies to the fifth embodiment described later.

[0045] Fifth Embodiment A fifth embodiment of the present disclosure will be described below. In this embodiment, as shown in FIG. 11 , the peeling processing target 30 is a bonded body of a semiconductor wafer 1, which is a single crystal body, a support substrate 201, and a device protection layer 202, as in the fourth embodiment. However, in this embodiment, the peeling layer 31 is formed along the bonding interface between the semiconductor wafer 1 and the support substrate 201. In other words, the peeling layer 31 is provided along the wafer back surface 12. The present disclosure can also be suitably applied to such a peeling processing target 30. In other words, according to this embodiment, the same effects as those of the fourth embodiment can be achieved.

[0046] (Variation) The present disclosure is not limited to the above-described embodiment. Therefore, the above-described embodiment can be modified as appropriate. Representative modifications will be described below. In the following description of the modifications, differences from the above-described embodiment will be mainly described. Furthermore, the same reference numerals are used for parts that are identical or equivalent to each other in the above-described embodiment and the modifications. Therefore, in the following description of the modifications, the description of the above-described embodiment can be used as appropriate for components that have the same reference numerals as the above-described embodiment, unless there is a technical contradiction or special additional explanation.

[0047] The present disclosure is not limited to the case where the semiconductor wafer 1 and the semiconductor ingot 2 are SiC semiconductors, and may be suitably applied to other semiconductors such as Si, SiN, and AlN.

[0048] The present disclosure is not limited to the specific configurations shown in the above embodiments. That is, for example, the delamination layer 31 may be formed on the first ingot main surface 21 side. Also, Figure 2 and other figures are simplified schematic diagrams for briefly explaining the delamination jig 100 used in the present disclosure and an overview of a semiconductor wafer manufacturing method that can be implemented using the delamination jig. Therefore, the configuration of the delamination jig 100 actually manufactured and sold does not necessarily match the exemplary configuration shown in Figure 2 and other figures. Furthermore, the configuration of the delamination jig 100 actually manufactured and sold may be appropriately modified from the exemplary configuration shown in Figure 2 and other figures. Therefore, for example, referring to Figure 3, the engagement or coupling between the engagement hole 126 and the engagement portion 127 can be achieved using means other than screwing.

[0049] The present disclosure is not limited to the specific processing modes shown in the above embodiments. For example, the peeling layer 31 is not limited to those formed by laser irradiation marks. That is, the present disclosure can also be suitably applied to a peeling processing target 30 having a peeling layer 31 formed by a method other than laser irradiation. Therefore, the present disclosure can typically be suitably applied to the peeling process in so-called laser slicing technology, but is not limited to such modes.

[0050] It goes without saying that the elements constituting the above-described embodiments are not necessarily essential unless expressly stated as essential or clearly considered essential in principle. Furthermore, when numerical values ​​such as the number, amount, and range of components are mentioned, the present disclosure is not limited to those specific numerical values ​​unless expressly stated as essential or clearly limited to specific numerical values ​​in principle. Similarly, when the shape, direction, positional relationship, etc. of components are mentioned, the present disclosure is not limited to those shapes, directions, positional relationships, etc., unless expressly stated as essential or clearly limited to specific shapes, directions, positional relationships, etc. in principle.

[0051] The modified examples are not limited to the above examples. For example, other than those exemplified above, multiple embodiments may be combined with each other as long as there is no technical contradiction. Similarly, multiple modified examples may be combined with each other as long as there is no technical contradiction.

[0052] (Disclosure perspective) As is clear from the above description of the embodiments and modifications, the present specification and drawings disclose at least the following matters, although the disclosed matters are not limited to those described below.

[0053] [First viewpoint] 1. A semiconductor wafer manufacturing method, comprising: A peeling processing object (30) is prepared, which includes a columnar or plate-shaped semiconductor single crystal (1, 2) having a pair of front and back main surfaces and a peeling layer (31) provided along the main surfaces; a tensile stress is applied to the object of peeling processing in a manner that separates one of the main surfaces from the other of the main surfaces, thereby forming a stress concentration region in the peeling layer inside an outer edge (13, 23) in a radial direction centered on a central axis (CL) orthogonal to the main surfaces of the single crystal body, and a crack is propagated from the stress concentration region as a starting point, thereby peeling one side from the other side of the peeling layer in an axial direction parallel to the central axis; Semiconductor wafer manufacturing method. [Second perspective] The semiconductor is SiC. The semiconductor wafer manufacturing method according to the first aspect. [Third Perspective] The object to be peeled off is a bonded body of the single crystal body and a support substrate (201). A semiconductor wafer manufacturing method according to the first or second aspect. [Fourth viewpoint] The object to be peeled is a semiconductor wafer (1) that is the single crystal body and has a surface device (D) formed on a wafer surface (11) that is one of the main surfaces; a device protection layer (202) bonded to the wafer surface to protect the surface devices; The support substrate bonded to the wafer back surface (12) as the other main surface; and The release layer is along the backside of the wafer, A semiconductor wafer manufacturing method according to a third aspect. [Fifth viewpoint] a first jig body (112) that holds the object to be peeled on one of the main surfaces; A second jig body (122) that holds the object to be peeled on the other main surface side; a tension joint (111, 121) provided to protrude from the first jig body or the second jig body along the central axis; A peeling jig (100) having the following is used: The tension joint is disposed inside the outer edge in the radial direction, applying an external force to the tensile joint in a manner that separates the tensile joint from the single crystal body, thereby causing delamination in the delamination layer starting from a position corresponding to the tensile joint in an in-plane direction along the main surface; The semiconductor wafer manufacturing method according to any one of the first to fourth aspects. [Sixth viewpoint] The peeling jig is a first tension joint (111) that is the tension joint provided so as to protrude from the first jig body along the central axis; A second tension joint (121) that is the tension joint provided so as to protrude from the second jig body along the central axis; Equipped with applying an external force in a manner that separates the first tension joint and the second tension joint; A semiconductor wafer manufacturing method according to a fifth aspect. [Seventh viewpoint] The peeling jig has a configuration in which the position of the tensile joint in the in-plane direction is variable. A semiconductor wafer manufacturing method according to the fifth or sixth aspect. [Eighth viewpoint] The peeling layer is formed by laser irradiation marks. The semiconductor wafer manufacturing method according to any one of the first to seventh aspects. [Explanation of symbols]

[0054] 1 wafer 2 ingots 30 Peeling processing target 31 Peeling layer 100 Peeling jig 111 Lower jig tension joint 112 Lower jig body 121 Upper jig tension joint 122 Upper jig body CL center axis

Claims

1. 1. A semiconductor wafer manufacturing method, comprising: A peeling processing object (30) is prepared, which includes a columnar or plate-shaped semiconductor single crystal (1, 2) having a pair of front and back main surfaces and a peeling layer (31) provided along the main surfaces; A tensile stress is applied to the object to be peeled in a manner that separates one of the main surfaces from the other of the main surfaces, thereby forming a stress concentration region in the peeled layer inside an outer edge (13, 23) in a radial direction centered on a central axis (CL) orthogonal to the main surface of the single crystal body, and a crack is propagated from the stress concentration region as a starting point, thereby peeling one side from the other side of the peeled layer in an axial direction parallel to the central axis. Semiconductor wafer manufacturing method.

2. The semiconductor is SiC.

2. The method for manufacturing a semiconductor wafer according to claim 1.

3. The object to be peeled off is a bonded body of the single crystal body and a support substrate (201), 2. The method for manufacturing a semiconductor wafer according to claim 1.

4. The object to be peeled is a semiconductor wafer (1) that is the single crystal body and has a surface device (D) formed on a wafer surface (11) as one of the main surfaces; a device protection layer (202) bonded to the wafer surface to protect the surface devices; The support substrate bonded to the wafer back surface (12) as the other main surface; and The release layer is provided along the back surface of the wafer.

4. The method for manufacturing a semiconductor wafer according to claim 3.

5. A first jig body (112) that holds the peel processing target on one of the main surfaces; A second jig body (122) that holds the peel processing target on the other main surface side; A tension joint (111, 121) provided to protrude from the first jig body or the second jig body along the central axis; A peeling jig (100) equipped with The tension joint is disposed inside the outer edge in the radial direction, applying an external force to the tensile joint in a manner that separates the tensile joint from the single crystal body, thereby causing delamination in the delamination layer starting from a position corresponding to the tensile joint in an in-plane direction along the main surface; 5. The method for producing a semiconductor wafer according to claim 1.

6. The peeling jig is A first tension joint (111) that is the tension joint provided so as to protrude from the first jig body along the central axis; A second tension joint (121) that is the tension joint provided so as to protrude from the second jig body along the central axis; Equipped with applying an external force in a manner that separates the first tension joint and the second tension joint; 6. The method for manufacturing a semiconductor wafer according to claim 5.

7. The peeling jig has a configuration in which the position of the tensile joint in the in-plane direction is variable.

6. The method for manufacturing a semiconductor wafer according to claim 5.

8. The peeling layer is formed by laser irradiation marks.

2. The method for manufacturing a semiconductor wafer according to claim 1.

Images