Vertical cavity surface emitting laser array

Abstract

To provide a device having a plurality of vertical cavity surface emitting lasers (VCSELs) that is addressable in groups.SOLUTION: The device has a bottom RDL that is able to electrically couple a first group of VCSELs to a first bond pad through a bond pad via. The device also has a top RDL that is able to electrically couple a second group of VCSELs to a second bond pad through a group of VCSEL vias. Each VCSEL of the second group of VCSELs is electrically coupled to a corresponding VCSEL via of the group of VCSEL vias. Furthermore, the plurality of VCSEL may be positioned in any manner including random positioning.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 659,567, filed June 13, 2024, entitled "METHODS FOR AND SYSTEM OF VERTICAL CAVITY SURFACE EMITTING LASERS ARRAYS," the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002]

[0002] The limitations and drawbacks of conventional systems and methods for addressing vertical-cavity surface-emitting lasers (VCSELs) will become apparent to those skilled in the art by comparing such approaches with certain aspects of the present methods and systems described in the remainder of this disclosure with reference to the drawings. Summary of the Invention

[0003]

[0003] Systems and methods for addressing a vertical cavity surface emitting laser (VCSEL) are provided substantially as shown in and / or described in connection with at least one of the figures, and as more fully described by the claims. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 4 illustrates an example of an ohmic RDL in a system with an independently addressable VCSEL, according to various implementations of the present disclosure. [Figure 2]

[0005] FIG. 1 illustrates an example of an insulating layer in a system with independently addressable VCSELs, according to various implementations of the present disclosure. [Figure 3]

[0006] FIG. 2 illustrates an example of a first address layer in a system with independently addressable VCSELs, according to various implementations of the present disclosure. [Figure 4]

[0007] FIG. 1 illustrates an example of a top RDL in a system with independently addressable VCSELs, in accordance with various implementations of the present disclosure. [Figure 5]

[0008] 1A-1C illustrate example cross-sections of systems with independently addressable VCSELs in accordance with various implementations of the present disclosure. [Figure 6]

[0009] FIG. 1 illustrates another example of a system with independently addressable VCSELs, in accordance with various implementations of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005]

[0010] Vertical-cavity surface-emitting laser (VCSEL) arrays can be used for three-dimensional sensing applications. This disclosure describes a VCSEL array design with multiple independent channels (or subarrays). The VCSEL emitters of different channels can be mixed and arranged in irregular (e.g., random or semi-random) locations.

[0006]

[0011] Multi-channel regular arrays can be relatively simple in design and processing, as can single-channel irregular arrays. However, irregular arrays with many independent mixing channels tend to be complex in design and / or processing.

[0007]

[0012] The present disclosure provides systems and methods for designing multi-channel arrays with mixed and irregularly spaced emitters while retaining the relative simplicity of layout, processing, and design rules enjoyed by multi-channel arrays with alternating row contacts.

[0008]

[0013] Multi-channel VCSEL arrays can have sub-arrays of emitters that are physically separated from one another or intermixed in the form of alternating row contacts. These alternating row contact designs typically place rows of emitters within the centers of the row contacts. As a result, these designs tend to have regular emitter locations and the emitters are not well intermixed.

[0009]

[0014] An addressable VCSEL array can comprise an array of emitters arranged in a primary (i.e., row or column), secondary, or tertiary configuration. The emitters in the array can be arranged such that emitters belonging to different channels are spatially separated and / or interleaved within the array location.

[0010]

[0015] In an interleaved configuration, emitters belonging to different arrays are connected via multi-layer redistribution layers (RDLs), with one RDL assigned to one array channel. The RDLs are routed and overlaid to connect to the individual ohmic contacts of the VCSELs, allowing for any desired interleaved pattern.

[0011]

[0016] This disclosure describes a method for multi-channel interleaved VCSEL arrays in which ohmic RDLs and multiple RDLs can be used in conjunction to connect assigned emitters together, minimizing the number of RDLs required and thus simplifying device design and fabrication.

[0012]

[0017] Multi-channel VCSEL arrays with mixed emitters and irregular emitter locations can use vertically stacked sheet contacts. While these solutions allow for significant mixing and irregularity in emitter locations, processing and layout requirements tend to be more complex to ensure effective isolation between different channels, and there are concerns regarding capacitance between parallel sheet contacts (which can potentially limit the pulsing speed of these arrays), emitter output uniformity (as the lower sheet contacts can have significantly different series resistances for different emitters), and dielectric breakdown (as the lower sheet contacts introduce additional topology).

[0013]

[0018] This disclosure relates to the design of individual vertical cavity surface emitting lasers (VCSELs) and methods for arranging and electrically contacting the VCSELs in arrays. Such VCSEL arrays can be used, for example, for three-dimensional sensing.

[0014]

[0019] FIG. 1 illustrates an example of an ohmic RDL in a system with independently addressable VCSELs, according to various implementations of the present disclosure.

[0020] The device of Figure 1 includes a plurality of VCSELs, each of which is shown with an emitter 101 and 103. Each VCSEL of the plurality of VCSELs includes an emitter aperture that may have a diameter of, for example, 10 microns to 15 microns. Each VCSEL of the plurality of VCSELs may be operable to emit light (e.g., infrared light) at a particular wavelength (e.g., 1000 nm or less).

[0015]

[0021] 1 comprises a first continuous metal surface 102 and one or more discrete metal surfaces 104. Each VCSEL of the plurality of VCSELs is connected to an ohmic contact metal 102 or 104 in the bottom RDL.

[0016]

[0022] The first continuous metal surface 102 can electrically couple a first group of VCSELs (e.g., one VCSEL having emitter 103) to a first bond pad (see 115 in Figures 3-5) via a first bond pad via 107. As shown, the first group of VCSELs (with emitter B 103) forms channel B.

[0017]

[0023] Each discrete metal surface 104 can electrically couple one VCSEL in the second group of VCSELs (e.g., one VCSEL with emitter 101) to a second bond pad (see 111 in FIGS. 4 and 5 ) via a VCSEL via 105. As shown, the second group of VCSELs (with emitter A 101) forms channel A. Each VCSEL in the second group of VCSELs is connected to another discrete metal surface 104 in the lower RDL. Each separate discrete metal surface 104 is coupled to another VCSEL via 105. Each discrete metal surface 104 in the lower RDL is physically separated 106 from the first continuous metal surface 102. The physical separation can be between 1.5 microns and 2 microns.

[0018]

[0024] In various implementations, the first and second VCSEL groups each include one or more VCSELs from the plurality of VCSELs. For illustrative purposes, Figures 1-5 show the first and second VCSEL groups as one VCSEL per group. Figure 6 shows the first and second VCSEL groups as two or more VCSELs per group.

[0019]

[0025] 2 shows an example of an insulating layer 109 in a system with independently addressable VCSELs 101 and 103 according to various implementations of the present disclosure. The insulating layer 109 (e.g., comprising SiO2 and / or SiN) can electrically isolate the lower RDL (see 102 and 104 in FIG. 1) from the upper RDL (see upper RDL 113 in FIGS. 4 and 5). A group of VCSEL vias 105 and a first bond pad via 107 extend through the insulating layer 109.

[0020]

[0026] 3 illustrates an example of a first address layer in a system with independently addressable VCSELs according to various implementations of the present disclosure. First bond pads 115 are physically connected to (and on) insulating layer 109 and electrically coupled to a first group of VCSELs (with emitter B 103) through vias 107 and first continuous metal surface 102.

[0021]

[0027] FIG. 4 illustrates an example of an upper RDL 113 in a system with independently addressable VCSELs, according to various implementations of the present disclosure.

[0028] The second bond pad (bond pad A111) is physically connected to the top RDL 113. The top RDL 113 is operable to electrically couple the second VCSEL group 101 to the second bond pad 111 via a group of VCSEL vias 105. The second VCSEL group 101 includes one or more SCSELs from the plurality of VCSELs. The first VCSEL group 103 includes VCSELs that are different from the second VCSEL group 101. Each VCSEL in the second group of VCSELs 101 is electrically coupled to a corresponding VCSEL via 105 in the group of VCSEL vias.

[0022]

[0029] FIG. 5 illustrates an example cross section of a system with independently addressable VCSELs in accordance with various implementations of the present disclosure.

[0030] The lower RDL 123 includes dedicated or assigned ohmic contact metal for connecting each emitter to an assigned channel in the emitter array, where the RDL is connected to the device's bond pads 111 or 115. Optical paths 117 and 119 for each of the multiple VCSELs 101 and 103 pass through the aperture.

[0023]

[0031] Emitter A 101 and emitter B 103 are connected to a lower RDL 123. The lower RDL 123 is connected directly to a bond pad 115, bypassing the upper RDL 113. The lower RDL 123 comprises a continuous metal surface 102 and discrete metal surfaces 104 as shown in FIG.

[0024]

[0032] This approach, in which the bottom RDL 123 is used for addressability, reduces the number of RDL layers to achieve an interleaved-addressed VCSEL design, thereby simplifying the process flow.

[0025]

[0033] FIG. 6 illustrates another example of a system with independently addressable VCSELs in accordance with various implementations of the present disclosure.

[0034] The multiple VCSELs in Figure 6 include three channel groups. Channel A addresses a group of A devices 601 with bond pad A 607. Channel B addresses a group of B devices 603 with bond pad B 609. Channel C addresses a group of C devices 605 with bond pad C 611. All VCSELs in a particular channel (e.g., A, B, or C) are driven simultaneously.

[0026]

[0035] The group of B devices 603 and the group of C devices 605 are each bonded to a different continuous metal surface within the lower RDL. As shown, the VCSELs are randomly arranged. Also, the number of VCSELs within each particular channel / group (e.g., A, B, or C) may not need to be the same. For example, in some embodiments, the number of VCSELs in one group may be more than 10 times the number of VCSELs in another group.

[0027]

[0036] As used herein, the terms “circuit” and “circuitry” refer to physical electronic components (i.e., hardware) and any software and / or firmware (“code”) that may comprise, be executed by, and / or otherwise be associated with hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code, and a second “circuit” when executing a second one or more lines of code. As used herein, “and / or” means any one or more of the items in the list joined by “and / or.” As one example, “x and / or y” means any element of the three-element set {(x),(y),(x,y)}. As another example, “x, y, and / or z” means any element of the seven-element set {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}. As used herein, the term "exemplary" means serving as a non-limiting example, instance, or illustration. As used herein, the terms "eg" and "for example" emphasize a list of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is "operable" to perform a function whenever the circuitry has the necessary hardware and code (if any) and whether performance of the function is disabled or enabled (e.g., by a user-configurable setting, factory trim, etc.). As used herein, the term "based on" means "based at least in part on." For example, "x based on y" means that "x" is based at least in part on "y" (e.g., could also be based on z).

[0028]

[0037] Although the present methods and / or systems have been described with reference to particular implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present methods and / or systems. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is not intended that the present methods and / or systems be limited to the particular implementations disclosed, but rather that the present methods and / or systems include all implementations falling within the scope of the appended claims.

Claims

1. a plurality of vertical cavity surface emitting lasers (VCSELs); a bottom redistribution layer (RDL) operable to electrically couple the first group of VCSELs to the first bond pads via the first bond pad vias; an upper RDL operable to electrically couple the second group of VCSELs to the second bond pads through the VCSEL vias; an insulating layer operable to electrically isolate the lower RDL from the upper RDL; An apparatus comprising: the first group of VCSELs comprises one or more VCSELs of the plurality of VCSELs; the second group of VCSELs comprises one or more VCSELs of the plurality of VCSELs; the first group of VCSELs comprises different VCSELs than the second group of VCSELs; each VCSEL in the second group of VCSELs is electrically coupled to a corresponding VCSEL via in the group of VCSEL vias; Device.

2. 10. The apparatus of claim 1, each VCSEL of the plurality of VCSELs comprises an emitter aperture having a diameter of less than 15 microns; Device.

3. 10. The apparatus of claim 1, each VCSEL of the plurality of VCSELs is operable to emit light in the infrared spectrum; Device.

4. 10. The apparatus of claim 1, Each VCSEL of the plurality of VCSELs is connected to an ohmic contact metal in the lower RDL. Device.

5. 10. The apparatus of claim 1, each VCSEL in the first group of VCSELs is connected to a first continuous metal surface in the lower RDL; Device.

6. 6. The apparatus of claim 5, the first continuous metal surface is electrically coupled to the first bond pad via; Device.

7. 6. The apparatus of claim 5, each VCSEL in the second group of VCSELs is connected to a discrete metal surface in the lower RDL; Device.

8. 8. The apparatus of claim 7, each discrete metal surface connected to each VCSEL in the second group of VCSELs is electrically coupled to the corresponding VCSEL via; Device.

9. 8. The apparatus of claim 7, each discrete metal surface in the lower RDL is physically separated from the first continuous metal surface; Device.

10. 9. The apparatus of claim 8, the physical separation is between 1.5 microns and 2 microns; Device.

11. 10. The apparatus of claim 1, the VCSEL vias and the first bond pad via extend through the insulating layer; Device.

12. 10. The apparatus of claim 1, the first bond pad is physically connected to the insulating layer; Device.

13. 10. The apparatus of claim 1, the second bond pad is physically connected to the upper RDL; Device.

14. 10. The apparatus of claim 1, an optical path for each of the plurality of VCSELs passes through the insulating layer and the top RDL; Device.

15. 10. The apparatus of claim 1, the lower RDL is operable to electrically couple a third group of VCSELs to a third bond pad via a second bond pad via; Device.

16. 16. The apparatus of claim 15, each VCSEL in the third group of VCSELs is connected to a second continuous metal surface in the lower RDL; Device.

17. 17. The apparatus of claim 16, the second continuous metal surface is electrically coupled to the second bond pad via; Device.

18. 10. The apparatus of claim 1, the plurality of VCSELs are randomly arranged; Device.

19. 10. The apparatus of claim 1, the second group of VCSELs comprises more than 10 times the number of VCSELs in the first group of VCSELs; Device.

Images