Chip Deterioration Testing Equipment

JP2025500168AInactive Publication Date: 2025-01-09HAITUO INSTR (JIANGSU) CO LTD
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Patent Information

Application Number
JP2024534398
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2022-02-16
Filing Date
2022-10-12
Publication Date
2025-01-09
Estimated Expiration
Not applicable · inactive patent

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Abstract

The chip deterioration test device includes a box (1) and at least one test module (2), each of which includes a test cabin (21), a circulating air duct (22), a first honeycomb panel (28), and a second honeycomb panel (29). Several test areas (27) are provided in the test cabin (21), and each of the test areas (27) has an air outlet (272) and an air intake (271) on both inner walls of the test areas (27). The first honeycomb panel (28) is installed on the upstream side of the airflow direction of the air intake (271), and the second honeycomb panel (29) is installed on the downstream side of the airflow direction of the air outlet (272), and guide plates (221) are installed on the inner wall facing the air intake (271) in the air circulation duct (22), and each guide plate (221) is installed at an incline from the upstream to the downstream in the airflow direction from the side away from the air intake (271) to the side approaching the air intake (271). This device can meet the high heat dissipation demand when performing deterioration tests on a large number of chips arranged closely together, and can also ensure the consistency of the test environment where each chip is located, thereby improving the test efficiency and the accuracy of the test results.
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Citation Information

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