Quantum error mitigation based on scaled gates

Abstract

Techniques related to quantum error mitigation are provided. For example, one or more embodiments described herein may include a system that may include a memory that may store computer-executable components. The system may also include a processor that is operatively coupled to the memory and may execute the computer-executable components stored in the memory. The computer-executable components may include an error mitigation component that may add a set of scaled quantum gates to the quantum circuit for error mitigation. The set of scaled quantum gates may include a quantum gate and an inversion of the quantum gate. The set of scaled quantum gates may also have a rotation angle based on a pulse schedule to achieve a target stretch factor.

Description

[Technical field]

[0001] The present disclosure relates to error mitigation in quantum circuits, and more particularly to the incorporation of scaled quantum gates into quantum circuits to achieve one or more stretching factors that can control the amount of noise introduced into the quantum circuit. [Background technology]

[0002] Quantum computers can be adversely affected by inherent noise that may be present throughout the runtime of a quantum circuit. For example, qubit operations of a quantum circuit may be associated with error values ​​that arise from one or more noise sources, such as the coherence time of the qubits. The error values ​​can degrade the computational results of the quantum circuit. Furthermore, the amount of error may increase as the number of qubit operations and / or circuit components (e.g., quantum gates) increases. To mitigate the amount of error in the results of a quantum circuit, quantum error mitigation techniques introduce a controlled amount of noise into the quantum circuit to extrapolate the noise-free results.

[0003] An exemplary quantum error mitigation technique is Richardson extrapolation, in which a quantum circuit is executed with various circuit execution times, with each execution corresponding to a particular stretch factor. There are pulse-based and digital-based approaches for Richardson extrapolation. Pulse-based Chardson extrapolation is implemented by varying the pulse schedule duration for the same set of quantum gates required to execute a quantum circuit. Multiple copies of the gate set, executed by schedules with identical but different durations, can be adjusted and used to execute the same quantum circuit. Digital-based Richardson extrapolation is implemented by inserting noisy quantum gates as a way to extend quantum circuit execution times. Typically, two CNOT gates, including an identity gate, are inserted into the original quantum circuit for each CNOT gate. Summary of the Invention

[0004] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements, nor is it intended to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, and / or computer program product capable of performing quantum error mitigation of quantum operations is described.

[0005] According to one embodiment, a system is provided. The system can include a memory capable of storing computer executable components. The system can also include a processor operatively coupled to the memory and capable of executing the computer executable components stored in the memory. The computer executable components can include an error mitigation component capable of adding a set of scaled quantum gates to the quantum circuit for error mitigation. The set of scaled quantum gates can include a quantum gate and an inversion of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor. An advantage of such a system can be improved stretch factor resolution employed in error mitigation.

[0006] In some cases, the rotation angle of a set of scaled quantum gates can control the amount of noise introduced into the quantum circuit. An advantage of such a system can be the control of noise introduction through the quantum gates without having to be calibrated.

[0007] According to an embodiment, a computer-implemented method is provided. The computer-implemented method can include adding a set of scaled quantum gates to a quantum circuit for error mitigation by a system operatively coupled to a processor. The set of scaled quantum gates can include a quantum gate and an inversion of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor. An advantage of such a computer-implemented method can be the use of quantum error mitigation techniques using quantum circuits of various depths.

[0008] In some examples, the computer-implemented method may include inserting, by the system, a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit. An advantage of such a computer-implemented method may be use of the set of inserted quantum gates to facilitate the Richardson extrapolation algorithm within a cloud-based computing environment.

[0009] According to an embodiment, a computer program product for mitigating errors in a quantum circuit is provided. The computer program product may include a computer readable storage medium having program instructions embodied therein. The program instructions are executable by a processor and cause the processor to add a set of scaled quantum gates to the quantum circuit. The set of scaled quantum gates may include a quantum gate and an inversion of the quantum gate. Also, the set of scaled quantum gates may have a rotation angle based on a pulse schedule to achieve a target stretch factor. An advantage of such a computer program product may be an increase in the allowable circuit depth for execution of the Richardson extrapolation algorithm.

[0010] In some examples, the program instructions may further cause the processor to extract a calibration of the target quantum gate to determine a pulse implementation of the target quantum gate. The program instructions may also further cause the processor to generate a pulse schedule for the set of quantum gates based on the pulse implementation of the target quantum gate and the target stretch factor. The pulse schedule may scale rotation angles of the set of quantum gates to define a set of scaled quantum gates. An advantage of such a computer program product may be an enabled implementation of a dense distribution of stretch factor values. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 illustrates a block diagram of an example non-limiting system that can perform quantum error mitigation through a set of one or more inserted quantum gates implemented using a scaled pulse schedule in accordance with one or more embodiments described herein. [Figure 2A] FIG. 1 illustrates an example, non-limiting quantum circuit that may be implemented to run one or more quantum algorithms on one or more quantum computers in accordance with one or more embodiments described herein. [Figure 2B] FIG. 1 illustrates an example modified non-limiting quantum circuit created by inserting a set of one or more quantum gates based on the presence of multi-qubit quantum gates in the original quantum circuit, in accordance with one or more embodiments described herein. [Diagram 3] FIG. 1 illustrates an example non-limiting system that can generate one or more scaled pulse schedules implemented using a quantum circuit modified to include one or more sets of quantum gates in conjunction with one or more native multi-qubit quantum gates in accordance with one or more embodiments described herein. [Figure 4] FIG. 1 illustrates an example, non-limiting graph that can characterize the relationship between stretch factor values ​​and rotation angles that may be exhibited by a set of one or more quantum gates inserted into a quantum circuit in accordance with one or more embodiments described herein. [Diagram 5] FIG. 1 illustrates an exemplary, non-limiting scaled pulse schedule that may be implemented on one or more quantum circuits modified to include one or more sets of scalable quantum gates in accordance with one or more embodiments described herein. [Figure 6] FIG. 1 illustrates an example, non-limiting system that executes a modified quantum circuit using various scaled pulse schedules over multiple iterations in accordance with one or more embodiments described herein. [Figure 7] FIG. 1 illustrates an example, non-limiting system that employs the Richardson extrapolation algorithm to determine error-mitigated computational results associated with the execution of a quantum circuit using various scaled pulse schedules, in accordance with one or more embodiments described herein. [Figure 8] FIG. 1 illustrates an example non-limiting graph that may illustrate improved stretch factor resolution that may be achieved by various quantum error mitigation techniques in accordance with one or more embodiments described herein. [Figure 9] FIG. 1 illustrates a flow diagram of an exemplary, non-limiting computer-implemented method that can facilitate quantum error mitigation through the execution of various scaled pulse schedules on one or more quantum circuits that have been modified to include one or more sets of quantum gates, in accordance with one or more embodiments described herein. [Figure 10] FIG. 1 illustrates a cloud computing environment in accordance with one or more embodiments described herein. [Figure 11] FIG. 1 illustrates an abstract model layer in accordance with one or more embodiments described herein. [Figure 12] FIG. 1 is a block diagram illustrating an exemplary non-limiting operating environment that can facilitate one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following detailed description is exemplary only and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections, or in the "Description of the Preferred Embodiments" section.

[0013] One or more embodiments are now described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

[0014] Pulse-based Richardson extrapolation requires a large amount of calibration overhead for each stretched pulse schedule. For example, by implementing alternating durations, other pulse parameters may also be altered. For example, implementing an X-gate with a longer duration may require scaling the amplitude and possibly additional parameters accordingly. Thus, pulses in a schedule that include different parameter values ​​require calibration, thereby causing a large calibration overhead. Furthermore, digital-based Richardson extrapolation has limited resolution (e.g., limited range of applicable stretch factors based on gate count) and therefore cannot be used in quantum circuits with significant circuit depth. Given the problems with other implementations of quantum error mitigation (e.g., pulse-based Richardson extrapolation and digital-based Richardson extrapolation), the present disclosure may be implemented to create a solution to one or more of these problems by an error mitigation technique that inserts into a quantum circuit two-qubit gates with scaled pulse schedules to achieve one or more target stretch factors. Advantageously, one or more embodiments described herein may increase the allowable circuit depth compared to digital-based Richardson extrapolation. Additionally, various embodiments described herein may be efficiently employed within cloud computing environments, at least because the scaled two-qubit gates implemented do not need to be calibrated with each pulse schedule (e.g., as required in pulse-based Richardson extrapolation).

[0015] Various embodiments of the present invention may be directed to a computer processing system, computer-implemented method, apparatus, or computer program product, or combination thereof, that facilitates efficient, effective, and autonomous (e.g., without direct human guidance) quantum error mitigation. For example, one or more embodiments described herein may include the insertion of a set of one or more scaled two-qubit gates into a particular quantum circuit in association with one or more native gates of the quantum circuit. The gates inserted may be inverses of each other such that the added gates constitute an identity of the original quantum circuit. Additionally, a pulse schedule of the added two-qubit gate may be scaled to achieve one or more target stretch factors. For example, a rotation angle of the added two-qubit gate may be based on a scaled pulse schedule relative to one or more native gates of the quantum circuit. The quantum circuit including the added two-qubit gate may be executed using multiple pulse schedules, with each execution achieving a respective stretch factor and, thereby, a respective amount of noise introduced. After multiple executions of the modified quantum circuit, the computational results may be extrapolated to a near-zero noise determination.

[0016] A computer processing system, computer-implemented method, apparatus, or computer program product, or any combination thereof, employs hardware and / or software to solve problems that are highly technical in nature, not abstract, and cannot be performed as a series of mental activities by a human (e.g., quantum error mitigation). For example, one or more individuals cannot execute a quantum circuit with various stretch factors controlled by scaled quantum gates to extrapolate a near-zero noise computation.

[0017] Also, one or more embodiments described herein may constitute a technical improvement over conventional quantum error mitigation by modifying a particular quantum circuit to include a set of one or more quantum gates with a scaled pulse schedule to achieve a target stretch factor. Moreover, various embodiments described herein may represent a technical improvement over conventional quantum error mitigation by employing a set of one or more scaled quantum gates without the large amount of calibration overhead typically required to implement a target pulse schedule. Furthermore, one or more embodiments described herein may have practical applications by allowing fine resolution of the possible stretch factor values ​​that may be implemented by the set of one or more inserted quantum gates. For example, various embodiments described herein may include a parametric distribution of possible stretch factors to facilitate greater circuit depth than standard quantum error mitigation techniques.

[0018] FIG. 1 illustrates a block diagram of an exemplary, non-limiting system 100 capable of mitigating error values ​​in one or more quantum circuit computations. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. Aspects of a system (e.g., system 100, etc.), apparatus, or process in various embodiments of the invention may comprise one or more machine-executable components embodied in one or more machines (e.g., embodied in one or more computer-readable media associated with one or more machines). Such components, when executed by one or more machines (e.g., computers, computing devices, or virtual machines, or combinations thereof, etc.), may cause the machines to perform the operations described.

[0019] As shown in FIG. 1, the system 100 may include one or more servers 102, one or more networks 104, input devices 106, and / or quantum computers 108. The server 102 may include an error mitigation component 110. The error mitigation component 110 may further include a gating component 114. The server 102 may also include or be otherwise associated with at least one memory 116. The server 102 may further include a system bus 118 that may couple to various components, such as, but not limited to, the error mitigation component 110 and associated components, the memory 116, and / or a processor 120. Although the server 102 is shown in FIG. 1, in other embodiments, a plurality of devices of various types may be associated with or include the features shown in FIG. 1. Additionally, the server 102 may be in communication with one or more cloud computing environments.

[0020] The one or more networks 104 may include wired and wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN). For example, the server 102 may communicate with the one or more input devices 106 and / or the quantum computer 108 (and vice versa) using substantially any desired wired or wireless technology, including, but not limited to, cellular, WAN, wireless fidelity (WiFi), Wi-Max, WLAN, or Bluetooth technology, or a combination thereof. Additionally, in the illustrated embodiment, the error mitigation component 110 may be provided on the one or more servers 102, although it should be understood that the architecture of the system 100 is not so limited. For example, the error mitigation component 110 or one or more components of the error mitigation component 110 may reside on another computing device, such as another server device, or a client device, or a combination thereof.

[0021] The one or more input devices 106 may include one or more computerized devices, including, but not limited to, a personal computer, a desktop computer, a laptop computer, a mobile phone (e.g., a smartphone), a computerized tablet (e.g., equipped with a processor), a smart watch, a keyboard, a touch screen, or a mouse, or a combination thereof. The one or more input devices 106 may be employed to input one or more quantum circuits 122 or stretch factor settings 124 or both into the system 100, thereby sharing such data with the server 102 (e.g., via a direct connection or via one or more networks 104, or both). For example, the one or more input devices 106 may transmit data to the communication component 112 (e.g., via a direct connection or via one or more networks 104, or both). Additionally, the one or more input devices 106 may include one or more displays capable of presenting one or more outputs generated by the system 100 to a user. For example, the one or more displays may include, but are not limited to, a cathode ray tube display (CRT), a light-emitting diode display (LED), an electroluminescent display (ELD), a plasma display panel (PDP), a liquid crystal display (LCD), or an organic light-emitting diode display (OLED), or combinations thereof.

[0022] In various embodiments, one or more input devices 106 and / or one or more networks 104 can be employed to input one or more settings and / or commands into the system 100. For example, in various embodiments described herein, one or more input devices 106 can be employed to operate and / or manipulate the server 102 and / or associated components. Additionally, one or more input devices 106 can be employed to display one or more outputs (e.g., displays, data, and / or visualizations) generated by the server 102 and / or associated components. Additionally, in one or more embodiments, one or more input devices 106 can be included within and / or operably coupled to a cloud computing environment.

[0023] For example, one or more input devices 106 may be employed to input one or more quantum circuits 122 into the system 100. In various embodiments, the error mitigation component 110 may employ various quantum error mitigation techniques described herein to mitigate the amount of error associated with computation resulting from executing one or more quantum circuits 122. For example, one or more quantum computers 108 may execute one or more quantum algorithms using one or more quantum circuits 122. One or more quantum circuits 122 may represent computational routines of one or more quantum computers 108. For example, one or more quantum circuits 122 may represent one or more coherent quantum operations on quantum data. In various embodiments, one or more quantum circuits 122 may delineate the number of qubits or the connectivity of qubits or both employed by one or more quantum computers 108 to execute one or more quantum algorithms. For example, one or more quantum circuits 122 may represent, with respect to one or more qubits, initialization and reset operations (e.g., initialization of one or more qubits to one or more desired states), quantum gates (e.g., Hadamard gates, phase shifter gates, controlled gates, uncontrolled gates, phase rotation gates, controlled-NOT gates (CNOT) gates, single-qubit gates, multi-qubit gates, cross-resonant gates, or the like, or combinations thereof), measurement operations, and / or classically controlled quantum gates.

[0024] Additionally, one or more input devices 106 may be employed to input one or more stretch factor settings 124 into the system 100 (e.g., where the one or more stretch factor settings 124 may be stored, for example, in one or more memories 116). In various embodiments, one or more quantum gates of one or more quantum circuits 122 may be driven according to one or more pulse schedules. The pulse schedule may represent a sequence of microwave pulses (e.g., generated by one or more quantum computers 108), which may be parameterized, for example, by waveform, amplitude, or time, or a combination thereof. In various embodiments, one or more parameters of the microwave pulses driving the quantum gates may be altered by increments defined by a stretch factor value. For example, the stretch factor value may define incremental changes to the waveform, amplitude, or time, or a combination thereof, of the driving microwave pulses. For example, the stretch factor value may define a stretch in time or amplitude, or both, of the microwave pulses. In another example, the stretch factor value can define a scaling of a pulse time, a rise time / fall time, a latency time, a constant amplitude portion of a pulse, or the like, or a combination thereof. The stretch factor value can thereby define an amount of modification to one or more parameters of a microwave pulse driving a quantum gate. In various embodiments, one or more stretch factor settings 124 can define a range of stretch factor values ​​implemented by the error mitigation component 110. Additionally, one or more stretch factor settings 124 can define a microwave pulse parameter that is modified by the stretch factor value. For example, the quantum circuit 122 can be executed through multiple iterations, each iteration using a respective stretch factor value from the stretch factor settings 124. By modifying the pulse schedule of the quantum gate with each iteration of execution, the quantum circuit 122 can generate a different amount of noise associated with the same quantum computation with each execution.In one or more embodiments, one or more expansion factor settings 124 may be generated by the error mitigation component 110, or the error mitigation component 110 may use one or more default expansion factor settings 124 (stored in one or more memories 116), or both.

[0025] In various embodiments, one or more quantum computers 108 may comprise quantum hardware devices that can exploit the laws of quantum mechanics (e.g., superposition and / or entanglement) to facilitate computational processing (e.g., while satisfying the DiVincenzo criterion). In one or more embodiments, one or more quantum computers 108 may comprise a quantum data plane, a control processor plane, a control and measurement plane, and / or qubit technology.

[0026] In one or more embodiments, the quantum data plane can include one or more quantum hardware components that include physical qubits, structures for fixing the positions of the qubits, and / or supporting circuitry. The supporting circuitry can, for example, facilitate measurement of the states of the qubits and / or perform gate operations on the qubits (e.g., in the case of gate-based systems). In some embodiments, the supporting circuitry can include a wired network that can enable multiple qubits to communicate with each other. Additionally, the wired network can facilitate transmission of control signals via direct electrical connections or electromagnetic radiation (e.g., optical signals, microwave signals, or low frequency signals, or combinations thereof). For example, the supporting circuitry can include one or more superconducting resonators operably coupled to one or more qubits. As described herein, the term "superconducting" can characterize a material that exhibits superconducting properties below a superconducting critical temperature, such as aluminum (e.g., superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., superconducting critical temperature of 9.3 Kelvin). Additionally, those skilled in the art will recognize that other superconductor materials (e.g., hydride superconductors such as lithium hydride / magnesium hydride alloys) may be used in the various embodiments described herein.

[0027] In one or more embodiments, the control processor plane can identify and / or trigger Hamiltonian sequences of quantum gate operations and / or measurements that execute programs (e.g., provided by a host processor, such as server 102 via error mitigation component 110) to implement quantum algorithms (e.g., defined by one or more quantum circuits 122). For example, the control processor plane can translate compiled code into commands for the control and measurement planes. In one or more embodiments, the control processor plane can further execute one or more quantum error correction algorithms.

[0028] In one or more embodiments, the control and measurement plane can convert digital signals generated by the control processor plane, which can specify a quantum operation to be performed, into analog control signals for performing operations on one or more qubits in the quantum data plane, and the control and measurement plane can convert one or more analog measurement outputs of qubits in the data plane into classical binary data that can be shared with other components of system 100 (e.g., via the control processor plane, such as with error mitigation component 110).

[0029] Those skilled in the art will recognize that a variety of qubit technologies can provide the basis for one or more qubits of one or more quantum computers 108. Additionally, the control and measurement plane can include a laser or microwave source directed at one or more of the ions to affect the quantum state of the ions, a laser to cool the ions or enable measurement of the ions, or both, and / or one or more photon detectors to measure the state of the ions. In another instance, a superconducting qubit (e.g., a superconducting quantum interference device (SQUID) or the like) can be a lithographically defined electronic circuit that can be cooled to millikelvin temperatures to exhibit quantized energy levels (e.g., due to quantized states of electronic charge or magnetic flux). A superconducting qubit can be based on Josephson junctions, such as a transmon qubit. A superconducting qubit can also be compatible with microwave control electronics and can be utilized with gate-based technologies or integrated cryogenic control. Further exemplary qubit technologies can include, but are not limited to, photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically gated or electrically gated), or topological qubits, or combinations thereof, etc.

[0030] In one or more embodiments, the communications component 112 can receive one or more quantum circuits 122 from one or more input devices 106 (e.g., via a direct electrical connection, or via one or more networks 104, or both) and share that data with various associated components of the error mitigation component 110. Additionally, the communications component 112 can facilitate the sharing of data between the error mitigation component 110 and one or more quantum computers 108, or vice versa, or both (e.g., via a direct electrical connection, or via one or more networks 104, or both).

[0031] In various embodiments, the gate component 114 can analyze one or more quantum circuits 122 and identify the native multi-qubit quantum gates of the quantum circuits 122. For example, the gate component 114 can identify each multi-qubit quantum gate included in one or more quantum circuits 122, such as a two-qubit quantum gate. In one or more embodiments, the gate component 114 can identify the type, location, or sequence of the multi-qubit quantum gates, or a combination thereof. For example, one or more multi-qubit quantum gates may be represented in one or more quantum circuits 122 by one or more standardized representations, such as lines connecting each qubit operation. The gate component 114 can scan one or more quantum circuits 122 and correlate the standardized representations to associate the multi-qubit quantum gates.

[0032] FIG. 2A illustrates an exemplary, non-limiting quantum circuit 122a that may be input to the system 100 via one or more input devices 106, analyzed by the error mitigation component 110, or executed by one or more quantum computers 108, or a combination thereof. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. As illustrated in FIG. 2A, the exemplary quantum circuit 122a represents a quantum operation with respect to a first qubit q0 and a second qubit q1. Additionally, the exemplary quantum circuit 122a includes two CNOT quantum gates 202. The CNOT gates 202 of the exemplary quantum circuit 122a are constructed from cross-resonant gates (e.g., Hadamard gates and / or Pauli gates) between the first qubit q0 and the second qubit q1. In various embodiments, the gate component 114 can analyze the exemplary quantum circuit 122a and identify each of the two CNOT quantum gates 202 as multi-qubit gates (e.g., two-qubit gates) contained within the exemplary quantum circuit 122a.

[0033] In various embodiments, the gate component 114 can further query the calibration component 126 regarding calibrated parameters associated with each of the identified multi-qubit quantum gates. For example, each multi-qubit quantum gate included in the one or more quantum circuits 122 can be implemented by quantum gate hardware included in the one or more quantum computers 108. The calibration component 126 can calibrate the hardware to reduce systematic errors in the one or more quantum computers 108. When executing a quantum circuit 122 that includes one or more multi-qubit gates (e.g., two-qubit gates), the realized results may differ from the intended effect due to one or more errors, such as drift or crosstalk. The calibration component 126 can determine a calibrated pulse schedule for each of the identified multi-qubit gates using one or more calibration techniques (e.g., Floquet calibration and / or XEB calibration).

[0034] Additionally, the gate component 114 can modify one or more quantum circuits 122 based on the identified multi-qubit quantum gate. In various embodiments, the gate component 114 can insert a set of quantum gates into one or more quantum circuits 122 for each identified multi-qubit quantum gate. The set of quantum gates can include a pair of inverse quantum gates that constitute an identity gate. For example, the set of quantum gates can include a first quantum gate and a second quantum gate, where the second quantum gate is the inverse of the first quantum gate. If the set of quantum gates operates ideally (e.g., without error), the computational results realized by the new quantum circuit 122 can be the same as the original quantum circuit 122 due to the identity nature of the set of inserted quantum gates.

[0035] FIG. 2B illustrates a diagram of an exemplary modified non-limiting quantum circuit 122b that may include one or more sets of inserted quantum gates added by the gate component 114 in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. The modified quantum circuit 122b illustrated in FIG. 2B is based on the exemplary quantum circuit 122a illustrated in FIG. 2A. For each of the multi-qubit quantum gates (e.g., two CNOT gates 202) included in the exemplary quantum circuit 122a, the gate component 114 may insert an additional set of quantum gates (e.g., a first quantum gate and its inverse).

[0036] In one or more embodiments, the type of quantum gate inserted into quantum circuit 122 can be based on the physical mechanism that results in the native multi-qubit quantum gate of quantum circuit 122. Additionally, the physical mechanism and / or hardware architecture of the multi-qubit quantum gates included in one or more quantum computers 108 can be defined by calibration component 126 as part of the calibration information shared with error mitigation component 110 (e.g., via one or more networks 104). For example, in exemplary quantum circuit 122a, the two identified multi-qubit quantum gates are CNOT gates based on RZX rotation established by cross resonance. Thus, for each CNOT gate 202, gate component 114 selects a RZX rotation based on the ... ZX A set of gates 204 can be inserted such that the gate component 114 can insert a set of quantum gates that correspond to the physical mechanisms underlying native multi-qubit gates. For example, as shown in FIG. 2B, the gate component 114 can insert R ZX A set of gates 204 can be inserted to generate a modified quantum circuit 122b. ZX Gate set 204 is R ZX(θ) gate and subsequent inversion R ZX As shown in FIG. 2B, a set of quantum gates (e.g., R ZX A set of gates 204) may be inserted into the quantum circuit 122 (e.g., the exemplary quantum circuit 122a) in a position next to the associated native multi-qubit quantum gate (e.g., the CNOT gate 202). In another example, one or more of the identified multi-qubit quantum gates may be implemented as commutated gates, such as tunable combiner gates, in one or more quantum computers 108, and the gate component 114 may insert a set of one or more quantum gates corresponding to a scalable version of the commutated gate (e.g., a scalable version of a tunable combiner gate). In one or more embodiments in which a quantum gate is characterized as exp(-iθG / 2), the gate component 114 may insert an inversion of the quantum gate by employing -θ. θ may be a rotation angle, "G" may be a generator (e.g., "G" may be a Hermitian operator), and "i" may be the square root of "-1". For example, an Rzx gate may include a generator ZX, where Z and X are Pauli operators, whereby, in one or more examples, the gate component 114 identifies a generator G from a native multi-qubit gate and G (θ) and R G For example, the CNOT gate 202 can include a generator G equal to ZX, and the gate component 114 can include a set of quantum gates characterized by R ZX (θ) and R ZX R characterized by (-θ) ZX A set of gates 204 can be inserted. In another example, the tunable combiner gate can include a generator G equal to XX+YY, and the gate component 114 can include a generator G equal to R. XX+YY (θ) and R XX+YYA set of quantum gates characterized by (-θ) can be inserted.

[0037] In one or more embodiments, the gate component 114 may refer to a gate insertion table 128 to determine a set of types of quantum gates to be inserted into one or more quantum circuits 122. For example, the gate insertion table 128 may include native quantum gate types and / or hardware architecture types (e.g., cross resonant gates, tunable combiner gates, or the like, or a combination thereof) along with associated insertable gate types. For example, the gate insertion table 128 may include, for example, a set of types of quantum gates, such as R ZX As a type of insertable gate associated with hardware based on cross resonance, a CNOT gate can be created using the R ZX 1, the gate insertion table 128 may be stored in one or more memories 116, for example.

[0038] 3 illustrates a diagram of an exemplary non-limiting error mitigation component 110 further comprising a scaling component 302, in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. In various embodiments, the scaling component 302 can generate a scaled pulse schedule for the set of inserted quantum gates based on the calibration information and stretch factor settings 124 of the identified native multi-qubit quantum gates. In one or more embodiments, the pulse schedule can scale the rotation angles of the set of inserted quantum gates to achieve a set of scaled quantum gates that achieves a target stretch factor value.

[0039] In various embodiments, the set of one or more inserted quantum gates may be scaled by the error mitigation component 110 to achieve the stretch factor values ​​defined by one or more stretch factor settings 124. For example, the target stretch factor value of the set of inserted quantum gates may be a function of the rotation angle of the set of inserted quantum gates. For example, as the rotation angle of the set of inserted quantum gates changes, the stretch factor value associated with a particular execution of the modified quantum circuit 122 may also change. In one or more embodiments, the scaling component 302 may set the stretch factor values ​​to be generated for the set of one or more inserted quantum gates by defining the rotation angle of the set of one or more inserted quantum gates. For example, the one or more stretch factor settings 124 may define multiple stretch factor values, or ranges of stretch factor values, or both, to be executed using the one or more quantum circuits 122 over multiple iterations of execution. The scaling component 302 can determine, for each target stretch factor value, a rotation angle for a set of one or more inserted quantum gates based on a defined relationship between the stretch factor value and the rotation angle (which may be defined, for example, by one or more formulas, charts, tables, or graphs, or a combination thereof, stored in one or more scaling reference databases 304, as described below).

[0040] For example, Equation 1 shown below determines the R ZX The relationship between the stretch factor values ​​and the rotation angles of the set of gates 204 can be characterized.

[0041]

number

[0042] In various embodiments, the relationship between the gate rotation angles and stretch factor values ​​for various quantum gate types may be defined in one or more scaling reference databases 304. For example, the one or more scaling reference databases 304 may include multiple quantum gate types that may be inserted into one or more quantum circuits 122 by the gate component 114. In association with each quantum gate type, the one or more scaling reference databases 304 may include a mathematical formula, graph, table, or the like, or a combination thereof, that characterizes the mathematical relationship between the stretch factor values ​​occurring for a particular quantum gate and the rotation angle of the particular quantum gate. In one or more embodiments, the one or more scaling reference databases 304 may be populated via one or more input devices 106. Also, the one or more scaling reference databases 304 may be stored in one or more memories 116.

[0043] 4 illustrates an example, non-limiting graph 400 that may show the relationship between stretch factor values ​​characterized by Equation 1 and rotation angles in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein has been omitted for the sake of brevity. In various embodiments, graph 400 may be plotted against one or more target stretch factor values, such as R ZX To determine the rotation angle of the set of gates 204, it may be included in one or more scaling reference databases 304 and / or may be referenced by the scaling component 302.

[0044] 4, in various embodiments, the range of possible stretching factors that may be implemented in a set of inserted quantum gates may be limited by one or more characteristics of the associated native multi-qubit quantum gates. For example, an exemplary R ZX The set of gates 204 can implement a minimum stretch factor value of 1.8. In various embodiments, the minimum and / or maximum stretch factor values ​​that can be realized for the set of inserted quantum gates can be based on parameters (e.g., included in the calibration information determined by the calibration component 126) of the native multi-qubit quantum gates of the initial quantum circuit 122. For example, for an echo crossover resonant gate, the minimum stretch factor value achievable without pulse calibration can be determined by the rise or fall of single and two-qubit pulses. The maximum stretch factor value can be set based on the capabilities of the hardware of the one or more quantum computers 108, including, but not limited to, the control electronic memory, coherence time, constraints imposed (e.g., total duration of the schedule), or the like, or a combination thereof.

[0045] In various embodiments, the scaling component 302 can define a set of target stretch factor values ​​that can be within a minimum and / or maximum threshold of a set of one or more inserted quantum gates and within a plurality of stretch factor values ​​and / or a range of stretch factor values ​​defined by one or more stretch factor settings 124. Additionally, the scaling component 302 can determine a rotation angle of a quantum gate associated with each target stretch factor of the set of target stretch factor values.

[0046] In one or more embodiments, the scaling component 302 can further generate a set of pulse schedules to implement each of the determined rotation angles of the quantum gates. The set of pulse schedules can include pulse schedules scaled from the calibrated pulse schedules of the native multi-qubit quantum gates of the initial quantum circuit 122 (e.g., exemplary quantum circuit 122a) to implement particular rotation angles of the associated set of inserted quantum gates of the adjusted quantum circuit 122 (e.g., modified quantum circuit 122b). In various embodiments, the scaling component 302 can use one or more scaling techniques on the calibrated pulse schedules of the native multi-qubit quantum gates to generate scaled pulse schedules for the associated set of inserted quantum gates. Exemplary scaling techniques that may be used by the scaling component 302 to generate a scaled pulse schedule may include, but are not limited to, using a single cross-resonant pulse, using a rotating term, using a pulse echo, scaling the flat top of a square pulse with a Gaussian rise or fall, scaling a tunable combiner pulse to generate a switched gate or a controlled phase gate or both, or the like, or combinations thereof.

[0047] In one or more embodiments, the scaling component 302 can implement one or more scaling techniques to modify one or more parameters of the calibrated pulse schedule of a native multi-qubit quantum gate. For example, the one or more scaling techniques can modify the amplitude or cycle time or both of the calibrated pulse schedule. The scaled pulse schedule generated by the scaling component 302 can thereby result in alternative execution durations of one or more quantum circuits 122.

[0048] 5 illustrates an exemplary, non-limiting diagram of a scaled pulse schedule that may be generated by scaling component 302 implemented using a set of one or more inserted quantum gates in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. FIG. 5 illustrates the use of one or more inserted R gates of modified quantum circuit 122b to achieve one or more of the stretch factors and / or rotation angles characterized by graph 400. ZX 3 shows three exemplary scaled pulse schedules that may be generated by scaling component 302 to be implemented on set of gates 204. Each of the exemplary scaled pulse schedules may be implemented across both quantum gates (e.g., the first inserted quantum gate and its inverse) of the set of quantum gates.

[0049] As shown in FIG. 5, a first exemplary scaled pulse schedule 502 may be generated by the scaling component 302 by adjusting one or more parameters, such as the width of the cross-resonance pulse. A second exemplary scaled pulse schedule 504 may be generated by the scaling component 302 by adding one or more pulse echoes to the calibrated pulse schedule. A third exemplary scaled pulse schedule 506 may be generated by the scaling component 302 by modifying the waveform of the calibrated pulse schedule using a rotation term. In various embodiments, a set of one or more inserted quantum gates may be implemented as scaled pulse schedules generated by multiple scaling techniques. For example, the scaling component 302 may implement at least one or a combination of the first exemplary scaled pulse schedule 502, the second exemplary scaled pulse schedule 504, and the third scaled pulse schedule 506. For example, the scaling component 302 may adjust the waveform of the calibrated pulse schedule and introduce one or more echo pulses to generate a scaled pulse schedule. In another example, the scaling component 302 can adjust the waveform of the calibrated pulse schedule to generate a scaled pulse schedule using one or more rotation terms. In a further example, the scaling component can introduce one or more echo pulses and / or rotation terms into the calibrated pulse schedule to generate one or more scaled pulse schedules.

[0050] 6 illustrates a diagram of an exemplary non-limiting error mitigation component 110 further comprising an execution component 602 in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. In various embodiments, the execution component 602 may execute one or more tuned (e.g., tuned to include one or more sets of inserted quantum gates) quantum circuits 122 multiple times, with each iteration using a respective scaled pulse schedule generated by the scaling component 302.

[0051] In one or more embodiments, the execution component 602 may execute the tuned quantum circuit 122 (e.g., including the set of one or more inserted quantum gates) multiple times on one or more quantum computers 108, with each execution iteration being associated with a respective target stretch factor value. Each target stretch factor value may also be associated with a rotation angle (e.g., determined by the scaling component 302) of the set of one or more inserted quantum gates. Further, each rotation angle may be implemented by a respective scaled pulse schedule generated by the scaling component 302, which may be scaled based on a calibrated pulse schedule (e.g., determined by the calibration component 126) of one or more native multi-qubit quantum gates identified by the gate component 114.

[0052] For example, the execution component 602 may execute a first execution of the tuned quantum circuit 122 (e.g., including one or more sets of inserted quantum gates) on one or more quantum computers 108. During the first execution, the one or more quantum computers 108 may drive the one or more sets of inserted quantum gates according to a first scaled pulse schedule to achieve a first stretch factor value (e.g., from a set of stretch factor values ​​set by the scaling component 302, e.g., based on the stretch factor setting 124). Additionally, the execution component 602 may execute a second execution of the same tuned quantum circuit 122 (e.g., including one or more sets of inserted quantum gates) on one or more quantum computers 108. During the second execution, the one or more quantum computers 108 may drive the one or more sets of inserted quantum gates according to a second scaled pulse schedule to achieve a second stretch factor value (or establish a second gate rotation angle that is different from the gate rotation angle established during the first execution, e.g., or both). Similarly, the execution component 602 can execute any number of additional executions of the same tuned quantum circuit 122, with each execution implementing a different scaled pulse schedule.

[0053] At each execution of the adjusted quantum circuit 122, the execution component 602 can collect the computation results output by the one or more quantum computers 108. Because each execution is associated with a different stretch factor value, the computation results of each execution can vary due to the inclusion of different amounts of noise. Furthermore, the execution component 602 can generate a results database 604 associated with the one or more adjusted quantum circuits 122. For example, the results database 604 can include computation results from each execution along with a target stretch factor value associated with each execution of the one or more adjusted quantum circuits 122. For example, the one or more results databases 604 can be stored in the one or more memories 116.

[0054] FIG. 7 illustrates a diagram of an exemplary non-limiting error mitigation component 110 further comprising an extrapolation component 702, in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. In various embodiments, the extrapolation component 702 can use one or more extrapolation techniques with respect to one or more result databases 604 to determine near-zero noise calculations associated with one or more particular quantum circuits 122. An exemplary extrapolation technique that may be used by the extrapolation component 702 can be Richardson extrapolation or another extrapolation method. For example, the extrapolation component 702 can use a Richardson extrapolation algorithm to extrapolate the calculation results contained in one or more result databases 604 to the zero-noise limit.

[0055] FIG. 8 illustrates an example, non-limiting diagram of a graph 800 that may illustrate improved resolution achievable by the system 100 in accordance with one or more embodiments described herein, as compared to standard error mitigation techniques. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. The graph 800 may evaluate one or more quantum circuits 122 (e.g., the example quantum circuit 122a) utilized to calculate the ground state energy of a hydrogen molecule. The square symbols may represent exact values ​​of the ground state energy. The black circles may represent each execution of the example quantum circuit 122a using various scaled pulse schedules in accordance with various embodiments described herein. As illustrated in the graph 800, each scaled pulse schedule may be associated with a different stretch factor value, which may result in different computational results. The black triangles may represent an execution of the example quantum circuit 122a using a digitally based Richardson extrapolation technique. Additionally, the white circles represent extrapolated results determined from an execution of the scaled pulse schedule using the Richardson extrapolation algorithm. Additionally, the white triangles represent extrapolated results determined from digital-based Richardson implementations using the Richardson extrapolation algorithm.

[0056] A comparison of the implementation of the scaled pulse schedule to the implementation of the digitally based Richardson extrapolation shows that the various embodiments described herein can achieve a greater number of stretch factor values. Furthermore, the greater number of stretch factor values ​​can be densely spaced within a finer range (e.g., from the minimum stretch factor value implemented to the maximum stretch factor value implemented). In contrast, the implementation of the standard stretch factor values ​​is limited to fewer usable stretch factor values ​​over a broader range. Furthermore, the improved resolution of the set of implemented target stretch factor values ​​allowed for more accurate calculation of the extrapolation of the ground state energy.

[0057] 9 illustrates a flow diagram of an exemplary, non-limiting, computer-implemented method 900 that may be implemented by system 100 to perform quantum error mitigation in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0058] At 902, the computer-implemented method 900 may include receiving, by the system 100 operatively coupled to the processor 120 (e.g., via the communications component 112), one or more quantum circuits 122. In various embodiments, the one or more quantum circuits 122 may be input to the system 100 via one or more input devices 106. Also, the one or more quantum circuits 122 may represent one or more quantum operations and / or quantum gates for execution of one or more quantum algorithms on one or more quantum computers 108.

[0059] At 904, the computer-implemented method 900 may include determining, by the system 100 (e.g., by the scaling component 302), a set of target stretch factor values. In various embodiments, the stretch factor values ​​may define modifications to a pulse schedule that drives one or more multi-qubit quantum gates during execution of one or more quantum circuits 122. In one or more embodiments, one or more input devices 106 may be employed to input stretch factor settings 124 into the system 100, where the stretch factor settings 124 may include a plurality of stretch factor values ​​and / or ranges of stretch factor values ​​targeted for implementation in one or more error mitigation techniques.

[0060] At 906, the computer-implemented method 900 may include identifying, by the system 100 (e.g., by the gate component 114), one or more multi-qubit quantum gates included within the one or more quantum circuits 122. For example, the one or more multi-qubit quantum gates may be two-qubit quantum gates. Examples of types of multi-qubit quantum gates may include, but are not limited to, cross-resonant gates (e.g., CNOT gates), Pauli gates, entanglement gates, exchange-like gates, controlled phase gates, multi-control phase gates, or the like, or combinations thereof. At 908, the computer-implemented method 900 may include retrieving, by the system 100 (e.g., by the calibration component 126), calibrated pulse schedules for the one or more identified multi-qubit quantum gates. For example, the one or more quantum computers 108 may calibrate quantum hardware associated with the multi-qubit quantum gates defined by the one or more quantum circuits 122 and return the calibration data to the error mitigation component 110. At 910, the computer-implemented method 900 may include inserting, by system 100 (e.g., by gate component 114) a set of quantum gates into one or more quantum circuits 122 for each identified multi-qubit quantum gate native to the quantum circuit. In various embodiments, each inserted set of quantum gates may include a first quantum gate and a second quantum gate that is an inverse of the first quantum gate, such that the set of quantum gates may constitute an identity of the original quantum circuit 122.

[0061] At 912, the computer-implemented method 900 may include determining, by the system 100 (e.g., by the scaling component 302), a rotation angle for the set of inserted quantum gates based on the stretch factor from the set of target stretch factors. For example, the relationship between the one or more stretch factor values ​​and the rotation angle for the set of inserted quantum gates may be defined by one or more formulas, charts, tables, or the like, or combinations thereof, included in one or more gate insertion tables 128 according to one or more embodiments described herein. For example, the determining at 910 may use a graph, such as graph 400, that may characterize how the stretch factor values ​​realized by the set of inserted quantum gates may be based on the rotation angles of the gates.

[0062] At 914, the computer-implemented method 900 may include generating, by the system 100 (e.g., by the scaling component 302), a scaled pulse schedule for the set of inserted quantum gates based on the rotated and / or calibrated pulse schedule. In various embodiments, the generating at 914 may use one or more scaling techniques to generate a scaled pulse schedule that may be implemented in the set of inserted quantum gates. For example, the scaled pulse schedule may be generated by modifying a waveform of the calibrated pulse schedule, introducing one or more pulse echoes, or using one or more rotation terms, or a combination thereof. In one or more embodiments, scaling the pulse schedule may, for example, modify a cycle duration associated with executing one or more quantum circuits 122.

[0063] At 916, the computer-implemented method 900 may include executing, by the system 100 (e.g., by the execution component 602), one or more tuned quantum circuits 122 (e.g., including one or more sets of inserted quantum gates) using the scaled pulse schedule on one or more quantum computers 108. At 918, the computer-implemented method 900 may evaluate whether there are additional target stretch factor values ​​to be implemented. If there are additional target stretch factor values ​​to be implemented, the computer-implemented method 900 may then repeat 912-916. For example, the computer-implemented method 900 may include, for each target stretch factor value of the set of target stretch factor values, determining a rotation angle of the gates, generating a scaled pulse schedule, and executing the tuned quantum circuit 122. The computer-implemented method 900 may thereby execute the tuned quantum circuit 122 over multiple iterations, each iteration achieving a different stretch factor value with a different scaled pulse schedule.

[0064] If there are no additional target stretch factor values ​​to be implemented, the computer-implemented method 900 may proceed to 920. At 920, the computer-implemented method 900 may include collecting, by the system 100 (e.g., by the execution component 602), computational results associated with each execution of the one or more tuned quantum circuits. At 922, the computer-implemented method 900 may include extrapolating, by the system 100 (e.g., by the extrapolation component 702), computational results from the one or more quantum computers 108 to determine error-mitigated results. For example, the Richardson extrapolation algorithm may be used to extrapolate zero-noise results from multiple executions of the one or more tuned quantum circuits 122.

[0065] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the subject matter presented herein is not limited to a cloud computing environment. Embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0066] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with the service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0067] The features are as follows:

[0068] On-Demand Self-Service: Cloud customers can automatically provision server time and computing power, such as network storage, as needed, without the need for unilateral, human interaction with the service provider.

[0069] Broad network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0070] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Different physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence, consumers usually have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction they may be able to specify a location (e.g. country, state, or data center).

[0071] Rapid Elasticity: Cloud capacity can be provisioned quickly and elastically, in some cases automatically, to scale out quickly, and quickly released to scale in quickly. Capacity available for provisioning often appears to consumers as unlimited, available for purchase in any amount at any time.

[0072] Metered Services: Cloud systems leverage metering to automatically control and optimize resource usage at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services utilized.

[0073] The service model is as follows:

[0074] SaaS (Software as a Service): The capability provided to the consumer is the use of the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application functionality, except for the possibility of limited user-specific application configuration settings.

[0075] PaaS (Platform as a Service): The capability provided to a consumer is to deploy applications that the consumer creates or acquires, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0076] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources over which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, and deployed applications, and in some cases has limited control over selected network components (e.g., host firewalls).

[0077] The deployment model is as follows:

[0078] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by the organization or a third party and can exist on-premise or off-premise.

[0079] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared concerns (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premise or off-premise.

[0080] Public Cloud: This cloud infrastructure is available for use by general users or large industry organizations and is owned by an organization that sells cloud services.

[0081] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique but are bound together by standardized or proprietary technologies that allow for the portability of data and applications (e.g., cloud bursting to balance the load between clouds).

[0082] A cloud computing environment is a service-oriented environment with an emphasis on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0083] Referring now to FIG. 10, an exemplary cloud computing environment 1000 is illustrated. As illustrated, the cloud computing environment 1000 includes one or more cloud computing nodes 1002 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 1004, a desktop computer 1006, a laptop computer 1008, and / or an automobile computer system 1010, etc.) can communicate. The nodes 1002 may communicate with each other. The nodes 1002 may be physically or virtually grouped together in one or more networks (not shown), such as in a private cloud, community cloud, public cloud, or hybrid cloud, or combination thereof, as previously described herein. This allows the cloud computing environment 1000 to provide an infrastructure, platform, and / or SaaS that does not require the cloud consumer to maintain resources on a local computing device. The types of computing devices 1004-1010 shown in FIG. 10 are intended to be illustrative only, and it will be understood that the computing nodes 1002 and cloud computing environment 1000 may communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0084] Referring now to Figure 11, a set of functional abstraction layers provided by cloud computing environment 1000 (Figure 10) is shown. Repeated descriptions of similar elements used in other embodiments described herein are omitted for the sake of brevity. It should be understood in advance that the components, layers, and functions shown in Figure 11 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0085] The hardware and software layer 1102 includes hardware and software components. Examples of hardware components include a mainframe 1104, a Reduced Instruction Set Computer (RISC) architecture based server 1106, a server 1108, a blade server 1110, a storage device 1112, and a network and network components 1114. In some embodiments, the software components include network application server software 1116 and database software 1118.

[0086] The virtualization layer 1120 comprises an abstraction layer that can provide virtual entities such as virtual servers 1122 , virtual storage 1124 , virtual networks including virtual private networks 1126 , virtual applications and operating systems 1128 , and virtual clients 1130 .

[0087] As an example, the management layer 1132 may provide the following functions: Resource provisioning 1134 dynamically procures computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 1136 tracks costs as resources are utilized within the cloud computing environment and generates and sends bills for the utilization of those resources. As an example, those resources may include application software licenses. Security verifies the identity of cloud users and tasks, and protects data and other resources. User portal 1138 provides users and system administrators with access to the cloud computing environment. Service level management 1140 allocates and manages cloud computing resources to meet required service levels. Service level agreement (SLA) planning and execution 1142 pre-provisions and procures cloud computing resources in anticipation of upcoming demands and in accordance with SLAs.

[0088] Workload layer 1144 illustrates example functionality available in a cloud computing environment. Examples of workloads and functionality that may be provided from this layer include mapping and navigation 1146, software development and lifecycle management 1148, virtual classroom instruction delivery 1150, data analytics processing 1152, transaction processing 1154, and quantum computing 1156. Various embodiments of the present invention may utilize the cloud computing environment described with reference to Figures 10 and 11 to perform one or more quantum error mitigation techniques on one or more quantum circuits in accordance with one or more embodiments described herein.

[0089] The present invention may be a system, a method, or a computer program product, or a combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer readable storage medium containing computer readable program instructions for causing a processor to perform aspects of the present invention. The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which the instructions are recorded, and any suitable combinations of these. As used herein, computer-readable storage media should not itself be construed as being ephemeral signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over wires.

[0090] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing device / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing device / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage on a computer readable storage medium within each computing device / processing device.

[0091] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the invention, electronic circuitry including, for example, programmable logic circuitry, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer readable program instructions to customize the electronic circuitry by utilizing state information of the computer readable program instructions.

[0092] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks included in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0093] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / operations specified in the blocks of the flowcharts and / or block diagrams. These computer readable program instructions may be stored on a computer readable storage medium in a specific manner, such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / operations specified in the blocks of the flowcharts and / or block diagrams, and may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function.

[0094] Computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in the blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to generate a computer-implemented process.

[0095] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously or in reverse order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks included in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0096] To provide further context for the various embodiments described herein, Figure 12 and the following discussion are intended to provide a general overview of a suitable computing environment 1200 in which various embodiments described herein may be implemented. Although the embodiments are described above in the general context of computer-executable instructions that may be executed on one or more computers, those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0097] Typically, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the methods of the present invention can be practiced using other computer system configurations, including single or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

[0098] The embodiments described herein may also be practiced in a distributed computing environment where certain tasks are performed by remote processing devices linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from a memory that may include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute code of computer-executable components in a distributed manner, e.g., with multiple processors coupled or working in concert to execute code from one or more distributed memory units. As used herein, the term "memory" may encompass a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0099] A computing device typically includes various media, which may include computer-readable storage media, machine-readable storage media, or communication media, or a combination thereof, and in this specification, the two terms are used differently from each other as follows. A computer-readable storage medium or machine-readable storage medium can be any available storage medium that can be accessed by a computer, and includes both volatile and non-volatile media, removable and non-removable media. By way of example, a computer-readable storage medium or machine-readable storage medium can be implemented in association with any method or technology for storage of information, such as, but not limited to, computer-readable or machine-readable instructions, program modules, structured or unstructured data, etc.

[0100] A computer-readable storage medium may include, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disc (BD) or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device, solid state drive or other solid state storage device, or other tangible and / or non-transitory medium that may be used to store the desired information. In this regard, the terms "tangible" or "non-transitory" as applied to storage, memory, or computer-readable medium should be understood to exclude only propagating, ephemeral signals as modifiers and not to waive all claims to all standard storage, memory, or computer-readable media that are not themselves merely propagating, ephemeral signals.

[0101] The computer-readable storage medium can be accessed by one or more local or remote computing devices for various operations on the information stored by the medium, such as via access requests, queries, or other data retrieval protocols.

[0102] Communication media typically embodies computer readable instructions, data structures, program modules, or other structured or unstructured data in a data signal, such as a modulated data signal (e.g., carrier wave or other transport mechanism) and includes any information delivery or transport media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal or signals. By way of example, and not limitation, communication media includes wired media, such as a wired network or direct-wired connection, and wireless media, such as acoustic, RF, infrared and other wireless media.

[0103] Referring again to FIG. 12, an exemplary environment 1200 for implementing various embodiments of the aspects described herein includes a computer 1202 including a processing unit 1204, a system memory 1206, and a system bus 1208. The system bus 1208 couples system components including, but not limited to, the system memory 1206 to the processing unit 1204. The processing unit 1204 can be any of a variety of commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 1204.

[0104] The system bus 1208 can be any of several types of bus structures that can be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1206 includes a ROM 1210 and a RAM 1212. A basic input / output system (BIOS) can be stored in a non-volatile memory, such as a ROM, erasable programmable read only memory (EPROM), or EEPROM, and the BIOS includes basic routines that help transfer information between elements within the computer 1202, such as during startup. The RAM 1212 can also include a high-speed RAM, such as a static RAM, for caching data.

[0105] The computer 1202 further includes an internal hard disk drive (HDD) 1214 (e.g., EIDE, SATA), one or more external storage devices 1216 (e.g., a magnetic floppy disk drive (FDD), a memory stick or flash drive reader, a memory card reader, combinations thereof, etc.), and an optical disk drive 1220 (e.g., a drive that can read from or write to CD-ROM disks, DVDs, BDs, etc.). Although the internal HDD 1214 is shown as being within the computer 1202, the internal HDD 1214 can also be configured for use within an external suitable enclosure (not shown). Additionally, although not shown within the environment 1200, a solid state drive (SSD) can be used in addition to or in place of the HDD 1214. The HDD 1214, external storage device 1216, and optical disk drive 1220 can be connected to the system bus 1208 by a HDD interface 1224, an external storage interface 1226, and an optical drive interface 1228, respectively. The interface 1224 for external drive implementations can include at least one or both of Universal Serial Bus (USB) interface technology and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technology. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0106] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. The drives and storage media of the computer 1202 accommodate the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to various storage devices, it should be understood by those skilled in the art that other types of storage media that can be read by a computer, whether currently existing or developed in the future, can also be used within the exemplary operating environment, and further, any such storage media can include computer-executable instructions for performing the methods described herein.

[0107] A number of program modules, including an operating system 1230, one or more application programs 1232, other program modules 1234, and program data 1236, may be stored in the drives and RAM 1212. All or portions of the operating system, applications, modules, and / or data may also be cached in RAM 1212. The systems and methods described herein may be implemented using various commercially available operating systems or combinations of operating systems.

[0108] The computer 1202 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment of the operating system 1230, and the emulated hardware may optionally be different than the hardware shown in FIG. 12. In such an embodiment, the operating system 1230 may include one of a number of virtual machines (VMs) hosted on the computer 1202. Additionally, the operating system 1230 may provide a runtime environment, such as the Java runtime environment or the .NET framework, for the application 1232. The runtime environment is a consistent execution environment that allows the application 1232 to run on any operating system that includes the runtime environment. Similarly, the operating system 1230 may support containers, and the application 1232 may be in the form of a container, which is a lightweight, standalone, executable software package that includes, for example, code, runtime, system tools, system libraries, and settings for the application.

[0109] Additionally, computer 1202 can be enabled with a security module, such as a trusted processing module (TPM). For example, with a TPM, a boot component can hash the next boot component in time and wait for a match of the hash result with a protected value before loading the next boot component. This process can occur at any layer in the code execution stack of computer 1202, for example, at the application execution level or at the operating system (OS) kernel level, thereby enabling security at any level of code execution.

[0110] A user may enter commands and information into the computer 1202 through one or more wired / wireless input devices (e.g., a keyboard 1238, a touch screen 1240, and a pointing device such as a mouse 1242). Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, a joystick, a virtual reality controller and / or a virtual reality headset, a game pad, a stylus, an image input device (e.g., a camera), a gesture sensor input device, a vision movement sensor input device, an emotion or face detection device, a biometric input device (e.g., a fingerprint or iris scanner), and the like. These and other input devices are often connected to the processing unit 1204 through an input device interface 1244 that may be coupled to the system bus 1208, but may be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH interface, and the like.

[0111] A monitor 1246 or other type of display device can also be connected to the system bus 1208 via an interface, such as a video adapter 1248. In addition to the monitor 1246, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, or a combination thereof.

[0112] The computer 1202 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1250, via wired and / or wireless communications. The remote computer 1250 can be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment device, a peer device, or other common network node, and typically includes many or all of the elements described relative to the computer 1202, although for purposes of brevity, only a memory / storage device 1252 is shown. The logical connections shown in the figure include wired / wireless connections to a local area network (LAN) 1254 and / or larger networks (e.g., a wide area network (WAN) 1256). Such LAN and WAN networking environments are commonplace in offices and companies, facilitating enterprise-wide computer networks, such as intranets, all of which may be connected to a global communications network (e.g., the Internet).

[0113] When used in a LAN networking environment, the computer 1202 can be connected to the local network 1254 via a wired and / or wireless communication network interface or adapter 1258. The adapter 1258 can facilitate wired or wireless communication with the LAN 1254, and the LAN 1254 can also include a wireless access point (AP) disposed for communicating with the adapter 1258 in a wireless mode.

[0114] When used in a WAN network environment, the computer 1202 can include a modem 1260 or can be connected to a communications server on the WAN 1256 by other means for establishing communications over the WAN 1256, such as via the Internet. The modem 1260, which can be a wired or wireless device present internally or externally, can be connected to the system bus 1208 via the input device interface 1244. In a networked environment, program modules depicted relative to the computer 1202 or portions thereof can be stored in the remote memory / storage device 1252. It will be understood that the network connections shown are examples and other means of establishing a communications link between the computers can be used.

[0115] When used in either a LAN or WAN network environment, the computer 1202 can access a cloud storage system or other network-based storage system in addition to or instead of the external storage device 1216 as described above. In general, a connection between the computer 1202 and the cloud storage system can be established via the LAN 1254 or the WAN 1256, for example, by an adapter 1258 or a modem 1260, respectively. When connecting the computer 1202 to an associated cloud storage system, the external storage interface 1226 can manage the storage provided by the cloud storage system as well as other types of external storage, using the adapter 1258 or the modem 1260, or both. For example, the external storage interface 1226 can be configured to provide access to the cloud storage sources as if the cloud storage sources were physically connected to the computer 1202.

[0116] The computer 1202 may be operable to communicate with any wireless device or entity operatively arranged in wireless communication (e.g., a printer, a scanner, a desktop computer or portable computer or both, a portable data assistant, a communications satellite, any piece or location of equipment associated with a wirelessly detectable tag (e.g., a kiosk, a newsstand, a store shelf, etc.), and a telephone). This communication may include Wireless Fidelity (WiFi®) and BLUETOOTH® wireless technologies. Thus, this communication may be of a predefined structure, similar to a conventional network, or may simply be an ad-hoc communication between at least two devices.

[0117] The foregoing includes merely examples of systems, computer program products, and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components, products, or computer-implemented methods, or combinations thereof, but one of ordinary skill in the art will recognize that many other combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "including," "having," "owning," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising," as "comprising" is interpreted when used as a transitional term in a claim. The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive, and is not limited to the disclosed embodiments. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the marketplace, or to enable other skilled in the art to understand the embodiments disclosed herein.

Claims

1. a memory for storing computer executable components; a processor operatively coupled to the memory, the processor executing the computer-executable components stored in the memory; a system comprising:

1. A system comprising: an error mitigation component that adds a set of scaled quantum gates to a quantum circuit for error mitigation, the set of scaled quantum gates including a quantum gate and an inverse of the quantum gate, the set of scaled quantum gates having a rotation angle based on a pulse schedule to achieve a target stretch factor.

2. 10. The system of claim 1, wherein the rotation angle of the set of scaled quantum gates controls an amount of noise introduced into the quantum circuit.

3. 3. The system of claim 1, further comprising a gate component that inserts a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit.

4. The set of quantum gates may be implemented by a single cross-resonance pulse, a cross-resonance pulse with a rotation term, an echo cross-resonance pulse with the rotation term, or a direct CX gate. ＺＸ The system of claim 3 including a gate.

5. 5. The system of claim 3, further comprising a calibration component that performs a calibration of the target quantum gate and determines a pulse implementation of the target quantum gate.

6. 6. The system of claim 5, further comprising a scaling component that generates the pulse schedule for the set of quantum gates based on the pulse implementation of the target quantum gate and the target stretch factor, the pulse schedule scaling rotation angles of the set of quantum gates to define the scaled set of quantum gates.

7. 7. The system of claim 5, further comprising an execution component that executes the quantum circuit using the scaled set of quantum gates.

8. 8. The system of claim 7, further comprising an extrapolation component that extrapolates results achieved by the execution component to mitigate noise in the quantum circuit.

9. 1. A computer-implemented method, comprising: Adding a set of scaled quantum gates to the quantum circuit for error mitigation by a system operatively coupled to the processor. wherein the scaled set of quantum gates includes a quantum gate and an inverse of the quantum gate, the scaled set of quantum gates having a rotation angle based on a pulse schedule to achieve a target stretch factor.

10. 10. The computer-implemented method of claim 9, wherein the rotation angle of the scaled set of quantum gates controls an amount of noise introduced into the quantum circuit.

11. 11. The computer-implemented method of claim 9, further comprising inserting, by the system, a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit.

12. The set of quantum gates may be implemented by a single cross-resonance pulse, a cross-resonance pulse with a rotation term, an echo cross-resonance pulse with the rotation term, or a direct CX gate. ＺＸ The computer-implemented method of claim 11 including a gate.

13. 13. The computer-implemented method of claim 11 or 12, further comprising extracting, by the system, a calibration of the target quantum gate to determine a pulse implementation of the target quantum gate.

14. 14. The computer-implemented method of claim 13, further comprising generating, by the system, the pulse schedule for the set of quantum gates based on the pulse implementation of the target quantum gate and the target stretch factor, wherein the pulse schedule scales rotation angles of the set of quantum gates to define the scaled set of quantum gates.

15. executing, by the system, the quantum circuit using the scaled set of quantum gates; the system extrapolating results from the runs to mitigate noise in the quantum circuit; The computer-implemented method of claim 14 further comprising:

16. 1. A computer program product for mitigating errors in a quantum circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therein, the program instructions being executable by a processor, the processor comprising:

11. A computer program product for causing a set of scaled quantum gates to be added to the quantum circuit, the set of scaled quantum gates including a quantum gate and an inverse of the quantum gate, the set of scaled quantum gates having a rotation angle based on a pulse schedule to achieve a target stretch factor.

17. 20. The computer program product of claim 16, wherein the rotation angle of the scaled set of quantum gates controls an amount of noise generated in the quantum circuit.

18. The program instructions cause the processor to:

18. A computer program product as claimed in claim 16 or 17, further comprising: inserting a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit.

19. The program instructions cause the processor to: extracting a calibration of the target quantum gate to determine a pulse implementation of the target quantum gate; generating the pulse schedule for the set of quantum gates based on the pulse implementation of the target quantum gate and the target stretch factor; 20. The computer program product of claim 18, further comprising: wherein the pulse schedule scales rotation angles of the set of quantum gates to define the scaled set of quantum gates.

20. The program instructions cause the processor to: executing the quantum circuit using the scaled set of quantum gates; Extrapolating results achieved by execution of said quantum circuit to reduce noise in said quantum circuit; 20. The computer program product of claim 19, further comprising:

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