Package with spacers between integrated devices - Patents.com

Abstract

The package (100) includes a first integrated device (105) having a first plurality of interconnects (254), a plurality of solder interconnects (170a) coupled to the first plurality of interconnects (254), a second integrated device (107a) having a second plurality of interconnects (270a+272a), the second integrated device (107a) coupled to the first integrated device (105) via the second plurality of interconnects (270a+272a), the plurality of solder interconnects (170a), and the first plurality of interconnects (254), a polymer layer (192a) located between the first integrated device (105) and the second integrated device (107a), and a plurality of spacer balls (109a) located between the first integrated device (105) and the second integrated device (107a). The spacer balls (190a) help ensure that variations in the gap between the integrated devices (105, 107a) (e.g., due to tilting of one of the integrated devices (105, 107a) relative to an adjacent integrated device (105, 107a)) are reduced and / or eliminated. The polymer layer (192a) may include an adhesive layer. The spacer balls (190a) may be located at least partially within the polymer layer (192a). The spacer balls (190a) may include monodisperse particles, silica, glass, polymer, ceramic, and / or metal-containing particles, and may include polyethylene polymer particles, in particular. The package (100) may further include an underfill (204a) between the first integrated device (105) and the second integrated device (107a). The first plurality of interconnects (254) may include a first plurality of pillar interconnects, and the second integrated device is coupled to the first integrated device via the second plurality of interconnects (270a+272a), the plurality of solder interconnects (170a), and the first plurality of pillar interconnects. The second integrated device (107a) may include a second die (e.g., a first memory die), and the first integrated device (105) may include a first die (e.g., a logic die or a second memory die).The package (100) may further comprise a third integrated device (107b) having a third plurality of interconnects (270b+272b), a second polymer layer (192b) located between the third integrated device (107b) and the second integrated device (107a), and a second plurality of spacer balls (190b) located between the third integrated device (107b) and the second integrated device (107a), and the third integrated device (107b) may be coupled to the second integrated device (107a) via the third plurality of interconnects (270b+272b) and the second plurality of solder interconnects (170b), and the second integrated device (107a) may include a plurality of through-substrate vias (275a). The first plurality of interconnects (254) may include a first plurality of pillar interconnects and / or a first plurality of pad interconnects (254), and the second plurality of interconnects (270a+272a) may include a second plurality of pillar interconnects (272a) and / or a second plurality of pad interconnects (270a). The first integrated device (105) may include a third plurality of interconnects (250+252), where the first plurality of interconnects (254) is located on a first surface of the first integrated device (105) and the third plurality of interconnects (250+252) is located on a second surface of the first integrated device (105). The package (100) may comprise a substrate (104) and a stack (101) of first and second integrated devices (105, 107a) coupled to the substrate (104) via a further plurality of solder interconnects (150). The first integrated device (105) may be coupled to the second integrated device (107a) via front-to-front bonding, front-to-backside bonding, back-to-front bonding, or back-to-backside bonding.In a method of fabricating a package (100), the second plurality of pad interconnects (370), the second plurality of pillar interconnects (372), and the plurality of solder interconnects (170) are formed on a second wafer (600) including uncut second integrated devices (307a, 307b), and a plurality of spacer balls (190) and a polymer layer (192) are disposed between the uncut second integrated devices (307a, 307b), for example, in a cut region ( 504), an underfill (204) is formed on the uncut second integrated devices (307a, 307b), a first wafer (610) including the uncut first integrated devices (305a, 305b), the first plurality of pad interconnects (350), and the first plurality of pillar interconnects (352) is bonded to the second wafer (600) by a solder reflow process, and the wafers (600, 610) are cut along the cut lines (620).

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to nonprovisional application Ser. No. 17 / 574,360, filed in the United States Patent Office on Jan. 12, 2022, the entire contents of which are incorporated by reference herein as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various features relate to packages that include integrated devices and, more particularly, to packages that include several integrated devices. [Background technology]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There is a continuing need to provide better performing packages and reduce the overall dimensions of the package. Summary of the Invention

[0004] Various features relate to packages that include integrated devices and, more particularly, to packages that include several integrated devices.

[0005] One example provides a package including a first integrated device having a first plurality of interconnects, a plurality of solder interconnects coupled to the first plurality of interconnects, a second integrated device having a second plurality of interconnects, the second integrated device coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects, a polymer layer located between the first integrated device and the second integrated device, and a plurality of spacer balls located between the first integrated device and the second integrated device.

[0006] Another example provides a package that includes a substrate and a stack of integrated devices coupled to the substrate via a first plurality of solder interconnects, the stack of integrated devices including a first integrated device having the first plurality of interconnects, a second plurality of solder interconnects coupled to the first plurality of interconnects, a second integrated device having the second plurality of interconnects, the second integrated device coupled to the first integrated device via the second plurality of interconnects, the second plurality of solder interconnects, and the first plurality of interconnects, a polymer layer located between the first integrated device and the second integrated device, and a plurality of spacer balls located between the first integrated device and the second integrated device.

[0007] Another example provides a method for making a package. The method provides a second integrated device comprising a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects. The method provides a polymer layer and a plurality of spacer balls on the second integrated device. The method couples the first integrated device comprising the first plurality of interconnects to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects. The first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device.

[0008] Various features, nature and advantages may become apparent from the following detailed description when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates a cross-sectional side view of a package including an integrated device coupled to another integrated device with spacer balls between the integrated devices. [Diagram 2]1 illustrates a cross-sectional side view of a package including a first integrated device coupled to a second integrated device with spacer balls between the first and second integrated devices. [Diagram 3] 1 illustrates a cross-sectional side view of a package including a first integrated device coupled to a second integrated device with spacer balls between the first and second integrated devices. [Figure 4] 1 illustrates a cross-sectional side view of a package including a first integrated device coupled to a second integrated device without spacer balls between the first integrated device and the second integrated device. [Diagram 5] 1 shows a wafer containing several integrated devices with a polymer layer and spacer balls. [Figure 6A] 1 illustrates an exemplary sequence for making a package that includes a first integrated device coupled to a second integrated device with spacer balls between the first and second integrated devices. [Figure 6B] 1 illustrates an exemplary sequence for making a package that includes a first integrated device coupled to a second integrated device with spacer balls between the first and second integrated devices. [Figure 7] FIG. 1 illustrates an example flow diagram of a method for making a package including a first integrated device coupled to a second integrated device using spacer balls between the first integrated device and the second integrated device. [Figure 8A] 1 illustrates an exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 8B] 1 illustrates an exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 9] 1 shows an exemplary flow diagram of a method for fabricating an integrated device having pillar interconnects. [Figure 10]Various electronic devices are illustrated that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are described for a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011] The present disclosure describes a package including a first integrated device having a first plurality of interconnects, a plurality of solder interconnects coupled to the first plurality of interconnects, a second integrated device having a second plurality of interconnects, the second integrated device being coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects, a polymer layer located between the first integrated device and the second integrated device, and a plurality of spacer balls located between the first integrated device and the second integrated device. The use of the plurality of spacer balls helps ensure that the space (e.g., bond line thickness) between the first integrated device and the second integrated device is constant and / or uniform, which helps provide a robust and reliable joint (e.g., solder joint) between the first integrated device (e.g., first die) and the second integrated device (e.g., second die).

[0012] Exemplary Package with Inter-Integrated Device Coupling Using Spacers Between Integrated Devices 1 shows a package 100 including integrated device-to-integrated device bonding (e.g., die-to-die bonding) using spacers between the integrated devices. The package 100 includes an integrated device stack 101, an integrated device 103, a substrate 102, and a substrate 104. The substrate 102 may be a package substrate. The substrate 104 may be an interposer.

[0013] The substrate 104 is coupled to the substrate 102 via a plurality of solder interconnects 110. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and the plurality of interconnects 142. The integrated device 103 is coupled to a first surface (e.g., a top surface) of the substrate 104 via a plurality of solder interconnects 130. The integrated device stack 101 is coupled to the first surface of the substrate 104 via a plurality of solder interconnects 150.

[0014] FIG. 2 shows an expanded view of an integrated device stack 101 (e.g., a stack of integrated devices, a vertical stack of integrated devices) including a number of integrated devices. The integrated device stack 101 can be a package including several integrated devices. The integrated device stack 101 includes integrated devices stacked on top of each other (e.g., vertically stacked integrated devices). The integrated device stack 101 includes an integrated device 105, an integrated device 107a, an integrated device 107b, and an integrated device 107c. The integrated device stack 101 includes a number of spacer balls 190a, a number of spacer balls 190b, a number of spacer balls 190c, a polymer layer 192a, a polymer layer 192b, a polymer layer 192c, an underfill 204a, an underfill 204b, and an underfill 204c. As described further below, a number of spacer balls (e.g., 190a, 190b, 109c) are spacers located between the integrated devices to help provide a constant and uniform gap between the integrated devices, which helps to ensure proper, robust, and / or reliable joints (e.g., solder joints) between the integrated devices.

[0015] As described above, the integrated device stack 101 may be coupled to a substrate 104. The integrated device 105 may be coupled to a first surface of the substrate 104 via a number of solder interconnects 150.

[0016] The integrated device 107a is coupled to the integrated device 105 via a plurality of solder interconnects 170a. A plurality of spacer balls 190a, a polymer layer 192a, and an underfill 204a are located between the integrated device 105 and the integrated device 107a. The integrated device 107b is coupled to the integrated device 107a via a plurality of solder interconnects 170b. A plurality of spacer balls 190b, a polymer layer 192b, and an underfill 204b are located between the integrated device 107b and the integrated device 107a. The integrated device 107c is coupled to the integrated device 107b via a plurality of solder interconnects 170c. A plurality of spacer balls 190c, a polymer layer 192c, and an underfill 204c are located between the integrated device 107c and the integrated device 107b.

[0017] The integrated device 105 includes pad interconnects 250, pillar interconnects 252, pad interconnects 254, and interconnects 255. Pad interconnects 250, pillar interconnects 252, and / or pad interconnects 254 may be examples of interconnects of the integrated device 105. Interconnects 255 are coupled to pad interconnects 250 and pad interconnects 254. Interconnects 255 may include die interconnects and / or through-substrate vias.

[0018] The integrated device 107a includes a plurality of pad interconnects 270a, a plurality of pillar interconnects 272a, a plurality of pad interconnects 274a, a plurality of pillar interconnects 276a, and a plurality of interconnects 275a. The plurality of pad interconnects 270a, the plurality of pillar interconnects 272a, the plurality of pad interconnects 274a, and / or the plurality of pillar interconnects 276a may be examples of a plurality of interconnects of the integrated device 107a. The plurality of interconnects 275a are coupled to the plurality of pad interconnects 270a and the plurality of pad interconnects 274a. The plurality of interconnects 275a may include a plurality of die interconnects and / or a plurality of through-substrate vias.

[0019] The integrated device 107b includes a plurality of pad interconnects 270b, a plurality of pillar interconnects 272b, a plurality of pad interconnects 274b, a plurality of pillar interconnects 276b, and a plurality of interconnects 275b. The plurality of pad interconnects 270b, the plurality of pillar interconnects 272b, the plurality of pad interconnects 274b, and / or the plurality of pillar interconnects 276b may be examples of a plurality of interconnects of the integrated device 107b. The plurality of interconnects 275b are coupled to the plurality of pad interconnects 270b and the plurality of pad interconnects 274b. The plurality of interconnects 275b may include a plurality of die interconnects and / or a plurality of through-substrate vias.

[0020] The integrated device 107c may include pad interconnects 270c, pillar interconnects 272c, and interconnects 275c. The pad interconnects 270c and pillar interconnects 272c may be examples of interconnects of the integrated device 107c. The interconnects 275c may be coupled to the pad interconnects 270c. The interconnects 275c may include die interconnects and / or through-substrate vias.

[0021] The plurality of solder interconnects 150 are coupled to the plurality of pillar interconnects 252. The plurality of solder interconnects 170a are coupled to the plurality of pad interconnects 254 and to the plurality of pillar interconnects 272a. The plurality of solder interconnects 170b are coupled to the plurality of pillar interconnects 276a and to the plurality of pillar interconnects 272b. The plurality of solder interconnects 170c are coupled to the plurality of pillar interconnects 276b and to the plurality of pillar interconnects 272c.

[0022] In some implementations, integrated device 105 may include a logic die (e.g., a logic semiconductor die). In some implementations, integrated device 107a may include a memory die (e.g., a memory semiconductor die). In some implementations, integrated device 107b may include a memory die (e.g., a memory semiconductor die). In some implementations, integrated device 107c may include a memory die (e.g., a memory semiconductor die).

[0023] The integrated device may include a die substrate (e.g., a silicon substrate), through substrate vias (TSVs), transistors and / or logic cells (not shown), die dielectric layers, and die interconnects. The transistors and / or logic cells may be formed in and / or on the die substrate. Front end of line (FEOL) processes may be used to form the transistors and / or logic cells in and on the die substrate. Die dielectric layers and die interconnects may be formed on the die substrate and the transistors and / or logic cells. Back end of line (BEOL) processes may be used to form the die dielectric layers and die interconnects. The die interconnects may be coupled to the transistors and / or logic cells. The die interconnects may be coupled to the through substrate vias (TSVs). It should be noted that the interconnects 275 (e.g., 275a, 275b, 275c) may conceptually represent interconnects that may be located within an integrated device. For example, the interconnects 275 (e.g., 275a, 275b, 275c) of an integrated device may conceptually represent one or more through-substrate vias (TSVs) and / or one or more die interconnects of the integrated device. The integrated device may include a front side and a back side. The back side of the integrated device may include a side or surface that includes the die substrate. The front side of the integrated device may be the side facing opposite the back side. As shown in FIG. 2, the integrated device may include a plurality of interconnects located on a back surface of the integrated device. The plurality of interconnects located on a back surface of the integrated device may be a plurality of back surface interconnects. The backside interconnects may include pillar interconnects (eg, backside surface pillar interconnects) and / or pad interconnects (eg, backside surface pad interconnects).

[0024] In one example, the multiple pad interconnects 250 and the multiple pillar interconnects 252 can be considered as front side interconnects of the integrated device 105, and the multiple pad interconnects 254 can be considered as back side interconnects of the integrated device 105.

[0025] In one example, the multiple pad interconnects 250 and the multiple pillar interconnects 252 can be considered as backside interconnects of the integrated device 105, and the multiple pad interconnects 254 can be considered as frontside interconnects of the integrated device 105.

[0026] In one example, the pad interconnects 270a and the pillar interconnects 272a can be considered as the front side interconnects of the integrated device 107a, and the pad interconnects 274a and the pillar interconnects 276a can be considered as the back side interconnects of the integrated device 107a. In one example, the pad interconnects 270a and the pillar interconnects 272a can be considered as the back side interconnects of the integrated device 107a, and the pad interconnects 274a and the pillar interconnects 276a can be considered as the front side interconnects of the integrated device 107a.

[0027] In one example, the pad interconnects 270b and the pillar interconnects 272b can be considered as the front side interconnects of the integrated device 107b, and the pad interconnects 274b and the pillar interconnects 276b can be considered as the back side interconnects of the integrated device 107b. In one example, the pad interconnects 270b and the pillar interconnects 272b can be considered as the back side interconnects of the integrated device 107b, and the pad interconnects 274b and the pillar interconnects 276b can be considered as the front side interconnects of the integrated device 107b.

[0028] In one example, the pad interconnects 270c and the pillar interconnects 272c can be considered as front side interconnects of the integrated device 107c. In one example, the pad interconnects 270c and the pillar interconnects 272c can be considered as back side interconnects of the integrated device 107c.

[0029] FIG. 3 illustrates a package 300 including an integrated device 305 (e.g., a first integrated device, a first die) and an integrated device 307 (e.g., a second integrated device, a second die). The package 300 illustrates an example of an integrated device-to-integrated device bond (e.g., die-to-die bond). The integrated device 305 is bonded to the integrated device 307 via a plurality of solder interconnects 170. The integrated device 305 includes a passivation layer 353, a plurality of pad interconnects 350, and a plurality of pillar interconnects 352. The integrated device 307 includes a passivation layer 373, a plurality of pad interconnects 370, and a plurality of pillar interconnects 372. The plurality of solder interconnects 170 are bonded to the plurality of pillar interconnects 352 and the plurality of pillar interconnects 372. An underfill 204 is present between the integrated device 305 and the integrated device 307. The underfill 204 may laterally surround the solder interconnects 170 , the pillar interconnects 352 , and / or the pillar interconnects 372 .

[0030] Located between the integrated device 305 and the integrated device 307 are a plurality of spacer balls 190 (e.g., spacers) and a polymer layer 192. The plurality of spacer balls 190 may be located at least partially within the polymer layer 192. The plurality of spacer balls 190 and the polymer layer 192 are located along the periphery of the integrated device 305, the integrated device 307, and / or the package 300.

[0031] In some implementations, the pitch between adjacent solder interconnects from the plurality of solder interconnects 170 is about 5-20 micrometers. In some implementations, the pitch between adjacent pillar interconnects from the plurality of pad interconnects 350 is about 5-20 micrometers. In some implementations, the pitch between adjacent pillar interconnects from the plurality of pillar interconnects 352 is about 5-20 micrometers. In some implementations, the pitch between adjacent pillar interconnects from the plurality of pad interconnects 370 is about 5-20 micrometers. In some implementations, the pitch between adjacent pillar interconnects from the plurality of pillar interconnects 372 is about 5-20 micrometers. In some implementations, the plurality of spacer balls 190 (e.g., spacers) may have a diameter of about 5-20 micrometers.

[0032] A gap 301 exists between the passivation layer 353 of the integrated device 305 and the passivation layer 373 of the integrated device 307. The gap 301 may represent a bond line thickness (BLT) between the integrated device 305 and the integrated device 307. The gap 301 is provided by the use of a plurality of spacer balls 190 (e.g., spacers). The plurality of spacer balls 190 help to provide a uniform, constant, or substantially constant gap between the integrated device 305 and the integrated device 307. This, in turn, helps to ensure that there is a robust and reliable bond between the integrated device 305 and the integrated device 307. In some implementations, the gap 301 may be about 5 to 20 micrometers.

[0033] FIG. 3 shows an example of front-to-front bonding of integrated devices. That is, the front side of a first integrated device is bonded to the front side of a second integrated device. However, two integrated devices may be bonded together via front-to-backside bonding, where the front side of an integrated device is bonded to the back side of another integrated device. In another example, two integrated devices may be bonded together via back-to-backside bonding, where the back side of an integrated device is bonded to the back side of another integrated device. The integrated device stack 101 (e.g., a stack of integrated devices) of FIGS. 1 and 2 may include integrated devices bonded to each other via front-to-front bonding, front-to-backside bonding, back-to-front bonding, and / or back-to-backside bonding.

[0034] For clarity, it should be noted that package 300 does not necessarily show all of the components of an integrated device. For example, integrated device 305 and / or integrated device 307 may each include other components such as a die substrate (e.g., silicon substrate), a plurality of transistors and / or logic cells, a plurality of die interconnects, at least one die dielectric layer, a plurality of through-substrate vias, and / or a plurality of backside interconnects (e.g., backside pad interconnects, backside pillar interconnects). The plurality of through-substrate vias may be coupled to a plurality of die interconnects. The plurality of through-substrate vias may be coupled to a plurality of backside interconnects. The plurality of die interconnects may be coupled to a plurality of pad interconnects. Integrated device 305 and / or integrated device 307 may be similar or the same as integrated device 105, 107a, 107b, and / or 107c of FIG. 1 and FIG. 2.

[0035] FIG. 4 shows an example of what can happen when integrated device-to-integrated device bonding without using spacer balls. FIG. 4 shows a package 400 similar to package 300. However, package 400 does not include spacer balls. During the process of bonding integrated device 307 to integrated device 305, more pressure may be applied to one side of the integrated device, resulting in one side of package 400 having gap 401a and the other side of package 400 having gap 401b. Gap 401b is larger than gap 401a. Gap differences and / or gap variations may result in a bad or open joint between integrated device 305 and integrated device 307. For example, solder interconnect 470 between integrated device 305 and integrated device 307 is not as robust and reliable as solder interconnect 170 because solder interconnect 470 is stretched due to the higher gap 401b between integrated device 305 and integrated device 307. The plurality of spacer balls 190 helps ensure that such variations in the gap are minimized, reduced, and / or eliminated.

[0036] FIG. 5 shows a wafer 500 including a plurality of integrated devices 502 (e.g., uncut integrated devices). The plurality of integrated devices 502 are fabricated simultaneously and then singulated in a fabrication process. The plurality of integrated devices 502 includes an integrated device 502a and an integrated device 502b. The plurality of integrated devices 502 may be separated by a sawing region 504. The sawing region 504 may be an area of ​​the wafer 500 that may be filled with a plurality of spacer balls 190 and a polymer layer 192. The sawing region 504 may include a sawing line 506 that is a portion of the wafer that is cut or removed to singulate the integrated devices. The plurality of spacer balls 190 may be at least partially located within the polymer layer 192. The polymer layer 192 may include an adhesive. The polymer layer 192 helps to position the spacer balls 190 in the appropriate areas between the uncut integrated devices. The plurality of spacer balls 190 may include particles including monodisperse particles, silica, glass, polymer, ceramic, and / or metal. For example, the spacer balls 190 may include polyethylene polymer particles. An underfill 204 (e.g., a non-conductive film (NCF) underfill, a wafer level underfill (WLUF)) may laterally surround the solder interconnects 170 and / or the pillar interconnects 352.

[0037] The integrated device (e.g., 105, 107, 305, 307) may include a die (e.g., a semiconductor bare die). The integrated device may include a die substrate (e.g., a silicon substrate), a plurality of transistors and / or logic cells, a plurality of die interconnects, and a plurality of pad interconnects. The integrated device may include a logic die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor (e.g., a power management integrated circuit (PMIC)), and / or combinations thereof. An integrated device (e.g., 105, 107, 305, 307) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). In some implementations, the integrated device may be a chiplet. Chilets may improve yield during fabrication and may lower the overall cost of fabricating the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., another integrated device). Using several chiplets to perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0038] Having described various packages having integrated inter-device bonds using spacers (e.g., spacer balls) between the integrated devices, a process for fabricating packages including integrated inter-device bonds will now be described below.

[0039] Exemplary sequence for making a package with integrated device-to-integrated device bonds using spacers between the integrated devices 6A and 6B show an example sequence for providing or making a package. In some implementations, the sequence of FIG. 6A and 6B can be used to provide or make the package 300 of FIG. 3 or any of the packages described in this disclosure.

[0040] It should be noted that the sequence of Figures 6A and 6B may combine one or more steps to simplify and / or clarify the sequence for providing or making the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be exchanged or substituted without departing from the scope of the present disclosure. In different implementations, the packages may be made differently. The sequence of Figures 6A and 6B shows an example of making two packages together. However, the sequence of Figures 6A and 6B may be used to make two or more packages stacked vertically on top of each other.

[0041] Stage 1 shows a subsequent state of a wafer 600 including integrated devices 307a and 307b, as shown in FIG. 6A. Integrated devices 307a and 307b are uncut integrated devices from the integrated devices of wafer 600. Each integrated device may include pad interconnects 370, pillar interconnects 372, and solder interconnects 170. Wafer 600 may be a second wafer including a second plurality of integrated devices. FIGS. 8A and 8B show an example of a process that may be used to form a wafer including integrated devices.

[0042] Stage 2 shows the state after the spacer balls 190 and the polymer layer 192 are provided on the wafer 600 such that the spacer balls 190 and the polymer layer 192 are located between the uncut integrated devices. For example, the spacer balls 190 and the polymer layer 192 may be provided in the cutting region 504 of the wafer. The cutting region 504 may be the region that will be cut to singulate the integrated devices of the wafer 600. The polymer layer 192 may include an adhesive layer to help position the spacer balls in the appropriate areas of the wafer 600.

[0043] Stage 3 illustrates the state after underfill 204 has been formed over the integrated devices (e.g., uncut integrated devices) of wafer 600 such that the underfill can laterally surround multiple pillar interconnects 372 and / or multiple solder interconnects 170.

[0044] Stage 4, as shown in FIG. 6B, illustrates a subsequent state of the wafer 610 including integrated devices 305a and 305b. Integrated devices 305a and 305b are undiced integrated devices from the integrated devices of the wafer 610. Each integrated device may include a plurality of pad interconnects 350, a plurality of pillar interconnects 352, and a plurality of solder interconnects 170. The wafer 610 may be a first wafer including a plurality of first integrated devices. FIGS. 8A and 8B illustrate an example of a process that may be used to form a wafer including integrated devices.

[0045] Stage 5 shows the state after wafer 600 has been bonded to wafer 610. A solder reflow process can be used to bond wafer 600 to wafer 610. Wafer 600 (with integrated devices 307) is bonded to wafer 610 (with integrated devices 305) via multiple solder interconnects 170. Multiple spacer balls 190 help ensure a uniform or near uniform gap between wafer 600 and wafer 610.

[0046] Stage 6 shows the state after wafers 600 and 610 have been singulated to create multiple packages with integrated device-to-device bonds. Wafers 600 and 610 may be cut along cut lines 620. After singulation, packages 300a and 300b may be formed. Mechanical processes (e.g., saws) or laser processes may be used to singulate the wafers. In some implementations, prior to singulation, additional wafers may be bonded to form packages including three or more integrated devices as shown in FIG. 2.

[0047] FIG. 1 is an exemplary flow diagram of a method for fabricating a package with integrated device-to-integrated device bonds using spacers between the integrated devices; In some implementations, producing the package includes several processes. Figure 7 shows an example flow diagram of a method 700 for providing or producing a package. In some implementations, the method 700 of Figure 7 can be used to provide or produce the package 300 of Figure 3 described in this disclosure. However, the method 700 can be used to provide or produce any of the packages described in this disclosure.

[0048] It should be noted that the method of Figure 7 may combine one or more processes to simplify and / or clarify the method for providing a package having several integrated devices. In some implementations, the order of the processes may be changed or modified.

[0049] The method prepares (at 705) a wafer including a plurality of integrated devices. For example, the method can prepare a wafer 600 including a plurality of integrated devices. The plurality of integrated devices are uncut integrated devices. The wafer 600 can be a second wafer including a plurality of second integrated devices. Each uncut integrated device can include a plurality of pad interconnects 370, a plurality of pillar interconnects 372, and a plurality of solder interconnects 170. Figures 8A and 8B show an example of a process that can be used to form a wafer including integrated devices. Stage 1 of Figure 6A illustrates and describes an example of preparing a wafer having uncut integrated devices.

[0050] The method provides (at 710) a plurality of spacer balls 190 and a polymer layer 192 on a wafer (e.g., 600) such that the plurality of spacer balls 190 and the polymer layer 192 are located between the uncut integrated devices. For example, the plurality of spacer balls 190 and the polymer layer 192 may be provided in a cutting region 504 of the wafer. The cutting region 504 may be an area that is cut to singulate the integrated devices of the wafer (e.g., 600). The polymer layer 192 may include an adhesive layer to help position the spacer balls in the appropriate areas of the wafer (e.g., 600). Step 2 of FIG. 6A illustrates and describes an example of providing spacer balls and a polymer layer.

[0051] The method provides (at 715) an underfill (e.g., 204) over the integrated device of the wafer (e.g., 600) such that the underfill can laterally surround the pillar interconnects 372 and / or the solder interconnects 170. Step 3 of Figure 6A illustrates and describes one example of providing the underfill.

[0052] The method prepares (at 720) a wafer (e.g., 610) including a plurality of integrated devices. For example, the method can prepare a wafer 610 including a plurality of integrated devices. The wafer 610 includes uncut integrated devices. Each uncut integrated device can include a plurality of pad interconnects 350, a plurality of pillar interconnects 352, and a plurality of solder interconnects 170. The wafer 610 can be a first wafer including a plurality of first integrated devices. Figures 8A and 8B show an example of a process that can be used to form a wafer including integrated devices. Step 4 of Figure 6B illustrates and describes an example of preparing a wafer including uncut integrated devices.

[0053] The method includes (at 725) bonding a second wafer (e.g., 600) to the first wafer (e.g., 610). A solder reflow process can be used to bond the second wafer to the first wafer. The second wafer (e.g., 600) comprising a plurality of second integrated devices can be bonded to the first wafer (e.g., 610) comprising a plurality of first integrated devices via a plurality of solder interconnects (e.g., 170). A plurality of spacer balls 190 helps ensure a uniform or near-uniform gap between the wafers 600 and 610. Stage 5 of FIG. 6B illustrates and describes an example of bonding wafers. In some implementations, additional wafers can be bonded to the bonded wafers.

[0054] The method singulates (at 730) the wafer to form a singulated package including several integrated devices with spacer balls and a polymer layer between the integrated devices. A mechanical process (e.g., a saw) or a laser process can be used to singulate the wafer. Step 6 of FIG. 6B illustrates and describes one example of singulating the wafer.

[0055] Exemplary Sequence for Fabricating an Integrated Device Having Pillar Interconnects 8A and 8B show an example sequence for providing or fabricating an integrated device having pillar interconnects. In some implementations, the sequence of FIG. 8A and 8B can be used to provide or fabricate the integrated device of FIG. 3 (e.g., 305, 307) or any of the integrated devices described in this disclosure.

[0056] 8A and 8B may combine one or more steps to simplify and / or clarify the sequence for providing or making the integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure. In different implementations, the integrated device may be made differently.

[0057] As shown in Figure 8A, stage 1 illustrates a state after an integrated device 305 is prepared. The integrated device 305 may include a die (e.g., a bare semiconductor die). The integrated device 305 may include a die substrate (e.g., a silicon substrate) and a number of transistors (e.g., active devices). The integrated device 305 may include a number of pad interconnects 350. The integrated device 305 may include die interconnects and / or through-substrate vias.

[0058] Stage 2 shows the state after a seed layer 811 is formed on the front side of the integrated device 305. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 305. A plating process may be used to form the seed layer 811.

[0059] Stage 3 shows the state after a photoresist layer 800 is formed on the seed layer 811. The photoresist layer 800 may be deposited on the seed layer 811.

[0060] Stage 4 shows the state after the photoresist layer 800 has been patterned to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811 .

[0061] 8B, stage 5 shows the state after a plurality of pillar interconnects 830 and a plurality of solder interconnects 832 are formed on the seed layer 811 through the openings 801 in the photoresist layer 800. The plurality of pillar interconnects 830 may be formed on the seed layer 811 by a plating process. The plurality of solder interconnects 170 may be formed on the plurality of pillar interconnects 830 by a deposition process.

[0062] Stage 6 shows the state after the photoresist layer 800 has been removed and a portion of the seed layer 811 has been removed (e.g., etched). Removing the photoresist layer 800 may include stripping the photoresist layer 800.

[0063] Stage 7 illustrates a state after a reflow solder process that couples (e.g., bonds) the solder interconnects 170 to the pillar interconnects 830. Stage 7 may illustrate an integrated device (e.g., 305, 307) having pillar interconnects. The pillar interconnects 830 may represent the pillar interconnects 352. The seed layer 811 may be considered a part of the pillar interconnect 830. Thus, the seed layer 811 and the pillar interconnects 830 may represent the pillar interconnects 352.

[0064] 1 is an exemplary flow diagram of a method for fabricating an integrated device with pillar interconnects; In some implementations, fabricating an integrated device with pillar interconnects includes several processes. Figure 9 shows an example flow diagram of a method 900 for providing or fabricating an integrated device with pillar interconnects. In some implementations, the method 900 of Figure 9 can be used to provide or fabricate the integrated device of Figure 3 (e.g., 305, 307) described herein. However, the method 900 can be used to provide or fabricate any of the integrated devices described herein.

[0065] It should be noted that the method 900 of Figure 9 may combine one or more processes to simplify and / or clarify a method for providing or fabricating an integrated device having pillar interconnects. In some implementations, the order of the processes may be changed or modified.

[0066] The method provides (at 905) an integrated device (e.g., 305, 307). Step 1 of FIG. 8A illustrates and describes the provided integrated device 305. The integrated device 305 may include a die having active devices such as transistors. The integrated device may include a plurality of pad interconnects. The integrated device may include a die substrate, die interconnects, and / or through-substrate vias.

[0067] The method forms (at 910) a seed layer (e.g., 811) on a front side of the integrated device. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 305. A plating process may be used to form the seed layer 811. Step 2 of FIG. 8A illustrates and describes one example of forming a seed layer.

[0068] The method includes (at 915) forming a photoresist layer (e.g., 800) on the seed layer (e.g., 811). The photoresist layer 800 may be formed and patterned on the seed layer 811. The photoresist layer 800 may be deposited on the seed layer 811 and patterned to form at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811. Steps 3 and 4 of FIG. 8A illustrate and describe one example of forming and patterning a photoresist layer on a seed layer.

[0069] The method forms (at 920) a plurality of pillar interconnects (e.g., 830) and / or solder interconnects (e.g., 170) on a seed layer (e.g., 811) through openings 801 in a photoresist layer (e.g., 800). The plurality of pillar interconnects may be formed on the seed layer by a plating process. The plurality of solder interconnects may be formed on the plurality of pillar interconnects by a deposition process and / or a printing process. Step 5 of FIG. 8B illustrates and describes one example of forming a plurality of pillar interconnects and / or a plurality of solder interconnects.

[0070] The method removes (at 925) the photoresist layer (e.g., 800). Removing the photoresist layer may include stripping the photoresist layer. Step 6 of FIG. 8B illustrates an example of removing the photoresist layer. In some implementations, (at 925) a portion of the seed layer 811 may also be removed. An etching process may be used to remove the portion of the seed layer. Step 6 of FIG. 8B illustrates and describes an example of a portion of the seed layer that is removed. It should be noted that forming the photoresist layer, pillar interconnects and / or solder interconnects, and removing the photoresist layer as described at 915, 920, and 925 may be repeated.

[0071] The method performs (at 930) a reflow solder process to couple (e.g., bond) the plurality of solder interconnects (e.g., 170) to the plurality of pillar interconnects (e.g., 830). The plurality of pillar interconnects 830 and / or the seed layer 811 may represent the plurality of pad interconnects 350. Step 7 of Figure 8B illustrates and describes one example of a reflow solder process.

[0072] In some implementations, the integrated devices are part of a wafer, and singulation can be performed to cut the wafer into individual integrated devices. Method 900 can be used to fabricate any of the integrated devices described in this disclosure.

[0073] Exemplary Electronic Devices FIG. 10 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1002, a laptop computer device 1004, a stationary terminal device 1006, a wearable device 1008, or an automobile vehicle 1010 may include a device 1000 described herein. The device 1000 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1002, 1004, 1006, and 1008 and the automobile vehicle 1010 illustrated in FIG. 10 are merely exemplary. Other electronic devices may also be equipped with device 1000, including any group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0074] One or more of the components, processes, features, and / or functions shown in Figures 1-5, 6A and 6B, 7, 8A and 8B, and / or 9 and 10 may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 1-5, 6A and 6B, 7, 8A and 8B, and / or 9 and 10 and corresponding descriptions in the present disclosure are not limited to dies and / or ICs. In some implementations, Figures 1-5, 6A and 6B, 7, 8A and 8B, and / or 9 and 10 and corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0075] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0076] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate an electric current between the two objects. The terms "first", "second", "third" and "fourth" (and / or ordinal numbers greater than fourth) are used optionally. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulating" means that one object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are used optionally. A top component may be located above a bottom component. A top component may also be considered a bottom component, and vice versa. As described in this disclosure, a first component "over" a second component may mean that the first component is located above or below the second component, depending on how bottom or top is optionally defined.In another example, a first component may be located on (e.g., above) a first surface of a second component, and a third component may be located on (e.g., below) a second surface of the second component, where the second surface is the opposite side to the first surface. It is further noted that in the context of one component being located on another component, the term "over" as used herein may be used to mean a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component that is on a second component may mean (1) that the first component is on but not in direct contact with the second component, (2) that the first component is on (e.g., on the surface of) the second component, and / or (3) that the first component is within (e.g., embedded within) the second component. A first component that is "in" a second component may be partially located within the second component or completely located within the second component. A value that is about X to XX may mean a value between X and XX, inclusive. The value or values ​​between X and XX may be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0077] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), a ground, and / or a power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process can be used to form the interconnects.

[0078] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0079] The following provides a summary of aspects of the disclosure. Aspect 1: A package comprising: a first integrated device having a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device having a second plurality of interconnects, the second integrated device coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

[0080] Embodiment 2: The package of embodiment 1, wherein the polymer layer comprises an adhesive layer.

[0081] Embodiment 3: The package of embodiments 1-2, wherein the plurality of spacer balls are at least partially located within the polymer layer.

[0082] Aspect 4: The package of aspects 1-3, wherein the plurality of spacer balls comprises monodisperse particles, particles comprising silica, glass, polymer, ceramic, and / or metal.

[0083] Embodiment 5: The package of embodiments 1-3, wherein the plurality of spacer balls comprises polyethylene polymer particles.

[0084] Example 6: The package of Examples 1-5, further comprising an underfill between the first integrated device and the second integrated device.

[0085] Embodiment 7: The package of embodiments 1-6, wherein the pitch between adjacent interconnects from the first plurality of interconnects is about 20 micrometers or less.

[0086] Example 8: A package as described in Examples 1-7, wherein the pitch between adjacent solder interconnects from the plurality of solder interconnects is about 20 micrometers or less.

[0087] Aspect 9: A package as described in aspects 1 to 8, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of pillar interconnects.

[0088] Embodiment 10: The package of embodiments 1-9, wherein the first integrated device includes a first die and the second integrated device includes a second die.

[0089] Aspect 11: The package of aspects 1-10, wherein the first integrated device includes a first memory die and the second integrated device includes a logic die or a second memory die.

[0090] Example 12: The package of Examples 1 to 11, further comprising: a third integrated device having a third plurality of interconnects, a second polymer layer located between the third integrated device and the second integrated device, and a second plurality of spacer balls located between the third integrated device and the second integrated device.

[0091] Example 13: The package of example 12, wherein the third integrated device is coupled to the second integrated device via a third plurality of interconnects and / or a second plurality of solder interconnects.

[0092] Example 14: The package of example 12, wherein the second integrated device includes a plurality of through-substrate vias.

[0093] Aspect 15: A package as described in aspects 1 to 14, wherein the first plurality of interconnects includes a first plurality of pillar interconnects and / or a first plurality of pad interconnects, and the second plurality of interconnects includes a second plurality of pillar interconnects and / or a second plurality of pad interconnects.

[0094] Aspect 16: A package described in aspects 1 to 15, wherein the first integrated device includes a third plurality of interconnects, the first plurality of interconnects being located on a first surface of the first integrated device, and the third plurality of interconnects being located on a second surface of the first integrated device.

[0095] Aspect 17: The package described in aspects 1 to 16, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0096] A package including a substrate and a stack of integrated devices coupled to the substrate via a first plurality of solder interconnects, the stack of integrated devices including a first integrated device having a first plurality of interconnects, a second plurality of solder interconnects coupled to the first plurality of interconnects, a second integrated device having a second plurality of interconnects, the second integrated device coupled to the first integrated device via the second plurality of interconnects, the second plurality of solder interconnects, and the first plurality of interconnects, a polymer layer located between the first integrated device and the second integrated device, and a plurality of spacer balls located between the first integrated device and the second integrated device.

[0097] Example 19: The package of example 18, wherein a first integrated device from the stack of integrated devices is coupled to the substrate via a first plurality of solder interconnects.

[0098] Aspect 20: The package of aspects 18 and 19, wherein the plurality of spacer balls comprises monodisperse particles, polyethylene polymer particles, particles comprising silica, glass, polymer, ceramic, and / or metal.

[0099] Example 21: The package of any one of Examples 18-20, further comprising an underfill between the first integrated device and the second integrated device.

[0100] Aspect 22: A package described in aspects 18 to 21, wherein the first integrated device is bonded to the second integrated device via a front-to-front bond, a front-to-back bond, a back-to-front bond, or a back-to-back bond.

[0101] Aspect 23: A method for making a package, comprising: preparing a second integrated device comprising a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects; providing a polymer layer and a plurality of spacer balls on the second integrated device; and coupling the first integrated device comprising the first plurality of interconnects to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects, wherein the first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device.

[0102]

[0046] Example 24: The method of example 23, wherein the polymer layer comprises an adhesive layer.

[0103] Aspect 25: The method of aspects 23 and 24, wherein the plurality of spacer balls comprises monodisperse particles, polyethylene polymer particles, particles comprising silica, glass, polymer, ceramic, and / or metal.

[0104] Example 26: The method of any of Examples 23 to 25, further comprising providing an underfill on the second integrated device, wherein the first integrated device is bonded to the second integrated device such that the underfill is located between the first integrated device and the second integrated device.

[0105] Various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the above aspects of the disclosure are merely examples and should not be construed as limiting the disclosure. The description of the aspects of the disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0106] 100 packages 101 Integrated Device Stack 102 Substrate 103 Integrated Devices 104 Substrate 105 Integrated Devices 107a Integrated Devices 107b Integrated Devices 107c Integrated Device 109a Spacer ball 110 Interconnection 120 Dielectric layer 122 Interconnection 130 Interconnection 140 Dielectric layer 142 Interconnection 150 Interconnect 170 Interconnection 170a Interconnect 170b Interconnect 170c Interconnect 190 Spacer ball 190a Spacer ball 190b Spacer ball 190c spacer ball 192 Polymer Layer 192a Polymer layer 192b Second polymer layer 192b Polymer layer 192c Polymer layer 204 Underfill 204a Underfill 204b Underfill 204c Underfill 250 pad interconnect 252 Pillar Interconnect 254 pad interconnect 255 Interconnect 270a Pad interconnect 270b Pad interconnect 270c pad interconnect 272a Pillar Interconnect 272b Pillar Interconnect 272c Pillar Interconnect 274a Pad Interconnect 274b Pad Interconnect 275 Interconnection 275a Interconnect 275b Interconnect 275c Interconnect 276a Pillar Interconnect 276b Pillar Interconnect 300 packages 300a Package 300b Package 301 Gap 305 Integrated Devices 305a Integrated Devices 305b Integrated Devices 307 Integrated Devices 307a Integrated Devices 307b Integrated Devices 350 Pad Interconnect 352 Pillar Interconnect 353 Passivation Layer 370 Pad Interconnect 372 Pillar Interconnect 373 Passivation Layer 400 packages 401a Gap 401b Gap 470 Interconnect 500 wafers 502 Integrated Devices 502a Integrated Device 502b Integrated Device 504 Cutting area 506 Cutting line 600 wafers 610 Wafer 620 cutting line 800 photoresist layers 801 Aperture 811 Seed Layer 830 Pillar Interconnect 832 Interconnection 1000 devices 1002 Mobile Phone Devices 1004 Laptop Computer Device 1006 Fixed terminal device 1008 Wearable Devices 1010 Automobiles

Claims

1. a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, the second integrated device being coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; a plurality of spacer balls located between the first integrated device and the second integrated device, the plurality of spacer balls being at least partially located within the polymer layer, the plurality of spacer balls being located along the periphery of the first integrated device and the second integrated device; A package comprising:

2. The package of claim 1 , wherein the polymer layer comprises an adhesive layer.

3. The plurality of spacer balls comprises monodisperse particles, particles comprising silica, glass, polymer, ceramic, and / or metal, preferably 10. The package of claim 1, wherein the plurality of spacer balls comprises polyethylene polymer particles.

4. The package of claim 1 further comprising an underfill between the first integrated device and the second integrated device.

5. a pitch between adjacent interconnects from the first plurality of interconnects is about 20 micrometers or less; 10. The package of claim 1, wherein the pitch between adjacent solder interconnects from the plurality of solder interconnects is about 20 micrometers or less.

6. the first plurality of interconnects includes a first plurality of pillar interconnects; the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of pillar interconnects. The package of claim 1.

7. the first integrated device includes a first die; The second integrated device includes a second die, preferably the first integrated device includes a first memory die; the second integrated device includes a logic die or a second memory die; The package of claim 1.

8. a third integrated device comprising a third plurality of interconnects; a second polymer layer located between the third integrated device and the second integrated device; a second plurality of spacer balls located between the third integrated device and the second integrated device; Furthermore, the third integrated device is coupled to the second integrated device via the third plurality of interconnects and a second plurality of solder interconnects; The package of claim 1 , wherein the second integrated device includes a plurality of through-substrate vias.

9. the first plurality of interconnects includes a first plurality of pillar interconnects and / or a first plurality of pad interconnects; the second plurality of interconnects includes a second plurality of pillar interconnects and / or a second plurality of pad interconnects; The package of claim 1.

10. the first integrated device includes a third plurality of interconnects; the first plurality of interconnects are located on a first surface of the first integrated device; the third plurality of interconnects are located on a second surface of the first integrated device; The package of claim 1.

11. 10. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

12. A substrate; a stack of integrated devices coupled to the substrate via a first plurality of solder interconnects; A package comprising: the stack of integrated devices comprising the package of any one of claims 1 to 11; the first integrated device from the stack of integrated devices is coupled to the substrate via the first plurality of solder interconnects; The package, wherein the first integrated device is coupled to the second integrated device via a front-to-front bond, a front-to-back bond, a back-to-front bond, or a back-to-back bond.

13. 1. A method for making a package, comprising: providing a second integrated device comprising a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects; providing a polymer layer and a plurality of spacer balls on the second integrated device; coupling the first integrated device, including the first plurality of interconnects, to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects; Including, the first integrated device is bonded to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device, the plurality of spacer balls are at least partially located within the polymer layer, and the plurality of spacer balls are located along the periphery of the first integrated device and the second integrated device; method.

14. the polymer layer comprises an adhesive layer; The method of claim 13 , wherein the plurality of spacer balls comprises monodisperse particles, polyethylene polymer particles, silica, glass, polymer, ceramic, and / or metal-containing particles.

15. 14. The method of claim 13, further comprising providing an underfill on the second integrated device, wherein the first integrated device is bonded to the second integrated device such that the underfill is located between the first and second integrated devices.

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