Interconnect Structures

Abstract

Disclosed is a semiconductor device having a semiconductor portion, a non-conductive layer disposed on the semiconductor portion, an inner conductive layer formed of a first material and at least partially embedded within the non-conductive layer, a lower conductive layer disposed below and electrically connected to the inner conductive layer, and a barrier layer disposed between the inner conductive layer and the lower conductive layer. The barrier layer is formed of a second material different from the first material, the second material having a thermal conductivity of 30×10 at 20° C. -8 It has an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

Description

[Technical field]

[0001] The technical field relates to interconnect structures and methods of making interconnect structures.

[0002] [Citation to Related Applications] This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 63 / 288,991, entitled "INTERCONNECT STRUCTURES," filed on December 13, 2021, which is incorporated by reference in its entirety and incorporated herein by reference for all purposes. [Background technology]

[0003] Interconnect structures located within or at the surface of a die transmit signals, power, or ground to other circuits within the die or to other dies or elements. For example, semiconductor elements, such as semiconductor wafers or integrated device dies, can be stacked and directly bonded together without adhesives. For example, in some hybrid direct bonded structures, non-conductive field regions of the elements can be directly bonded together, and corresponding conductive contact structures can be directly bonded together. It can be important to ensure that the contact structures are electrically reliable. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device is disclosed having a semiconductor portion, a non-conductive layer disposed on the semiconductor portion, an inner conductive layer formed of a first material and at least partially embedded within the non-conductive layer, a lower conductive layer disposed below and electrically connected to the inner conductive layer, and a barrier layer disposed between the inner conductive layer and the lower conductive layer. The barrier layer is formed of a second material different from the first material, the second material having a thermal conductivity of 30×10 at 20° C. -8 It has an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

[0005] The detailed description is provided with reference to the accompanying drawings, in which the same reference numbers used in different drawings refer to similar or identical items, and in which:

[0006] For purposes of this description, the devices and systems depicted in the figures are shown as having a large number of components. Various implementations of the devices and / or systems described herein may include fewer components and remain within the scope of this disclosure. Alternatively, other implementations of the devices and / or systems may include additional components or different combinations of the components described and still fall within the scope of the invention.

[0007] These and other aspects will become apparent from the following description of the preferred embodiments and the accompanying drawings, which are intended to illustrate, but not to limit, the invention. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of two elements prior to direct bonding according to one embodiment. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements of FIG. 1A after being direct bonded according to one embodiment. [Figure 2A] FIG. 1 is a cross-sectional side view taken under a microscope of a conventional interconnect illustrating the electromigration sequence. [Figure 2B] 1 is a schematic cross-sectional side view of a conventional interconnect illustrating an electromigration sequence in accordance with the present invention; [Diagram 3] 1 is a schematic cross-sectional side view of a portion of a semiconductor device according to one embodiment. [Figure 4A] 1 is a schematic cross-sectional side view of a conventional interconnect before current flowing through the conventional interconnect causes voids to form. [Figure 4B] 4B is a schematic cross-sectional side view of the conventional interconnect of FIG. 4A after voids have formed to increase the resistance through the circuit. [Figure 4C] 1 is a schematic cross-sectional side view of a semiconductor device before current flows through the semiconductor device, according to one embodiment. [Figure 4D] FIG. 4D is a schematic cross-sectional side view of the semiconductor device of FIG. 4C illustrating current flow that uses redundant (extra) paths for flow to suppress void formation. [Figure 5A] 1 is a schematic cross-sectional side view of a bonded structure including dual damascene features according to one embodiment. [Figure 5B] 1 is a schematic cross-sectional side view of a bonded structure including single and dual damascene features according to one embodiment. [Figure 5C] 1 is a schematic cross-sectional side view of a bonded structure including a single damascene feature according to one embodiment. [Figure 6] FIG. 2 is a schematic cross-sectional side view of the layering between a dielectric layer, a low resistance barrier layer, and a conductive layer according to one embodiment. [Figure 7A-7D] 7A-7D are a series of schematic cross-sectional side views illustrating successive steps of a multi-step method by which a conventional interconnect can be formed. [Fig. 7E-7H] 7E-7H are a series of schematic cross-sectional side views illustrating successive steps of a multi-step method by which a conventional interconnect can be formed. [Figure 8A-8E] 8A-8E are a series of schematic cross-sectional side views illustrating a sequence of steps in a multi-step method by which a bonded structure can be formed according to one embodiment. [Fig. 8F-8I] 8F-8I are a series of schematic cross-sectional side views illustrating a sequence of steps in a multi-step method by which a bonded structure can be formed according to one embodiment. [Fig. 8I1-8K]8I1-8K are a series of schematic cross-sectional side views illustrating a sequence of steps in a multi-step method by which a bonded structure can be formed in accordance with one embodiment. [Figure 9A-9D] 9A-9D are schematic cross-sectional side views illustrating a sequence of steps in a multi-step method by which a semiconductor device can be formed having lower, middle, and upper conductive layers, according to one embodiment. [Figure 9E] FIG. 9E is a schematic cross-sectional side view illustrating a sequence of steps in a multi-step method by which a semiconductor device can be formed having lower, middle, and upper conductive layers, according to one embodiment. [Figure 10] 1 is a schematic cross-sectional side view of a semiconductor device according to one embodiment. [Figure 11] 9E is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor elements similar to the semiconductor element shown in FIG. 9E according to one embodiment. [Figure 12] 11 is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor elements similar to the semiconductor element shown in FIG. 10 according to one embodiment. [Figure 13A-13D] 13A-13D are a series of schematic cross-sectional side views illustrating a multi-step method by which a semiconductor device may be formed through the use of plasma processing, according to one embodiment. [Figure 14A] 1 is a schematic cross-sectional side view of a semiconductor device according to one embodiment. [Figure 14B] 14B is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor elements similar to the semiconductor element shown in FIG. 14A. [Figure 14C] 1 is a schematic cross-sectional side view of a semiconductor device according to one embodiment. [Figure 14D] 14D is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor elements similar to the semiconductor element shown in FIG. 14C. [Figure 15A]1 is a schematic cross-sectional side view of a bonded structure formed by direct hybrid bonding of two semiconductor devices, one of which has a through-substrate via (TSV), according to one embodiment. [Figure 15B] 1 is a schematic cross-sectional side view of a bonded structure formed by direct hybrid bonding of two semiconductor devices, one of which has a through-substrate via (TSV), according to one embodiment. [Figure 16] 1 is a schematic cross-sectional side view of a semiconductor device including an inner manganese barrier layer, according to one embodiment. [Figure 17A] 1 is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor devices, one of which has a through-substrate via (TSV), according to one embodiment. [Figure 17B] 1 is a schematic cross-sectional side view of a bonded structure formed by bonding two semiconductor elements together, according to one embodiment. [Figure 17C] 1 is a schematic cross-sectional side view of a semiconductor device including both an inner manganese barrier layer and a through-substrate via (TSV), according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Metal interconnect structures are subject to electromigration and / or other diffusion effects, for example, electromigration may occur in metallization or interconnect layers within a bonding layer of a semiconductor device (e.g., a metallization or interconnect layer made of copper), interconnects within a back-end-of-line (BEOL) of an integrated device die, interconnects within a redistribution layer (RDL), or any other metallization layer with interconnects that include contact structures where there is a transition between metallization layers of different resistivity or different cross-sectional size (e.g., a layer buried within the BEOL, or a semiconductor device bonding layer to be direct hybrid bonded).

[0010] Electromigration is a phenomenon in which metal atoms in the conductive path of a circuit are induced to move in the direction of electron flow. This may be caused by momentum transfer from the atoms to the metal electrons as the electrons flow along the conductive path of the circuit. This movement of metal atoms in the direction of electron flow may be referred to as the atoms being subjected to an "electron wind." Electromigration may cause circuit damage either by creating a short circuit "tailwind" or by creating an open circuit "headwind." Electromigration may create a short circuit "tailwind" because metal atoms moving in the direction of electron flow may be pushed beyond the intended conductive path, thereby creating a metal whisker that can electrically connect to a portion of the circuit that the metal whisker was not intended to electrically connect to. Electromigration may also create an open circuit "headwind" because if there are too many metal atoms moving in the direction of electron flow, there may not be enough metal atoms to be "headwind" to keep the circuit intact. When metal atoms move, they leave behind vacancies if they do so once, and a collection of vacancies may become voids (shown as 22 in FIG. 2A and FIG. 2B), which may impede the flow of electrons. Electromigration problems worsen, for example, as temperatures increase, current densities increase, and interconnect sizes decrease. Electromigration (e.g., current crowding) may also occur when current moves from a more conductive material (e.g., copper) to a less conductive material (e.g., a conventional barrier layer shown as 24 in FIG. 4) and / or when moving from a wide, highly conductive path to a narrow, highly resistive path.

[0011] Various embodiments disclosed herein can provide an improved barrier layer that has a lower electrical resistivity and a higher melting point, thereby reducing electromigration and increasing thermal stability, compared to interconnects without a barrier layer or interconnects including a conventional barrier layer (shown as 24 in FIGS. 4A and 4B). Some embodiments disclosed herein relate to interconnects within a bonding layer (e.g., a layer configured for direct hybrid bonding) of a device, such as contact structures and / or underlying metallization within a bonding layer where transitions exist between metal levels. The embodiments disclosed herein can also reduce electromigration within metallization layers embedded within other layers of a die, such as BEOL and RDL structures.

[0012] As shown in Figures 1A and 1B, in some embodiments, the metallization solutions disclosed herein relate to a bonding layer for a direct bonded structure 1 in which a first element 2 and a second element 3 can be directly bonded to each other without an intervening adhesive. Figure 1A shows the elements 2, 3 before direct bonding. Figure 1B shows the bonded structure after the elements 2, 3 are directly bonded. Two or more semiconductor elements (e.g., integrated device dies, wafers, etc.) 2, 3 can be stacked or bonded to each other to form the bonded structure 1. A conductive contact structure including a contact pad 4a (pad, via, trench) of the first element 2 can be electrically connected to a corresponding conductive contact pad 4b or other conductive contact structure of the second element 3 (e.g., pad to via, pad to trench, etc.). Although only exposed contact pads 4a, 4b are shown in Figures 1A and 1B for purposes of illustrating direct bonding, one skilled in the art will recognize that the bonding layer may include wiring including multiple metal layers and connections between these layers, as shown in Figures 2A-17C. Any suitable number of elements may be stacked within the bonded structure 1. For example, a third element (not shown) may be stacked on the second element 3, a second element (not shown) may be stacked on the third element, and so on. Through substrate vias (TSVs, not shown) may be included to facilitate electrical connections for such further stacks. Additionally or alternatively, one or more additional elements (not shown) may be stacked laterally adjacent to one another along the first element 2.

[0013] In some embodiments, the elements 2, 3 are directly bonded to each other without adhesive. In various embodiments, a non-conductive or dielectric material can serve as the non-conductive bonding layer of the first element 2, which can be directly bonded to a corresponding non-conductive or dielectric field container that can serve as the non-conductive bonding layer 5b of the second element 3 without adhesive. The non-conductive bonding layers 5a, 5b can be provided on the front surfaces 14 of the device portions 6a, 6b, e.g., the semiconductor (e.g., silicon) portions of the elements 2, 3, respectively. Active devices and / or circuitry can be patterned and / or otherwise provided in or on the device portions 6a, 6b. The active devices and / or circuitry can be provided at or near the front surfaces 14 of the device portions 6a, 6b and / or at or near the opposite back surfaces 15 of the device portions 6a, 6b. The non-conductive material may be referred to as the non-conductive bonding region or bonding layer 5a of the first component 2. In some embodiments, the non-conductive bonding layer 5a of the first component 2 may be directly bonded to the corresponding non-conductive bonding layer 5b of the second component 3 using a dielectric-dielectric bonding technique. For example, the non-conductive or dielectric-dielectric bond may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, which are incorporated by reference in their entirety and incorporated by reference for all purposes. It should be appreciated that in various embodiments, the non-conductive bonding layer 5a and / or 5b may be comprised of a non-conductive material, such as a dielectric, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon.

[0014] As shown in FIG. 1A, in various embodiments, the bonding surfaces 8a, 8b include one or more non-conductive portions (e.g., exposed surfaces of the non-conductive bonding layers 5a, 5b) and one or more conductive portions (e.g., exposed surfaces of the contact pads 4a, 4b).

[0015] In various embodiments, the direct bond can be formed without an intervening adhesive. For example, the non-conductive (e.g., dielectric) portions of the bonding surfaces 8a, 8b can be polished to a high degree of smoothness. The non-conductive portions of the bonding surfaces 8a, 8b can be cleaned and exposed to a plasma and / or an etchant to activate the non-conductive portions. In some embodiments, the non-conductive portions of the bonding surfaces 8a, 8b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces 8a, 8b, and a termination process can provide one or more additional chemical species at the bonding surfaces 8a, 8b that improve the bond energy during the direct bond. In some embodiments, activation and termination can be performed in the same step, e.g., plasma can activate and terminate the bonding surfaces 8a, 8b. In other embodiments, the bonding surfaces 8a, 8b can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. Additionally, in some embodiments, the bonding surfaces 8a, 8b can be exposed to fluorine. For example, one or more fluorine peaks can be generated near the layers and / or bonding interface 7 (shown in FIG. 1B). Thus, in the directly bonded structure 1, the bonding interface 7 between the non-conductive portions of the two bonding surfaces 8a, 8b can comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the interface of the bonding interface 7. In various embodiments, the non-conductive portions of the bonding surfaces 8a, 8b comprise the surfaces of the non-conductive bonding layers 5a, 5b.Additional examples of activation and / or end group treatments can be found throughout U.S. Pat. Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0016] In various embodiments, the conductive contact pads 4a of the first component 2 may also be directly bonded to the corresponding conductive contact pads 4b of the second component 3. For example, hybrid bonding techniques may be used to provide conductor-conductor direct bonds along a bonding interface that includes a covalently directly bonded (direct covalent bond) non-conductive-non-conductive (dielectric-dielectric) surface that has been pretreated as described above. In various embodiments, the covalently directly bonded non-conductive surface includes an exposed portion of the surface of the non-conductive bonding layer 5a, 5b. In various embodiments, the conductor-conductor (e.g., contact pad 4a-contact pad 4b) direct bonds and the dielectric-dielectric hybrid bonds may be formed using direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference in its entirety and for all purposes.

[0017] For example, the non-conductive (e.g., dielectric) portions of the bonding surfaces 8a, 8b may be pretreated and directly bonded to one another without an intervening adhesive as described above. The conductive contact pads 4a, 4b (which may be surrounded by a non-conductive dielectric field region in the bonding layers 5a, 5b) may also be directly bonded to one another without an intervening adhesive. In some embodiments, the respective contact pads 4a, 4b may be recessed below the dielectric field or outer (e.g., upper) bonding surfaces 8a, 8b of the non-conductive bonding layers 5a, 5b, e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, or may be recessed within a range of, e.g., 2 nm to 20 nm, or 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses of the opposing elements 2, 3 may be dimensioned such that the overall gap between the opposing contact pads 4a, 4b is less than 15 nm or less than 10 nm. The non-conductive bonding layers 5a, 5b may be direct bonded to one another in some embodiments without a contact agent at room temperature and without applying an external pressure greater than that which brings the bonding surfaces 8a, 8b into contact. Upon annealing, the contact pads 4a, 4b may expand and contact one another, thereby forming a metal-metal direct bond and completing the hybrid direct bonding process. Advantageously, the use of Direct Bond Interconnect, or DBI® technology, commercially available from Adeia, Inc., San Jose, Calif., may provide a high density (e.g., small or fine pitch pads 4a, 4b for a regular array) connected across the direct bonding interface 7. In some embodiments, the pitch p of the conductive traces embedded within the bonding pads 4a, 4b or the bonding surface 8a, 8b of one of the bonded elements, e.g., bonded elements 2 or 3, may be less than 40 microns, less than 10 microns, or even less than 2 microns.For some applications, the ratio of the pitch p of the bond pads 4a, 4b to the bond pad dimensions (e.g., diameter) is less than 5, less than 3, or in some cases desirably less than 2. In other applications, the width of the bonded elements, e.g., the conductive traces embedded within the bonding surface 8 of one of the bonded elements 2 or 3, may range from 0.1 microns to 5 microns. In various embodiments, the contact pads 4a, 4b and / or the traces may be made of copper, although other metals may be suitable.

[0018] Thus, in a direct bonding process, the first element 2 can be directly bonded to the second element 3 without an intervening adhesive. In some configurations, the first element 2 can be a singulated element, such as a singulated integrated device die. In other configurations, as shown in Figures 1A and 1B, the first element 2 can be a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 3 can be a singulated element, such as a singulated integrated device die, as shown in Figures 1A and 1B. In other configurations, the second element 3 can be a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein can be applied to wafer-wafer, die-die, die-wafer, panel-panel, die-panel, or wafer-panel bonding processes.

[0019] As described herein, the first element 2 and the second element 3 may be directly bonded to each other without adhesive, which is different from a deposition process. In one application, the width of the first element 2 in the bonded structure 1 is approximately the same as the width of the second element 3. In some other embodiments, the width of the first element 2 in the bonded structure 1 is different from the width of the second element 3. Similarly, the width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements 2, 3 are non-deposited elements. Furthermore, unlike a deposition layer, the direct bonded structure 1 may include a defect area along the bonding interface 7, in which nanovoids exist. The nanovoids may be formed due to activation (e.g., exposure to plasma) of the bonding surfaces 8a, 8ab. As described above, the bonding interface 7 may include a concentration of material from the activation and / or the final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bonding interface 7. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bonding interface 7. In some embodiments, the bonding interface 7 may be made of silicon nitride, silicon oxycarbonitride, or silicon carbonitride, sapphire, oxide of aluminum, glass, ceramic material, or even glass-ceramic or polymeric material. As described herein, the direct bond may include a covalent bond, which is stronger than a van der Waals bond. The non-conductive bonding layer 5a, 5b may further have a polished bonding surface 8a, 8ab that is planarized to a high degree of smoothness.

[0020] In various embodiments, the metal-metal bond between the contact pads 4a, 4b may be bonded such that the copper grains grow into one another across the bonding interface 7. In some embodiments, the copper may have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bonding interface 7 is such that there is substantially no gap between the non-conductive bonding layers 5a, 5b at or near the bonded contact pad 4a. In some embodiments, a barrier layer (not shown in FIGS. 1A and 1B) may be provided under the contact pads 4a, 4b. However, in other embodiments, there may be no barrier layer under the contact pads 4a, 4b, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference in its entirety and incorporated by reference herein for all purposes.

[0021] Beneficially, the hybrid bonding technique described herein allows for a very fine pitch p between adjacent contact pads 4a or 4b and / or small pad sizes. For example, in various embodiments, the pitch p (see FIG. 1A) between adjacent pads 4a (or 4b) may be in the range of 0.5 microns to 25 microns, 0.75 microns to 25 microns, 1 micron to 25 microns, 1 micron to 10 microns, or 1 micron to 5 microns. Furthermore, the larger lateral dimension (e.g., pad diameter) may be small, for example in the range of 0.25 microns to 8 microns, 0.25 microns to 5 microns, or 0.5 microns to 5 microns. Apart from the pads 4a, 4b, conductive vias and traces of approximately the same pitch as the pad pitch may be provided or embedded in the non-conductive bonding layer 5a, 5b at the bonding interface 7.

[0022] In various embodiments, the second element 3 may comprise a singulated device die and the first element 2 may comprise a wafer or panel. In other embodiments, both elements 2,3 may comprise singulated device dies. In such embodiments, the second element 3 may be initially provided in the form of a wafer or a large substrate and may be singulated to form the singulated first element 2. However, the singulation process and / or other processing steps may generate debris that may contaminate the flat bonding surfaces 8a,8b, thereby leaving behind voids and / or defects when the two elements 2,3 are bonded. Therefore, prior to singulation, a protective layer may be applied to the bonding layer surface 8a or 8b, followed by activation and direct bonding, in order to prevent debris from contaminating the bonding surfaces 8a or 8b. A protective layer (not shown) may consist of an organic or inorganic layer (e.g., photoresist) that is deposited (e.g., spin-coated) onto bonding surface 8a or 8b. Additional details regarding protective layers can be found throughout U.S. Patent No. 10,714,449, which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0023] The wafer containing the first elements 2 may be singulated using a suitable method. A protective layer applied to the bonding surface 8a or 8b may advantageously protect the bonding surface 8a or 8b from debris. Prior to direct bonding, the protective layer may be removed from the bonding surface 8a, 8b using a cleaning agent, for example using a suitable solvent, for example an alkaline solution or other suitable cleaning agent recommended by the protective layer provider. The cleaning agent for the protective layer may be selected such that it does not substantially roughen the smooth bonding surface 8a or 8b of the non-conductive bonding layer 5a or 5b, and does not substantially etch or contaminate the metal of the contact pad 4a or 4b so as to increase the recession of the pad metal after a subsequent cleaning operation. Excessive pad recesses may form recesses that are too deep, thereby preventing pad-pad bonding (or reducing the strength of the pad-pad bond) under suitable annealing conditions (e.g. annealing temperature and time). The cleaning agent may be applied by a fan spray of a liquid cleaning agent or other known methods. For example, the cleaned bonding surfaces 8a, 8b may be ashed (e.g., with oxygen plasma) and cleaned with deionized water (DIW). In some embodiments, the cleaned elements 2, 3 may be activated before direct bonding. Another die may be bonded over the back surface 15 of the cleaned and pre-treated element 3 as needed. After performing various required further processing steps, the bonded structure 1 may be further singulated by known methods. Further processing steps may include thinning the back surface 15 of the bonded element 3 or activating the back surface 15 of the die of the bonded element 3, and direct bonding an additional die to the back surface 15 or coating the back surface 15 of the bonded element 3 with, for example, a dielectric layer.

[0024] As shown in Figures 2A and 2B, in some high temperature and / or high current density applications and / or for small interconnects, electromigration may create voids 22 in the conventional interconnect 26. For example, the voids 22 may form at the interface between conductive layers, thereby reducing the reliability of the contacts and / or bonded structures. Figures 2A and 2B show a conventional interconnect 26 including such voids 22 at the interface between a lower conductive layer 62, which may include lateral traces (not shown), and an upper conductive layer 100, which may include dual damascene contact pads and vias. The lower conductive layer 62 and the upper conductive layer 100 may be disposed within a non-conductive layer 56, which may be made of a dielectric, such as an inorganic dielectric, such as silicon dioxide. The pinching between the conductive layers 62, 100 at the via and stack interfaces contributes to electromigration creating the voids 22. FIG. 2A shows electromigration failure in a conventional interconnect 26, which may be made of copper, and FIG. 2B is a schematic diagram of the conventional interconnect 26 modified by a direct hybrid bonding process. In FIG. 2B, the conventional interconnect 26 is shown with two elements 42, 44 directly bonded at a bonding surface 106. The first element 42 has a lower conductive layer 62 disposed within a non-conductive layer 56. A conventional top barrier layer 28 is disposed on the lower conductive layer 62. The non-conductive barrier layer 28 is further described below. The second element 44 - bonded to the second element 42 at a bonding interface 106 - has a lower conductive layer 124 of the second element 44 and a contact structure 130 of the second element 44, which is similar to the upper conductive layer 100 of the first element 42.

[0025] Such problems caused by voids 22 are not limited to copper metallization. Thus, various embodiments may reduce, inhibit, or eliminate electromigration damage in contact structures of semiconductor devices of bonded structures in this case. To mitigate or eliminate electromigration damage in bonded structures formed by direct hybrid bonding processes, for example, redundant barriers and structures may be formed that may provide, for example, alternative (redundant or extra) current paths. As discussed above, such redundant barriers and structures become more important in high temperature, high current density applications as metal interconnect dimensions become smaller.

[0026] FIG. 3 is a schematic cross-sectional side view of various embodiments of a semiconductor device 52. The semiconductor device 52 may include a semiconductor portion 54. The semiconductor portion 54 may be comprised of a semiconductor material, such as silicon or any other suitable semiconductor material. The semiconductor portion 54 may include one or many devices, such as active devices (e.g., transistors), passive devices (e.g., resistors), and the like. A non-conductive layer 56 (e.g., a non-conductive bonding layer) may be provided on the semiconductor portion 54 and may have an upper non-conductive surface 114 that forms part of the bonding surface 106 of the semiconductor device 52. The non-conductive layer 56 may be comprised of a dielectric material in some embodiments. For example, the non-conductive layer 56 may be comprised of an inorganic dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonitride, and the like, and the non-conductive layer may include a high concentration of nitrogen or fluorine at the upper non-conductive surface 114, as described above. In some embodiments, non-conductive layer 56 includes multiple dielectric layers disposed over semiconductor portion 54. In other embodiments, non-conductive layer 56 consists of a single dielectric layer. Upper non-conductive surface 114 may be prepared for direct bonding to second semiconductor element 108 (shown in FIG. 8K), as described above.

[0027] The metallization structure of FIG. 3 includes an electrically connected upper contact structure (e.g., upper conductive layer 100) and a lower conductive feature (e.g., lower conductive layer 62). The lower conductive layer 62 may have a top surface 64 (having a length 66), a bottom surface 68, and a side surface 70. The bottom surface 68 and the side surface 70 of the lower conductive layer 62 may be lined with a lower barrier 78, described below. The upper conductive layer 100 of the illustrated semiconductor device 52 embodiment may have a contact structure that may be at least partially embedded within the non-conductive layer 56, which may have an upper contact surface 116 that forms a second portion of the bonding surface 106 of the semiconductor device 52. In some embodiments, the upper contact surface 116 may be recessed below the upper non-conductive surface 114 prior to direct bonding, as described above. The contact structure may be formed of a first material. As shown, the contact structure may include an upper conductive layer 100 made of copper. In the illustrated embodiment, the upper conductive layer 100 includes a dual damascene structure including a structure in which the portion of the upper conductive layer 100 located relatively closer to the upper contact surface 116 is laterally wider than the portion of the upper conductive layer 100 located relatively closer to the lower conductive layer 112. In other embodiments, the upper conductive layer 100 may include a single damascene structure.

[0028] 3, the semiconductor device 52 may have a lower conductive feature (e.g., lower conductive layer 62) underlying and electrically connected to the contact structure (e.g., upper conductive layer 100). The lower conductive layer 62 may be made of copper in various embodiments. In the illustrated embodiment, the lower conductive layer 62 has lateral traces that may act as a redistribution layer (RDL) or back-end-of-line (BEOL) layer embedded within the non-conductive layer 56. The RDL may communicate laterally with other circuits and / or vias.

[0029] The semiconductor device 52 of FIG. 3 may include a barrier layer 74 (also referred to as a "first barrier layer") disposed between the upper conductive layer 100 and the lower conductive layer 62. The barrier layer 74 may be made of a second material that is different from the first material of the upper conductive layer 100 and different from the materials of the second and third barrier layers 86, 96 described below (the third barrier layer 96 is shown in FIG. 9D). The second material of the first barrier layer 74 may have a thermal resistivity lower than that of conventional barrier materials, such as TaN, WN, etc. (see the description of the materials of the second and third layers 86, 96 below). In particular, the electrical resistivity of the second material of the first barrier layer 74 may be 80×10 at 20° C. and with a melting point above 1200° C. -8 mΩ (e.g., 60×10 -8 In some embodiments, the electrical resistivity of the second material is less than 4.5×10 at 20° C. -8 mΩ to 60 x 10 at 20°C -10 Range up to mΩ or 4.5 x 10 at 20°C -8 mΩ to 30 x 10 at 20°C -8 The melting point of the second material may be in the range of 1200°C to 3600°C in some embodiments.

[0030] In various embodiments, the second material of the first barrier layer 74 may be at least one of copper, alpha-tantalum, hexagonal tantalum nitride, cobalt, tungsten, vanadium, molybdenum, and nickel. In some embodiments, the second material may be an alloy. For example, the alloy may be at least one of cobalt-tungsten phosphate (CWP), cobalt phosphate (CoP), low phosphorus nickel phosphate (NiP) with less than 3.5% phosphorus, low phosphorus and low tungsten (NiWP) with less than 3.5% phosphorus and tungsten, nickel-tungsten (NiW), titanium-tungsten (TiW), nickel-vanadium (NiV), stoichiometric borides, and non-stoichiometric borides. The stoichiometric borides may include nickel borides (NiB, Ni2B, Ni3B) and cobalt borides. In some embodiments, the second material comprises an alloy and metal stack, such as TaN / Ta, TiN / Ti, TiW / Ti, TiW / Mo or TiW / Co. In such a case, the alloy can act as a seed layer for coating the metal element. The thickness of the alloy seed can vary from 2 nm to 20 nm, and the thickness of the metal element can range from 25 nm to 1000 nm. In some applications, the alloy seed can serve to reduce the resistivity of the coated metal element, for example the resistivity of thin film Mo is about 13-18×10 at 20° C. -8 mΩ. A very thin 3 nm coating of the TiW seed layer can reduce the resistivity of the Mo overcoat by over 40%. Additional information about the second material is provided in Table 1 below.

[0031] 3, a second barrier layer 86 may be provided to line at least a portion of a cavity 98 (shown in FIG. 8F) containing an upper conductive layer 100, the second barrier layer 86 being disposed between the non-conductive layer 56 and the upper conductive layer 100. Such second barrier layer 86 may line the sidewalls of the cavity 98 (shown in FIG. 8F) and help to prevent bulk diffusion of the upper conductive layer 100 (e.g., copper) into the non-conductive layer 56 (e.g., silicon oxide-based material). This diffusion prevention may be beneficial as such diffusion may risk shorting to other conductive features. The illustrated second barrier layer 86 also extends along the bottom of the upper conductive layer 100 (i.e., the bottom of the lower via portion of the upper conductive layer 100 closest to the lower conductive layer 92), although one skilled in the art will recognize that bottomless barrier liners are also known in the art and are shown, for example, in FIG. 13D. In the illustrated embodiment, the second barrier layer 86 is made of a third material that is different from the first material of the upper conductive layer 100 and the second material of the first barrier layer 74. For example, in the illustrated embodiment, the third material is made of a metal nitride, such as tantalum nitride. In the illustrated embodiment, the thickness 76 of the first barrier layer 74 may be greater than the thickness 88 of the second barrier layer 86.

[0032] In FIG. 3, the first barrier layer 74 may be disposed along a length 66 of the top surface 64 of the lower conductive layer 62, which length 66 is greater than the width 104 of the upper conductive layer 100. The lower conductive layer 62 may be encapsulated along its top surface 64 by the first barrier layer 74 and along the bottom surface 68 and sides 70 of the lower conductive layer 62 by one or more additional barrier layers. In the illustrated embodiment, the one or more additional barrier layers include a lower barrier layer 78 lining a cavity containing the lower conductive layer 62. The lower barrier layer 78 may comprise a material different from the first and second materials, but may be different from or similar to the third material. For example, in the illustrated embodiment, the lower barrier layer 78 may be comprised of the same material as the second barrier layer 86, such as a metal nitride, such as tantalum nitride or titanium nitride. In other embodiments, as described herein, one or more additional barrier layers located along the lower surface 68 and side surfaces 70 of the lower conductive layer 62 may be made of a material similar to the second material of the first barrier layer 74.

[0033] 4A and 4B show a conventional interconnect 26 in which copper is placed in a cavity in a non-conductive layer 56, the cavity being lined with a conventional barrier layer 24, such as a metal nitride, e.g., tantalum nitride. The copper may form each of a lower conductive layer 62 and an upper conductive layer 100, which may be at least partially lined with a conventional barrier layer 24, which may be made of the same material as the conventional barrier layer 24 adjacent to the lower conductive layer 62, such as a metal nitride, e.g., tantalum nitride. FIG. 4A is a schematic diagram of such a conventional interconnect 26, and FIG. 4B is a schematic diagram of the direction of electron flow 20 in such a conventional interconnect 26, including voids. As shown in Figures 4A and 4B, electromigration (e.g., current crowding) may occur when current flows from a more conductive material (e.g., copper, which may be the material of construction of the lower conductive layer 62 and / or the upper conductive layer 100) to a less conductive material (e.g., conventional barrier layer 24) and / or when current flows from a wider, more conductive path to a narrower, more resistive path. The induced electromigration stress may create voids 22, which may reduce the electrical reliability or performance of the interconnect. In some embodiments, the top surface of the lower conductive layer 62 may be coated with an interlayer dielectric (not shown), such as SiN, prior to coating the non-conductive layer 56. The interlayer dielectric coating enhances adhesion of the non-conductive layer 56 to the top surface of the lower conductive layer 62.

[0034] In contrast, as shown in Figures 4C and 4D, in various embodiments of a semiconductor device 52, the second material of the barrier layer 74 may be advantageously selected to have a low thermal resistivity and a high melting point, thereby reducing the risk of electromigration and voids 22. Figures 4C and 4D show a semiconductor device 52 having a non-conductive layer 56, in which the lower conductive layer 62 and the upper conductive layer 100 are at least partially embedded. A conventional barrier layer 24 may be provided between the upper conductive layer 100 and the non-conductive layer 56, with the conventional barrier layer 24 being at least partially embedded in the non-conductive layer 56. Another conventional barrier layer 24 may then line either or both of the lower surface 68 and the side surface 70 of the lower conductive layer 62.

[0035] 4C and 4D, even when electromigration stress is introduced, the first barrier layer 74 can act as a redundant electrical path between the upper conductive layer 100 and the lower conductive layer 62, thereby avoiding open circuits and thereby enhancing electrical connection and electrical stability. As shown in FIG. 4D, even if a void 22 occurs in the lower conductive layer 62 near the upper conductive layer 100, the electron flow direction 20 is not impeded because the electrons can still flow along the conductive first barrier layer 74.

[0036] 5A-5C provide an example of a direct bonded structure 50 in which the redundant current path is in the form of a metallic first barrier layer 74, 126. FIGS. 5A-5C illustrate a bonded structure 50 in which a first semiconductor element 52 may be bonded to a second semiconductor element 118 along a bonding surface 106. Specifically, FIGS. 5A-5C illustrate a bonded structure 50 in which a non-conductive layer 56 of the first semiconductor element 52 is directly bonded to an opposing second non-conductive layer 122 of the second semiconductor element 118, and a conductive layer 100 of the first semiconductor element 52 is directly bonded to a contact structure 130 of the second semiconductor element 118. The non-conductive layers 56, 122 may be directly bonded by bonding an upper non-conductive surface 114 of the first semiconductor element 52 to an upper non-conductive surface 128 of the second semiconductor element 118. The upper conductive layer 100 of the first semiconductor element 52 may then be bonded to the contact structure 130 of the second semiconductor element 118 by bonding the upper contact surface 116 of the first semiconductor element 52 to its corresponding surface of the second semiconductor element 118.

[0037] 5A-5C, the first and second semiconductor elements 52, 118 are shown directly bonded along the bonding surface 106. The first semiconductor element 52 and the second semiconductor element 118 may have substantially the same components. The first semiconductor element may have a lower conductive layer 62 encapsulated by a lower barrier layer 78 and a first barrier layer 74, and an upper conductive layer 100 at least partially lined by a second barrier layer 86, and the second semiconductor element 118 may have a second lower conductive layer 124 encapsulated by a lower barrier layer 132 and a first barrier layer 126 of the second semiconductor element 118, and a contact structure 130 of the second semiconductor element 118 at least partially lined by a second barrier layer, which may be substantially the same as the second barrier layer 86 of the first semiconductor element 52. As shown, the upper conductive layer 100 of the first semiconductor device 52 may include a contact structure, such as a single and / or dual damascene structure, and the first barrier layer 74 (of a second material) may provide a redundant current path. In each of Figures 5A-5C, the first barrier layer 74 of the first semiconductor device 52 provides a bottom redundant current path, and the first barrier layer 126 of the second semiconductor device 118 provides a top redundant current path. The first barrier layer 126 of the second semiconductor device 118 may be of a second material as described herein.

[0038] Figure 5A is a schematic diagram of two direct bonded semiconductor elements 52, 118 including dual damascene features, Figure 5B is a schematic diagram of two direct bonded semiconductor elements 52, 118 including single and dual damascene features, and Figure 5C is a schematic diagram of two direct bonded semiconductor elements 52, 118 including a single feature. Table 1: Exemplary materials that can be used as part of the second material ( * (indicated by) TIFF2025501484000002.tif55158

[0039] Table 1 provides examples of second materials that can be used, for example, for the first barrier layer 74, 126. Such materials are indicated in Table 1 with an asterisk ( * ) in Table 1. In Table 1, generally speaking, it is desirable for the material to have low resistivity (to reduce electrical losses), low thermal expansion, and high melting point. Exemplary materials include Co, W, V, Ni, alloys such as CWP, CoP, NiP, NiW, or NiV, or laminates such as TiW / Co, TiW / Mo, TaN / Ta, TaN / Ti, TiN / Ta, etc. The use of laminates can reduce electrical resistivity, for example, by reducing defect density. Exemplary criteria for electromigration resistance shown in Table 1 are high melting point and low resistivity (i.e., high conductivity). Desirably, conductivity is further improved by increasing the thickness 76 of the first barrier layer 74 compared to the conventional second barrier layer 86. For example, the thickness 76 of the first barrier layer 74 may be selected to be about 1.5 to about 4 times the thickness 88 of the second barrier layer 86, and more particularly, about 2 to about 8 times the thickness 88 of the second barrier layer 86 (e.g., 5 to 50 nm versus 100 to 150 nm). In some embodiments, the thickness 76 of the first barrier layer 74 may be in the range of 10 nm to 150 nm, or in the range of 100 nm to 150 nm. The thickness of the second material (100 to 150 nm) may be at least 2 to 3 times the thickness 88 of the sidewall barrier (Ta or Ti) of the second barrier layer 86 (5 to 50 nm).

[0040] In FIG. 6, the conductive layer 62 has a low resistivity (e.g., 10×10 -8 The first barrier layer 74 may be made of one or more second materials, as described above, that also have a low resistivity (e.g., less than 100×10 -86 has a resistivity of less than 1000 mΩ and a high melting point (e.g., greater than 1200° C.). The use of first barrier layer 74 in FIG. 6 can provide electrical redundancy for bonded structure 50 of FIGS. 5A-5C and can help prevent or mitigate the effects of electromigration of metal atoms from within conductive layer 62 into surrounding non-conductive layer 56 in which conductive layer 62 can be at least partially embedded. It should also be understood that FIG. 6 does not limit first barrier layer 74 to being a horizontal layer, and in some embodiments, first barrier layer 74 can be a vertical layer.

[0041] 7A-7H illustrate a process flow for fabricating a conventional interconnect 26, including conventional bonding layers and contact structures. In FIG. 7A, a non-conductive layer 56 may be provided on the semiconductor portion 54, and an RDL or BEOL trace cavity 60 may be formed in the non-conductive layer 56. In FIG. 7B, a conventional barrier layer 24 (e.g., a metal nitride, e.g., TaN) and a lower conductive layer 62 (e.g., copper) may be provided in the cavity 60. In FIG. 7C, excess metal in the lower conductive layer 62 may be removed, and the non-conductive layer 56 may be planarized by CMP. In FIG. 7D, a conventional non-conductive top barrier layer 28 (e.g., SiN), which may be, for example, 30-100 nm thick, may be deposited on the lower conductive layer 62. Although not shown, a conventional non-conductive top barrier layer 28 may be blanket deposited over the entire surface of the non-conductive layer 56, such that such top barrier layer extends beyond the length of the lower conductive layer 62. FIG. 7D also illustrates that a thick dielectric layer 30 may be coated over the conventional non-conductive barrier layer 28. The thick dielectric layer 30 may also be coated over the non-conductive layer 56. Throughout this application, where applicable, the thick dielectric layer 30 and the non-conductive layer 56 may be described as either separate parts or as a consolidated non-conductive layer 56. In other words, where applicable, "non-conductive layer 56" may refer to either the very portion of the non-conductive layer 56 that is flush with or below the lower conductive layer 62 (as shown in FIG. 7C) or the larger non-conductive layer 56 that results from the coating of the thick dielectric layer 30 in FIG. 7D. In further alternative terms, it will be understood that the non-conductive layer 56 is described herein as having a single dielectric layer in certain embodiments, while in other embodiments, it includes multiple dielectric layers. In some embodiments, the thick dielectric layer 30 may be planarized. In FIG. 7E, an opening 32 may be formed in the thick dielectric layer 30 and the conventional non-conductive top barrier layer 28 to expose a lower conductive layer 62, such as an RDL or BEOL layer. In FIG. 7F, another conventional barrier layer 24 may be disposed within the opening 32 over the lower conductive layer 62.In Figure 7G, an upper conductive layer 100 (e.g., copper) may be provided over the conventional barrier layer 24. The upper conductive layer 100 may be in electrical contact with the lower conductive layer 62 and may fill the opening 32 in the thick dielectric layer 30. In Figure 7H, the upper conductive layer 100 and the thick dielectric layer 30 may be planarized to form a conventional interconnect 26 and a bonding layer with a smooth and flat bonding surface 106. The bonding surface 106 of Figure 7H may be cleaned, pretreated, activated, and bonded to form a structure similar to that of Figure 4A without electromigration defects.

[0042] 8A-8K illustrate a process flow for fabricating a semiconductor device 52 with constituent conductive layers 62, 100 and barrier layers 74, 78, 86, and how to fabricate a bonded structure 50 having two semiconductor devices 52, 118, according to various embodiments. In FIG. 8A, a non-conductive layer 56 may be provided on the semiconductor portion 54, and an RDL or BEOL trace cavity 60 may be formed in the non-conductive layer 56. This step may be completed in a manner similar to that shown in FIG. 7A. In FIG. 8B, a lower barrier layer 78 and a lower conductive layer 62 (e.g., copper) may be provided in the cavity 60. In the illustrated embodiment, the lower barrier layer 78 may be comprised of a conventional barrier layer 24 material, such as a metal nitride, e.g., TaN or TiN. In other embodiments, the lower barrier layer 78 may be comprised of the second material of the first barrier layer 74, as described herein. In FIG. 8C, excess metal and non-conductive layer 56 may be planarized, initially stopping on lower barrier layer 78, which is then removed from above non-conductive layer 56. In some embodiments, as shown in FIG. 8C, a defined portion of the top surface of lower conductive layer 62 may be selectively removed, for example, by a wet etching process. The defined portion may have a thickness in the range of, for example, 27 nm to 300 nm. Lower conductive layer 62 may have a top surface 64 (having a length 66), a bottom surface 68, and side surfaces 70a, 70b. The bottom surface 68 and side surfaces 70a, 70b of lower conductive layer 62 may be lined with lower barrier layer 78. In FIG. 8C1, a first barrier layer 74 of a second material may be deposited on non-conductive layer 56 and remaining lower conductive layer 62. The first barrier layer 74 may be selectively removed from over the conductive layer 56 by a chemical mechanical polishing (CMP) process to form the structure of Figure 8D. In another embodiment, a first barrier layer 74 of a second material may be selectively deposited on the lower conductive layer 62, as in Figure 8D. The first barrier layer 74 may have a thickness 76 that is greater than the thickness of the lower barrier layer 78 or the thickness of the second barrier layer.Using various techniques, such as damascene processing (recessing the lower conductive layer 62, depositing a second material, and polishing), blanket deposition, masking and etching, and selective deposition, the first barrier layer 74 can be patterned so as to overlie the lower conductive layer 62. In FIG. 8E, another non-conductive layer 56a (also referred to as a single item 56 together with the non-conductive layer disposed on the semiconductor portion 54) can be deposited on the lower conductive layer 62. In FIG. 8E, the lower conductive layer 62 can be encapsulated by a combination of a lower barrier layer 78 lining its bottom and sides 70a, 70b (shown in FIG. 8C) and a first barrier layer 74 lining the length 66 of its top surface 64 (shown in FIG. 8C). In some embodiments, a thin intermediate non-conductive layer (not shown), such as SiN, can be coated over the substrate prior to coating the non-conductive layer 56a. A thin intermediate non-conductive layer can help bond non-conductive layer 56 a to lower conductive layer 62 .

[0043] In some embodiments, the non-conductive layer 56 may be planarized. An upper non-conductive surface 114 of the non-conductive layer 56, which will form a portion of the bonding surface 106 (shown in FIG. 8K), may be an inorganic semiconductor or dielectric, as described above. In FIG. 8F, a cavity 98 may be formed in the non-conductive layer 56, 56a, extending to the first barrier layer 74. In FIG. 8G, a second barrier layer 86 may be provided over the first barrier layer 74 and within the cavity 98. In the illustrated embodiment, the second barrier layer 86 may be any of the second materials described herein, such as a copper layer. In some embodiments, the first and second barrier layers 74, 86 may be made of the same material (e.g., a cobalt alloy, a nickel alloy, etc.). In other embodiments, the first and second barrier layers 74, 86 may be made of dissimilar materials (e.g., the first barrier layer 74 may be made of a cobalt alloy and the second barrier layer 86 may be made of a nickel alloy, or vice versa). In yet other embodiments, such as the structure shown in Figures 4C and 4D, the first barrier layer 74 may be made of a cobalt alloy and the second barrier layer 86 may be made of a nickel alloy, or vice versa. The metal layer 74 may be made of any of the second materials (e.g., cobalt alloy, nickel alloy, etc.), and the second barrier layer 86 may be made of the material of the conventional barrier layer 24, for example, a third material, for example, a metal nitride, for example, tantalum nitride or titanium nitride. In FIG. 8H, an upper conductive layer 100 (e.g., copper) may be deposited on the second barrier layer 86. In FIG. 8I, the upper conductive layer 100 and the non-conductive layer 56 may be planarized to form the semiconductor device 52. FIG. 8I1 shows an alternative embodiment. As shown in FIG. 8I, the second The barrier layer 86 may contact the top of the first barrier layer 74, but as shown in FIG. 8I1, the second barrier layer 86 may extend into or through the first barrier layer 74 all the way to the lower conductive layer 62. As one skilled in the art will note, in any of these variations, the first barrier layer 74 still acts as a redundant path through which current can flow. In FIG. 8I1, the first barrier layer 74 may be provided around some portions of the second barrier layer 86 and / or the upper conductive layer 100.

[0044] 8J, the bonding surface 106 of the semiconductor element 54 may be formed. For example, the bonding surface 106 may be activated and / or terminated as described above. The bonding surface 106 of the semiconductor element 52 may include at least a non-conductive portion (e.g., an upper non-conductive surface 114) and a conductive portion (e.g., an upper contact surface 116). The upper non-conductive surface 114 may be the activated surface of the non-conductive layer 56, and the upper contact surface 116 may be the exposed surface of the upper conductive layer 100.

[0045] In FIG. 8K, the bonded structure 50 may be formed by directly bonding the semiconductor element 52 to the second semiconductor element 118 without an intervening adhesive. As shown in FIG. 8K, in some embodiments, the lower conductive layer 62, 124 of each semiconductor element 52, 118 may be encapsulated (e.g., completely surrounded) by one or more barrier layers (e.g., including the first barrier layer 74, 126 and the lower barrier layer 78, 132). As described herein, the lower barrier layer 78, 132 may be made of a conventional barrier layer 24 material, such as Ta or TaN. In other embodiments, the lower barrier layer 78, 132 may be made of the same material as the first barrier layer 74, 126, such as one of the second materials described herein. Each semiconductor element 52, 118 further includes a semiconductor portion 54, 120, which may be made of a semiconductor material, such as silicon. The first semiconductor element 52 and the second semiconductor element 118 are bonded at the bonding surface 106. The upper non-conductive surface 114 of the first semiconductor element 52 may be direct bonded to the second upper non-conductive surface 128 of the second semiconductor element 118 as described herein. The upper non-conductive surface 114 may be an active surface of the non-conductive layer 56 of the first semiconductor element 52, and the second upper non-conductive surface 128 may be an active surface of the second non-conductive layer 122 of the second semiconductor element 118. In addition, the conductive portions of the semiconductor elements 52, 118—the upper conductive layer 100 of the first semiconductor element 52 and the contact structure 130 of the second semiconductor element 118—may be direct bonded to one another. The contact structures (e.g., the upper conductive layer 100 of the first semiconductor device 52 and the contact structures 130 of the second semiconductor device 118) may be at least partially lined with a barrier layer (e.g., the second barrier layer 86).

[0046] 9A-9E illustrate a process flow for fabricating a semiconductor device 52 with constituent conductive layers 62, 92, 100 and barrier layers 74, 78, 86, in accordance with various embodiments. The embodiment of semiconductor device 52 illustrated in FIG. 9E is similar to the semiconductor device illustrated in FIG. 8I, except that the semiconductor device 52 illustrated in FIG. 9E includes an additional conductive layer (e.g., middle conductive layer 92) and an additional barrier layer (e.g., third barrier layer 96) between the upper conductive layer 62 and the lower conductive layer 100.

[0047] As shown in FIG. 9A, the semiconductor device 52 may have a non-conductive layer 56 disposed on the semiconductor portion 54. A lower conductive layer 62 may be embedded within the non-conductive layer 56, and the lower conductive layer may be encapsulated by at least one barrier layer (e.g., a first barrier layer 74 and a lower barrier layer 78). A second barrier layer 86 may be disposed on the first barrier layer 74, a step similar to that shown in FIG. 8G. In FIG. 9A, an intermediate conductive layer 92 (e.g., cobalt, nickel, or tungsten) is disposed above the first barrier layer 74. In the illustrated embodiment, the lower barrier layer 78, the first barrier layer 74, and the second barrier layer 86 may be comprised of any of the second materials disclosed herein. The formulations of the lower barrier layer 78, the first barrier layer 74, and the second barrier layer 86 may be the same, nearly the same, or different from one another.

[0048] Referring to FIG. 9B, an opening or controlled recess 93 may be formed in the intermediate conductive layer 92 by selectively removing a controlled portion of the intermediate conductive layer 92. The controlled recess 93 may be formed, for example, by a wet process and may be recessed to a depth of, for example, 50 nm to 500 nm. In FIG. 9C, a third barrier layer 96 having a top encapsulation layer may be formed on the remaining intermediate conductive layer 92. The third barrier layer 96 may be comprised of any of the second materials described herein. The third barrier layer 96 may be formed of a second material that is the same as or different from the second material used for the lower barrier layer 78, the first barrier layer 74, and / or the second barrier layer 86. Referring to FIG. 9D, an upper conductive layer 100 (e.g., copper, copper-zinc alloy, copper-cadmium alloy, copper-tin alloy, copper-cobalt alloy, <111> copper) may be deposited on the second barrier layer 86 and the third barrier layer 96 by, for example, physical vapor deposition, electroless plating, or electrolytic plating.

[0049] FIG. 9E shows a semiconductor device 52 with conductive layers 62, 92, 100 and barrier layers 74, 78, 86, 96 as components. In FIG. 9E, a planarization process may be used to remove excess conductive material from the upper conductive layer 100, which may also remove the unwanted second barrier layer 86 located on the non-conductive layer 56. The remaining upper conductive layer 100 on the intermediate conductive layer 92 may serve as a contact structure forming a portion of a bonding surface 106 on the third barrier layer 96. The contact structure (e.g., upper conductive layer 100) may be made of copper, copper alloy, or other alloy material that can be easily planarized or polished and can be used in direct hybrid bonding. Beneficially, the contact structure (e.g., upper conductive layer 100) of FIG. 9E may serve as a bonding surface 106 that bonds to a contact structure 130 of a second semiconductor device 118 (shown in FIGS. 5A-5C). The upper conductive layer 100 can act as a bonding material. Moreover, the thickness 102 of the upper conductive layer 100 can be less than one or both of the thickness 94 of the middle conductive layer 92 and the thickness 67 of the lower conductive layer 62. The multiple barrier layers 74, 78, 86, 96 can each be made of one of the second materials described herein, such as a cobalt alloy, thus providing multiple redundant paths to provide alternative paths around any voids 22 (shown in FIGS. 2A and 2B) formed, for example, from electromigration, while the contact structure (e.g., the upper conductive layer 100) at the bonding surface 106 provides excellent direct bonding properties. As will be appreciated by those skilled in the art, the contact structure (e.g., the upper conductive layer 100) can be recessed such that the upper contact surface 116 is located below the upper non-conductive surface 114 of the non-conductive layer 56. This allows the contact structure to expand after initial bonding of the non-conductive material to make metal-metal contact with another contact structure on a different device, for example, forming a covalent bond at room temperature and without the application of pressure as disclosed herein.In other words, the contact structure (e.g., upper conductive layer 100) may be recessed below upper non-conductive surface 114 as a way of preparing bonding surface 106 to enable a hybrid direct bonding process as described in detail above.

[0050] The embodiment shown in FIG. 9E provides advantages over conventional structures (e.g., the structure shown in FIG. 4A). The second material (e.g., Co alloy) serves as a redundant conductive path in case the material (e.g., copper) in the conductive layer becomes defective. In addition, when copper is encapsulated in the second material (e.g., Co alloy), it exhibits high stress migration and electromigration resistance. Furthermore, the second material (e.g., Co alloy) of the barrier layer can diffuse into the copper of the conductive layer 62, 92, 100, thereby further enhancing the reliability of the interconnection of the semiconductor device 52.

[0051] FIG. 10 illustrates another embodiment of the semiconductor layer 52 according to various embodiments. As with the other embodiments, the semiconductor element 52 illustrated in FIG. 10 may include a semiconductor portion 54 and a non-conductive layer 56 disposed on the semiconductor portion 54. The semiconductor element 52 may include a bonding surface 106 including an upper non-conductive surface 114 of the non-conductive layer 56 and an upper contact surface 116 of a contact structure 99. The contact structure 99 (similar to the upper conductive layer 100 illustrated in FIG. 9E) may be made of a first material as described herein, such as copper. In FIG. 10, the semiconductor element 52 may include a conductive barrier material 91 underlying and electrically connected to the contact structure 99. The contact structure 99 may extend over the entire upper length of the conductive barrier material 61. The conductive barrier material 91 may be comprised of any of the second materials described herein, including alloys (e.g., CWP, CoP, NiP, NiW, or NiV) and laminates (e.g., TiW / Co, TiW / Mo, TaN / Ta, TaN / Ti, TiN / Ta, etc.), and unlike the previous embodiment, the bulk of the conductive features (e.g., including the lower conductive layer 62, optional intermediate conductive feature 92, and upper conductive layer 100, all of which are shown in FIG. 9E) is formed of the second material, except for the contact structures 99. For example, the conductive barrier material 61 has a thermal conductivity of 50×10 at 20° C. -8 It should have an electrical resistivity of less than mΩ and a melting point of greater than 1200° C. In some embodiments, the electrical resistivity of the conductive barrier material 61 is 4.5×10 at 20° C. -8 mΩ to 50 x 10 at 20°C -8The conductive barrier material 61 may range from 0.1 to 1.0 mΩ. In some embodiments, the melting point of the conductive barrier material 61 may be greater than 1200° C. and may range from 1200° C. to 3600° C. In the illustrated embodiment, the contact structure 99 is made of copper. The conductive barrier material 61 may be made of at least one of cobalt, tungsten, vanadium, molybdenum, and nickel. In various embodiments, the material of the conductive barrier material 61 may diffuse into the contact structure 99. For example, the contact structure 99 may be made of less than 20% or less than 15% conductive barrier material 61 during manufacture, but then may include more than 50% conductive barrier material 61 when the product is in use. As an example, the copper contact structure 99 may include less than 20% or less than 15% cobalt when manufactured, but then may include more than 50% cobalt when the product is in use. One advantage of the embodiment shown in Figure 10 over conventional structures (e.g., the structure shown in Figure 4A) is that Co and Ni alloys exhibit superior heat resistance compared to pure Cu, making such materials suitable for high temperature applications, e.g., in automobiles, switches and relays.

[0052] In FIG. 10, the thickness 101 of the contact structure 99 may be less than the thickness 63 of the conductive barrier material 61. For example, the thickness 63 of the conductive barrier material 61 may be at least twice the thickness 101 of the contact structure 99. Thus, the bulk of the upper and / or lower conductive layer 62, 100 (shown in FIG. 3) is made of a second material with good thermal resistance and reduced susceptibility to electromigration, whereas the contact structure 99 has a high copper content for superior properties for direct metal bonding, especially hybrid direct bonding at comparable low temperatures. As will be appreciated by those skilled in the art, the upper contact surface 116 of the contact structure 99 may be recessed below the upper non-conductive surface 114 of the non-conductive layer 56, so that the contact structure can expand after the non-conductive material is initially bonded to make metal-metal contact with another contact structure on a different device, for example, forming a covalent bond at room temperature without the application of pressure as disclosed herein. In other words, the contact structures 99 may be recessed below the upper non-conductive surface 114 as a way of preparing the bonding surface 106 to enable the hybrid direct bonding process described in detail above.

[0053] FIG. 11 illustrates a bonded structure 50 in which first and second semiconductor elements 52, 118 are directly hybrid bonded to one another without adhesive. The first and second semiconductor elements 52, 118 of FIG. 11 may be substantially the same as or identical to the semiconductor element 52 shown in FIG. 9E. Both semiconductor elements 52, 118 may have a non-conductive layer 56, 122 on a semiconductor portion 54, 120. Each non-conductive layer 56, 122 may have an upper non-conductive surface 114, 128 that may be directly bonded at the bonding surface 106. Additionally, each semiconductor element 52, 118 may have a lower conductive layer 62, 124 with a third barrier layer 74, 126 lining at least a portion of the lower conductive layer 62, 124 connected to the intermediate conductive layer 92. The lower conductive layer 62, 124 may also be at least partially lined with at least one barrier layer (e.g., lower barrier layer 78, 132). In addition, the middle conductive layer 92 may have a third barrier layer 96 lining at least a portion of the middle conductive layer 92 connected to the upper conductive layer 100. The middle conductive layer 92 may be at least partially lined on all other sides with a second barrier layer 86. Finally, the upper conductive layer 100 of the first semiconductor device 52 may be direct bonded to a contact structure 130 of the second semiconductor device 118.

[0054] FIG. 12 shows a bonded structure 50 in which a first and a second semiconductor element 52, 118 are directly hybrid bonded to each other without adhesive. The first and second semiconductor elements 52, 118 in FIG. 12 may be substantially the same as or identical to the semiconductor element 52 shown in FIG. 10. Both of the semiconductor elements 52, 118 may have a non-conductive layer 56, 122 on the semiconductor portion 54, 120. The two semiconductor elements 52, 118 may be directly bonded to each other at the bonding surface 106. As described herein, the first semiconductor element 52 has a contact structure 99 on the conductive barrier material 61, and the second semiconductor element 118 has a contact structure 99a on the conductive barrier material 61a.

[0055] 13A-13D show another process flow for fabricating a semiconductor device 52. The method of FIG. 13A-13D may be substantially similar to the method shown in FIG. 8F-8I. FIG. 13A shows a non-conductive layer 56 on a semiconductor portion 54, with a lower conductive layer 62 embedded within the non-conductive layer 56. The lower conductive layer 62 may be encapsulated by a lower barrier layer 78, except for the portion of the lower conductive layer 62 that is intended to bond to an upper conductive layer 100 (shown in FIG. 13C and FIG. 13D), which is lined with a first barrier layer 74. In FIG. 13A, an upper non-conductive surface 114 of the non-conductive layer 56 may be exposed to a surrounding dielectric, for example, a plasma 117 that improves adhesion of the second barrier layer 86 to the non-conductive layer 56 for direct hybrid bonding. In some embodiments, the sidewalls of the cavities in the non-conductive layer 56 may also be exposed to the plasma 117 to improve adhesion of the second barrier layer 86. The top surface of the first barrier layer 74 may also be exposed to the plasma 117. The plasma may comprise a nitrogen or oxygen-containing (e.g., water vapor plasma) plasma in various embodiments. In FIG. 13B, a second barrier layer 86 may be provided on the non-conductive layer 56. Although FIG. 13B shows a bottomless second barrier layer 86, those skilled in the art will appreciate that the second barrier layer 86 may alternatively cover the first barrier layer 74. In FIG. 13C, a contact structure (e.g., an upper conductive layer 100) may be provided on the first and second barrier layers 74, 86. In FIG. 13D, excess metal (e.g., copper) on the upper conductive layer 100 may be removed by a planarization process. 13D, the planarization process may remove all excess metal from upper conductive layer 100, but may stop on second barrier layer 86, thus leaving non-conductive layer 56 underlying second barrier layer 86 unexposed. The resulting bonding surface 106 of semiconductor device 52 is ready for direct bonding to another semiconductor device.

[0056] Figures 14A and 14C show an example semiconductor device 52 as described herein. Figure 14B shows a bonded structure 50 in which two semiconductor devices 52, 118 similar to the semiconductor device of Figure 14A are directly hybrid bonded to one another. Figure 14D shows a bonded structure 50 in which two semiconductor devices 52, 118 similar to the semiconductor device of Figure 14C are directly hybrid bonded to one another.

[0057] Figures 14A-14D all show semiconductor elements 52, 118, which may each have a non-conductive layer 56, 122 on a semiconductor portion 54, 120. Each semiconductor element may have a bonding surface 106 that includes a non-conductive portion (e.g., upper non-conductive surface 114, 128 of the non-conductive layer 56, 122) and a conductive portion (e.g., upper contact surface 116). The bonding structures 50 of Figures 14B and 14D may each be formed by direct hybrid bonding the semiconductor elements 52, 118 to one another at the bonding surfaces 106, as described herein.

[0058] In Fig. 14A, the upper contact surface 116 may be a surface of the upper conductive layer 100. As described further herein, the upper conductive layer 100 may be disposed on the third barrier layer 96, which may be disposed on the intermediate conductive layer 92, which may be disposed on the first barrier layer 74, which may be disposed on the lower conductive layer 62. The portion of the intermediate conductive layer 92 that is not lined with either the first or third barrier layers 74, 96 may be lined with the second barrier layer 86, as described herein. Both of the semiconductor elements 52, 118 of Fig. 14B may be substantially the same or identical to the semiconductor elements shown in Fig. 14A. Both semiconductor elements 52, 118 may have a lower conductive layer 62, 124, a first barrier layer 74, 126, an intermediate conductive layer 92, 92a, a second barrier layer 86, a third barrier layer 96, and a contact structure (e.g., an upper conductive layer 100 of the first semiconductor element 52 and a contact structure 130 of the second semiconductor element 118).

[0059] In Figure 14C, the upper contact surface 116 may be a surface of a contact structure 99. Both of the semiconductor elements 52, 118 of Figure 14D may be substantially the same as or identical to the semiconductor element shown in Figure 14C. Both of the semiconductor elements 52, 118 may include a contact structure 99, 99a (with a thickness 101) disposed on a conductive barrier material 61, 61a (with a width 63).

[0060] 15A and 15B illustrate a bonded structure 50 in which at least one semiconductor element 52 of the bonded structure 50 includes a through-substrate via (TSV) 110. Both FIGs. 15A and 15B illustrate a bonded structure 50 that may be formed by direct hybrid bonding of semiconductor elements 52, 118 to one another at a bonding surface 106 as described herein. FIG. 15A is similar to FIG. 11, except that the bonded structure 50 illustrated in FIG. 15A may include a TSV 110 and a TSV barrier 112. FIG. 15B is similar to FIG. 12, except that the bonded structure 50 illustrated in FIG. 15B may include a TSV 110.

[0061] Both of the semiconductor elements 52, 118 in Figure 15A may include the following components described in Figure 11: lower barrier layer 78, 132, lower conductive layer 62, 124, first barrier layer 74, 126, middle conductive layer 92, 92a, second barrier layer 86, third barrier layer 96, 96a, contact structures (e.g., upper conductive layer 100 of the first semiconductor element 52 and contact structure 130 of the second semiconductor element 118), non-conductive layer 56, 122, and semiconductor portion 54, 120. However, unlike Figure 11, Figure 15A shows TSV 110 and TSV barrier layer 112. In Figure 15A, TSV 110 may be comprised of a conductive material (e.g., copper) electrically connected to lower conductive layer 62 and extending through semiconductor portion 54 of semiconductor element 52. A TSV barrier layer 112 may line the TSV 110. In the illustrated embodiment, the TSV barrier layer 112 may be comprised of a second material described herein that provides high electrical conductivity and may reduce or eliminate electromigration damage. Advantageously, the use of cobalt or nickel alloy as the material of construction for the TSV barrier layer 112 acts as a redundant current path and conductive layer.

[0062] Both of the semiconductor elements 52, 118 of Figure 15B may include the following components described in Figure 12: contact structures 99, 99a, conductive barrier materials 61, 61a, non-conductive layers 56, 122, and semiconductor portions 54, 120. However, unlike Figure 12, Figure 15B shows a TSV 110. In Figure 15B, the TSV 110 may be comprised predominantly of (e.g., substantially of) the second material.

[0063] FIG. 16 illustrates another embodiment of a semiconductor device 52 that may have an inner manganese barrier layer 108. Like the other embodiments, the semiconductor device 52 of FIG. 16 has a non-conductive layer 56 on the semiconductor portion 54. Like FIG. 15A, FIG. 16 illustrates that a lower conductive layer 62 may be embedded within the non-conductive portion 56 and may be electrically connected to the semiconductor portion 54 by TSVs 110 and a TSV barrier layer 112. In FIG. 16, a barrier layer 74 formed of a second material (e.g., cobalt, a cobalt alloy, a nickel alloy) may line at least a portion of the lower barrier layer 62 and may extend vertically to an upper surface of the non-conductive layer 56. The inner manganese barrier layer 108 may be disposed adjacent to the barrier layer 74 made of the second material. The inner manganese barrier layer 108 may line at least a portion of the cavity containing the contact structure, with the barrier layer 74 disposed external to the manganese barrier layer 108. In this case, several layers are disposed within the manganese barrier layer 108, which may be the intermediate conductive layer 92, the inner manganese barrier layer 108 material, and the upper conductive layer 100.

[0064] At high bonding temperatures, the manganese barrier layer 108 may be alloyed with the contact structure (e.g., the upper conductive layer 100 and / or the intermediate conductive layer 92) or the barrier layer 74, or both, to improve the electromigration resistance of the semiconductor device 52 after the high temperature bonding operation. Apart from Mn, other metals or metal alloys may improve the electromigration resistance of the contact structure, (e.g., the upper conductive layer 100), for example, indium, gallium, tin and their respective alloys may be deposited as the inner barrier layer 108 between the barrier layer 74 and the contact structure (e.g., the upper conductive layer 100 and / or the intermediate conductive layer 92). In some embodiments, the thickness of the inner manganese barrier layer 108 may be less than the thickness of the contact structure (e.g., the upper conductive layer 100). Also, in some embodiments, after the high temperature bonding operation, the material of the inner manganese barrier layer 108 may be dispersed between (diffused into) the contact structures (e.g., the upper conductive layer 100 and / or the intermediate conductive layer 92) and the barrier layer 74.

[0065] FIG. 17A shows a bonded structure 50 similar to the bonded structure shown in FIG. 15B. The components of this bonded structure may be identical. FIG. 17A looks very similar to FIG. 15B, but FIG. 17A has been rotated 180 degrees to emphasize that these figures are intended to be illustrative and not limiting of the invention. As shown in FIG. 17A, by way of example, the first semiconductor element 52 may be the semiconductor element that is physically located above the second semiconductor element 118. This is true for all embodiments disclosed herein.

[0066] FIG. 17B illustrates a different embodiment of a bonded structure 50 that can be formed by direct bonding two semiconductor elements 52, 118 along the bonding surface 106. FIG. 17B illustrates a bonded structure 50 similar to FIG. 14B. Each semiconductor element 52, 118 can be identical to the other semiconductor elements. Each semiconductor element 52, 118 can have a non-conductive layer 56, 122 on a semiconductor portion 54, 120, and each non-conductive layer 56, 122 can have an upper non-conductive surface 114, 128 along the bonding surface 106. Each semiconductor element 52, 118 has a contact structure (e.g., an upper conductive layer 100 of the first semiconductor element 52 and a contact structure 130 of the second semiconductor element 118) that is at least partially embedded in the non-conductive layer 56, 122 and has a surface substantially along the bonding surface 106. Except for the portions of the contact structures along the bonding surface 106 (e.g., the upper conductive layer 100 of the second semiconductor element 52 and the contact structure 130 of the second semiconductor element 118), all other surfaces of the contact structures may be lined with a barrier layer 74, 126. In other words, the barrier layer 74, 126 may line the trenches of the contact structures (e.g., the upper conductive layer 100 of the first semiconductor element 52 and the contact structure 130 of the second semiconductor element 108). These barrier layers 74, 126 may be made of any of the second materials disclosed herein. And finally, each semiconductor element 52, 118 may have a lower conductive layer 124 coupled to the barrier layer 74, 126 and at least partially embedded within the non-conductive layer 56, 122. In this embodiment, as well as all others disclosed herein, problems associated with electromigration are mitigated by the provision of a barrier layer 74, 126 made of a second material as described herein (see Table 1 above).

[0067] FIG. 17C shows a semiconductor device 52 similar to FIG. 16. The semiconductor device 52 may have both an inner manganese barrier layer 108 and TSVs 110 lined with TSV barriers 112. Advantageously, the use of cobalt or nickel alloy as the material of construction of the TSV barrier layer 112 acts as a redundant current path and conductive layer. In some embodiments, the second material of the barrier layer 74 may be a nickel-vanadium (NiV) alloy with up to 20% vanadium, for example in the range of 0.01% to 5% vanadium. In some embodiments, the second material of the barrier layer 74 may be Cu / Fe for radiation resistance. In some embodiments, the second material of the barrier layer 74 may include a bimetallic overbarrier (e.g., Mm / Co bimetallic overbarrier structure) including materials such as vanadium, chromium, manganese, iron, and / or nickel.

[0068] summary In one embodiment, the semiconductor device can have a semiconductor portion, a non-conductive layer, and an upper conductive layer at least partially embedded within the non-conductive layer, the upper conductive layer being formed of a first material, the semiconductor device can further have a lower conductive layer below and electrically connected to the upper conductive layer, and a barrier layer between the upper and lower conductive layers, the barrier layer being laterally wider than the cavity, the barrier layer being formed of a second material different from the first material, the second material having a thermal conductivity of 50×10 at 20° C. -8 It has an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

[0069] In some embodiments, the first material comprises copper. In some embodiments, the lower conductive layer comprises copper. In some embodiments, the second material comprises at least one of cobalt, tungsten, vanadium, molybdenum, and nickel. In some embodiments, the second material comprises cobalt. The second material comprises an alloy. In some embodiments, the alloy comprises at least one of cobalt-tungsten phosphate (CWP), cobalt phosphate (CoP), nickel phosphate (NiP), nickel-tungsten (NiW), titanium-tungsten (TiW), TiW / Mo, TiW / Co, and nickel-vanadium (NiV). In some embodiments, the electrical resistivity is 4.5×10 at 20° C. -8 mΩ to 30 x 10 at 20°C -8In some embodiments, the melting point of the second material is in the range of 1200° C. to 3600° C. In some embodiments, the non-conductive layer is comprised of silicon oxide. In some embodiments, the barrier layer is at least partially disposed within the cavity in which the upper conductive layer is contained. In some embodiments, the barrier layer lines at least a portion of the cavity in which the upper conductive layer is contained. The barrier layer lines at least a portion of the cavity in which the upper conductive layer is contained. In some embodiments, the semiconductor device can include a second barrier layer lining at least a portion of the cavity in which the upper conductive layer is contained, the second barrier layer being disposed between the barrier layer and the upper conductive layer. In some embodiments, the second barrier layer is comprised of a second material. In some embodiments, the second barrier layer is comprised of a third material different from the first material and the second material. In some embodiments, the third material is comprised of a metal nitride. In some embodiments, the third material is titanium nitride or tantalum nitride, and the thickness of the barrier layer is greater than the thickness of the second barrier layer. In some embodiments, the semiconductor device may have an intermediate conductive layer deposited on the barrier layer and a third barrier layer deposited on the intermediate conductive layer, and the upper conductive layer is deposited on the third barrier layer. In some embodiments, the intermediate conductive layer is encapsulated by the barrier layer and one or more additional barrier layers. In some embodiments, the one or more additional barrier layers comprise a barrier layer. In some embodiments, the third barrier layer comprises the second material. In some embodiments, the barrier layer lines a cavity in which the intermediate conductive layer is contained, and the barrier layer extends vertically above the third barrier layer substantially to the bonding surface. In some embodiments, the thickness of the upper conductive layer is less than the thickness of the lower conductive layer. In some embodiments, the lower conductive layer comprises a redistribution layer (RDL) embedded within a non-conductive layer. In some embodiments, the non-conductive layer comprises a plurality of dielectric layers disposed over the semiconductor portion. In some embodiments, the semiconductor device may include a manganese barrier layer disposed adjacent to the barrier layer.In some embodiments, the manganese barrier layer lines at least a portion of the cavity in which the upper conductive layer is located, the manganese barrier layer being disposed inside the barrier layer. In some embodiments, the barrier layer is disposed along a length of the top surface of the lower conductive layer, the length being greater than the width of the upper conductive layer. In some embodiments, the lower conductive layer is encapsulated along the top surface by the barrier layer and along the bottom and side surfaces of the lower conductive layer by one or more additional barrier layers. In some embodiments, the one or more additional barrier layers are comprised of a second material. In some embodiments, the one or more additional barrier layers are comprised of a third material different from the first and second materials. In some embodiments, the semiconductor device can have through-substrate vias (TSVs) electrically connected to the lower conductive layer and extending through the semiconductor portion. In some embodiments, the semiconductor device can have a TSV barrier layer lining the TSVs, the TSV layer being comprised of a second material. In some embodiments, the upper conductive layer can be comprised of a dual damascene structure. In some embodiments, the upper conductive layer comprises a single damascene structure.

[0070] In some embodiments, the bonded structure may include a semiconductor element and a second semiconductor element, the second upper non-conductive surface of the semiconductor element being direct-bonded to the second upper non-conductive surface of the second semiconductor element without an intervening adhesive, and the upper contact surface of the upper conductive layer being direct-bonded to the contact structure of the second semiconductor element. In some embodiments, the second semiconductor element has a second semiconductor portion and a second non-conductive layer disposed on the second semiconductor portion and forming a second upper non-conductive surface, the contact structure being at least partially embedded within the second non-conductive layer, the second semiconductor element having a second lower conductive layer disposed below the contact structure and electrically connected to the contact structure, a first barrier layer of the second semiconductor element being disposed between the contact structure and the second lower conductive layer, and the first barrier layer of the second semiconductor element having a thermal conductivity of 30×10 at 20° C. -8It is made of a material having an electrical resistivity of less than mΩ and a melting point of greater than 1200° C. In some embodiments, the contact structure is made of copper and the material of the first barrier layer of the second semiconductor element is made of at least one of cobalt, tungsten, vanadium, and nickel.

[0071] In another embodiment, a semiconductor device may have a semiconductor portion and a non-conductive bonding layer disposed on the semiconductor portion, the non-conductive bonding layer having an upper non-conductive surface forming a first portion of a bonding surface of the semiconductor device, the upper non-conductive surface being pretreated to enable direct bonding to a second semiconductor device, the semiconductor device may have a contact structure at least partially embedded within the non-conductive bonding layer, the contact structure forming a second portion of the bonding surface of the semiconductor device, the contact structure being comprised of a first material, the semiconductor device may have a conductive layer disposed below and electrically connected to the contact structure and a barrier layer disposed between the contact structure and the conductive layer, the barrier layer being comprised of a second material different from the first material, the second material being comprised of at least one of cobalt, tungsten, vanadium, and nickel.

[0072] In some embodiments, the contact structure is made of copper. In some embodiments, the conductive layer is made of copper. In some embodiments, the barrier layer is made of cobalt. In some embodiments, the barrier layer is made of an alloy. In some embodiments, the alloy is made of at least one of cobalt-tungsten phosphate (CWP), cobalt-phosphate (CoP), nickel-phosphate (NiP), nickel-tungsten (NiW), and nickel-vanadium (NiV). In some embodiments, the non-conductive bonding layer is made of silicon oxide. In some embodiments, the barrier layer lines at least a portion of the cavity in which the contact structure is located. In some embodiments, the semiconductor device may have a second barrier layer lining at least a portion of the cavity in which the contact structure is located, the second barrier layer being disposed between the barrier layer and the contact structure. In some embodiments, the second barrier layer is made of a second material. In some embodiments, the second barrier layer is made of a third material different from the first material and the second material. In some embodiments, the third material is made of a metal nitride. In some embodiments, the third material is made of titanium nitride or tantalum nitride. The thickness of the barrier layer is greater than the thickness of the second barrier layer. In some embodiments, the semiconductor device may have an intermediate conductive layer deposited on the barrier layer and a third barrier layer deposited on the intermediate conductive layer, and the contact structure is deposited on the third barrier layer. In some embodiments, the second conductive layer is encapsulated by the third barrier layer and one or more additional barrier layers. In some embodiments, the one or more additional barrier layers are made of a barrier layer. In some embodiments, the third barrier layer is made of the second material. In some embodiments, the barrier layer lines a cavity in which the second conductive layer is contained, and the barrier layer extends vertically above the third barrier layer substantially to the bonding surface. In some embodiments, the contact structure has a thickness less than a thickness of the second conductive layer. In some embodiments, the conductive layer comprises a redistribution layer (RDL) embedded within the non-conductive bonding layer. In some embodiments, the non-conductive bonding layer comprises a plurality of dielectric layers disposed over the semiconductor portion.In some embodiments, the semiconductor device may include a manganese barrier layer adjacent to the barrier layer. In some embodiments, the manganese barrier layer lines at least a portion of the cavity in which the contact structure is located, the manganese barrier layer being disposed inside the barrier layer. In some embodiments, the barrier layer is disposed along a length of the top surface of the conductive layer, the length being greater than a width of the contact structure. In some embodiments, the conductive layer is encapsulated along the top surface by the barrier layer and along the bottom and sides of the conductive layer by one or more additional barrier layers. In some embodiments, the one or more additional barrier layers are comprised of a second material. In some embodiments, the one or more additional barrier layers are comprised of a third material different from the first and second materials. In some embodiments, the semiconductor device may include through-substrate vias (TSVs) electrically connected to the conductive layer and extending through the semiconductor portion. In some embodiments, the semiconductor device may include a TSV barrier layer lining the TSVs, the TSV layer being comprised of a second material. In some embodiments, the contact structure comprises a dual damascene structure. In some embodiments, the contact structure comprises a single damascene structure.

[0073] In some embodiments, the bonded structure may include a semiconductor element and a second semiconductor element, an upper non-conductive surface of the semiconductor element being direct-bonded to a second upper non-conductive surface of the second semiconductor element without an intervening adhesive, and an upper contact surface of the contact structure being direct-bonded to the contact structure of the second semiconductor element. In some embodiments, the second semiconductor element includes a second semiconductor portion and a second non-conductive layer on the second semiconductor portion forming a second upper non-conductive surface, the second contact structure being at least partially embedded within the second non-conductive bonding layer, the bonded structure, a second conductive layer disposed beneath the second contact structure and electrically connected to the second contact structure, a first barrier layer of the second semiconductor element being disposed between the second contact structure and the second conductive layer, and the first barrier layer of the second semiconductor element having a thermal conductivity of 30×10 at 20° C. -8It is made of a material having an electrical resistivity of less than mΩ and a melting point of greater than 1200° C. In some embodiments, the second contact structure is made of copper and the material of the first barrier layer of the second semiconductor device is made of at least one of cobalt, tungsten, vanadium, and nickel.

[0074] In another embodiment, a semiconductor device may have a semiconductor portion, a non-conductive layer disposed on the semiconductor portion, and a contact structure at least partially embedded within the non-conductive bonding layer, the contact structure having an upper contact surface forming at least a portion of a bonding surface of a surface of the semiconductor device, the contact structure being made of a first material, and the semiconductor device may have a conductive layer disposed below and electrically connected to the contact structure, and one or more barrier layers encapsulating the conductive layer, the one or more barrier layers disposed around the top, bottom, and side surfaces of the conductive layer.

[0075] In some embodiments, the contact structure is comprised of copper. In some embodiments, the conductive layer is comprised of copper. In some embodiments, the one or more barrier layers include a first barrier layer disposed along a length of a top surface of the conductive layer, the length being greater than a width of the contact structure, the barrier layer being comprised of a second material different from the first material. In some embodiments, the second material is comprised of at least one of cobalt, tungsten, vanadium, and nickel. In some embodiments, the second material has a viscosity of 30×10 at 20° C. -8The conductive layer has an electrical resistivity of less than mΩ and a melting point of greater than 1200° C. In some embodiments, the one or more barrier layers include a second barrier layer disposed along the bottom and side surfaces of the conductive layer. In some embodiments, the second barrier layer is comprised of a second material. The second barrier layer is comprised of a third material different from the second material. In some embodiments, the third material is comprised of a metal nitride. In some embodiments, the third material is comprised of titanium nitride or tantalum nitride. In some embodiments, the semiconductor device has a second conductive layer disposed on the one or more barrier layers and a third barrier layer disposed on the second conductive layer, and the contact structure is disposed on the third barrier layer. In some embodiments, the second conductive layer is encapsulated by the third barrier layer and one or more additional barrier layers. In some embodiments, the third barrier layer is comprised of the second material. In some embodiments, the thickness of the contact structure is less than the thickness of the second conductive layer. In some embodiments, the conductive layer comprises a redistribution layer (RDL) embedded within a non-conductive bonding layer.

[0076] In another embodiment, the semiconductor device can have a semiconductor portion with an upper non-conductive surface forming a first portion of a bonding surface of the semiconductor device, the upper non-conductive surface being prepared for direct bonding to a second semiconductor device, the semiconductor device can have a contact structure with an upper contact surface forming a second portion of the bonding surface of the semiconductor device, the contact structure being made of a first material, the semiconductor device can have a conductive barrier layer disposed below and electrically connected to the contact structure, the conductive barrier layer being made of a second material different from the first material, the second material having a thermal conductivity of 30×10 at 20° C. -8 It has an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

[0077] In some embodiments, the contact structure is comprised of copper. In some embodiments, the contact structure comprises less than 20% of the conductive barrier layer. The second material is comprised of at least one of cobalt, tungsten, vanadium, and nickel. In some embodiments, the second material is comprised of cobalt. In some embodiments, the electrical resistivity of the second material is less than 4.5×10 at 20° C. -8 mΩ to 30 x 10 at 20°C -8 In some embodiments, the melting point of the second material is in the range of 1200° C. to 3600° C. In some embodiments, the thickness of the contact structure is less than the thickness of the conductive layer. In some embodiments, the thickness of the conductive layer is at least twice the thickness of the contact structure.

[0078] In another embodiment, a method is provided that may include forming a cavity in a non-conductive layer of a semiconductor device, providing a lower conductive layer in the cavity, depositing a barrier layer on the lower conductive layer, and depositing an upper conductive layer on the barrier layer, wherein the upper conductive layer is formed of a first material and the barrier layer is formed of a second material different from the first material, the second material having a thermal conductivity of 30×10 at 20° C. -8 It has an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

[0079] In some embodiments, the first material comprises copper and the second material comprises at least one of cobalt, tungsten, vanadium, and nickel. In some embodiments, depositing the barrier layer comprises providing a barrier layer along a length of the top surface of the lower conductive layer, the length being greater than a width of the upper conductive layer. In some embodiments, the method may further comprise encapsulating the lower conductive layer with the barrier layer and one or more additional barrier layers. In some embodiments, the method may comprise, prior to depositing the upper conductive layer, depositing a second non-conductive layer on at least a portion of the barrier layer and the non-conductive layer, and forming an opening in the second non-conductive layer that extends to the barrier layer. In some embodiments, the method may comprise providing a second barrier layer in the opening over at least a portion of the barrier layer. In some embodiments, providing the second barrier layer comprises providing a second barrier layer formed of a second material. In some embodiments, the method may include providing an intermediate conductive layer in the opening over the second barrier layer. In some embodiments, the method may include depositing a third barrier layer onto the intermediate conductive layer. In some embodiments, depositing the third barrier layer comprises providing a third barrier layer formed of a second material. In some embodiments, the method may include depositing an upper conductive layer onto the third barrier layer. In some embodiments, the method may include plasma treating an upper surface of the second non-conductive layer. In some embodiments, the plasma treating comprises exposing the second non-conductive layer to a plasma comprising nitrogen or oxygen. In some embodiments, the method may include direct bonding the upper conductive layer of the semiconductor device to a contact structure of a second semiconductor device without an intervening adhesive. In some embodiments, the method may include direct bonding a non-conductive bonding layer of a semiconductor device to a second non-conductive bonding layer of a second semiconductor device, hi some embodiments, the non-conductive bonding layer comprises a non-conductive layer.

[0080] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Additionally, the terms "herein," "above," "below," and words of similar import as used herein refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above Detailed Description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0081] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0082] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. A semiconductor device, having a semiconductor portion, a non-conductive layer disposed on the semiconductor portion; an upper conductive layer at least partially embedded within the non-conductive layer and having a first lateral width, the upper conductive layer being formed of a first material; a lower conductive layer disposed below the upper conductive layer and electrically connected to the upper conductive layer, the lower conductive layer having a second lateral width greater than the first lateral width; a third lateral width greater than the first lateral width, the barrier layer being laterally wider than the cavity, the barrier layer being formed of a second material different from the first material, the second material having a viscosity of 50×10 at 20° C. -8 A semiconductor device having an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

2. The semiconductor device of claim 1 , wherein the second material comprises at least one of cobalt, tungsten, vanadium, molybdenum, or nickel.

3. The electrical resistivity is 4.5×10 at 20° C. -8 mΩ to 30 x 10 at 20°C -8 3. The semiconductor device of claim 2, wherein the resistance is in the range of up to mΩ.

4. 3. The semiconductor device of claim 2, wherein the melting point of the second material is in the range of 1200 to 3600 degrees Celsius.

5. 2. The semiconductor device of claim 1, further comprising a second barrier layer lining at least a portion of said upper conductive layer, said second barrier layer being disposed between said barrier layer and said upper conductive layer.

6. 6. The semiconductor device of claim 5, wherein said second barrier layer is made of said second material.

7. 6. The semiconductor device of claim 5, wherein the second barrier layer is made of a third material different from the first material and the second material.

8. 6. The semiconductor device of claim 5, wherein the thickness of said barrier layer is greater than the thickness of said second barrier layer.

9. The semiconductor device of claim 1 , wherein the thickness of the upper conductive layer is less than the thickness of the lower conductive layer.

10. 2. The semiconductor device of claim 1, wherein said barrier layer is disposed along a length of an upper surface of said lower conductive layer, said length being greater than a width of said upper conductive layer.

11. 11. A hybrid bonded structure comprising the semiconductor element and a second semiconductor element according to any one of claims 1 to 10, wherein a second upper non-conductive surface of the semiconductor element is directly bonded to a second upper non-conductive surface of the second semiconductor element without an intervening adhesive, and an upper contact surface of the upper conductive layer is directly bonded to a contact structure of the second semiconductor element.

12. The second semiconductor element comprises: a second semiconductor portion; a second non-conductive layer disposed on the second semiconductor portion and forming the second upper non-conductive surface, the contact structure being at least partially embedded within the second non-conductive layer; a second lower conductive layer disposed below and electrically connected to the contact structure; a first barrier layer of the second semiconductor device disposed between the contact structure and the second lower conductive layer, the first barrier layer of the second semiconductor device having a thermal conductivity of 30×10 at 20° C. -8 12. The hybrid bonded structure of claim 11, made from a material having an electrical resistivity of less than mΩ and a melting point above 1200°C.

13. 13. The hybrid bonded structure of claim 12, wherein the contact structure is comprised of copper and the material of the first barrier layer of the second semiconductor device is comprised of at least one of cobalt, tungsten, vanadium, or nickel.

14. A semiconductor device, a bonding surface pretreated to be directly bondable to a second semiconductor element; a non-conductive portion having an upper non-conductive surface forming a non-conductive portion of the bonding surface; a contact structure at least partially embedded in the non-conductive portion, the contact structure having an upper contact surface that forms a conductive portion of the bonding surface of the semiconductor device, the contact structure having a lower surface opposite the upper contact surface, the contact structure being made of a first material; a conductive barrier layer disposed below the contact structure and electrically connected to the contact structure, the conductive barrier layer being closer to the lower surface of the contact structure than to the upper contact surface of the contact structure, the conductive barrier layer being made of a second material different from the first material, the second material having a thermal conductivity of 30×10 at 20° C. -8 A semiconductor device having an electrical resistivity of less than mΩ and a melting point of greater than 1200°C.

15. 15. The semiconductor device of claim 14, wherein the contact structure is made of copper, and the contact structure comprises less than 20% of the second material.

16. The semiconductor device of claim 14 , wherein the second material comprises at least one of cobalt, tungsten, vanadium, or nickel.

17. The electrical resistivity of the second material is 4.5×10 at 20° C. -8 mΩ to 30 x 10 at 20°C -8 15. The semiconductor device of claim 14, wherein the resistance is in the range of 1000 to 1000 mΩ and the melting point of the second material is in the range of 1200 to 3600°C.

18. 15. The semiconductor device of claim 14, wherein the thickness of the conductive layer is at least twice the thickness of the contact structure.

19. A semiconductor device, having a semiconductor portion, a non-conductive layer disposed on the semiconductor portion; an upper conductive layer at least partially embedded within the non-conductive layer, the upper conductive layer being formed of a first material; a lower conductive layer embedded within the non-conductive layer, the lower conductive layer being disposed below the upper conductive layer and electrically connected to the upper conductive layer; a first barrier layer disposed between the upper conductive layer and the lower conductive layer, the first barrier layer being formed of a second material different from the first material, the second material having a thermal conductivity of 50×10 at 20° C. -8 having an electrical resistivity of less than mΩ and a melting point of greater than 1200°C; a second barrier layer lining at least a portion of the upper conductive layer;

20. 20. The semiconductor device of claim 19, wherein the second barrier layer is disposed between the first barrier layer and the upper conductive layer.

21. The method of claim 20, further comprising: a non-conductive portion defined by at least a portion of a surface of the non-conductive layer opposite the semiconductor portion; 21. The semiconductor device of claim 19 or 20, further comprising: a conductive portion defined by an exposed surface of the upper conductive layer.

22. A bonded structure comprising: The semiconductor device of claim 21 ; a second semiconductor element, the second semiconductor element having a second hybrid bonding surface having a non-conductive region and a conductive region; the non-conductive region of the second hybrid bonding surface is directly bonded to the non-conductive portion of the hybrid bonding surface without an intervening adhesive; A bonded structure wherein the conductive region of the second hybrid bonding surface is directly bonded to the conductive portion of the hybrid bonding surface without an intervening adhesive.

23. A bonded structure comprising: The semiconductor element according to any one of claims 14 to 18; a second semiconductor element; the non-conductive portion of the bonding surface is directly bonded to a non-conductive region of a second bonding surface of the second semiconductor element without an intervening adhesive; A bonding structure wherein the conductive region of the bonding surface is directly bonded to the conductive portion of the second bonding surface of the second semiconductor element without an intervening adhesive.

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