METHOD FOR DETECTING MISMISMATCH BETWEEN PARALLEL POWER ELECTRONICS DEVICES, POWER ELECTRONICS MODULE, COMPUTER SOFTWARE, AND COMPUTER-READABLE NON-TRANSITORY RECORDING MEDIUM

Abstract

A method for detecting a mismatch between parallel power electronic elements 11.1, 11.2 on a power electronics module 1, the method comprising: a. triggering a measurement period in response to detecting a common turn-off of the elements; and b. detecting an emitter voltage V of at least one of the elements during the measurement period. eE and c. extracting data from the measurements, the data comprising: eE and d. including signs and / or amplitudes of local extrema of said elements; and d. estimating from the extracted data at least the presence or absence of mismatch between said elements.

Description

[Technical field]

[0001] The present disclosure relates to the field of power electronic modules. More specifically, the present invention relates to monitoring assemblies that contain multiple devices / elements in parallel. [Background technology]

[0002] Such power devices are subject to high thermal variations and high thermo-mechanical stresses. Due to the wide variety of compositions and structures of the different components / devices that make up the assembly, crack propagation, wire bond lift-off, delamination, metallization reconfiguration, and other effects lead to interconnect failures. The failure mechanisms are multi-related, and in most cases wire bond lift-off occurs. Such failures are very difficult to predict or detect before a total failure of the assembly. In addition, the aging of parallel devices may not be uniform, e.g. due to manufacturing or mounting mismatches, resulting in electrical-thermal life mismatches. Knowing the state of health of each power device in the assembly is important to perform life extension and selective maintenance / replacement during the operation and maintenance phases, respectively.

[0003] Online monitoring of wire bonds allows the steady-state voltage (V ce This can be done by using a threshold (referred to as V ) and comparing it to a limit value. ce To isolate the power supply to a single power device, the other parallel devices can be turned off. By operating the devices one at a time, it is possible to evaluate their individual degradation. However, this method requires separate drivers. The steady-state V ceis dependent on temperature and current (including ripple) and therefore requires calibration / correction. In addition, clamp circuits must be implemented to protect the measurement, imposing time responses that are incompatible with fast switching frequencies and / or extreme duty cycles. Finally, the connection to high voltages imposes high design and safety constraints that make this solution difficult to adopt. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure improves this situation. [Means for solving the problem]

[0005] 1. A method for detecting mismatch between parallel power electronic devices on a power electronics module, the method comprising: a. triggering a measurement period in response to detecting a common turn-off of said elements; b. During the measurement period, the emitter voltage V of at least one of the above elements eE measuring a sequence of c. extracting data from the measurement, the data being the emitter voltage V during the measurement period. eE and including the signs and / or amplitudes of the local extrema of d. Inferring from the extracted data at least the presence or absence of mismatches between said elements; A method is proposed, which includes:

[0006] In another aspect, a power electronics module is proposed, comprising at least two parallel power electronic elements and configured to implement such a method.

[0007] In another aspect, proposed is computer software comprising instructions which, when executed by a processor, perform at least a part of a method as defined herein. In another aspect, proposed is a computer readable non-transitory recording medium having registered thereon software for performing a method as defined herein, when executed by a processor.

[0008] The following features can optionally be implemented separately or in combination with each other.

[0009] The extracted data is The two emitter voltages V of the two elements eE1 and V eE2 the sign of the local extremum of the sequence of Emitter voltage V of one element eE the signs and amplitudes of the local extrema of the sequence At least If the presence of a mismatch between the elements is suspected, the method comprises: e. From the extracted data, the emitter voltage V eE Or V eE1 and V eE2 estimating whether the element for which the measured value is the most degraded; Further includes.

[0010] The extraction from the measurement is performed by analog logic circuits, making the use of analog-to-digital converters redundant.

[0011] The extracted data is the emitter voltage V during the measurement period. eE and further including the amplitudes of the local extrema of If the presence of a mismatch between the elements is suspected, the method comprises: f. estimating a quantification of said mismatch from the extracted data; Further includes.

[0012] The differential emitter voltage V of a pair of elements eeis measured.

[0013] Implemented on a module having at least three parallel power electronic elements, measurements are taken in a sequential manner for each pair of elements having a common monitoring circuit, and a multiplexer is operatively interfaced between said monitoring circuit and said elements.

[0014] The method is: imposing an auxiliary external gate resistor during the measurement operation; Further includes.

[0015] The estimation operation further includes identifying a most degraded element of the at least two elements, and then: The sequence of operations is repeated at least once, with the at least one repetition including inducing a delay d in the turn-off of at least one of the elements relative to another element before triggering a measurement period.

[0016] The sequence is repeated at least once so that the detection mismatch is performed along the operational life of the module.

[0017] The method is: generating an alert signal in response to the estimated information; Further includes.

[0018] Other features, details and advantages are set forth in the following detailed description and in the figures. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a cross-sectional side view of an assembly or module including two parallel semiconductor devices / elements. [Diagram 2] 2 is a top view of the assembly according to FIG. 1, where "Y" is the cut plane of FIG. [Diagram 3] 1 is a graph showing a turn-off delay versus a current flowing through a power device according to an embodiment. [Figure 4]4 is a graph illustrating turn-off delay versus threshold voltage of a power device according to one embodiment. [Diagram 5] 1 is a graph illustrating current flow through two parallel power devices during a turn-off period according to one embodiment. [Figure 6] FIG. 2 illustrates a power module architecture according to one embodiment. [Figure 7] FIG. 2 illustrates a power module architecture according to one embodiment. [Figure 8] 1 is a graph showing waveforms of emitter voltages of two parallel power elements during a turn-off period of a module according to one embodiment. [Figure 9] 4 is a graph showing a waveform superposition of the emitter voltage of a power device during a turn-off period according to one embodiment. [Figure 10] 10 is a graph showing overlaid emitter voltage waveforms for the power device of FIG. 9 and a power device in parallel during the same turn-off period according to one embodiment. [Figure 11] FIG. 1 is a schematic diagram illustrating identifying degraded power elements in a circuit according to one embodiment. [Figure 12] 1 is a graph showing the maximum value ("peak") of the emitter voltage of a power device as a function of the degradation of the power device, counted as the number n of wire lift-offs. [Figure 13] 7 is a graph showing the superposition of emitter-to-emitter voltage waveforms of two parallel power elements of a module according to the architecture of FIG. 6; [Figure 14] 8 is a graph showing the superposition of emitter-to-emitter voltage waveforms of two parallel power elements of a module according to the architecture of FIG. 7. [Figure 15] 7 is a graph illustrating the minimum emitter-to-emitter voltage of two parallel power elements of a module according to the architecture of FIG. 6 in accordance with one embodiment. [Figure 16] 10 is a graph illustrating the minimum emitter-to-emitter voltage of two parallel power elements of a module according to the architecture of FIG. 8 in accordance with one embodiment. [Figure 17]7 is a graph showing maximum emitter-to-emitter voltages of two parallel power elements of a module according to the architecture of FIG. 6 in accordance with one embodiment. [Figure 18] 8 is a graph showing maximum emitter-to-emitter voltages of two parallel power elements of a module according to the architecture of FIG. 7 in accordance with one embodiment. [Figure 19] FIG. 13 is a circuit diagram of an embodiment with an additional external resistor during turn-off switching; [Figure 20] FIG. 13 is a logic diagram illustrating a method for converting a voltage offset to a delay offset according to one embodiment. [Figure 21] 1 is a graph illustrating how an indicator for degradation of two parallel elements of a module can be constructed as a function of time, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Reference is now made to figures 1 and 2. In the following, an assembly or module 1 comprises at least two parallel power electronic elements 11. The power electronic elements 11 can be, for example, power semiconductor devices, power sub-modules or power converters. Here, the term "element" or "device" is used to indicate sub-parts of a power "module" or power "assembly" that are electrically connected in parallel with respect to each other. The elements 11 of the same module 1 can be packaged together or separately from each other.

[0021] FIG. 1 is an example of a cutaway view of module 1 shown in FIG. 2 along the line referenced "Y". In various embodiments, the top view can show separately packaged elements. The elements referenced "Z" on FIG. 2 represent, in a schematic manner, electrical isolation in a configuration in which elements 11.1 and 11.2 are disconnected from one another, as described below with reference to FIG. 7. The emitter pads (e1 and e2) of each element 11.1 and 11.2 are isolated from one another. The gate drivers (G1 and G2) of each element 11.1 and 11.2 are isolated from one another. In contrast, in a configuration in which elements 11.1 and 11.2 are connected to one another, as described below with reference to FIG. 6 (common emitter pad E and common gate driver G), the isolation Z of FIG. 2 does not exist. For simplicity, external connections to the system are not depicted. In another configuration, elements 11.1 and 11.2 are based on separate mechanical structures as illustrated in Figure 1, with external electrical connections for element E, gate drivers (G1 and G2), and emitter pads (e1 and e2). In other words, the connections of the elements can be determined and made at a system level outside the device structure.

[0022] 1 and 2 show an example of a module 1 including two elements 11 (separately referred to as 11.1 and 11.2 in FIG. 2) and including a superposition of layers. From bottom to top, FIG. 1 includes an element 11, namely an electrical insulator layer 101 (for example based on aluminum oxide) and a conductive layer 102 (for example copper). From bottom to top, the module 1 further includes components separately associated with each element 11, namely a solder layer 103, a semiconductor die 104 and a metallization layer 105. The module 1 further includes conductive wire bonds 2 that ensure an electrical connection between a part of the conductive layer 102 and the metallization layer 105 of the element 11 in the cross-sectional view (the module 1 includes at least two parallel power electronic elements 11).

[0023] Each element 11 here comprises a semiconductor die 104, which is a semiconductor element, for example an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor die 104 can be made of silicon, silicon carbide (SiC) and / or gallium nitride (GaN). The elements 11 are power electronic devices and are configured to operate under voltages of more than 50V and currents of more than 1A.

[0024] The semiconductor die 104 is metallized at least on one of its sides, here its top side. In other words, the semiconductor die 104 is covered with a metallization 105. The metallization layer is made, for example, from an aluminum alloy. Such a metallization 105 has a thickness between 1 micrometer and 20 micrometers. The free surface is used to fix the wire bonds 2, for example by thermosonic bonding. Such a connection is exposed to harsh conditions during the operational life of the module 1, which may lead to some cracks and failures at this particular location.

[0025] <Theory> In a module 1 with at least two parallel power electronic elements 11, the load current is distributed through the various parallel elements 11 according to their on-state resistance, which depends on the assembly and bonding temperature. When a wire bond 2 lift-off or any other electrical connection failure occurs, the on-resistance of the element increases. If one element 11 degrades more than the other power element(s) 11 connected in parallel, a drop in the current through one element can be observed, for example 1% to 20%. The drop in current is supported on the parallel power element(s) carrying more current.

[0026] Furthermore, in the case of thermal degradation (which typically leads to delamination), the temperature increases on the degraded power device 11, causing a drop in the threshold voltage by up to 0.5V.

[0027] In the following, the element 11 is an IGBT device, but those skilled in the art can translate the description based on such examples to other power electronic elements, such as MOSFET or MISFET semiconductors.

[0028] Applicants have found that the turn-off waveform is highly dependent on the current through device 11. cc to negative voltage V ee In a conventional gate drive circuit that imposes a voltage step to ge The saturation collector current can be calculated according to the following formula [Equation 1]. ge It depends on and is expressed by the following equation [Equation 2]. Current I sw The turn-off delay t of the element through which d is the gate resistance R g , input capacitance C ies , transconductance gfe, and threshold voltage V th As a function of, it can be calculated using the following equation [Equation 3].

[0029]

number

[0030]

number

[0031]

number

[0032] 3 and 4 show the turn-off current I toff (Here, the current I sw is subtracted) and the threshold voltage V th Turn-off delay t according to d3 and 4 are taken for device 11, which in this example is an IGBT known as "CM100RX-24S1" and has a V cc =15V, V ee =-5V, R g = 72Ω, C ies = 21nF, V th It has nominal characteristics of =6V and gfe=43A / V.

[0033] Therefore, the device(s) with higher current should initiate turn-off current switching before the device with lower current (deteriorated). Turn-off of the deteriorated device with reduced current passing through it may be delayed by a few nanoseconds to 100 ns. Furthermore, the threshold voltage V th The element with a high threshold voltage V th The lower voltage V th The turn-off of degraded elements exposed to this can be delayed by a few nanoseconds to 40 ns.

[0034] Table 1 below summarizes the effects of the two types of degradation of element 11, R on is the resistance of element 11 in the on state, and I c is the current through element 11, and T j is the junction temperature, and V ce is the steady-state voltage.

[0035] [Table 1]

[0036] FIG. 5 shows the current I flowing through two parallel elements 11.1 and 11.2 (here two IGBTs) of a module 1 during turn-off commutation, when the first element 11.1 is more degraded than the second element 11.2. cAs can be seen, the turn-off of the degraded device 11.1 is delayed. The current in device 11.1 increases momentarily because device 11.1 is now carrying a higher percentage of the total load current by itself.

[0037] A method for detecting a mismatch between parallel power electronic elements 11 in a power electronic module 1 includes: a. triggering a measurement period in response to detecting a common turn-off of said elements 11; b. During the measurement period, the emitter voltage V of at least one of the above elements eE measuring a sequence of c. extracting data from the measurement, the data being the emitter voltage V during the measurement period. eE and including the signs and / or amplitudes of the local extrema of d. Inferring from the extracted data at least the presence or absence of mismatches between said elements; may include.

[0038] Now, by way of example, reference is made to figures 6 and 7. Figure 6 corresponds to a configuration in which two parallel elements 11.1 and 11.2 (IGBTs) have a common gate driver, and figure 7 corresponds to a configuration in which two parallel elements 11.1 and 11.2 (IGBTs) each have their own gate driver. The respective variations of the currents I1 and I2 flowing through elements 11.1 and 11.2, respectively, can be observed with the corresponding voltages.

[0039] In Figures 6 and 7, the gate driver resistors and Kelvin resistors are not shown. Based on these examples, in various embodiments, each element 11 can comprise a single die or a combination of dies. The elements 11 of the same module 1 may or may not be packaged together. They can have a common gate driver configuration (Figure 6) or each can have their own corresponding gate driver (Figure 7). The number of parallel power elements 11 in a module 1 is at least two. In various embodiments, it can be, for example, three, four, up to ten, or even twenty.

[0040] In the examples of Figures 6 and 7, the corresponding emitter voltages of elements 11.1 and 11.2 are V eE1 and V eE2 and a parasitic inductor L between the emitter pads on the power semiconductor elements 11.1 and 11.2 and the external emitter pad of the module 1. eE1 and L eE2 Such an inductor L eE is formed by connecting the power semiconductor element 11 to the rest of the power module 1. The emitter pad on the power semiconductor element 11 can be measured, for example, with a Kelvin emitter located on the power module 1. In other words, V eE1 and V eE2 The change in (shape of the curve) is a proportional and differential expression of the power semiconductor current due to RL behavior. As one skilled in the art will appreciate, the corresponding voltage V eE1 and V eE2 can be measured at other points of the circuit depending on the structure and type of components of each module 1, the two IGBTs as well as the parasitic inductor L eE1 and L eE2 The above-mentioned architecture having is merely an example, and the solutions disclosed herein are not limited to such architectures.

[0041] In some embodiments, the turn-off event may occur directly from a trigger signal sent by the controller of module 1 or from the emitter voltage V eE To detect the peak, the measured emitter voltage V eE The value can be compared to a predetermined value. For example, the peak is eE It can be evaluated if the values ​​fall outside a nominal range centered around 0V, such as -1V;1V, or -2V;2V.

[0042] Next, referring to FIG. 8, the emitter voltage V of elements 11.1 and 11.2 eE1 and V eE2 are measured (and stored) starting from a moment t corresponding to a common turn-off command signal for the elements 11.1 and 11.2 in question. In other words, the measurements are synchronized with a common turn-off trigger. The values ​​shown in Figure 8 correspond to measurements made on the structure shown in Figure 7 (two IGBTs with separate gate driver configurations).

[0043] <Whether or not there is a mismatch> In some embodiments, if the objective is only to determine whether there is a mismatch in module 1, without needing to identify which element is most degraded, then a single emitter voltage V of a single element 11, for example, may be used. eE It is sufficient to monitor the absolute value of one emitter voltage V during the measurement period, even if its sign is unknown, by comparing the absolute value of V with a threshold value. eE The amplitude of the local extremum of makes it possible to deduce the presence or absence of a mismatch between the corresponding element 11 and another element 11 of the module 1. In some embodiments with the same objective (only to determine whether a mismatch is present or not in the module 1, without the need to identify which element is the most degraded), for example the emitter voltage V of the pair of elements 11.1 and 11.2 eE1 and V eE2By checking whether the two signs of the pair are different, it is sufficient to monitor the two signs even if the absolute values ​​themselves are unknown. eE1 and V eE2 The sign of the local extremum of makes it possible to deduce the presence or absence of a mismatch between the corresponding elements 11.1 and 11.2. These two possibilities (a single absolute value V eE , or two values ​​V to be compared with each other eE1 and V eE2 The two signs of V ) are the reason why we can say that the required data is the sign of the emitter voltage of "at least one element" and / or the amplitude of the local extremum. eE Data containing only one sign of α should be avoided, as it is less reliable to estimate the presence / absence of a mismatch.

[0044] <Whether it is most deteriorated or not> In some other embodiments, the purpose is to determine whether there is a mismatch in module 1 and, if there is, to increase the emitter voltage V eE The purpose of this study is to determine whether the element 11 being measured is the most degraded, for example to plan targeted interventions. eE1 and V eE2 Since the voltage V eE1 and V eE2 The extreme (minimum and / or maximum) values ​​of can be used to determine whether element 11.1 or 11.2 carries the higher current. In the example of FIG. 8, I C,11.1 =89A,I C,11.2 = 107 A. In Fig. 9 and Fig. 10, measurements for several test cases, namely 0, 1, 2, 3, 4 and 5 wire lift-off situations on one element 11, are superimposed. Each curve corresponds to one situation. Fig. 9 shows the measured emitter voltage V eE1 values, and Figure 10 shows the measured emitter voltage V of element 11.2. eE2Table 2 below shows an example of measurements (magnitude and sign) for amplitudes (absolute value) above 0.5V for both power elements 11.1 and 11.2 in a test case with 5 wire liftoffs.

[0045] [Table 2]

[0046] As an example, the first value outside a predefined range (e.g., [-0.5V; +0.5V]) is designated as a trigger "peak" referenced in the figure with "O." The trigger peak can be used to define a time reference to trigger measurement operations and synchronize them.

[0047] In this example, the emitter voltage V of element 11.1, which is the first peak "I" after the reference peak "O", eE1 The extreme value of is positive (+3.65V), and the emitter voltage V of element 11.2 eE2 The extreme value of is negative (-2.8 V). This allows identifying element 11.1 as being the most deteriorated of elements 11.1 and 11.2.

[0048] Single emitter voltage V eE is measured and it is possible to identify a first peak I corresponding to a turn-off trigger (e.g., in response to a command / trigger signal sent by the controller of module 1), the emitter voltage V of the first peak I eEThe sign of is sufficient to identify whether the corresponding element is the most degraded or not: if the sign is positive, it is the most degraded element; if the sign is negative, it is not the most degraded element. This also applies for modules with more than two parallel elements. Identifying the first peak I to be considered means to avoid confusion with the preliminary peak that comes directly from the turn-off command signal (corresponding to peak "O" in Figures 9 and 10). An example of distinguishing and identifying the preliminary peak O and the first peak I is to directly monitor the trigger / command signal sent by the controller of module 1.

[0049] The value of the extrema, and especially the sign, are important points of the measurement. Extracting such data from the raw measurement signal can be done by using an analog to digital converter (ADC). In some embodiments, the extraction of the extrema from the measurement (identification of the "peaks") is done by analog logic circuits, making the use of expensive analog to digital converters redundant.

[0050] An example of an analog logic circuit that can be used is shown in Figure 11. In the example described here, the analog logic circuit comprises a first signal conditioning circuit 201, a second signal conditioning circuit 202, and a module including an RS flip-flop and an inverter 203. In various embodiments, the analog logic circuit comprises other functionally equivalent parts.

[0051] Waveform A shows the emitter voltage V measured for the most degraded element 11. eE In reality, the relative degradation state of each element 11 is unknown since that is one of the pieces of information we want to determine. For example, if two power elements 11.1 and 11.2 are in parallel and 11.1 is more degraded, if the two emitters e1 and e2 of power elements 11.1 and 11.2 are disconnected, such a waveform will be the V eE1When processed by first signal conditioning circuit 201 and second signal conditioning circuit 202, logic signals A1 and A2 are output, respectively. When the pair of these two logic signals is analyzed by an RS flip-flop and an inverter (module 203), a logic signal (q=1) is output, which means that power element 11.1 is the most degraded.

[0052] Waveform B shows the emitter voltage V measured on the least degraded element 11. eE For example, if two power elements 11.1 and 11.2 are in parallel, and 11.2 is the least degraded, when the two emitters e1 and e2 of the power elements 11.1 and 11.2 are disconnected, such a waveform will be V e2e1 =V eE2 -V eE1 When processed by the first signal conditioning circuit 201 and the second signal conditioning circuit 202, logic signals B1 and B2 are output, respectively. When this pair of two signals is analyzed by an RS flip-flop and an inverter (module 203), a logic signal (q=0) is output, which means that power element 11.2 is the least degraded.

[0053] Waveform C shows the emitter voltage V measured on the least degraded element 11. eE For example, if two power elements 11.1 and 11.2 are in parallel, and 11.2 is the least degraded, if the two emitters e1 and e2 of the power elements 11.1 and 11.2 are disconnected, such a waveform will be eE2 It becomes.

[0054] After being processed by the first signal conditioning circuit 201 and the second signal conditioning circuit 202, logic signals C1 and C2 are output, respectively. When this pair of two signals is analyzed by an RS flip-flop and an inverter (module 203), a logic signal (q=0) is output, which means that power element 11.2 is the least degraded.

[0055] In summary, the output signals of the sequence analyzers 201, 202, 203 directly answer the logical question: "Is the monitored element the most degraded element?".

[0056] <Quantification of mismatch> In some embodiments, the degradation mismatch can be quantified. For example, an assembly of a diode, a capacitor and a resistor acting as a peak detector can be combined into the circuit shown in FIG. 11. Sampling can be performed by an ADC or the signal can be compared to a predefined threshold by a comparator, so that the quantification of the mismatch is the extreme emitter voltage max (V eE ) as a function of the amplitude of the wire lift-off. Figure 12 is an example of such a quantification to determine the number of wire lift-offs.

[0057] <Kelvin voltage measurement> In an embodiment in which the mismatch between only two elements 11 of a module 1 is monitored, a differential emitter voltage V ee In another embodiment, two measurements can be compared, and V e1e2 =V eE1 -V eE2 In this way, only one sensor and conditioning circuit is required (one for each pair of elements 11), increasing the sensitivity to degradation mismatch. Furthermore, some dependency on temperature and current is reduced. Such an implementation is compatible with both architectures, common or separate gate driver configurations (examples of Figures 6 and 7).

[0058] Figure 13 shows the emitter voltage V during a turn-off event in a separated gate driver configuration. e1e2 , where each curve corresponds to a particular number of wire lift-offs in element 11.1. FIG. 14 shows the variation of emitter voltage V during a turn-off event in a common gate driver configuration. e1e2, where each curve corresponds to a particular number of wire lift-offs in element 11.1. Figure 15 shows the peak value of the negative extreme (minimum) as a function of the degradation level imbalance quantified by the number of lift-offs (n) in a separate gate driver configuration, where each curve corresponds to a particular regime of current I and temperature T. Figure 17 shows the peak value of the negative extreme (minimum) as a function of the degradation level imbalance quantified by the number of lift-offs (n) in a separate gate driver configuration, where each curve corresponds to a particular regime of current I and temperature T. e1e2 16 shows the same as FIG 15 in a common gate driver configuration, and FIG 18 shows the same as FIG 16 in a common gate driver configuration.

[0059] Considering Figures 13 to 18, the amplitude of the peaks is a function of the degradation level. This is the case for both common and separate gate driver configurations. The extracted data is the measured emitter voltage V eE In embodiments involving the amplitude of the local extremum of V, it is possible to deduce a quantification of the mismatch from the extracted data. eE1 and V eE2 When a sequence of is measured by a Kelvin emitter sensor, it becomes possible to obtain such information about a module 1 equipped with such a sensor.

[0060] Using only a single Kelvin emitter sensor for a pair of elements 11 is possible for both connected element (as in FIG. 6) and disconnected element (as in FIG. 7) configurations. In addition, Kelvin emitter sensors are very convenient since they are available in several existing architectures, and there is no need to modify such existing architectures to add a Kelvin emitter sensor. Also, such sensors are inexpensive relative to other existing sensors.

[0061] <Pairwise monitoring> In some embodiments, to advantageously limit the number of monitoring circuits to a single one even for a large number of power elements 11 in module 1, a multiplexer can be provided to connect a single monitoring circuit to an appropriate pair of elements 11. The elements 11 are switched in pairs, with the emitter voltage V e1e2 Monitor.

[0062] <Higher sensitivity> In some embodiments, the method comprises: imposing an auxiliary external gate resistor during the measurement operation; Further includes.

[0063] By artificially increasing the gate resistance for the measurement, the mismatch sensitivity is increased during a single switching time, and the resulting increased losses are time-limited (only during the short measurement period). Figure 19 shows an example of a circuit that can be used to temporarily impose such a resistance increase. Switch M3 is opened only during the measurement in response to an inverted trigger signal. During the measurement, the total gate resistance is R gext and R gext2 Otherwise, module 1 is connected to the external gate resistor R gext Only operates in normal mode.

[0064] Feedback Loops and Synchronization In some embodiments, the method is performed first to identify the most degraded element, and then the method is repeated at least once with a retrofit loop arranged to induce a delay in the turn-off of at least one of the elements relative to the other(s) so as to converge towards a temporally synchronized first peak I.

[0065] Such an embodiment with two elements 11.1 and 11.2 is shown in FIG. 20. The delay of the turn-off of the first element 11.1 is referenced t1 and the delay of the turn-off of the second element 11.2 is referenced t2. In an embodiment with more than two elements, the same method can be used by applying the same delay t to the turn-off of the element not specified as the "most degraded". The value of the induced delay t1 and / or t2 can be adjusted stepwise until the time synchronization of the first peak I is reached. In this way, by reducing the time offset, even before the complete synchronization is reached, the turn-off losses are at least partially balanced in the module 1, the overcurrents in the module 1 are reduced and the resulting degradation effects in the module 1 are reduced. The value of the absolute difference (|t1-t2|) between the two imposed delays can be used as an indicator of the relative degradation between the elements 11.1 and 11.2. For example, as represented in FIG. 20, the value of the absolute difference (|t1-t2|) between the two imposed delays can be adjusted stepwise until the delays are greater than a predefined threshold t th It can be compared with the threshold t th If exceeded, an alert signal can be generated.

[0066] <Loop processing> In some embodiments, the method comprises a periodic sequence of operations. In other words, the method described at the beginning is repeated N times, for example with a period of several hours. The measurements and / or extracted data are stored to constitute a history of events related to the degradation of the element 11 during an operation period of the module 1 that is longer than a single turn-off period. Then, or in real time, the extracted data at the current time can be compared with the previous extracted data. If this comparison indicates that there is a change, a degradation indicator of the module 1 can be incremented. If such a degradation indicator reaches a predefined value (threshold), a warning signal is generated.

[0067] The degradation of module 1 is V eEEven if there is some mismatch in the waveforms, they can be observed during the entire lifetime. Furthermore, the current degradation level of each element 11 can be identified (not just in relation to each other). Table 3 below shows an example of four measurements, each taken at an interval of 1000 hours, where the voltage of the first peak I is measured and stored in a table.

[0068] [Table 3]

[0069] From the data extracted and stored in Table 3, we can see that: From measurement 2 compared to measurement 1, element 11.2 is degrading faster than element 11.1 → the degradation index of element 11.2 may increase. From measurement 3 compared to measurement 2, element 11.2 is degrading faster than element 11.1 → the degradation index of element 11.2 may increase. From measurement 4 compared to measurement 3, element 11.1 is degrading faster than element 11.2 → the degradation index of element 11.1 may increase.

[0070] In the example described here, the thresholds that trigger the alert / warning signal are pre-set to correspond to the situation where the fifth wire bond is lifted off. The thresholds are obtained by testing prototypes. The definition of the thresholds can be modified and adapted to the situation by those skilled in the art.

[0071] FIG. 21 shows the voltage V between the two emitters of elements 11.1 and 11.2. e1e2 4 shows a schematic example of the evolution of the luminance distribution over time and the corresponding degradation indicators.

[0072] <Conclusion> Differential electrical, thermal and degradation of parallel power elements leads to current imbalance at steady state. This is due to junction temperatures which generate uneven electrical resistance, uneven current distribution. Therefore, monitoring this current imbalance is a differential parameter that is sensitive to electrical, thermal and damage. However, it is necessary to monitor the individual power element currents with a relatively high resolution, which is technically complex and costly.

[0073] Methods based on monitoring transient switching waveforms have generally been considered expensive, inaccurate and non-robust due to high frequency sensor requirements, low sensitivity and complex dependencies on operating conditions and design.

[0074] To achieve high current capability, there is a technique of paralleling power elements (e.g., dies, converters, or subsets of elements). This solution is widely adopted considering the flexibility and scalability of current power electronic equipment. Among the problems that paralleling power electronic equipment must face, the current distribution caused by the non-uniform electrical-thermal damage characteristics needs to be identified during the commissioning, use, and maintenance phases.

[0075] The problem addressed by the method disclosed above is safe, accurate, low-cost current distribution and degradation monitoring of the electrical-thermal interconnects of individual power devices in parallel, and automatic generation of an alert signal. eE It is possible to address such issues by using (Kelvin-to-emitter voltage) to identify (at least) the mismatch based on the sign and / or amplitude of the sequence of peaks during the turn-off switching time. [Industrial Applicability]

[0076] The technical solutions presented in this specification can be used to automatically trigger an alert signal to implement corrective measures such as repair or functional adaptation of the power module, or even targeted replacement.

[0077] The present disclosure is not limited to the methods, modules, and computer programs described herein, which are merely examples, and the present invention encompasses all alternatives that a person skilled in the art would envision upon reading this document. [Explanation of symbols]

[0078] 1 System 11 Power electronics elements 2 Conductive Wire Bonds 101 Electrical insulator layer 102 Conductive layer 103 Solder layer 104 Semiconductor Die 105 Metallization Layer 201 Signal conditioning circuit 202 Signal conditioning circuit 203 RS Flip-Flop and Inverter O Trigger Peak I. First peak II. The Second Peak III. The Third Peak A waveform B waveform C waveform

Claims

1. A method for detecting mismatch between parallel power electronic elements (11) in a power electronic module (1), the method comprising the steps of: a. triggering a measurement period in response to said detecting a common turn-off of said elements (11); b. During the measurement period, the emitter voltage V of at least one of the elements ｅＥ measuring a sequence of c. extracting data from said measurements, said data comprising: ｅＥ and d. Inferring from the extracted data at least the presence or absence of mismatches between the elements; A method comprising:

2. The extracted data is The two emitter voltages V of the two elements ｅＥ１ and V ｅＥ２ or the sign of a local extremum of the sequence Emitter voltage V of one element ｅＥ the signs and the amplitudes of local extrema of a sequence of At least If the presence of a mismatch between the elements is suspected, the method further comprises: e. From the extracted data, the emitter voltage V ｅＥ Or V ｅＥ１ and V ｅＥ２ estimating whether the element for which the measured value is the most degraded; The method of claim 1 further comprising:

3. 3. The method of claim 1 or 2, wherein the extraction from the measurements is performed by analog logic circuitry, making the use of an analog-to-digital converter redundant.

4. The extracted data includes the emitter voltage V ｅＥ and further including the amplitudes of the local extrema of If the presence of a mismatch between the elements is suspected, the method further comprises: f. estimating a quantification of said mismatch from said extracted data; The method of any one of claims 1 to 3, further comprising:

5. The differential emitter voltage V of the pair of elements (11.1, 11.2) ｅｅ The method according to any one of claims 1 to 4, wherein:

6. The method according to any one of claims 1 to 5, implemented on a module (1) comprising at least three parallel power electronic elements (11), the measurements being performed in a sequential manner for each pair of elements (11) having a common monitoring circuit, a multiplexer being operatively interfaced between the monitoring circuit and the elements (11).

7. imposing an auxiliary external gate resistance during said measurement operation; The method of any one of claims 1 to 6, further comprising:

8. The estimation operation further includes identifying the most degraded element (11) of the at least two elements (11), and then: the sequence of operations being repeated at least one time, the at least one repetition including inducing a delay d of the turn-off of at least one of the elements relative to another element before triggering the measurement period. The method according to any one of claims 1 to 7.

9. The method according to any one of claims 1 to 8, wherein the sequence of operations is repeated at least once such that the detection mismatch is performed along the operational life of the module (1).

10. generating an alert signal in response to the estimated information; The method of any one of claims 1 to 9, further comprising:

11. A power electronics module (1), comprising at least two parallel power electronic elements (11), configured to implement the method according to any one of the claims 1 to 10.

12. Computer software comprising instructions for carrying out at least part of the method according to any one of claims 1 to 10, when said software is executed by a processor.

13. A non-transitory computer readable storage medium having software registered thereon for performing the method of any one of claims 1 to 10 when the software is executed by a processor.

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