METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Patent application

Abstract

The method includes providing a semiconductor body (1) having a mask (3) on a top surface of the semiconductor body, at least one trench (2) extending from the top surface into the semiconductor body. A functional portion (11) is formed laterally adjacent to the trench. In a first section (31) overlapping the trench, the mask is thicker than in a second section (32) overlapping the functional portion. A first region (12) of a first conductivity type is formed in the functional portion adjacent to the trench by implanting a dopant of the first type. A protective layer (4) is deposited on the mask, the protective layer extending laterally over the trench and the functional portion. A second region (13) of a second conductivity type is formed in the functional portion by implanting a dopant of the second type through the protective layer, thereby preserving a portion of the first region.

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and to a semiconductor device. [Background technology]

[0002] US 2010 / 155833 relates to a semiconductor device having a vertical MOSFET and a method for fabricating the same. CN 110581071 relates to a method for reducing the manufacturing cost of a trench DMOS. US 2020 / 066579 relates to a power semiconductor device having a reliable and verifiable p-contact. US 2009 / 246923 relates to a method for forming a shielded gate FET with self-aligned features. Summary of the Invention [Problem to be solved by the invention]

[0003] There is a need for improved methods for manufacturing semiconductor devices, for example methods that have a reduced number of process steps and / or that allow for the manufacture of small structures. Additionally, there is a need for improved semiconductor devices, for example semiconductor devices with small structures. [Means for solving the problem]

[0004] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to improved methods for manufacturing semiconductor devices, while other embodiments relate to improved semiconductor devices.

[0005] First, a method for manufacturing a semiconductor device is identified. According to one embodiment, a method for manufacturing a semiconductor device includes providing a semiconductor body having a mask on a top surface of the semiconductor body, at least one trench extending from the top surface into the semiconductor body. A functional portion of the semiconductor body is formed laterally adjacent to the trench. The mask is thicker in a first section overlapping the trench than in a second section overlapping the functional portion. In a further step, a first region of a first conductivity type is formed in the functional portion adjacent to the trench below the top surface. Forming the first region includes implanting a dopant of the first type into the functional portion through the top surface. In a further step, after forming the first region, a protective layer is deposited on the mask, the protective layer extending laterally over the trench and the functional portion. In yet a further step, a second region of a second conductivity type is formed in the functional portion below the top surface. Forming the second region includes implanting a dopant of the second type into the functional portion through the protective layer and through the top surface. This preserves at least a portion of the first region adjacent to the trench.

[0006] The semiconductor body may comprise or consist of Si or SiC. The top surface of the semiconductor body may extend parallel to a main extension plane of the semiconductor body. A lateral direction is defined herein as a direction parallel to the top surface of the semiconductor body and / or parallel to the main extension plane. A vertical direction is defined herein as a direction perpendicular to the top surface and / or the main extension plane of the semiconductor body.

[0007] At least one trench, i.e. one or more trenches, extends from the top surface into the semiconductor body. All features disclosed herein and below for one trench are also disclosed for all other trenches of the semiconductor device. For example, each trench may overlap with a first section of the mask.

[0008] For example, at least one trench has a depth, measured vertically, of at least 1 μm and at most 10 μm, or at least 2 μm and at most 6 μm. The maximum width of the trench, measured laterally, may be at most 2 μm or at most 1 μm. For example, the width of the trench is less than its depth. The trench may taper vertically from the top surface into the semiconductor body.

[0009] The functional portion is a part of the semiconductor body that is provided for an electrical function of the final semiconductor device. For example, during operation of the semiconductor device, electrons or holes are transported, for example vertically, through the functional portion. The functional portion is laterally adjacent to the trench. This means that the functional portion is located immediately next to the trench in the lateral direction. Thus, the side of the trench is at least partially formed by the functional portion. The functional portion may form part of the top surface or may extend starting from the top surface into the semiconductor body.

[0010] The mask may be formed of a semiconductor material and / or an insulating material. For example, the mask comprises or consists of Si or SiO2. The first section of the mask overlaps the trench. This means that, in a plan view of the top surface, the first section partially or completely covers the trench. For example, the first section of the mask only partially covers the trench such that a part of the trench adjacent to the functional portion protrudes laterally beyond the first section of the mask towards the functional portion. In other words, a step between the first and second sections of the mask may be formed in the area of ​​the trench, i.e. the step may overlap the trench. The mask may suspend or bridge the trench.

[0011] The second section of the mask overlaps the functional portion, for example at least partially covering the functional portion in a plan view of the top surface. For example, the second section completely overlaps the functional portion. The second section of the mask is thinner than the first section of the mask. For example, the first section is at least twice or at least three times or at least five times thicker than the second section. In the first section of the mask, the thickness may be at most 2 μm and / or at least 0.5 μm. In the second section of the mask, the thickness may be zero such that the top surface of the semiconductor body is exposed in the second section. Thus, the second section of the mask may be a hole or a recess in the mask. The thickness of the mask is measured in the vertical direction here. Everything above the top surface during the implantation of the first type of dopant may be considered to be part of the mask.

[0012] In forming the first region of the first conductivity type, the first region may be formed immediately below, i.e. adjacent to, the top surface. To form the first region, a dopant of the first type may first be implanted, thereby accumulating at the top surface. A driving process or an annealing process, respectively, may then be performed in which the dopant of the first type drifts further into the semiconductor body, causing the first region to expand.

[0013] The first conductivity type may be either electron-conducting or hole-conducting, i.e., the first region may be either n-doped or p-doped. Thus, the first type of dopant is an n-type dopant or a p-type dopant. The second conductivity type is the opposite conductivity type of the first conductivity type, i.e., either hole-conducting or electron-conducting. Thus, the second type of dopant is a p-type dopant or an n-type dopant. The first type of dopant is, for example, As or P. The second type of dopant is, for example, boron (B).

[0014] The protective layer may include or consist of an electrically insulating material such as SiO2. The protective layer may be deposited, for example, by sputtering or chemical vapor deposition. For example, the protective layer is deposited as a continuous layer without interruption. The protective layer may be conformally deposited on the mask so as to conformally cover the first section, the second section, and the step between them. In a plan view of the top surface, the protective layer may completely cover the trench and / or the feature. For example, the protective layer is deposited with a constant layer thickness. For example, the protective layer has a layer thickness of 50 nm to 200 nm, for example 80 nm to 150 nm.

[0015] In forming the second region of the second conductivity type, the second region may be formed directly below the top surface, i.e. adjacent to the top surface. Again, to form the second region, the second type dopant may first be implanted and accumulate at the surface of the semiconductor body, and then the second type dopant may drift further into the semiconductor body by applying a driving process or an annealing process, respectively. This may cause the second region to expand. The second type dopant may be, for example, boron.

[0016] In forming the second region, the second type of dopant must pass through the protective layer, in contrast to the first type of dopant. In regions where the second type of dopant has a longer travel path through the protective layer and, if applicable, the mask, the effective implantation intensity of the second type of dopant reaching the top surface is reduced compared to regions of the top surface where the travel path through the protective layer and / or mask is shorter. The length of the travel path through the protective layer is also determined by the profile of the mask. For example, when using a directional implantation method where the implantation direction is perpendicular to the top surface, the effective implantation intensity is reduced in the region overlapping the first section of the mask and in the region overlapping the second section of the mask close to the step, by at least the thickness of the protective layer, compared to the region overlapping the second section of the mask away from the step. The difference in the travel path is determined by the height of the step. The width of the region of the top surface overlapping the second section and having a reduced effective implantation intensity is determined primarily by the thickness of the protective layer.

[0017] Thus, by controlling the layer thickness and step height of the protective layer, it is possible to control which areas of the top surface overlapping the second section are exposed to a reduced effective implantation intensity. On the other hand, by controlling which areas are exposed to a reduced effective implantation energy, it is possible to control the area in which the first region is preserved, i.e., not converted to a second region. In other words, the thickness of the protective layer and the implantation process may be such that in the area where the second region is formed, sufficient second-type dopant reaches through the protective layer to form the second region, while at the same time, the protective layer is sufficient to prevent the second-type dopant from passing through the protective layer in the area where the first region is preserved. For example, in the area where the second region is formed, the protective layer is thinner than in the area where the first region is preserved.

[0018] Thus, the method described herein requires at most one lithography step to form a mask. With the help of this mask, two regions of different conductivity types can be formed laterally adjacent to each other with well-defined positions and sizes. Before depositing the protective layer, the mask is used to form a first region adjacent to the trench. The deposition of the protective layer then effectively forms a self-aligned mask with which a second region can be formed such that at least a portion of the first region adjacent to the trench is preserved. The width of the preserved portion of the first region can be controlled, for example, mainly by the layer thickness of the protective layer. Thus, the method allows to reduce the amount of lithography steps and allows to form doped regions with very small feature sizes.

[0019] According to a further embodiment, at least two trenches extend from the top surface into the semiconductor body. The two trenches are laterally spaced apart from each other. The functional portion is laterally disposed between the two trenches. For example, the functional portion is adjacent to each of these two trenches. For example, the two trenches are adjacent trenches, i.e. there is no further trench laterally between them. The functional portion disposed between the two trenches is also referred to herein as a channel portion or a mesa. The layer thickness of the protective layer is, for example, at most a maximum width of the functional portion, for example at most half or at most 1 / 3 or at most 1 / 4 of the maximum width.

[0020] According to a further embodiment, each trench overlaps a respective first section of the mask. Each trench may be assigned a first section of the mask in a one-to-one manner. The first sections assigned to a trench may each be formed as described above. All first sections may have the same thickness.

[0021] According to a further embodiment, the first section of the mask is laterally offset with respect to the feature, in other words the first section does not overlap with the feature.

[0022] According to a further embodiment, a directional implantation method is used to implant the first type of dopant. For example, first, implantation is performed with a tilt angle α greater than 0° (first implantation step). Then, implantation may be performed with a tilt angle α smaller than 0° (second implantation step). In other words, when switching from the first implantation step to the second implantation step, the component of the implantation direction parallel to the top surface is reversed. For example, the magnitude of the tilt angle is equal in the first implantation step and the second implantation step. For example, the implantation direction is mirrored from the first implantation step to the second implantation step. The mirror plane may be a plane that extends perpendicular to the top surface and parallel to the trench.

[0023] The tilt angle α of the implant is defined herein as the angle between the main implant direction and the normal to the top surface, for example, in the first implant step the tilt angle α is greater than 10° and in the second implant step the tilt angle α is less than −10°.

[0024] Additionally or alternatively, the tilt angle α of the implant is selected such that certain areas of the feature are exposed to the full dose of the implant while other areas are shielded by the first section of the mask and therefore exposed to a lower implant dose.

[0025] Thus, as a result of the angled implantation, certain regions of the functional part are shielded by the first section of the mask. For example, by using the two-step angled implantation process described above, the central region of the functional part, located in the center between the two trenches, is doped less with the first type of dopant than the edge regions closer to the two trenches. In other words, the doping profile of the first region before the second region is formed is such that the doping concentration in the center between the two trenches is smaller than near the trenches. This doping profile is preserved even after, for example, a drive process in which the dopants drift.

[0026] A central region of the functional portion, having a lower doping concentration, can be converted to a second region of the opposite conductivity type more easily than an edge region of the functional portion. For example, when forming the second region, a previously continuous first region of a first conductivity type extending from one trench to the other is converted at its center to a second region of a second conductivity type, leaving only the edge regions of the first region. Thus, effectively, the initially continuous first region is divided into two first regions, each adjacent a trench. Each of these first regions may itself be continuous.

[0027] According to a further embodiment, the inclination angle α is selected to have an absolute value of |atan((D+W) / H)|±10° or ±5°, i.e. a maximum deviation of 10° or 5°. Here, H is the thickness of the mask in the first section, W is the width of the functional part at the top surface measured in the lateral direction, i.e. the lateral distance between the two trenches, and D is the lateral distance between the first section of the mask and the functional part. In other words, D is the distance between the step of the mask and the side of the trench formed by the functional part. If the step recedes from the side of the trench in the direction towards the trench, D is positive, otherwise D is negative. Here, D is defined, for example, as the shortest distance between the first section of the mask and the functional part.

[0028] Such a tilt angle α allows the highest implantation intensity of the first type dopant reaching the feature to be adjusted to be in the region close to the trench, while the remainder of the feature, especially the central region of the feature, is blocked by the first section of the trench.

[0029] According to a further embodiment, a directional implantation method is used to implant the second type of dopant. For example, the main implantation direction is selected perpendicular to the top surface, in other words the tilt angle is 0°. As already explained, at such a tilt angle α the second type of dopant has a longer migration path through the protective layer in the region close to the step, so that in this region the second type of dopant reaches the semiconductor body less than, for example, in the center of the functional part. In this way the first region can be preserved at least near the trench.

[0030] According to a further embodiment, the layer thickness d of the protective layer is greater than the distance D between the first section of the mask and the functional part. For example, the difference dD is at least 50 nm or at least 100 nm. For example, if the mask step recedes towards the trench, i.e. the first section protrudes laterally beyond the functional part and partially overlaps the trench, a protective layer having a layer thickness d>D is useful to sufficiently protect the first region adjacent to the trench from being completely converted into the second region.

[0031] According to a further embodiment, after providing the semiconductor body with the mask, and before forming the first region, a third region of the second conductivity type is formed in the semiconductor body, in particular in the functional part. Forming the third region comprises implanting a second type dopant into the semiconductor body through the top surface. The second type dopant for forming the third region may be the same material as for forming the second region, e.g. B. Here too, after implantation, a drive process or an annealing process, respectively, may be performed. The implantation of the second type dopant for forming the third region may be performed before and / or after forming a trench in the semiconductor body. The implantation of the second type dopant for forming the third region may be performed before and / or after forming a mask on the semiconductor body.

[0032] At least in the functional portion, a third region may be formed immediately below, i.e. adjacent to, the top surface. A portion of the third region may later be converted to the first region.

[0033] According to a further embodiment, after forming the second region, a main electrode is applied on the top surface to electrically contact the semiconductor body in the region of the functional part. Before applying the main electrode and after forming the second region, an etching process may be performed to remove the protective layer at least in the region of the functional part and to expose the top surface. During this etching process, parts of the mask may be removed. However, residual structures of the mask may be preserved and may form part of the final semiconductor device, especially in the region of the trench formed by the first section, where the mask has a greater thickness.

[0034] The master electrode may be applied in direct electrical contact with the first region and / or the second region. The master electrode may be formed from a metal.

[0035] According to a further embodiment, the trench is filled with an electrically conductive material. The electrically conductive material may be electrically isolated from the semiconductor body by an insulating layer applied to the surface of the trench. In order to electrically isolate the functional part from the conductive material, in particular the side surfaces of the trench that laterally define the trench may be covered with an insulating layer. The conductive material is, for example, highly doped polysilicon, such as n-type polysilicon. The insulating layer may be formed from SiO2.

[0036] When providing the semiconductor body, i.e. before implanting the first type of dopant, the trench may already be filled with an electrically conductive material and / or an insulating layer.

[0037] Alternatively, the trenches may be filled with an electrical isolation material at least before the mask is applied, or may not be filled at all.

[0038] According to a further embodiment, the semiconductor device is an insulated gate transistor. For example, the semiconductor device is a MOSFET or an insulated gate bipolar transistor (IGBT). In that case, the main electrode may be a source electrode or an emitter electrode, respectively. The first region may be a source region or an emitter region of the semiconductor body. A further main electrode may be applied to a lower surface opposite to the upper surface of the semiconductor body, which may constitute a drain electrode or a collector electrode, respectively.

[0039] According to a further embodiment, the trench is part of an insulated gate. For example, the electrically conductive material in the trench is electrically connected to a gate electrode. The gate electrode may be applied on the top surface. Insulation between the gate electrode and the semiconductor material of the functional portion may be achieved by an insulating layer in the trench.

[0040] According to a further embodiment, in providing the semiconductor body, the functional portion is of the second conductivity type at least directly below, i.e. adjacent to, the top surface, e.g., an implantation process with a dopant of the second type has been previously performed to render this portion of the functional portion of the second conductivity type.

[0041] According to a further embodiment, the semiconductor body comprises at least one further functional part laterally disposed between the two trenches. The further functional part may also be referred to herein as a dummy functional part or a dummy channel part or a dummy mesa. The further functional part is, for example, spaced apart from the functional part by at least one trench. For example, the functional part and the further functional part are laterally separated from each other by exactly one trench.

[0042] "Dummy functional portion" does not necessarily mean that the functional portion has no function in the final device. Rather, it may mean that the function is different from the functional portions defined above.

[0043] According to a further embodiment, the maximum width of the further functional part is different from the maximum width of the functional part. For example, the further functional part has a smaller maximum width than the functional part. As an example, the maximum width of the further functional part is at most 80% or at most 60% of the maximum width of the functional part.

[0044] According to a further embodiment, implanting the first type of dopant is performed at a tilt angle α such that the further feature is completely blocked by the first section of the mask. In other words, the further feature, i.e. the top surface formed by the further feature, is completely in the shadow of the first section. This first section of the mask may overlap the trench adjacent to the further feature. For example, when performing a two-step tilted implantation process, in each of these implantation steps the further feature is completely blocked by the first section of the mask. In that case, in one implantation step the further feature is blocked by the first section on the trench to the left of the further feature and in the other implantation step the further feature is blocked by the first section on the trench to the right of the further feature.

[0045] The fact that the further functional part is completely blocked by the first section of the mask does not mean that the first type of dopant does not reach the further functional part, since some of the first type of dopant may, for example, pass through the first section of the mask or may be implanted due to the random nature of the implantation process. Rather, "completely blocked" means that each straight line that makes an angle α with the normal to the top surface and passes through the top surface in the area of ​​the further functional part passes at least partially through the first section of the mask. As a result of this, the conductivity type of the further functional part at the top surface, for example, does not change during the implantation of the first type of dopant. Thus, in the final device, the further functional part may not include any area of ​​the first conductivity type at the top surface. That is, after the fabrication process, the top surface of the further functional part may be entirely of the second conductivity type.

[0046] Next, a semiconductor device is identified. The semiconductor device may be manufactured by the method specifically specified herein. Thus, all features disclosed for the method are also disclosed for the semiconductor device and vice versa.

[0047] According to one embodiment, a semiconductor device comprises a semiconductor body having a top surface and at least one trench extending from the top surface into the semiconductor body. A functional portion of the semiconductor body is disposed laterally adjacent the trench. A first region of the functional portion at the top surface is of a first conductivity type and is adjacent to the trench. A second region of the functional portion at the top surface is of a second conductivity type. The first region is disposed laterally between the trench and the second portion and is adjacent to the second portion.

[0048] According to a further embodiment, a structure is disposed on the top surface and overlaps the trench. The structure may be a residual structure of a mask and / or a residual structure. This indicates that the method specified herein has been used to fabricate a semiconductor device.

[0049] There may be a plurality of such structures distributed over the top surface. For example, such structures are disposed in some or each trench. All such structures may have the same thickness within the limits of fabrication tolerances. The structures may not include any features in a semiconductor device. For example, the structures include traces of material removal such as an etching process. The structures may include or consist of semiconductor materials such as Si or SiC, or insulators such as SiO2. The structures may be residual structures.

[0050] For example, the structure tapers away from the top surface. The width of the structure in the region vertically furthest from the top surface is at most 75%, or at most 50%, or at most 10% of the width in the region vertically closest to the top surface. The width is measured in the lateral direction.

[0051] According to a further embodiment, the functional portion is laterally disposed between two trenches. A first region may be formed adjacent each of the trenches. The first regions may be laterally spaced apart from one another by second regions. Each first region may be contiguous with itself.

[0052] According to further embodiments, the width of the feature measured laterally is at most 1.5 μm, or at most 1.2 μm, or at most 1 μm, or at most 0.8 μm. The width of the first region between the second region and the trench may be at most 300 nm, or at most 200 nm, or at most 100 nm. For example, the ratio of the depth of the trench to the width of the feature is at least 3:1.

[0053] Such narrow features (narrow mesas) having a first region of a first conductivity type and a second region of a second conductivity type can be fabricated using the fabrication method described herein. Indeed, the width of the features can be chosen to be very small, especially due to the reduction in masking and related alignment steps. In this way, alignment requirements are kept to a minimum for a given lithography technique. The reduction of the feature width lowers the on-state losses due to the increase in plasma density. Thanks to the fine pattern fabrication of the first and second regions achieved with the method described herein, it is possible to reduce the width of the features to, for example, 0.8 um or less.

[0054] According to a further embodiment, the structure is a Si structure, i.e. consists of Si. According to a further embodiment, the trench is filled with an electrically conductive material that is electrically isolated from the semiconductor body by an insulating layer applied to the surfaces of the trench.

[0055] According to a further embodiment, a main electrode is on the top surface and in electrical contact with the functional part, in particular with the first and / or second regions of the functional part.

[0056] According to a further embodiment, a gate electrode is disposed on the top surface and in electrical contact with the electrically conductive material in the trench. A further main electrode may be disposed on a bottom surface opposite to the top surface of the semiconductor body and in electrical contact with the semiconductor body.

[0057] Hereinafter, a method for manufacturing a semiconductor device and a semiconductor device will be described in more detail based on an exemplary embodiment with reference to the drawings. The attached drawings are included to provide further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. Insofar as elements or components correspond to each other in terms of their functions in different drawings, the description thereof will not be repeated for each of the following drawings. For clarity, elements may not be labeled with corresponding reference numerals in all drawings. [Brief description of the drawings]

[0058] [Figure 1] 1 is a flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device. [Diagram 2] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Diagram 3] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 4] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Diagram 5] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 6] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 7] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 8]1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 9] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 10] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 11] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 12] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 13] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 14] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 15] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 16] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 17] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 18] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 19] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 20] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 21] 1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 22] FIG. 1 illustrates an exemplary embodiment of a semiconductor device. [Figure 23]1A-1D illustrate different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 24] FIG. 1 illustrates an exemplary embodiment of a semiconductor device. [Diagram 25] 5A-5C illustrate positions in a further exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 26] FIG. 1 illustrates a further exemplary embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] FIG. 1 shows a flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device. In step S1, a semiconductor body is provided having a mask on its top surface. At least one trench extends from the top surface into the semiconductor body, and a functional portion of the semiconductor body is formed laterally adjacent to the trench. The mask is thicker in a first section overlapping the trench than in a second section overlapping the functional portion. In step S2, a first region of a first conductivity type is formed in the functional portion adjacent to the trench on the top surface. Forming the first region includes implanting a first type of dopant into the functional portion through the top surface. In step S3, a protective layer is deposited on the mask. The protective layer extends laterally over the trench and the functional portion. In step S4, a second region of a second conductivity type is formed below the top surface. Forming the second region includes implanting a second type of dopant into the functional portion through the protective layer and through the top surface. This preserves at least a portion of the first region adjacent to the trench.

[0060] The semiconductor body 1 is provided in the position of the exemplary embodiment of the method shown in Fig. 2. The semiconductor body 1 has a top surface 10 parallel to the main extension plane of the semiconductor body 1. For example, the semiconductor body 1 consists of Si or SiC. The semiconductor body 1 may be lightly doped to be of a first conductivity type. In the following, by way of example, it is assumed that the first conductivity type is electronic conduction, the corresponding doping being n-type doping. For this reason, the semiconductor body 1 is lightly n-doped. On the top surface 10, a mask 7, for example of photoresist, is formed. The structure of the mask 7 is generated, for example, with the aid of photolithography.

[0061] In the position of Figure 3, an implantation process has been performed in which a second type dopant in the form of a p-type dopant, for example boron, is implanted into semiconductor body 1 through top surface 10. The second type dopant accumulates in the region immediately below top surface 10 to form a p-doped region 14 (referred to herein as third region 14). In Figure 3, the doping concentration in third region 14 is, for example, about 1·10 19 cm -3 The third regions 14 are formed primarily or only in the regions not covered by the mask 7.

[0062] Figure 4 shows the position after a drive or anneal process, respectively, has been performed, which causes the second type dopant to drift further into the semiconductor body 1. The p-doped third region 14 has thereby expanded into the semiconductor body 1 such that two laterally spaced p-wells are formed. In Figure 4, the doping profile of the third region 14 is shown with the help of two sections 14a, 14b with different doping concentrations. Section 14a has a higher doping concentration than section 14b. For example, section 14a has a doping concentration of about 8.3·10 16 cm -3 ~about 1.7·10 18 cm -3 and section 14b has a doping concentration of about 2.1·10 14 cm -3 ~about 8.3·10 16 cm-3 In practice, the doping concentration may increase gradually from the bottom of section 14b to the top of section 14a.

[0063] The fourth region 15 of the semiconductor body 1 remains n-doped, i.e., during the actuation process, this originally n-doped region of the semiconductor body 1 is not converted into a p-doped region. For example, the doping concentration of the fourth region 15 is about 1·10 13 cm -3 It is.

[0064] 5 shows the position in the way in which a number of trenches 2 are introduced into the semiconductor body 1. Each trench 2 extends from the top surface 10 into the semiconductor body 1, thereby tapering in a direction from the top surface 10 towards the inside of the semiconductor body 1. The surface of the trenches 2 is covered with an electrically insulating layer 21 which also covers the top surface 10 of the semiconductor body 1. The insulating layer 21 is formed, for example, from SiO2. Furthermore, the trenches 2 are filled with an electrically conductive material 20, for example highly doped polysilicon.

[0065] A functional portion 11, 11a, also called a channel portion or a mesa, is formed laterally between each pair of trenches 2. In this specification, the functional portion 11 between two inner trenches 2 is called functional portion 11, and the functional portions 11a to the left and right of the functional portion 11 are called further functional portions 11a or dummy functional portions 11a, respectively. The maximum width of the functional portion 11 is greater than the maximum width of the dummy functional portions 11a (see also FIG. 23, which shows the semiconductor body 1 in a plan view on the top surface 10).

[0066] In Fig. 6, an auxiliary mask 30, for example of photoresist, is formed on the upper surface 10 of the semiconductor body 1. The structuring of the auxiliary mask 30 is performed, for example, with the aid of a photolithography process. The structuring is performed in such a way that in the areas overlapping the functional parts 11, 11a, the photoresist 30 is completely removed so that the insulating layer 21 is exposed. In the areas overlapping the trenches 2, the photoresist 30 is not completely removed.

[0067] 7 shows the position where the etching process has been performed. In this etching process, the insulating layer 21 in the areas overlapping the functional parts 11, 11a is etched more than in the areas protected by the photoresist 30. In this way, a mask 3 of the material of the insulating layer 21 is formed. The mask 3 comprises a first section 31 overlapping the trench 2 and a second section 32 overlapping the functional parts 11, 11a. In the first section 31, the mask 3 is thicker than in the second section 32.

[0068] 11 and 12 show detailed views of the functional parts 11, 11a. Here, it can be seen that the step between the first section 31 and the second section 32 is set back relative to the side of the trench 2 in the direction towards the trench 2. The second section 32 therefore extends over the entire functional parts 11, 11a and partially overlaps the trench 2.

[0069] In the position shown in Fig. 8, a second type dopant is again implanted through the top surface 10 of the semiconductor body 1 into the functional parts 11, 11a. The second type dopant may again be a p-type dopant, for example boron. The p-doping concentration below the top surface 10 increases in the region of the functional parts 11, 11a. The implantation is performed in a directional implantation manner with a main implantation direction perpendicular to the top surface.

[0070] 9 shows the position after the drive process where the second type dopant has drifted further into the semiconductor body such that the doping profile of the p-doped third region 14 has changed. Here, the doping profile is shown using three sections 14a, 14b, 14c. The doping concentration is greatest in the third section 14c. The doping profile actually changes gradually from the first section 14a to the third section 14c.

[0071] In the position of FIG. 10, a process step is shown in which a first type dopant is implanted through the top surface 10 into the functional portions 11, 11a. The first type dopant is in this case an n-type dopant, for example As or P. To implant the first type dopant, a directional implantation method is used, with the magnitude of the tilt angle α being greater than 0, for example greater than 45°. Due to this tilted implantation, the area of ​​the functional portions 11, 11a is blocked by the first section 31 of the mask 3. This is further shown in FIG. 11 and FIG. 12, where the functional portions 11 and the dummy functional portions 11a are shown in more detail.

[0072] 11, the tilt angle α of the implant is selected to be about |atan((D+W) / H)|, for example |atan((D+W) / H)|±10°, where H is the thickness of the mask 3 at the first section 31, W is the width of the feature 11 at the top surface 10 measured laterally, and D is the lateral distance between the first section 31 of the mask 3 and the feature 11. This tilt angle α ensures that most of the area of ​​the feature 11 is blocked by the first section 31 of the mask 3, and only a small area adjacent to the trench 2 is unblocked.

[0073] 12 the dummy features 11a are shown in more detail. Due to the small width of the dummy features 11a compared to the features 11, the entire area of ​​the dummy features 11a is obscured by the first section 31 of the mask 3.

[0074] 10 and 11, the angled implantation results in the formation of an n-doped first region 12 adjacent to the trench 2. In the remainder of the functional portion 11, the blocking by the first section 31 is so efficient that no doping conversion occurs, i.e., this remainder remains p-doped. The dummy functional portion 11a also does not undergo any conversion, and remains p-doped at the top surface 10.

[0075] 13 and 14 show a further step of implantation of the first type dopant, where the tilt angle α is reversed (the implantation direction is mirrored). Here again only a small area of ​​the functional part 11 adjacent to the trench 2 is converted into an n-type first region 12. The rest is effectively blocked by the first section 31 of the mask 3.

[0076] Figures 15 and 16 show the position after the drive process has been performed, where the first type dopant has drifted further into the semiconductor body 1, resulting in the n-doped first regions 12 expanding and merging with each other to form one continuous first region 12. In Figures 15 and 16, the entire area of ​​the functional portion 11 directly below the top surface 10 is formed by the n-doped first regions 12, except that the doping concentration and extent of the first regions 12 adjacent to the trenches 2 is greater than in the middle between the trenches 2. The first regions 12 have a central cutout.

[0077] 17 shows the position in the way in which a protective layer 4 is conformally deposited on the upper surface 10, such that the first section 31 and the second section 32 of the mask 3 are covered by the protective layer 4. The protective layer 4 is, for example, SiO2. The protective layer 4 extends continuously over the trench 2 and the functional parts 11, 11a. The protective layer 4 has a layer thickness selected such that a groove 40 is formed in the region of the channel part. The thickness of the protective layer 4 is, for example, at most the width of the functional part 11. In the area of ​​the groove, the protective layer 4 has approximately the same thickness as in the region of the trench 2.

[0078] 17 shows that an implantation process is performed in which a second type of dopant, here in the form of a p-type dopant, is implanted through the protective layer 4 through the top surface 10 into the semiconductor body 1. Here too, a directional implantation method is used with an implantation angle of 0°, i.e. the main implantation direction is perpendicular to the top surface 10.

[0079] As can be seen in FIG. 17, which shows the functional part 11 in FIG. 18 in more detail, the migration path through the protective layer 4 close to the trench 2 is greater than in the center of the functional part 11. This is a result of the conformal deposition of the protective layer 4. The implantation intensity of the second type dopant is therefore greater in the central region of the functional part 11 than in the region adjacent to the trench 2. Due to the layer thickness d of the protective layer 4 being greater than D, the first region 12 adjacent to the trench is efficiently shielded by the protective layer 4 against the second type dopant, thereby protecting this part of the first region 12 from being converted into a p-doped region.

[0080] This result is shown in the locations of Figures 19 and 20, where the implantation of the second type dopant has resulted in the formation of a p-type second region 13 in the center of the functional portion 11, dividing the first region 12 into two first regions 12. Thus, adjacent to the trenches 2, a portion of the first region 12 is preserved, since the amount of the second type dopant was not sufficient to completely convert the n-type first region 12 into a p-type region in these areas.

[0081] Figure 21 shows a further position in the method after the protective layer 4 has been etched away to expose the functional parts 11, 11a. Furthermore, a first main electrode 5, for example made of metal, is deposited on the functional part 11, whereby the first main electrode 5 is in electrical contact with the first region 12 and the second region 13 of the functional part 11. In figure 21 it can further be seen that remnants of structures, i.e. mask 3, have been preserved in the area of ​​the trenches 2. These remaining structures will remain in the final semiconductor device.

[0082] Differently from what is shown in FIG. 21, the main electrode 5 may also contact the semiconductor body 1 in at least some areas of the dummy portion 11a.

[0083] Figure 22 shows an exemplary embodiment of a semiconductor device 100 manufactured by the above-mentioned method. A second main electrode 8 is deposited on the bottom surface opposite to the top surface 10 of the semiconductor body 1. The second main electrode 8 is in direct electrical contact with a p-type fifth region 16 (collector layer or drain layer or anode layer) of the semiconductor body 1. The semiconductor device 100 shown in Figure 22 is an IGBT.

[0084] FIG. 24 shows the semiconductor device 100 of FIG. 22 in a plan view of the top surface 10 of the semiconductor body 1. As can be seen, the functional parts 11 comprise different parts having larger and smaller widths, interleaved with each other. The sections of smaller width are so narrow that in these sections the n-type first regions 12 are not formed or preserved. In these sections the gate electrodes 6 are applied, electrically connected to the electrically conductive material 20 in the trenches 2. The dashed lines in FIG. 24 show a cross section relative to the representation in FIG. 22. The maximum width of the functional parts 11 is, for example, 1.5 μm.

[0085] It should be emphasized that the configuration of Fig. 24 is in fact only an example. In further exemplary embodiments, the interleaving of the gate electrode 6 and the first main electrode 5 may be omitted, and instead the first main electrode 5 may be applied all over the mask 3 and directly contact the functional parts 11, 11a wherever the insulating layer 3 is etched. The gate electrode 6 may then be in direct contact with the conductive material 20 in the trench 2 only at both ends of the "vertical stripes" formed by the functional parts 11, 11a.

[0086] In Fig. 23, a top surface of the semiconductor body 1 is shown before the first type of dopant is implanted. As can be seen, the mask 3 comprises a first section 31 and a second section 32, the second section 32 overlapping the functional portion 11 having alternating widths.

[0087] Figure 25 shows positions in a second exemplary embodiment of the method. The positions shown correspond to those shown in Figure 7. In contrast to Figure 7, the mask 3 is now partially made of silicon. An insulating layer 21 of SiO2 is arranged between the silicon (dashed area) and the semiconductor body 1 and covers the top surface 10.

[0088] 26 shows the final semiconductor device 100 with the remaining structure of the mask 3 which includes or consists of Si. Due to the mask 3 being at least partially Si, the etching process can be performed more precisely to expose the features 11, 11a due to the different selectivities of Si and SiO2.

[0089] 1-26 represent exemplary embodiments of the improved method and improved semiconductor device, and therefore, they do not constitute an exhaustive list of all embodiments of the improved method and improved semiconductor device. Actual semiconductor devices and methods may differ from the embodiments shown, for example, with respect to their layout.

[0090] Reference sign [Explanation of symbols]

[0091] 1. Semiconductor body 2. Trench 3. Mask 4 protective layer 5 First main electrode 6 Gate electrode 7. Mask 8 Second main electrode 10 Top side 11 Functional parts 11a Further functional parts 12 The First Area 13 The Second Area 14 The Third Region 14a Third Area Section 14b Third Area Section 14c Third Area Section 15 The Fourth Region 16 The Fifth Region 20 Electrically Conductive Materials 21 Insulating layer 30 Auxiliary Mask 31 Mask 3, 1st Section 32 Mask 3, second section 40 grooves 100 Semiconductor Devices H Thickness W width D Distance d layer thickness α Tilt angle S1~S4 Method steps

Claims

1. A method for manufacturing a semiconductor device (100) that is an insulated gate transistor, comprising: Providing a semiconductor body (1) having a mask (3) on a top surface (10) of said semiconductor body (1), at least one trench (2) extends from said top surface (10) into said semiconductor body (1), said trench (2) being filled with an electrically conductive material (20) electrically isolated from said semiconductor body (1) by an insulating layer (21) applied to a surface of said trench (2), said trench (2) being part of said insulated gate; A functional portion (11) of the semiconductor body (1) is formed laterally adjacent to the trench (2), providing that in a first section (31) overlapping the trench (2), the mask (3) is thicker than in a second section (32) overlapping the functional portion (11); forming a first region (12) of a first conductivity type in the functional portion (11) below the top surface (10) and adjacent to the trench (2), the forming of the first region (12) comprising implanting a dopant of the first type into the functional portion (11) through the top surface (10); Including, depositing a protective layer (4) on the mask (3) after forming the first region (12), the protective layer (4) extending laterally over the trench (2) and the functional portion (11); forming a second region (13) of a second conductivity type in the functional portion (11) below the top surface (10), forming the second region (13) comprises implanting a second type of dopant into the functional portion (11) through the protective layer (4) and through the top surface (10); forming a trench (2) adjacent to the first region (12), wherein at least a portion of the first region (12) is preserved; A method comprising:

2. At least two trenches (2) laterally spaced apart from one another extend from the top surface (10) into the semiconductor body (1); The functional part (11) is arranged laterally between the two trenches (2), Each trench (2) overlaps a respective first section (31) of the mask (3); To implant the first type of dopant, 2. The method of claim 1, wherein a directional implantation method is used, first the implantation is performed at a tilt angle α greater than 0°, and then the implantation is performed at a tilt angle α smaller than 0°, so that the doping concentration of the first type dopant in the functional part (11) is greater near the trenches (2) than in the center between the trenches (2).

3. the first section (31) of the mask (3) is laterally offset with respect to the functional portion (11); the tilt angle α is selected to have an absolute value of |atan((D+W) / H)|±10°; H is the thickness of the mask (3) in the first section (31), W is the width of the functional part (11) on the upper surface (10) measured laterally; 3. The method according to claim 2, wherein D is the lateral distance between the first section (31) of the mask (3) and the functional part (11).

4. To implant the second type of dopant, A directional injection method is used, 10. The method according to any one of the preceding claims, wherein the main injection direction is perpendicular to the upper surface (10).

5. 10. The method according to claim 1, wherein a layer thickness d of the protective layer (4) is greater than a distance D, measured laterally, between the first section (31) of the mask (3) and the functional part (11).

6. 10. The method of claim 1, wherein after providing the semiconductor body (1) with the mask (3), and before forming the first region (12), a third region (14) of the second conductivity type is formed in the functional portion (12) below the top surface (10), and forming the third region (14) comprises implanting a dopant of the second type into the semiconductor body (1) through the top surface (10).

7. 10. The method according to any one of the preceding claims, wherein after forming the second region (13), a main electrode (5) is applied on the top face (10) for electrically contacting the semiconductor body (1) in the region of the functional part (11).

8. the semiconductor body (1) comprises at least one further functional part (11a) arranged laterally between two trenches (2) and spaced apart from the functional part (11) by at least one trench (2), 10. The method according to any one of the preceding claims, wherein the maximum width of the further functional part (11a) is smaller than the maximum width of the functional part (11).

9. 9. The method according to claim 8, wherein the implantation of the first type of dopant is performed at a tilt angle α such that the further feature (11a) is completely blocked by a first section (31) of the mask (31).

10. a semiconductor body (1) having a top surface (10); At least one trench (2) extending from said top surface (10) into said semiconductor body (1), a functional portion (11) of the semiconductor body (1) arranged laterally adjacent to the trench (2); a first region (12) of the functional portion (11) on the top surface (10) is of a first conductivity type and is adjacent to the trench (2); a second region (13) of the functional portion (11) on the upper surface (10) is of a second conductivity type; the first region (12) is laterally disposed between the trench (2) and the second portion (13) and adjacent to the second portion (13); The trench (2) is filled with an electrically conductive material (20) electrically isolated from the semiconductor body (1) by an insulating layer (21) applied to the surface of the trench (2); An insulated gate transistor (100) comprising: An insulated gate transistor (100), characterized in that a structure of semiconductor material having evidence of material removal is on said top surface (10) and overlaps said trench (2).

11. The functional part (11) is arranged laterally between two trenches (2), 11. The insulated gate transistor (100) of claim 10, wherein the maximum width of the functional portion (11), measured laterally, is at most 1.5 μm.

12. The insulated gate transistor (100) of claim 10 or 11, wherein the structure is a Si structure.

13. A main electrode (5) on the top surface (11) is in electrical contact with the functional part (11); The insulated gate transistor (100) of any one of claims 10 to 11, wherein the gate electrode (6) on the top surface (12) is in electrical contact with the electrically conductive material (20) in the trench (2).

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