Data processing method and data processing device

Abstract

The embodiment of the present application discloses a data processing method and a data processing device. The method in the embodiment of the present application includes the following steps: separately performing convolutional interleaving on n lane data streams to obtain n first data streams, where n>1, and a first FEC encoding is performed on all of the n lane data streams. All a codewords obtained by the first FEC encoding are distributed into b lane data streams, where a≦b≦n and a≧1. Each z consecutive symbols of the first data stream are from z different codewords, where z>1. Then, all K first data streams of the n first data streams are multiplexed to obtain one second data stream, and a total of m second data streams are obtained. The n first data streams include G first data stream subsets, and the symbols in different first data stream subsets are from different codewords, where m=n / K, K>1, and G>1. The y consecutive symbols in each second data stream are from y different codewords, where y>z.

Description

[Technical Field]

[0001] This application is a continuation of Chinese Patent Application No. 202210109956.X, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on January 28, 2022; Chinese Patent Application No. 202210290887.7, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on March 23, 2022; Chinese Patent Application No. 202211065772.4, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on September 1, 2022; Chinese Patent Application No. 202211065772.4, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on October 24, 2022. This application claims priority to Chinese Patent Application No. 202211305113.3 entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the State Intellectual Property Office of the People's Republic of China on November 18, 2022; and Chinese Patent Application No. 202211448533.7 entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the State Intellectual Property Office of the People's Republic of China on November 18, 2022, each of which is incorporated herein by reference in its entirety.

[0002] The present application relates to the field of communications, and in particular to a data processing method and device. [Background technology]

[0003] With the continued proliferation of 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTN) are evolving to feature larger capacities and ultra-high speeds. Forward error correction (FEC) coding is used to correct transmitted data, resolve transmitted bit errors, and recover the original data sent by the transmitter from the received data.

[0004] A concatenated FEC transmission solution has been proposed. In this solution, a sending device is connected to a sending processing module via an attachment unit interface (AUI). The sending device performs a first FEC encoding on data to be transmitted and transmits the data obtained by the first FEC encoding to the sending processing module. The sending processing module performs a second FEC encoding on the data obtained by the first FEC encoding and transmits the data obtained by the second FEC encoding to a data receiving side via a channel. Specifically, the sending processing module receives multiple data streams, first performs convolutional interleaving on the multiple data streams separately, and then performs a second FEC encoding on each data stream obtained by the convolutional interleaving. It should be understood that, to improve performance, one data stream involved in the second FEC encoding needs to be from multiple codewords obtained by the first FEC encoding. However, this needs to be implemented by using convolutional interleaving, which involves long latency, but the application effect is not ideal in scenarios requiring low latency. Summary of the Invention

[0005] The embodiments of the present application provide a data processing method and a data processing apparatus, in which better performance of the concatenated FEC solution can be obtained in low latency scenarios. [Means for solving the problem]

[0006] According to a first aspect, the present application provides a data processing method, which includes the following steps: first, convolutional interleaving is performed separately on n lane data streams to obtain n first data streams, where n is an integer greater than 1, and first FEC encoding is performed on all of the n lane data streams. a each The codewords of are distributed among the b lane data streams, a≦b≦n, where n can be exactly divided by b and a is an integer greater than or equal to 1. The z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1. Then, Every K The n first data streams are multiplexed to obtain one second data stream, for a total of m second data streams. The n first data streams include G first data stream subsets, where symbols in different first data stream subsets are from different codewords, and m=n / K, where K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream are from y different codewords, and y>z. If K≦G, the K first data streams are each from K first data stream subsets. If K>G, the K first data streams include K / G first data streams in each first data stream subset.

[0007] In this embodiment, all n lane data streams are outer-code-encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by convolutional interleaving to obtain m second data streams, after which inner-code encoding is performed. According to the data interleaving and multiplexing processing solution provided in the present application, the following cases can be implemented with low latency: multiple symbols successively output from the m multiplexed data streams are from codewords of multiple different outer codes. As a result, the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in the present application can reduce the overall latency of the concatenated FEC solution and is more applicable to scenarios requiring low latency.

[0008] In some possible implementations, performing convolutional interleaving on one lane data stream to obtain one first data stream includes: delaying the one lane data stream according to p delay lines to obtain one first data stream, where p is an integer greater than 1 and each delay line includes a different number of storage units, wherein the delay line with the fewest number of storage units includes 0 storage units; Every twoThe difference between the numbers of storage units of adjacent delay lines is Q, and each storage unit is configured to store d symbols, where z=p*d. The symbols in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, and each delay line inputs d symbols once and outputs d symbols once, and p*d consecutive symbols in the first data stream include d symbols output from the delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. In this embodiment, a specific implementation of convolutional interleaving is provided, thereby improving the practicality of this solution.

[0009] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, d(p*Q+1)≧a*N / b, d≦a, N is the length of the codeword, and z consecutive symbols in each first data stream may be from z different codewords.

[0010] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, d(p*Q-1)≧a*N / b, d≦a, N is the length of the codeword, and z consecutive symbols in each first data stream may be from z different codewords.

[0011] In some possible implementations, y=K*z if K≦G; or y=G*z if K>G. Such multiplexing schemes are used to ensure that y>z can be implemented in multiple different application scenarios, and the concatenated FEC solution can be implemented with better performance and lower latency.

[0012] In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset including K symbol groups, each symbol group including Δ symbols, two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets, if K≦G, then Δ is a submultiple of z; or if K>G, then Δ=z.

[0013] In this embodiment, two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets, so that y consecutive symbols in the second data stream obtained by multiplexing are from y different codewords, where y>z (y=K*z or y=G*z). It should be understood that when only convolutional interleaving is performed, a long latency is required to implement the case where y consecutive symbols in the output data stream are from y different codewords. In this solution, the duration of convolutional interleaving is shortened, but equivalent performance can still be achieved by combining convolutional interleaving and multiplexing. Also, by combining convolutional interleaving and multiplexing, the duration of multiplexing is shortened, and equivalent performance can be achieved with shorter latency.

[0014] In some possible implementations, the jth symbol group of each second data stream symbol subset is from the jth first data stream of the K first data streams involved in the multiplexing, where 0≦j≦K−1. In the above manner, a rule is provided for selecting the K first data streams involved in the multiplexing to ensure that two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets.

[0015] In some possible implementations, when K>G, two adjacent first data streams among the K first data streams involved in the multiplexing are from different first data stream subsets. In the above manner, in the scenario where K>G, a rule is provided for selecting the K first data streams involved in the multiplexing, ensuring that y=G*z.

[0016] In some possible embodiments, if K>G, then the G pieces are from different first data stream subsets. In the above manner, in a scenario where K>G, a rule is provided for selecting the K first data streams involved in the multiplexing, which further ensures that y=G*z.

[0017] In some possible implementations, n=32 and K=2, 4, or 8. In the above manner, some specific types of multiplexers are provided to extend the application scenarios of this solution.

[0018] In some possible implementations, n=32, p=2, 3, 4, 6, or 8, and d=1 or 2. In the above manner, some specific types of convolutional interleavers are provided to extend the application scenarios of this solution.

[0019] In some possible implementations, a=1 or 2, and b=4, 8, or 16. In the above manner, several distribution manners of lane data streams are provided, which expands the application scenarios of this solution.

[0020] In some possible implementations, before the step of separately performing convolutional interleaving on the n lane data streams to obtain n first data streams, the method further includes the step of performing lane reordering on the n lane data streams such that the n lane data streams are arranged in a preset sequence.

[0021] In some possible implementations, before the step of separately performing convolutional interleaving on the n lane data streams to obtain the n first data streams, the method further includes the step of performing lane deskew on the n lane data streams. In this embodiment, a specific implementation of lane data alignment is provided, thereby improving the practicability of this solution.

[0022] In some possible implementations, before separately performing convolutional interleaving on the n lane data streams to obtain the n first data streams, the method further includes aligning the n lane data streams such that symbols within the n lane data streams are aligned. In this implementation, another specific implementation of lane data alignment is provided, thereby improving the flexibility of this solution.

[0023] In some possible implementations, after a total of m second data streams are obtained, the method further includes separately performing second FEC encoding on the m second data streams, wherein the length of information bits of the second FEC encoding is less than or equal to y symbols.

[0024] According to a second aspect, the present application provides a data processing device, the data processing device including a convolutional interleaver and a multiplexer, the convolutional interleaver being configured to separately perform convolutional interleaving on n lane data streams to obtain n first data streams, where n is an integer greater than 1, and a first FEC encoding being performed on all of the n lane data streams. a eachThe codewords of n are distributed among the b lane data streams, where a≦b≦n, and n can be exactly divided by b, and a is an integer greater than or equal to 1. The z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1. The multiplexer multiplexes the n symbols of the first data streams to obtain a total of m second data streams. Every K The multiplexing unit is configured to multiplex n first data streams to obtain one second data stream. The n first data streams include G first data stream subsets, and symbols in different first data stream subsets are from different codewords, where m=n / K, K is an integer greater than 1, and G is an integer greater than 1. y consecutive symbols in each second data stream are from y different codewords, where y>z. If K≦G, the K first data streams are from K first data stream subsets, respectively. If K>G, the K first data streams include K / G first data streams in each first data stream subset.

[0025] In some possible implementations, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units; Every twothe difference between the numbers of storage units of adjacent delay lines is Q, and each storage unit is configured to store d symbols, where z=p*d. The symbols in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, with d symbols input to each delay line once and d symbols output from the delay line once, and the p*d consecutive symbols in the first data stream include d symbols output from the delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0026] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p*Q+1)≧a*N / b, where N is the length of the codeword and d≦a.

[0027] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p*Q-1)≧a*N / b, where N is the length of the codeword and d≦a.

[0028] In some possible implementations, if K≦G, then y=K*z; or if K>G, then y=G*z.

[0029] In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset including K symbol groups, each symbol group including Δ symbols, two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets, if K≦G, then Δ is a submultiple of z; or if K>G, then Δ=z.

[0030] In some possible implementations, the jth symbol group of each second data stream symbol subset is from the jth first data stream of the K first data streams involved in the multiplexing, where 0≦j≦K−1.

[0031] In some possible implementations, if K>G, two adjacent first data streams of the K first data streams involved in the multiplexing are from different first data stream subsets.

[0032] In some possible embodiments, if K>G, then the G pieces The consecutive first data streams are from different first data stream subsets.

[0033] In some possible embodiments, n=32 and K=2, 4, or 8.

[0034] In some possible embodiments, n=32, p=2, 3, 4, 6, or 8, and d=1 or 2.

[0035] In some possible embodiments, a=1 or 2 and b=4, 8, or 16.

[0036] In some possible implementations, the data processing device further includes a lane reordering unit, configured to perform lane reordering on the n lane data streams before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams, such that the n lane data streams are arranged in a preset sequence.

[0037] In some possible implementations, the data processing apparatus further includes a lane data alignment unit configured to perform lane deskew on the n lane data streams before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams.

[0038] In some possible implementations, the data processing apparatus further includes a lane data alignment unit configured to align the n lane data streams such that symbols within the n lane data streams are aligned before the convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams.

[0039] In some possible implementations, the data processing device further includes an encoder, wherein after a total of m second data streams are obtained, the encoder is configured to perform second FEC encoding on the m second data streams separately, and the length of information bits of the second FEC encoding is less than or equal to y symbols.

[0040] According to a third aspect, the present application provides a data processing method, the method comprising the steps of: performing interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4; performing first forward error correction (FEC) encoding on all of the n lane data streams; and a eachcodewords are distributed among b lane data streams, a≦b≦n, and n can be exactly divided by b; F consecutive symbols in each target data stream are from F different codewords, F>a; F consecutive symbols in each target data stream are from at least K1 different lane data streams, and F consecutive symbols in each target data stream are from up to K2 symbols within n aligned symbols of n lane data streams, where K1 and K2 are sub-multiples of n and K2 is a sub-multiple of K1; up to K3 symbols within F consecutive symbols in each target data stream are from the same lane data stream;

number

[0041] In some possible implementations, K1=n / 4 and K2=n / 16.

[0042] In some possible implementations, performing interleaving on the n lane data streams to obtain m target data streams includes separately performing convolutional interleaving on the n lane data streams to obtain n first data streams, where z consecutive symbols in each of the first data streams are from at least e different codewords, z is an integer greater than 1, a≦e≦F, and e*k2≧F, and at most k1 / k2 symbols in the z consecutive symbols in each of the first data streams are from the same codeword; and performing convolutional interleaving on the n first data streams to obtain a total of m target data streams. Each Kperforming block interleaving on the first data stream to obtain S target data streams, where S is an integer greater than or equal to 1, m=S*n / K1, S≧k1 / k2, and the n first data streams include K1 first data stream groups, and Every two the symbols of the first data streams are from the same codeword, and the K1 first data streams are from the K1 first data stream groups, respectively.

[0043] In some possible implementations, the step of performing convolutional interleaving on one lane data stream to obtain one first data stream comprises delaying the one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1 and p*a≧F / k2, each delay line includes a different number of storage units, and the delay line with the fewest number of storage units includes 0 storage units; Every two a difference in the number of storage units of adjacent delay lines between the first data stream and the second data stream is Q, each storage unit is configured to store d symbols, and z=p*d. The symbols in each lane data stream are input sequentially to p delay lines based on sequence numbers of the p delay lines, d symbols are input to each delay line once, and d symbols are output from the delay line once, and p*d consecutive symbols in the first data stream include d symbols output from the delay line, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d≦a.

[0044] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p*Q+1)≧K4.

[0045] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p*Q-1)≧K4.

[0046] In some possible implementations, the K first data streams involved in block interleaving include a first symbol matrix, the first symbol matrix having K rows and B columns of symbols, where B = R*p*d, where R is an integer greater than or equal to 1, and the S target data streams obtained by block interleaving include a second symbol matrix, the second symbol matrix having S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and up to R*K1 / K2 symbols in the first symbol matrix are from the same codeword.

[0047] In some possible implementations, the F symbols in each row of the second symbol matrix are at least

number

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[0048] In some possible implementations, in each row of the second symbol matrix, the symbols from the odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and in each row of the second symbol matrix, the symbols from the even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

[0049] In some possible implementations, the symbols output from the delay line having the same delay value and in each row of the second symbol matrix are from different rows of the first symbol matrix.

[0050] In some possible implementations, up to K symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K symbols are output from two delay lines, respectively, with a delay difference greater than or equal to 2*Q*d.

[0051] In some possible implementations, performing interleaving on the n lane data streams to obtain m target data streams includes: performing first block interleaving on the n lane data streams to obtain T first data streams, where C consecutive symbols in each of the first data streams are from at least E different codewords, T=n / K1, C is a multiple of a, and E≧K2*a; performing convolutional interleaving on the T first data streams to obtain T second data streams, where H consecutive symbols in each of the second data streams are from at least F different codewords, F≧E, and up to K1 / K2 symbols of the H consecutive symbols in each of the second data streams are from the same codeword; and performing second block interleaving on each of the T second data streams to obtain S target data streams, obtaining a total of m target data streams, where m=T*S and S≧k1 / K2.

[0052] In some possible implementations, the n lane data streams involved in the first block interleaving include a third symbol matrix, the third symbol matrix including symbols in n rows and A columns, where A is a multiple of a, and the T first data streams obtained by the first block interleaving include a fourth symbol matrix, the fourth symbol matrix including symbols in T rows and C columns, where T is a submultiple of n, and n*A=T*C. Every T pieces are symbol submatrices, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

[0053] In some possible implementations, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix include the first to (n / T)th symbol submatrices arranged in the first sequence, and the (n / T)th symbol submatrices in the preceding column and the first symbol submatrices in the succeeding column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix can be deduced by analogy to be from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices; or the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the T symbols in the Cth column of the fourth symbol matrix are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices. T rows It can be deduced by analogy that the first to A columns of the fourth symbol matrix include the first to A symbol submatrices arranged in the second sequence, the A symbol submatrix in the first T rows and the first symbol submatrix in the second T rows of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrix in the third symbol matrix arranged in the second sequence, and the remaining T symbols in the C column of the fourth symbol matrix are from the last symbol submatrix in the third symbol matrix arranged in the second sequence.

[0054] In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream comprises delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1 and p*E≧F, each delay line including a different number of storage units, and the delay line with the fewest number of storage units includes 0 storage units; Every twothe difference in the number of storage units of adjacent delay lines is Q, each storage unit is configured to store C symbols, p*C=H, the symbols in each first data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, each delay line inputs C symbols once and outputs C symbols once, and p*C consecutive symbols in the second data stream include C symbols output from the delay line, and Q is an integer greater than or equal to 1.

[0055] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and C(p*Q+1)≧K1*K4.

[0056] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and C(p*Q-1)≧K1*K4.

[0057] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from p delay lines respectively, the symbols in each symbol set are from at least F different codewords, and each target data stream includes F symbols, where R*p*C=S*F, and R is an integer greater than or equal to. The F symbols in the target data stream are at least

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[0058] In some possible implementations, the F symbols in the target data stream include a first group of symbols from a first subset of symbols and a second group of symbols from a second subset of symbols, the first subset of symbols and the second subset of symbols belong to the same symbol set, the first subset of symbols and the second subset of symbols are output from two adjacent delay lines, respectively, the symbols in the first subset of symbols and the symbols in the second subset of symbols are sequentially arranged separately, and the ranking of the first group of symbols in the first subset of symbols is greater than the ranking of the second group of symbols in the second subset of symbols. or the F symbols in the target data stream include a third symbol group from the third symbol subset and a fourth symbol group from the fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are sequentially arranged separately, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

[0059] In some possible implementations, the maximum number of symbols in each target data stream is

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[0060] In some possible implementations, after a total of m target data streams is obtained, the method further includes a step of separately performing second FEC encoding on the m target data streams, wherein the length of information bits of the second FEC encoding is equal to F symbols.

[0061] According to a fourth aspect, the present application provides a data processing device, the data processing device including an interleaving module configured to perform interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4, and a first forward error correction (FEC) encoding is performed on all of the n lane data streams, and the m target data streams obtained through the first FEC encoding are a each are all distributed among the b lane data streams, a≦b≦n, and n can be exactly divided by b. The F consecutive symbols in each target data stream are from F different codewords, F>a. The F consecutive symbols in each target data stream are from at least K1 different lane data streams, and the F consecutive symbols in each target data stream are from up to K2 symbols within n aligned symbols of n lane data streams, where K1 and K2 are sub-multiples of n and K2 is a sub-multiple of K1. Up to K3 symbols within the F consecutive symbols in each target data stream are from the same lane data stream.

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[0062] In some possible implementations, K1=n / 4 and K2=n / 16.

[0063] In some possible implementations, the interleaving module includes a convolutional interleaver and a block interleaver, wherein the convolutional interleaver is configured to separately perform convolutional interleaving on the n lane data streams to obtain n first data streams, wherein z consecutive symbols of each of the first data streams are from at least e different codewords, z is an integer greater than 1, a≦e≦F, e*k2≧F, and at most k1 / k2 symbols among the z consecutive symbols of each of the first data streams are from the same codeword. The block interleaver is configured to perform block interleaving on every K1 first data streams of the n first data streams to obtain a total of m target data streams, where S is an integer greater than or equal to 1, m=S*n / K1, S≧k1 / k2, the n first data streams include K1 first data stream groups, symbols for every two first data streams in the same first data stream group are from the same codeword, and the K1 first data streams are each from the K1 first data stream groups.

[0064] In some possible implementations, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1, and p*a≧F / k2, and the number of storage units included in each delay line is different, and the delay line with the smallest number of storage units includes 0 storage units; Every twoThe difference in the number of storage units of adjacent delay lines is Q, and each storage unit is configured to store d symbols, where z=p*d. The symbols in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, with d symbols input to each delay line once and d symbols output from the delay line once, and the p*d consecutive symbols in the first data stream include d symbols output from the delay line, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d≦a.

[0065] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p*Q+1)≧K 4 .

[0066] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p*Q-1)≧K4.

[0067] In some possible implementations, the K first data streams involved in block interleaving include a first symbol matrix, the first symbol matrix having K rows and B columns of symbols, where B = R*p*d, where R is an integer greater than or equal to 1, and the S target data streams obtained by block interleaving include a second symbol matrix, the second symbol matrix having S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and up to R*K1 / K2 symbols in the first symbol matrix are from the same codeword.

[0068] In some possible implementations, the F symbols in each row of the second symbol matrix are at least

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[0069] In some possible implementations, in each row of the second symbol matrix, symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and in each row of the second symbol matrix, symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

[0070] In some possible implementations, the symbols output from the delay line having the same delay value and in each row of the second symbol matrix are from different rows of the first symbol matrix.

[0071] In some possible implementations, up to K symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K symbols are output from two delay lines, respectively, with a delay difference greater than or equal to 2*Q*d.

[0072] In some possible implementations, the convolutional interleaving module includes a first block interleaver, a convolutional interleaver, and a second block interleaver. The first block interleaver is configured to perform first block interleaving on the n-lane data stream to obtain T first data streams, where C consecutive symbols of each of the first data streams are from at least E different codewords, T=n / K1, C is a multiple of a, and E≧K2*a. The convolutional interleaver is configured to perform convolutional interleaving on the T first data streams to obtain T second data streams, where H consecutive symbols of each of the second data streams are from at least F different codewords, F≧E, and up to K1 / K2 symbols within the H consecutive symbols of each of the second data streams are from the same codeword. The second block interleaver is configured to perform second block interleaving on each of the T second data streams to obtain S target data streams, where m=T*S and S≧k1 / K2, to obtain a total of m target data streams.

[0073] In some possible implementations, the n lane data streams involved in the first block interleaving include a third symbol matrix, the third symbol matrix including symbols in n rows and A columns, where A is a multiple of a, and the T first data streams obtained by the first block interleaving include a fourth symbol matrix, the fourth symbol matrix including symbols in T rows and C columns, where T is a submultiple of n, and n*A=T*C. Every T piecesare symbol submatrices, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

[0074] In some possible implementations, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix include the first to (n / T)th symbol submatrices arranged in the first sequence, and the (n / T)th symbol submatrices in the preceding column and the first symbol submatrices in the succeeding column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix can be deduced by analogy to be from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices; or the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the T symbols in the Cth column of the fourth symbol matrix are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices. T rows It can be deduced by analogy that the first to A columns of the fourth symbol matrix include the first to A symbol submatrices arranged in the second sequence, the A symbol submatrix in the first T rows and the first symbol submatrix in the second T rows of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrix in the third symbol matrix arranged in the second sequence, and the remaining T symbols in the C column of the fourth symbol matrix are from the last symbol submatrix in the third symbol matrix arranged in the second sequence.

[0075] In some possible implementations, the convolutional interleaver is specifically configured to delay one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1 and p*E≧F, and each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units; Every two the difference in the number of storage units of adjacent delay lines is Q, and each storage unit is configured to store C symbols, where p*C=H. The symbols in each first data stream are input sequentially to p delay lines based on the sequence numbers of the p delay lines, with C symbols input to each delay line once and C symbols output from the delay line once, and the p*C consecutive symbols in the second data stream include C symbols output from the delay lines, where Q is an integer greater than or equal to 1.

[0076] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and C(p*Q+1)≧K1*K4.

[0077] In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and C(p*Q-1)≧K1*K4.

[0078] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from p delay lines respectively, the symbols in each symbol set are from at least F different codewords, and each target data stream includes F symbols, where R*p*C=S*F, and R is an integer greater than or equal to. The F symbols in the target data stream are at least

number

number

number

[0079] In some possible implementations, the F symbols in the target data stream include a first group of symbols from a first subset of symbols and a second group of symbols from a second subset of symbols, the first subset of symbols and the second subset of symbols belong to the same symbol set, the first subset of symbols and the second subset of symbols are output from two adjacent delay lines, respectively, the symbols in the first subset of symbols and the symbols in the second subset of symbols are sequentially arranged separately, and the ranking of the first group of symbols in the first subset of symbols is greater than the ranking of the second group of symbols in the second subset of symbols. or the F symbols in the target data stream include a third symbol group from the third symbol subset and a fourth symbol group from the fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are sequentially arranged separately, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

[0080] In some possible implementations, the maximum number of symbols in each target data stream is

number

number

[0081] In some possible implementations, the data processing apparatus further includes an encoder, wherein after a total of m target data streams are obtained, the encoder is configured to perform second FEC encoding on the m target data streams separately, and a length of information bits of the second FEC encoding is equal to F symbols.

[0082] According to a fifth aspect, the present application provides a data processing method, the method including the steps of: first, extracting n lane data streams to obtain a total of m first data streams; Every t pieces Block interleaving is performed on the n lane data streams to obtain s first data streams, where n=q*t, m=q*s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. First forward error correction (FEC) encoding is performed on all of the n lane data streams, and the data streams obtained by the first FEC encoding are a each are distributed among b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 1. a each consecutive symbols are from different codewords, and Each L are from at least two different codewords, L1=N*a / b, where N is the length of the codeword. The t lane data streams are ,each Consecutive symbols in the lane data stream A total of t*a symbols, and t*a symbols are ,each Δ bits in a symbol, D=Δ*t*a For a total of D bitswhere D bits are consecutive in any one of the s first data streams, and Δ=M / s, where M represents the number of bits contained in one symbol. Then, convolutional interleaving is performed separately on the m first data streams to obtain m second data streams.

[0083] In some possible implementations, in each first data stream Every d pieces are from v different codewords, and Every 2 L are from at least v different codewords, where v can be exactly divided by a, L2=t / s*L1, and d=D / M.

[0084] In some possible implementations, n=32, 16 lane data streams within odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams within even-numbered lanes of the n lane data streams are from the same codeword, and the data streams within odd-numbered lanes of the n lane data streams and the data streams within even-numbered lanes of the n lane data streams are from different codewords.

[0085] In some possible implementations, t=2, s=1, and the number of n lane data streams is determined to obtain the number s first data streams. Every t piecesThe step of performing block interleaving on the lane data streams includes: performing block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, where 0≦i<16. Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream are consecutive in the first data stream obtained through block interleaving, and two consecutive symbols in the first data stream obtained through block interleaving are consecutive in the first data stream obtained through block interleaving. Every fourth The consecutive symbols are from four different codewords.

[0086] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the (

number

number

number

[0087] In some possible implementations, t=2, s=1, and the number of n lane data streams is determined to obtain the number s first data streams. Every t piecesThe step of performing block interleaving on the lane data streams includes: performing block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, where 0≦i<16. The jth consecutive β bit groups in the (2*i)th lane data stream and the jth consecutive β bit groups in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via block interleaving, where j≧0, and β is 1, 2, 4, 5, 10, or 20. Every fourth The consecutive symbols are from four different codewords.

[0088] In some possible implementations, t=2, s=2, and n lane data streams are used to obtain s first data streams. Every t pieces The step of performing block interleaving on the lane data streams includes a step of performing block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain a (2*i)th first data stream and a (2*i+1)th first data stream, where 0≦i<16. 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream 5 bits in each, for a total of 20 bits are consecutive in the (2*i)-th first data stream, and in the (2*i)-th first data stream Every 20 are from four different codewords, 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream The other 5 bits in each ofare consecutive in the (2*i+1)-th first data stream, and Every 20 consecutive bits are from four different codewords.

[0089] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0090] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0091] In some possible implementations, t=4, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t piecesperforming block interleaving on the lane data streams, performing block interleaving on a total of four lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, and a (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4 Two consecutive symbols contained in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0092] In some possible implementations, t=4, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t pieces performing block interleaving on the lane data streams, performing block interleaving on a total of four lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, and a (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4jth two consecutive symbol groups included in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and j-th two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0093] In some possible implementations, t=4, s=1, and n lane data streams Every t pieces performing block interleaving on the lane data streams to obtain s first data streams, performing block interleaving on a total of four lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, and a (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4 The jth symbol included in each of the four lane data streams A total of four symbols areare consecutive in the first data stream obtained by block interleaving, j≧0, and Every fourth The successive symbols of,are from four different codewords, including,step,.

[0094] In some possible implementations, t=8, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t pieces the step of performing block interleaving on the lane data streams includes performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and 8 Two consecutive symbols contained in each of the two lane data streams A total of 16 symbols are consecutive, and in the first data stream obtained by block interleaving, Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols of are from different codewords.

[0095] In some possible implementations, t=8, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t pieces performing block interleaving on the lane data stream, performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and in the first data stream obtained by block interleaving, 8 The jth two consecutive symbol groups included in each of the two lane data streams A total of 16 symbols are consecutive, and the jth two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols of are from different codewords.

[0096] In some possible implementations, t=8, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t pieces performing block interleaving on the lane data streams, performing block interleaving on a total of eight lane data streams, including an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i≦3; 8 The jth symbol included in each of the four lane data streams A total of eight symbols areare consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from four different codewords and are obtained by block interleaving in the first data stream. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0097] In some possible implementations, n=32, and the 16 consecutive lane data streams sorted before the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted after the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted before the n lane data streams and the 16 consecutive lane data streams sorted after the n lane data streams are from different codewords.

[0098] In some possible implementations, t=2, s=1, and the number of n lane data streams is determined to obtain the number s first data streams. Every t piecesThe step of performing block interleaving on the lane data streams includes: performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16. Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained through block interleaving, and two consecutive symbols in the first data stream obtained through block interleaving are consecutive in the first data stream obtained through block interleaving. Every fourth The consecutive symbols are from four different codewords.

[0099] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the (

number

number

number

[0100] In some possible implementations, t=2, s=1, and the number of n lane data streams is determined to obtain the number s first data streams. Every t piecesThe step of performing block interleaving on the lane data streams includes: performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16. The jth consecutive β bit groups in the ith lane data stream and the jth consecutive β bit groups in the (i+16)th lane data stream are consecutive in the first data stream obtained via block interleaving, where j≧0, and β is 1, 2, 4, 5, 10, or 20. Every fourth The consecutive symbols are from four different codewords.

[0101] In some possible implementations, t=2, s=2, and n lane data streams are used to obtain s first data streams. Every t pieces The step of performing block interleaving on the lane data streams includes the step of: performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain a (2*i)-th first data stream and a (2*i+1)-th first data stream, where 0≦i<16. 4 Two symbols : Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream 5 bits in each, for a total of 20 bits are consecutive in the (2*i)-th first data stream, and in the (2*i)-th first data stream Every 20 are from four different codewords, 4 Two symbols : Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream The other 5 bits in each ofare consecutive in the (2*i+1)-th first data stream, and Every 20 consecutive bits are from four different codewords.

[0102] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0103] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0104] In some possible implementations, t=4, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t piecesperforming block interleaving on the lane data streams, performing block interleaving on a total of four lane data streams: a (2*i)th lane data stream, a (2*i+1)th lane data stream, a (2*i+16)th lane data stream, and a (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4 Two consecutive symbols contained in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and Every eighth are from at least four different code words, and all 272 consecutive symbols are from at least four different code words, in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0105] In some possible implementations, t=4, s=1, and the number of n lane data streams is used to obtain the s first data streams. Every t pieces performing block interleaving on the lane data streams, performing block interleaving on a total of four lane data streams: a (2*i)th lane data stream, a (2*i+1)th lane data stream, a (2*i+16)th lane data stream, and a (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4jth two consecutive symbol groups included in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and j-th two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0106] In some possible implementations, t=4, s=1, and n lane data streams Every t pieces performing block interleaving on the lane data streams to obtain s first data streams, performing block interleaving on a total of four lane data streams: a (2*i)th lane data stream, a (2*i+1)th lane data stream, a (2*i+16)th lane data stream, and a (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7; 4 The jth symbol included in each of the four lane data streams A total of four symbols areare consecutive in the first data stream obtained by block interleaving, j≧0, and Every fourth The successive symbols of,are from four different codewords, including,step,.

[0107] In some possible implementations, t=8, s=1, and the number of n lane data streams is 1 to obtain the number s first data streams. Every t pieces the step of performing block interleaving on the lane data streams includes performing block interleaving on a total of eight lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and 8 Two consecutive symbols contained in each of the two lane data streams A total of 16 symbols are consecutive, and in the first data stream obtained by block interleaving, Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols of are from different codewords.

[0108] In some possible implementations, t=8, s=1, and the number of n lane data streams is 1 to obtain the number s first data streams. Every t pieces the step of performing block interleaving on the lane data streams includes performing block interleaving on a total of eight lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and 8 The jth two consecutive symbol groups included in each of the two lane data streams A total of 16 symbols are consecutive, and the jth two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols of are from different codewords.

[0109] In some possible implementations, t=8, s=1, and the number of n lane data streams is 1 to obtain the number s first data streams. Every t pieces performing block interleaving on the lane data streams, performing block interleaving on a total of eight lane data streams, including a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, where 0≦i≦3; 8 The jth symbol included in each of the four lane data streams A total of eight symbols areare consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different code words, in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different codewords.

[0110] In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream includes delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every two the difference in the number of storage units of adjacent delay lines of the first data stream and the second data stream is Q, each storage unit is configured to store d symbols, the symbols in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, each delay line inputs d symbols once and outputs d symbols once, and p*d consecutive symbols in the second data stream include d symbols output from the delay line, and Q is an integer greater than or equal to 1.

[0111] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, d(p*Q+1)≧L2, and L2=t / s*L1; or the delay line with the lowest sequence number among the p delay lines contains 0 storage units, d(p*Q-1)≧L2, and L2=t / s*L1.

[0112] In some possible implementations, after separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein the information data of length K symbols in each coded data stream is from at most K different codewords, where K≧p*d.

[0113] In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream includes delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every two the difference in the number of storage units of adjacent delay lines of the first data stream and the second data stream is Q, each storage unit is configured to store four symbols, the symbols in each lane data stream are input to the p delay lines sequentially based on the sequence numbers of the p delay lines, each delay line inputs four symbols once and outputs four symbols once, the p*4 consecutive symbols in the second data stream include the four symbols output from the delay line, and Q satisfies 4(p*Q-1)≧272, 4(p*Q-1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

[0114] In some possible implementations, after the step of separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes the step of separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein the information data of length K symbols in each of the coded data streams is from up to K different codewords, where K≧p*4.

[0115] In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream includes delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every two the difference in the number of storage units of adjacent delay lines is Q, wherein each storage unit is configured to store 34 bits, and the bits in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, 34 bits are input to each delay line once and 34 bits are output from each delay line once, and p*34 consecutive bits in one second data stream comprise 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and the bits in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, 68 bits are input to each delay line once and 68 bits are output from each delay line once, and p*68 consecutive bits in one second data stream comprise 68 bits output from the delay lines.

[0116] In some possible implementations, p=2 and each storage unit is configured to store 68 bits, or p=4 and each storage unit is configured to store 34 bits.

[0117] According to a sixth aspect, the present application provides a data processing apparatus, the data processing apparatus including a block interleaver and a convolutional interleaver, the block interleaver being configured to interleave n lane data streams to obtain a total of m first data streams. Every t pieces The method is configured to perform block interleaving on the n lane data streams, where n=q*t and m=q*s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. A first forward error correction (FEC) encoding is performed on all of the n lane data streams, and the first FEC encoding is used to generate a first FEC signal. a each are distributed among b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 1. a each are from different codewords, and all L1 consecutive symbols in each lane data stream are from at least different codewords, where L1=N*a / b, where N is the length of the codeword. The t lane data streams are each Consecutive symbols in the lane data stream A total of t*a symbols, and t*a symbols are each Δ bits in a symbol, D=Δ*t*a A total of D bits where D bits are consecutive in any one of the s first data streams, and Δ=M / s, where M represents the number of bits included in one symbol. The convolutional interleaver is configured to separately perform convolutional interleaving on the m first data streams to obtain m second data streams.

[0118] In some possible implementations, in each first data stream Every d pieces are from v different codewords, and Every 2 Lare from at least v different codewords, where v can be exactly divided by a, L2=t / s*L1, and d=D / M.

[0119] In some possible implementations, n=32, 16 lane data streams within odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams within even-numbered lanes of the n lane data streams are from the same codeword, and the data streams within odd-numbered lanes of the n lane data streams and the data streams within even-numbered lanes of the n lane data streams are from different codewords.

[0120] In some possible implementations, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)-th lane data stream and the (2*i+1)-th lane data stream to obtain one first data stream, where 0≦i<16. Two consecutive symbols in the (2*i)-th lane data stream and two consecutive symbols in the (2*i+1)-th lane data stream are consecutive in the first data stream obtained through block interleaving, and two consecutive symbols in the first data stream obtained through block interleaving are consecutive in the first data stream obtained through block interleaving. Every fourth The consecutive symbols are from four different codewords.

[0121] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the (

number

number

number

[0122] In some possible implementations, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)-th lane data stream and the (2*i+1)-th lane data stream to obtain one first data stream, where 0≦i<16. The j-th consecutive β bit groups in the (2*i)-th lane data stream and the j-th consecutive β bit groups in the (2*i+1)-th lane data stream are consecutive in the first data stream obtained through block interleaving, where j≧0, and β is 1, 2, 4, 5, 10, or 20. Every fourth The consecutive symbols are from four different codewords.

[0123] In some possible implementations, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, where 0≦i<16. 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream 5 bits in each, for a total of 20 bits are consecutive in the (2*i)-th first data stream, and in the (2*i)-th first data stream Every 20 are from four different codewords, 4 Two symbols :Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream The other 5 bits in each of are consecutive in the (2*i+1)-th first data stream, and Every 20 consecutive bits are from four different codewords.

[0124] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0125] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0126] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (4*i)-th lane data stream, a (4*i+1)-th lane data stream, a (4*i+2)-th lane data stream, and a (4*i+3)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 Two consecutive symbols contained in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0127] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (4*i)-th lane data stream, a (4*i+1)-th lane data stream, a (4*i+2)-th lane data stream, and a (4*i+3)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 jth two consecutive symbol groups included in each of the two lane data streams A total of eight symbols areare consecutive in the first data stream obtained by block interleaving, and j-th two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0128] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (4*i)-th lane data stream, a (4*i+1)-th lane data stream, a (4*i+2)-th lane data stream, and a (4*i+3)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 The jth symbol included in each of the four lane data streams A total of four symbols are are consecutive in the first data stream obtained by block interleaving, j≧0, and Every fourth The codeword is specifically constructed such that consecutive symbols of are from four different codewords.

[0129] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving: 8 Two consecutive symbols contained in each of the two lane data streams A total of 16 symbols are consecutive, and in the first data stream obtained by block interleaving, Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 Specifically, the twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols are from different codewords.

[0130] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving: 8 The jth two consecutive symbol groups included in each of the two lane data streams A total of 16 symbols are consecutive, and the jth two consecutive symbol groups provided in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 Specifically, the twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols are from different codewords.

[0131] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream to obtain one first data stream, where 0≦i≦3; 8 The jth symbol included in each of the four lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from four different codewords and are obtained by block interleaving in the first data stream. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0132] In some possible implementations, n=32, and the 16 consecutive lane data streams sorted before the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted after the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted before the n lane data streams and the 16 consecutive lane data streams sorted after the n lane data streams are from different codewords.

[0133] In some possible implementations, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16. Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained through block interleaving, and two consecutive symbols in the first data stream obtained through block interleaving are consecutive in the first data stream obtained through block interleaving. Every fourth The consecutive symbols are from four different codewords.

[0134] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the (

number

number

number

[0135] In some possible implementations, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16. The jth consecutive β bit groups in the ith lane data stream and the jth consecutive β bit groups in the (i+16)th lane data stream are consecutive in the first data stream obtained through block interleaving, where j≧0, and β is 1, 2, 4, 5, 10, or 20. Every fourth The consecutive symbols are from four different codewords.

[0136] In some possible implementations, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, where 0≦i<16. 4 Two symbols : Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream 5 bits in each, for a total of 20 bits are consecutive in the (2*i)-th first data stream, and in the (2*i)-th first data stream Every 20 are from four different codewords, 4 Two symbols : Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream The other 5 bits in each ofare consecutive in the (2*i+1)-th first data stream, and Every 20 consecutive bits are from four different codewords.

[0137] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0138] In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (

number

number

[0139] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (2*i)-th lane data stream, a (2*i+1)-th lane data stream, a (2*i+16)-th lane data stream, and a (2*i+17)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 Two consecutive symbols contained in each of the two lane data streams A total of eight symbols areare consecutive in the first data stream obtained by block interleaving, and Every eighth are from at least four different codewords, Every 272 pieces are from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0140] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (2*i)-th lane data stream, a (2*i+1)-th lane data stream, a (2*i+16)-th lane data stream, and a (2*i+17)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 jth two consecutive symbol groups included in each of the two lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, and j-th two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different codewords, Every 272 piecesare from at least four different codewords and are in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0141] In some possible implementations, t=4 and s=1, and the block interleaver performs block interleaving on a total of four lane data streams: a (2*i)-th lane data stream, a (2*i+1)-th lane data stream, a (2*i+16)-th lane data stream, and a (2*i+17)-th lane data stream to obtain one first data stream, where 0≦i≦7; 4 The jth symbol included in each of the four lane data streams A total of four symbols are are consecutive in the first data stream obtained by block interleaving, j≧0, and Every fourth The codeword is specifically constructed such that consecutive symbols of are from four different codewords.

[0142] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving: 8 Two consecutive symbols contained in each of the two lane data streams A total of 16 symbols are consecutive, and in the first data stream obtained by block interleaving, Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 Specifically, the twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols are from different codewords.

[0143] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving: 8 The jth two consecutive symbol groups included in each of the two lane data streams A total of 16 symbols are consecutive, and the jth two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and Every 16 consecutive symbols of are from at least four different codewords, Every 544 are from at least four different codewords and are in the first data stream obtained by block interleaving. Every 16 The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 The fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16The eighth, ninth, tenth, and eleventh symbols in the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every 16 Specifically, the twelfth symbol, the thirteenth symbol, the fourteenth symbol, and the fifteenth symbol in the consecutive symbols are from different codewords.

[0144] In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream to obtain one first data stream, where 0≦i≦3; 8 The jth symbol included in each of the four lane data streams A total of eight symbols are are consecutive in the first data stream obtained by block interleaving, j≧0, and Every eighth are from at least four different code words, in the first data stream obtained by block interleaving. Every eighth The 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of the consecutive symbols of are from different code words and are in the first data stream obtained by block interleaving. Every eighth Specifically, the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol in the consecutive symbols are from different codewords.

[0145] In some possible implementations, the convolutional interleaver delays one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every two the difference in the number of storage units of adjacent delay lines of the first data stream is Q, each storage unit is configured to store d symbols, the symbols in each lane data stream are input to p delay lines sequentially based on the sequence numbers of the p delay lines, d symbols are input to each delay line once, and d symbols are output from the delay line once, and p*d consecutive symbols in the second data stream include d symbols output from the delay line, and Q is specifically configured to be an integer greater than or equal to 1.

[0146] In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, d(p*Q+1)≧L2, and L2=t / s*L1; or the delay line with the lowest sequence number among the p delay lines contains 0 storage units, d(p*Q-1)≧L2, and L2=t / s*L1.

[0147] In some possible implementations, the data processing apparatus further includes an encoder, wherein after the m second data streams are obtained, the encoder is configured to separately perform second FEC encoding on the m second data streams to obtain m encoded data streams, wherein the information data having a length of K symbols in each encoded data stream is from at most K different codewords, where K≧p*d.

[0148] In some possible implementations, the convolutional interleaver delays one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every two the difference in the number of storage units of adjacent delay lines of the first data stream is Q, each storage unit is configured to store four symbols, the symbols in each lane data stream are input sequentially to the p delay lines based on the sequence numbers of the p delay lines, four symbols are input to each delay line once and four symbols are output from the delay line once, p*4 consecutive symbols in the second data stream include four symbols output from the delay line, and Q is specifically configured to satisfy 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

[0149] In some possible implementations, the data processing apparatus further includes an encoder configured to: after the m second data streams are obtained, separately perform second FEC encoding on the m second data streams to obtain m encoded data streams, wherein the information data of length K symbols in each of the encoded data streams is from up to K different codewords, where K≧p*4.

[0150] In some possible implementations, the convolutional interleaver delays one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; Every twoThe difference in the number of storage units of adjacent delay lines is specifically configured to be Q, each storage unit configured to store 34 bits, the bits in each lane data stream being input to p delay lines sequentially based on the sequence numbers of the p delay lines, 34 bits being input to each delay line once and 34 bits being output from each delay line once, and p*34 consecutive bits in one second data stream comprising 34 bits output from the delay lines; or each storage unit configured to store 68 bits, the bits in each lane data stream being input to p delay lines sequentially based on the sequence numbers of the p delay lines, 68 bits being input to each delay line once and 68 bits being output from each delay line once, and p*68 consecutive bits in one second data stream comprising 68 bits output from the delay lines.

[0151] In some possible implementations, p=2 and each storage unit is configured to store 68 bits, or p=4 and each storage unit is configured to store 34 bits.

[0152] According to a seventh aspect, the present application provides a data processing method, the method including the following steps: first, n lane data streams are separately delayed based on p delay lines to obtain n first data streams, a first forward error correction (FEC) encoding is performed on all of the n lane data streams, where p is an integer greater than 1, and the number of storage units included in each delay line is different, and the delay line with the smallest number of storage units includes 0 storage units; Every twoThe difference between the numbers of storage units of adjacent delay lines is Q, and each storage unit is configured to store U bits, and bits in each lane data stream are input sequentially to the p delay lines according to the sequence numbers of the p delay lines, with U bits input to each delay line once and U bits output from the delay lines once, and p*U consecutive bits in one second data stream include U bits output from the delay lines, where Q is an integer greater than or equal to 1 and U is an integer greater than or equal to 1. Next, a second FEC encoding is separately performed on the n first data streams to obtain n second data streams. Information data of each codeword in the second data stream obtained by the second FEC encoding is p*U bits, output once from the p delay lines.

[0153] In some possible implementations, p*U=120, 136, or 160.

[0154] According to an eighth aspect, the present application provides a data processing device, the data processing device including a convolutional interleaver and an encoder, the convolutional interleaver is configured to separately delay n lane data streams based on p delay lines to obtain n first data streams, a first forward error correction (FEC) encoding is performed on all of the n lane data streams, p is an integer greater than 1, the number of storage units included in each delay line is different, and the delay line with the fewest number of storage units includes 0 storage units, Every twoThe difference between the numbers of storage units of adjacent delay lines is Q, and each storage unit is configured to store U bits, and bits in each lane data stream are input sequentially to the p delay lines according to the sequence numbers of the p delay lines, with U bits input to each delay line once and U bits output from the delay lines once, and p*U consecutive bits in one second data stream include U bits output from the delay lines, where Q is an integer greater than or equal to 1 and U is an integer greater than or equal to 1. Then, the encoder is configured to separately perform second FEC encoding on the n first data streams to obtain n second data streams. Information data of each codeword in the second data stream obtained by the second FEC encoding is p*U bits, output once from the p delay lines.

[0155] In some possible implementations, p*U=120, 136, or 160.

[0156] According to a ninth aspect, the present application provides a computer-readable storage medium storing a computer program, which, when executed by hardware, can perform some or all of the steps of the method of the first, third, fifth, or seventh aspect.

[0157] In an embodiment of the present application, all n lane data streams are outer-code encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by convolutional interleaving to obtain m second data streams, after which inner-code encoding is performed. According to the data interleaving and multiplexing processing solution provided in the present application, the following cases can be implemented with low latency: multiple symbols successively output from the m multiplexed data streams are from codewords of multiple different outer codes. As a result, the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in the present application can reduce the overall latency of the concatenated FEC solution and is more applicable to application scenarios requiring low latency. [Brief explanation of the drawings]

[0158] [Figure 1] 1 is a schematic diagram of a communication system according to an embodiment of the present application; [Figure 2] 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1; [Figure 3a] FIG. 2 is a schematic diagram of a first type of data processing by a sender processing module according to an embodiment of the present application; [Figure 3b] FIG. 10 is a schematic diagram of a second type of data processing by a sender processing module according to an embodiment of the present application; [Figure 3c] FIG. 10 is a schematic diagram of a third type of data processing by a sender processing module according to an embodiment of the present application. [Figure 3d] FIG. 10 is a schematic diagram of a fourth type of data processing by a sender processing module according to an embodiment of the present application. [Figure 3e] FIG. 2 is a schematic diagram of lane data alignment according to an embodiment of the present application. [Figure 3f]FIG. 10 is a schematic diagram of a fifth type of data processing by a sending-side processing module according to an embodiment of the present application. [Figure 3g] FIG. 10 is a schematic diagram of a sixth type of data processing by a sending-side processing module according to an embodiment of the present application. [Figure 3h] FIG. 10 is a schematic diagram of a seventh type of data processing by a sending-side processing module according to an embodiment of the present application. [Figure 3i] FIG. 10 is a schematic diagram of an eighth type of data processing by a sending-side processing module according to an embodiment of the present application. [Figure 4a] FIG. 2 is a schematic diagram of a first type of data processing by a receiver processing module according to an embodiment of the present application; [Figure 4b] FIG. 10 is a schematic diagram of a second type of data processing by a receiver processing module according to an embodiment of the present application. [Figure 4c] FIG. 10 is a schematic diagram of a third type of data processing by a receiver processing module according to an embodiment of the present application. [Figure 5] FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to a 1×800G interface used by a transmitting device. [Figure 6] FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to 2×400G interfaces used by a transmitting device. [Figure 7] FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to a 4×200G interface used by a transmitting device. [Figure 8] FIG. 1 is a schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. [Figure 9] FIG. 10 is another schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. [Figure 10] 1 is a schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 11]FIG. 2 is a schematic diagram of a structure in which convolutional interleaving is performed separately on n-lane data streams according to an embodiment of the present application. [Figure 12a] 2 is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application; [Figure 12b] FIG. 2 is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application; [Figure 13] 2 is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application; [Figure 14] FIG. 2 is a schematic diagram of a first structure of a multiplexer according to an embodiment of the present application; [Figure 15] FIG. 2 is a schematic diagram of a structure in which FEC encoding is performed on m second data streams according to an embodiment of the present application; [Figure 16a] FIG. 10 is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application; [Figure 16b] FIG. 10 is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application; [Figure 17a] FIG. 2 is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application; [Figure 17b] FIG. 10 is a schematic diagram of a third structure of a multiplexer according to an embodiment of the present application; [Figure 17c] FIG. 10 is a schematic diagram of a fourth structure of a multiplexer according to an embodiment of the present application; [Figure 18a] FIG. 10 is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application; [Figure 18b] FIG. 10 is a schematic diagram of a sixth structure of a convolutional interleaver according to an embodiment of the present application; [Figure 19a] FIG. 10 is a schematic diagram of a seventh structure of a convolutional interleaver according to an embodiment of the present application; [Figure 19b] FIG. 10 is a schematic diagram of an eighth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 20]FIG. 10 is a schematic diagram of a ninth structure of a convolutional interleaver according to an embodiment of the present application; [Figure 21] FIG. 16 is a schematic diagram of a tenth structure of a convolutional interleaver according to an embodiment of the present application; [Figure 22] FIG. 10 is a schematic diagram of a fifth structure of a multiplexer according to an embodiment of the present application. [Figure 23] FIG. 16 is a schematic diagram of an eleventh structure of a convolutional interleaver according to an embodiment of the present application. [Figure 24] FIG. 10 is a schematic diagram of a sixth structure of a multiplexer according to an embodiment of the present application. [Figure 25] FIG. 12 is a schematic diagram of a twelfth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 26] FIG. 13 is a schematic diagram of a thirteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 27a] FIG. 14 is a schematic diagram of a fourteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 27b] FIG. 15 is a schematic diagram of a fifteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 28a] FIG. 16 is a schematic diagram of a sixteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 28b] FIG. 17 is a schematic diagram of a seventeenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 29a] FIG. 18 is a schematic diagram of an eighteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 29b] FIG. 19 is a schematic diagram of a nineteenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 30a] FIG. 10 is a schematic diagram of a twentieth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 30b] FIG. 21 is a schematic diagram of a 21st structure of a convolutional interleaver according to an embodiment of the present application. [Figure 31a] FIG. 22 is a schematic diagram of a 22nd structure of a convolutional interleaver according to an embodiment of the present application. [Figure 31b]FIG. 23 is a schematic diagram of a 23rd structure of a convolutional interleaver according to an embodiment of the present application. [Figure 32a] 2 is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application; FIG. [Figure 32b] 1 is a schematic diagram of the structure of a block interleaver according to an embodiment of the present application; [Figure 33] 1 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application; [Figure 34] 1 is a schematic flowchart of interleaving according to an embodiment of the present application; [Figure 35] 2 is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application; FIG. [Figure 36] FIG. 2 is a schematic diagram of an implementation of performing block interleaving according to an embodiment of the present application; [Figure 37] Schematic diagram of lane-aligned data stream format for 2 x 400GbE host interface. [Figure 38] FIG. 1 is a schematic diagram of an implementation of block interleaving. [Figure 39] FIG. 10 is a schematic diagram of another embodiment of block interleaving. [Figure 40] FIG. 10 is a schematic diagram of another embodiment of block interleaving. [Figure 41] FIG. 10 is a schematic diagram of another embodiment of block interleaving. [Figure 42] 10 is another schematic flowchart of interleaving according to an embodiment of the present application; [Figure 43] FIG. 2 is a schematic diagram of an implementation of performing first block interleaving according to an embodiment of the present application. [Figure 44a] FIG. 10 is a schematic diagram of an implementation of performing second block interleaving according to an embodiment of the present application. [Figure 44b]FIG. 10 is a schematic diagram of a specific implementation of performing second block interleaving according to an embodiment of the present application. [Figure 45a] FIG. 1 is a schematic diagram of a first block interleaving implementation. [Figure 45b] FIG. 1 is a schematic diagram of an implementation of convolutional interleaving. [Figure 45c] FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. [Figure 45d] FIG. 10 is a schematic diagram of a second block interleaving embodiment. [Figure 46a] FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. [Figure 46b] FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. [Figure 46c] FIG. 10 is a schematic diagram of another embodiment of a second block interleave. [Figure 47] FIG. 10 is a schematic diagram of another embodiment of a second block interleave. [Figure 48] FIG. 10 is a schematic diagram of another embodiment of a second block interleave. [Figure 49] FIG. 10 is a schematic diagram of another embodiment of first block interleaving. [Figure 50a] FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; [Figure 50b] FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; [Figure 51] 1 is a schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 52] FIG. 2 is a schematic diagram of a structure in which block interleaving is performed on n-lane data streams according to an embodiment of the present application. [Figure 53] FIG. 2 is a schematic diagram of an application scenario of block interleaving according to an embodiment of the present application; [Figure 54] 3A-3C are schematic diagrams of several specific embodiments of block interleaving according to embodiments of the present application; [Figure 55]FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; [Figure 56] 3A-3C are schematic diagrams of several specific embodiments of block interleaving according to embodiments of the present application; [Figure 57] FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; [Figure 58] FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; [Figure 59] FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; [Figure 60] FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; [Figure 61] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 62] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 63] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 64] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 65] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 66] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 67] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 68] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 69] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 70] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 71] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 72] FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; [Figure 73] 2 is a schematic diagram of a structure in which convolutional interleaving is performed separately on m first data streams according to an embodiment of the present application; FIG. [Figure 74] 1 is a schematic diagram of an embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 75] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 76] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 77] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 78] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 79] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 80] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 81] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 82] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 83] FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; [Figure 84] FIG. 2 is a schematic diagram of an implementation of inner code encoding according to an embodiment of the present application. [Figure 85]1 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application; [Figure 86] 4 is another schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 87] FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; [Figure 88] FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0159] The embodiments of the present application provide a data processing method and a data processing apparatus so that better performance of a concatenated FEC solution can be achieved in low-latency scenarios. It should be noted that in the specification, claims, and accompanying drawings of this application, the terms “first,” “second,” etc. are intended to distinguish between similar objects, but do not necessarily indicate a specific order or sequence. It should be understood that the foregoing terms are interchangeable under appropriate circumstances, and thus the embodiments described in this application may be performed in an order other than that described in this application. Furthermore, the terms “include,” “have,” or any other variants thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units is not limited to the explicitly recited steps or units and may include other steps and units not explicitly recited or inherent to the process, method, product, or device.

[0160] FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present application. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. For example, the communication system is a data center network. The sending device 01 and the receiving device 05 may be devices such as a switch or a router, where the sending device 01 is also called a host chip located in the transmitter, and the receiving device 05 is also called a host chip located in the receiver, and the channel transmission medium 03 may be optical fiber. The host chip is also called a host device. The sending device 01 may be connected to the sending processing module 02 via an attachment unit interface (AUI), and the receiving device 05 may be connected to the receiving processing module 04 via the AUI. The transmitting processing module 02 and the receiving processing module 04 may each be an optical module, an electrical module, a connector, or another module that processes data in the data transmission process. For example, the processing module may be an 800LR module (an 800LR module, which is a coherent optical module). Furthermore, the transmitting device 01, the transmitting processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system may all support bidirectional transmission or unidirectional transmission. This is not specifically limited herein.

[0161] 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1. As shown in FIG. 2, in the process of transmitting data from a transmitting device 01 to a receiving device 05, the transmitting device 01 is configured to perform outer code encoding on the data and then transmit the outer code encoded data to a transmitting processing module 02. The transmitting processing module 02 is configured to perform inner code encoding on the outer code encoded data to obtain outer code encoded and inner code encoded data and transmit the outer code encoded and inner code encoded data to a channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer code encoded and inner code encoded data to a receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the outer code encoded and inner code encoded data and transmit the inner code decoded data to a receiving device 05. The receiving device 05 is configured to perform outer code decoding on the inner code decoded data.

[0162] It should be understood that the distinction between "internal" in the internal code and "external" in the external code is based solely on the distance between the performing entity that performs operations on data and the channel transmission medium 03. The performing entity that performs operations on the internal code is close to the channel transmission medium, and the performing entity that performs operations on the external code is far from the channel transmission medium. In an embodiment of the present application, data is transmitted from a sending device 01 to a channel transmission medium 03 via a sending processing module 02, and then transmitted from the channel transmission medium 03 to a receiving device 05 via a receiving processing module 04. The distance traveled by data encoded by the sending device 01 on the channel transmission medium 03 is longer than the distance traveled by data encoded by the sending processing module 02, and the distance traveled by data decoded by the receiving device 05 on the channel transmission medium 03 is longer than the distance traveled by data decoded by the receiving processing module 04. Thus, data encoded by the transmitting device 01 is referred to as outer-code-encoded data, data encoded by the transmitting processing module 02 is referred to as inner-code-encoded data, data decoded by the receiving device 05 is referred to as outer-code-decoded data, and data decoded by the receiving processing module 04 is referred to as inner-code-decoded data. In a possible implementation, both the inner code encoding and the outer code encoding use an FEC encoding style to form a concatenated FEC transmission solution. For example, the transmitting device 01 may perform outer code encoding using an RS code, and the transmitting processing module 02 may perform inner code encoding using a Hamming code. As another example, the transmitting device 01 may perform outer code encoding using an RS code, and the transmitting processing module 02 may perform inner code encoding using a Bose-Chaudhuri-Hocquenghem (BCH) code.

[0163] It should be noted that the above is an exemplary description of the application scenario of the data interleaving method provided in the embodiments of this application, and does not constitute any limitation on the application scenario of the data interleaving method. Those skilled in the art can know that as service requirements change, the application scenario of the data interleaving method can be adjusted based on the applicable requirements. In the embodiments of this application, the application scenarios are not listed one by one.

[0164] In the above-mentioned concatenated FEC transmission solution, a data processing solution including "convolutional interleaving" and "multiplexing" is designed in this application to achieve good performance and low latency for the entire concatenated FEC solution. Therefore, the concatenated FEC transmission solution can be applied to multiple transmission scenarios, and is particularly applicable to transmission scenarios that require low transmission latency, such as low-latency data center interconnection scenarios. Data processing is performed via the above-mentioned sender processing module 02.

[0165] 3(a) is a schematic diagram of a first type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(a), after processing data from multiple synchronous client lanes, a Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module can obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a designated processor, including convolutional interleaving and multiplexing, for data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0166] 3(b) is a schematic diagram of a second type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(b), in some practical application scenarios, the n aligned lane data streams obtained by lane data alignment are already arranged in a specified sequence. In this case, lane rearrangement does not need to be performed, and the n aligned lane data streams are directly sent to a designed processor including a convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding.

[0167] It should be understood that in some possible implementations, unlike the data processing procedures described in Figures 3(a) and 3(b), the n aligned lane data streams obtained by lane data alignment may alternatively not be convolutionally interleaved, but may be directly multiplexed and sent to an inner code encoder for inner code encoding.

[0168] 3(c) is a schematic diagram of a third type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(c), unlike the data processing procedure shown in FIG. 3(a), the n lane data streams obtained by lane rearrangement are directly multiplexed without convolutional interleaving, and are also sent to an inner code encoder for inner code encoding.

[0169] 3(d) is a schematic diagram of a fourth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(d), unlike the data processing procedure shown in FIG. 3(b), the n lane data streams obtained by lane data alignment are directly multiplexed without convolutional interleaving and sent to an inner code encoder for inner code encoding.

[0170] FIG. 3(e) is a schematic diagram of lane data alignment according to an embodiment of the present application. It should be understood that the aforementioned "lane data alignment" may be lane de-skew defined in existing standards, which ensures that the data of the n lane data streams output through lane data alignment are perfectly aligned. Alternatively, the aforementioned "lane data alignment" may simply be lane symbol alignment, which ensures that the data of the n lane data streams output through lane data alignment are aligned based on an outer code symbol. Specifically, data may be aligned based on one outer code symbol or multiple outer code symbols. In FIG. 3(e), two lane data streams are used as an example to describe the specific operation of "lane data alignment." It is assumed that the outer code is an RS code, and the length of one RS code symbol is 10 bits. Scenario (a) in Figure 3(e) shows that there is a 75-bit deviation between the two lane data streams, with AM0 and AM1 being the alignment markers for lane data stream 0 and lane data stream 1, respectively. Scenario (b) in Figure 3(e) shows that lane de-skew defined in existing standards is used, so there is no deviation between output lane data stream 0 and output lane data stream 1. Scenario (c) in Figure 3(e) shows that one RS symbol-based alignment is performed, aligning one RS symbol in output lane data stream 0 and one RS symbol in output lane data stream 1. In this case, there is still a 70-bit deviation between the two lanes. Scenario (d) in Figure 3(e) shows that two RS symbol-based alignments are performed, aligning two RS symbols in output lane data stream 0 and two RS symbols in output lane data stream 1. In this case, there is still a 60-bit deviation between the two lanes.

[0171] 3(f) is a schematic diagram of a fifth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(f), after processing data from multiple synchronous client lanes, a Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Then, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane rearrangement are sent to a processor designed to interleave and randomize data sequences, including convolutional interleaving and block interleaving, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0172] 3(g) is a schematic diagram of a sixth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(g), after processing data from multiple synchronous client lanes, a Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams, where the PCS lane data stream and the FEC lane data stream are collectively referred to as lane data streams, and may perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Then, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane rearrangement are sent to a designed processor, including a first block interleaving, a convolutional interleaving, and a second block interleaving, for interleaving and data sequence irregularity, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0173] 3(h) is a schematic diagram of a seventh type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(h), after processing data from multiple synchronous client lanes, a Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Then, based on the alignment markers, lane reordering is performed on the n lanes of data, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane rearrangement are sent to a processor designed to interleave and randomize data sequences, including block interleaving and convolutional interleaving, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0174] FIG. 3(i) is a schematic diagram of an eighth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(i), after processing data from n synchronous client lanes, such as an AUI-n interface, a physical medium attachment (PMA) sublayer of the transmitting-side processing module can obtain n outer-code-encoded lane data streams. The PMA sublayer herein only needs to perform signal recovery operations, such as clock data recovery (CDR) and PAM4 symbol demodulation, on the data from each client lane to obtain one lane data stream, and does not need to perform other complex operations, such as AM locking, lane deskew, and lane reordering. The n lane data streams are sent to a processor designed with a convolutional interleaving processor for interleaving and data sequence irregularization, and then sent to an inner-code encoder for inner-code encoding. After data processing is performed on the inner-code-encoded data stream, the data-processed data stream is transmitted to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. Herein, n is a positive integer greater than 1.

[0175] In some practical application scenarios, RS outer code encoding means that encoding is performed by using two encoders, and then interleaving, such as two-way interleaving, is performed, such that RS symbols on lane data streams with even sequence numbers are transmitted in the format of "ABABA B..." and RS symbols on lane data streams with odd sequence numbers are transmitted in the format of "BABAB A...", where A and B are two RS symbols generated by different encoders. In the case of two RS symbol-based alignment, the effect of the embodiment is that the RS symbols on all lane data streams with even sequence numbers are generated by the same encoder at the same moment, and the RS symbols on all lane data streams with odd sequence numbers are generated by another encoder at the same moment; or the effect of another embodiment is that the RS symbols on all lane data streams are generated by the same encoder at the same moment. The specific manner is not limited herein.

[0176] 4(a) is a schematic diagram of a first type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(a), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a processor including convolutional deinterleaving and demultiplexing for processing to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. Convolutional de-interleaving and de-multiplexing in the receiving-side processing module are the reverse operations of convolutional interleaving and multiplexing in the transmitting-side processing module. Convolutional de-interleaving is the reverse operation of convolutional interleaving in the transmitting-side processing module, and de-multiplexing is the reverse operation of multiplexing in the transmitting-side processing module. The convolutional interleaving and multiplexing in the transmitting-side processing module will be described in detail below. The convolutional de-interleaving and de-multiplexing in the receiving-side processing module are the reverse operations of the convolutional interleaving and multiplexing in the transmitting-side processing module shown in Figures 3(a) and 3(b). This is well known to those skilled in the art and will not be described herein.

[0177] 4(b) is a schematic diagram of a second type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(b), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a processor for processing, including block deinterleaving and convolutional deinterleaving, to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. In this specification, block deinterleaving and convolutional deinterleaving in the receiving-side processing module are the reverse operations of block interleaving and convolutional interleaving in the transmitting-side processing module shown in Figure 3(f). Convolutional deinterleaving is the reverse operation of convolutional interleaving in the transmitting-side processing module, and block deinterleaving is the reverse operation of block interleaving in the transmitting-side processing module.

[0178] 4(c) is a schematic diagram of a third type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(c), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a second block deinterleaver, a convolutional deinterleaver, and a first block deinterleaver for processing to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. In this specification, the first block deinterleaving, convolutional deinterleaving, and second block deinterleaving in the receiving-side processing module are respectively the reverse operations of the first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module shown in Figure 3(g). The first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module will be described in detail below. The first block deinterleaving, convolutional deinterleaving, and second block deinterleaving in the receiving-side processing module are respectively the reverse operations of the first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module. This is well known to those skilled in the art and will not be described herein.

[0179] In the following, we first provide several specific scenarios to which the embodiments of this application can be applied. Please note that for ease of explanation, the following specific scenarios are described by using an example in which the "lane data alignment" is lane deskew.

[0180] 5 is a schematic diagram of 32 PCS lane data streams corresponding to a 1×800G interface used by a transmitting device. As shown in FIG. 5, the transmitting device performs outer code encoding of KP4 RS (544, 514) code on one channel of the 800GbE service data stream to be transmitted to obtain 32 PCS lane data streams. Each of PCS lane data streams 0 to 15 Every 68 pieces Consecutive symbols in each PCS lane data stream form a total of 16*68=1088 symbols, containing two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols in the same location in two adjacent PCS lane data streams are from different RS codewords. Similarly, each of PCS lane data streams 16 to 31 Every 68 pieces The consecutive symbols form a total of 16*68=1088 symbols, containing two RS code words. Two adjacent symbols in each PCS lane data stream are from different RS code words, and two symbols in the same location in two adjacent PCS lane data streams are from different RS code words. After PMA processing, the 32 PCS lane data streams are sent to the transmit processing module via the Mounting Unit Interface 800GAUI-8.

[0181] Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the Ethernet Technology Consortium 800G Specification). The transmitting-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers, lane reordering is performed on the data of the n=32 lanes, so that the data of the n=32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from 0 to 31 from top to bottom, which is the same as that shown in FIG. 5.

[0182] 6 is a schematic diagram of 32 PCS lane data streams corresponding to 2×400G interfaces used by a transmitting device. As shown in FIG. 6, the transmitting device performs outer code encoding of KP4 RS (544, 514) code on two channels of the 400GbE service data stream to be transmitted, P Two channels of CS lane data stream A total of 32 PCS lane data streams Each channel contains 16 PCS lane data streams. PCS lane data streams 0 to 15 or PCS lane data streams 16 to 31 are Every 68 piecesThe consecutive symbols form a total of 16*68=1088 symbols, containing two RS code words. Two adjacent symbols in each PCS lane data stream are from different RS code words, and two symbols in the same location in two adjacent PCS lane data streams are from different RS code words. After PMA processing, the 32 PCS lane data streams are sent to the transmit processing module via the Mounting Unit Interface 2x400GAUI-4.

[0183] Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 16-lane data stream based on the known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. PCS lanes 0 to 15 may be considered as PCS lanes 0 to 15 of the 0th channel of 400G, and PCS lanes 16 to 31 may be considered as PCS lanes 0 to 15 of the 1st channel of 400G. The known alignment markers of the 16 lanes in the 0th channel of 400G are the same as the known alignment markers of the 16 lanes in the 1st channel of 400G. The transmitting-side processing module then performs lane de-skew on the 32-lane data stream to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31, lane reordering is performed on the data of the 16 lanes so that the data of the 16 lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as that shown in Figure 6.

[0184] 7 is a schematic diagram of 32 PCS lane data streams corresponding to a 4×200G interface used by a transmitting device. As shown in FIG. 7, the transmitting device performs outer code encoding of KP4 RS (544, 514) code on the four channels of the 200GbE service data stream to be transmitted, P 4 channels of CS lane data stream That is a total of 32 Each channel contains eight PCS lane data streams: PCS lane data streams 0 to 7, PCS lane data streams 8 to 15, PCS lane data streams 16 to 23, or PCS lane data streams 24 to 31. Every 136 The consecutive symbols form a total of 8*136=1088 symbols, containing two RS code words. Two adjacent symbols in each PCS lane data stream are from different RS code words, and two symbols in the same location in two adjacent PCS lane data streams are from different RS code words. After PMA processing, the 32 PCS lane data streams are sent to the transmit processing module via the Mounting Unit Interface 4x200GAUI-2.

[0185] Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channel of 200G, respectively. The transmitting-side processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data of the eight lanes, and the data of the eight lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as that shown in FIG. 7.

[0186] 8 is a schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. As shown in FIG. 8, the transmitting device performs outer code encoding of KP4RS (544, 514) code on the 8 channels of the 100GbE service data stream to be transmitted, F EC Lane (FEC lane) 8 channels of data streams A total of 32 FEC lane data streamsIn the "100G RS-FEC-Int" mode with two KP4 RS (544,514) codeword-based interleaving, each channel contains four FEC lane data streams. In the "100G RS-FEC-Int" mode, consecutive FEC lane data streams 0 to 3, 4 to 7, 8 to 11, 12 to 15, 16 to 19, 20 to 23, 24 to 27, or 28 to 31 are used. Every 272 The symbols form a total of 4*272=1088 symbols, containing two RS code words. Two adjacent symbols in each FEC lane data stream are from different RS code words, and two symbols in the same location in two adjacent FEC lane data streams are from different RS code words. After PMA processing, the 32 FEC lane data streams are sent to the transmit processing module via the Attachment Unit Interface 8x100GAUI-1.

[0187] 9 is another schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. As shown in FIG. 9, unlike the scenario in FIG. 8, in this scenario, the transmitting device uses the “100G RS-FEC” mode and transmits FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31. Every 136 The symbols form a total of 4*136=544 symbols, which contain one RS codeword. After PMA processing, the 32 FEC lane data streams are sent to the transmit processing module via the attachment unit interface 8x100GAUI-1.

[0188] Based on the aforementioned schematic data processing diagram of the transmitting side processing module shown in FIG. 3(a), the transmitting side processing module performs alignment marker lock for the four lane data stream based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channel of 100G, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering is performed on the data of the four lanes so that the data of the four lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figures 8 and 9.

[0189] FIG. 10 is a schematic flowchart of a data processing method according to an embodiment of the present application.

[0190] 1001: Perform convolutional interleaving on the n lane data streams separately to obtain n first data streams.

[0191] In this embodiment, the lane data stream may be a PCS lane data stream or an FEC lane data stream. This is not specifically limited herein. All of the n lane data streams are data streams obtained by the first FEC encoding, i.e., the aforementioned outer code encoded data streams, where n is an integer greater than 1. For example, the outer code encoding may be performed using an RS code, and the n outer code encoded data streams may include multiple RS code words. In practical applications, other encoding methods may be used to perform the outer code encoding. For ease of explanation, hereinafter, an RS code word will be used to represent a code word generated by the outer code encoding. a each It should be understood that the codewords of are distributed among b lane data streams, where a≦b≦n, n can be exactly divisible by b, and a is an integer greater than or equal to 1. In different application scenarios shown in Figures 5 to 9, the values ​​of a and b can also be different. The application scenario shown in Figure 5 is used as an example, where n=32, a=2, and b=16, in other words, Every two are distributed among the 16 lane data streams. The values ​​of a and b in the application scenarios of Figures 6 to 9 can be estimated with reference to the accompanying drawings, and will not be described in detail again herein. It should be noted that in this application, the code length of the outer code is measured in symbols, and a symbol may contain one or more bits. For example, the outer code used is a KP4 RS(544,514) code, with a code length of N=544 symbols and one symbol containing 10 bits.

[0192] In the example, when a=1, no interleaving is performed on the codeword obtained by the transmitting device 01 through outer-code encoding, and the codeword is directly distributed in the b lane data streams. As shown in Figure 9, when a=1, no interleaving is performed on the codeword having N=544 symbols obtained by the transmitting device 01 through outer-code KP4 encoding, and the codeword is directly distributed in the b=4 lane data streams. The 544 symbols in one dashed box shown in Figure 9 are from the same KP4 codeword, and N / b=544 / 4=136 consecutive symbols in one lane data stream in each dashed box are from the same KP4 codeword.

[0193] Another example indicates that when a>1, the codewords obtained by outer-code encoding by the transmitting device 01 are first interleaved and then distributed among b lane data streams. As shown in FIG. 8, when a=2, two-way symbol interleaving is first performed on two codewords having a total of a*N=2*544=1088 symbols obtained by outer-code KP4 encoding by the transmitting device 01, and then the two codewords are distributed among b=4 lane data streams. One dashed box shown in FIG. 8 includes 1088 symbols from a=2 KP4 codewords, and the 2*N / b=2*544 / 4=272 consecutive symbols in one lane data stream in each dashed box are from a=2 KP4 codewords, and two adjacent symbols are from different KP4 codewords. As shown in Figure 5, two-way symbol interleaving is first performed on two codewords with a = 2 and a total of a*N = 2 * 544 = 1088 symbols obtained by outer code KP4 encoding by the transmitting device 01, and then the two codewords are distributed into b = 16 lane data streams. One dashed box shown in Figure 5 contains 1088 symbols from a = 2 KP4 codewords, and the 2 * N / b = 2 * 544 / 16 = 68 consecutive symbols in one lane data stream in each dashed box are from a = 2 KP4 codewords, and two adjacent symbols are from different KP4 codewords.

[0194] Note that after convolutional interleaving, z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1. A specific implementation of convolutional interleaving is described below.

[0195] FIG. 11 is a schematic diagram of a structure in which convolutional interleaving is performed separately on n lane data streams according to an embodiment of the present application. As shown in FIG. 11, convolutional interleaving may be performed separately on the n lane data streams through n convolutional interleavers. After convolutional interleaving is performed on each lane data stream, a first data stream, which is an irregular data sequence, may be obtained. Note that in this embodiment, each convolutional interleaver performs convolutional interleaving on the input lane data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays the input lane data stream based on the p delay lines to obtain the first data stream. p is an integer greater than 1, and the number of storage units included in each delay line is different, with the delay line with the fewest number of storage units including 0 storage units, and the difference in the number of storage units between all two adjacent delay lines is Q. Each storage unit is configured to store d symbols, where z=p*d. The symbols in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, with each delay line receiving d symbols once and outputting d symbols once, such that p*d consecutive symbols in the first data stream include d symbols output from the delay lines. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, the p delay lines may include 0 storage units, Q storage units, 2Q storage units, ..., (p-1)Q storage units, respectively, with each storage unit configured to store d symbols. In this case, each of the p delay lines corresponds to p delay values, which include 0 symbols, Q×d symbols, 2Q×d symbols, ..., (p-1)Q×d symbols. Note that in this application, delay values ​​are measured in symbols, and a symbol can include one or more bits. A greater number of symbols included in the delay value of a delay line indicates a longer delay (also called latency) of the data stream delay line.It should be understood that if the delay line does not include a storage unit, the delay of the delay line is 0 symbols, in other words a transparent transmission without delay is performed.

[0196] The specific structure of the convolutional interleaver will be described below with reference to the accompanying drawings.

[0197] 12(a) is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 12(a), the number of storage units in p delay lines is in descending order based on the sequence numbers of the p delay lines. Specifically, delay line 0 has (p-1)Q storage units, and Q storage units are sequentially reduced in each delay line, and delay line (p-1) has 0 storage units. FIG. 12(b) is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 12(b), the number of storage units in p delay lines is in ascending order based on the sequence numbers of the p delay lines. Specifically, delay line 0 has 0 storage units, and Q storage units are sequentially increased in each delay line, and delay line (p-1) has (p-1)Q storage units.

[0198] It should be noted that the input switch and output switch of the convolutional interleaver are simultaneously located on the same delay line. After d symbols are input into the current delay line once and d symbols are output from the current delay line once, the switch position is updated to the next delay line, and the symbols in each lane data stream are input into the p delay lines sequentially based on the sequence numbers of the p delay lines, ensuring that p*d consecutive symbols in the first data stream include d symbols output from each delay line. The specific data read / write operation is as follows: d symbols are read from the storage unit closest to the output port and on the current delay line; the d symbols stored in each storage unit on the current delay line are transferred to the next storage unit; and then d symbols are written into the storage unit closest to the input port and on the current delay line. Then, switching to the next delay line is performed, and the above operations are repeated, and the rest can be deduced by analogy. In a possible implementation, if the convolutional interleaver shown in Figure 12(a) is used, the parameters of the convolutional interleaver will satisfy d(p*Q+1)≥a*N / b, where N is the length of the codeword, and p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of p*d different outer codes, and d≤a. In another possible implementation, if the convolutional interleaver shown in Figure 12(b) is used, the parameters of the convolutional interleaver will satisfy d(p*Q-1)≥a*N / b, where N is the length of the codeword, and p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of p*d different outer codes, and d≤a.

[0199] It should be understood that the convolutional interleaving of Figure 12(a) and the convolutional interleaving of Figure 12(b) are reciprocal operations when the same parameters p, Q, and d are used. In other words, if a transmitting-side processing module uses the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving of a receiving-side processing module uses the structure shown in Figure 12(b). Similarly, if a transmitting-side processing module uses the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving of a receiving-side processing module uses the structure shown in Figure 12(a).

[0200] It should be further understood that any one of the n convolutional interleavers may use the structure shown in Figure 12(a) or Figure 12(b). In practical applications, all of the n convolutional interleavers may use the structure shown in Figure 12(a); all of the n convolutional interleavers may use the structure shown in Figure 12(b); or some of the convolutional interleavers may use the structure shown in Figure 12(a), and the remaining convolutional interleavers use the structure shown in Figure 12(b).

[0201] It should be noted that in some specific application scenarios, n=32 is used as an example, the value of p can be 2, 3, 4, 6, or 8, and the value of d can be 1 or 2.

[0202] For ease of explanation, the following embodiment of convolutional interleaving will be explained by using an example in which all n convolutional interleavers use the structure shown in Figure 12(a). Of course, this example may be simply extended to other structures as mentioned above, the specific implementation of which may be known to those skilled in the art and will not be described in detail herein.

[0203] In some possible implementations, before convolutional interleaving is separately performed on the n lane data streams to obtain n first data streams, lane permutation may further be performed on the n lane data streams, so that the n data streams are arranged in a preset sequence. 32 data streams are used as an example. The 32 data streams may be sorted from 0 to 31 from top to bottom. Of course, this example may simply be extended to sorting in another sequence, the specific implementation of which may be known to those skilled in the art and will not be described in detail herein.

[0204] In some possible implementations, before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams, lane data alignment may be further performed on the n lane data streams. The lane data alignment may be lane de-skew defined in existing standards, ensuring that the data of the n lane data streams output through lane data alignment are perfectly aligned. Alternatively, the above-mentioned "lane data alignment" may simply be lane symbol alignment, ensuring that the data of the n lane data streams output through lane data alignment are aligned based on an outer code symbol. Specifically, the data may be aligned based on one outer code symbol or multiple outer code symbols. For a detailed description of lane data alignment, please refer to the related description of FIG. 3(e). This description will not be described in detail herein.

[0205] 1002: A method for generating a total of m second data streams by dividing n first data streams by n first data streams. Every K The first data streams are multiplexed to obtain one second data stream.

[0206] FIG. 13 is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application. As shown in FIG. 13, m multiplexers are used and multiplexing can be performed. Specifically, among the n first data streams Every K one of the first data streams is input to one multiplexer, and the multiplexer outputs one second data stream. The m multiplexers output a total of m second data streams, where m = n / K, and K is an integer greater than 1. For ease of explanation, in the present embodiment of the present application, an example in which the integer n can be exactly divided by K is used for explanation. The n first data streams include G first data stream subsets, where G is an integer greater than 1, and it should be noted that symbols in different first data stream subsets are from different codewords. In a possible embodiment, when K ≤ G, one first data stream is selected from each of any K first data stream subsets. In other words, the K first data streams input to one multiplexer are each from K first data stream subsets. In another possible embodiment, when K > G, K / G first data streams are selected from each first data stream subset. In other words, the K first data streams input to one multiplexer include K / G first data streams within each first data stream subset. For example, when n = 32, G = 2, K = 4, and m = 8, since K > G, in order to obtain the four first data streams input to the multiplexer, two first data streams need to be selected from each of the two first data stream subsets. In another example, when n = 32, G = 4, K = 2, and m = 8, since K < G, in order to obtain the two first data streams input to the multiplexer, two first data stream subsets need to be selected from the four first data stream subsets, and one first data stream needs to be selected from each of the two first data stream subsets.

[0207] Note that in some specific application scenarios, n=32 is used as an example, and the value of K can be 2, 4, or 8.

[0208] It should be understood that the first data stream subset is a concept introduced simply for ease of explanation, and in actual application, the n first data streams are whole without division, and each first data stream subset can be regarded as one or more data streams within the n first data streams.

[0209] It should be noted that since z consecutive symbols in each first data stream involved in the multiplexing are from z different code words, y consecutive symbols in each second data stream obtained by multiplexing are from y different code words, with y>z. In a possible implementation, y=K*z if K≦G. In another possible implementation, y=G*z if K>G.

[0210] A specific implementation of multiplexing will be described below. For ease of explanation, the K first data streams input to the multiplexer will be referred to as multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, ..., multiplexed input data stream (K-1).

[0211] 14 is a schematic diagram of a first structure of a multiplexer according to an embodiment of the present application. As shown in FIG.

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[0212] Note that because two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets, y consecutive symbols in the second data stream obtained by multiplexing are from y different codewords, where y>z (y=K*z or y=G*z). It should be understood that when only convolutional interleaving is performed, a long latency is required to implement the case where y consecutive symbols in the output data stream are from y different codewords. Although this solution shortens the duration of convolutional interleaving, comparable performance can still be achieved by combining convolutional interleaving and multiplexing. Also, combining convolutional interleaving and multiplexing can shorten the duration of multiplexing and achieve comparable performance with shorter latency.

[0213] It should be understood that the second data stream symbol subset is merely a concept introduced for ease of explanation, and in actual applications, the symbols in the second data stream are undivided wholes, and each second data stream symbol subset can be considered as multiple symbols in the second data stream.

[0214] Figure 14 is used as an example.

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[0215] In other words, in the above manner, the multiplexer outputs data in the K input data streams to one second data stream in a polling manner every Δ symbols, in other words, sequentially outputs Δ symbols from each of multiplexed input data streams 0 to multiplexed input data stream (K-1) to generate the second data stream, and the data sequence corresponding to the second data stream is

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[0216] 1003: Perform second FEC encoding separately for m second data streams to obtain encoded data streams. [[ID=⑧]]

[0217] [[ID=⑨]] FIG. 15 is a schematic diagram of a structure in which FEC encoding is performed on m second data streams according to an embodiment of the present application. As shown in FIG. 15, second FEC encoding, that is, the above-described inner code encoding, is performed separately on m second data streams, and the length of the information bits of the inner code encoding is less than or equal to y RS symbols. After data processing is performed on the inner code encoded data stream, the data processed data stream is transmitted to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, in order to improve the ability of the system to withstand burst errors, the inner code encoded data stream may be interleaved and then transmitted.

[0218] It should be noted that there is an error in the original text where "図15は" is followed by "図15に示されるように" which seems a bit redundant. Also, in the translation, the tags like Every G*z etc. are kept as they are as per the requirement. And the "⑧" in the original text is likely a mislabeling and should be "" in a proper format. The translation is adjusted accordingly while maintaining the overall structure and content integrity.In an embodiment of the present application, all n lane data streams are outer-code encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the convolutionally interleaved n data streams to obtain m second data streams, after which inner-code encoding is performed. According to the data interleaving and multiplexing processing solution provided in the present application, the following cases can be implemented with low latency: multiple symbols consecutively output from the m multiplexed data streams are from codewords of multiple different outer codes, and the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in the present application enables the overall latency of the concatenated FEC solution to be lowered, making it more applicable to application scenarios requiring low latency.

[0219] The following further describes the steps of the data processing method described in FIG. 10 with reference to several specific embodiments.

[0220] Embodiment 1: The application scenario is a 1×800G interface, the information bit length of the inner code encoding is 120 bits, a 2:1, 4:1 or 8:1 multiplexer is used, and lane deskew is used.

[0221] Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the Ethernet Technology Consortium 800G Specification). The transmitting-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 fully aligned lane data streams. Then, based on the alignment markers, lane reorder is performed on the data of the n=32 lanes, so that the data of the n=32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from 0 to 31 from top to bottom, which is the same as in FIG. 5.

[0222] The n=32 lane data streams on which lane permutation is performed are sent to a designed processor including a convolutional interleaving and multiplexing for convolutional interleaving and multiplexing, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc.

[0223] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0224] 16(a) is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 16(a), p=3 delay lines are included. The p=3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

[0225] As shown in Figure 16(a), C r (.) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (6t) and C r (6t+1) represents the two RS symbols in lane data stream r currently input to delay line 0, and C r (6t-12Q) and C r (6t-12Q+1) are the two RS symbols output from delay line 0; C r (6t+2) and C r (6t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (6t-6Q+2) and C r (6t-6Q+3) are the two RS symbols output from delay line 1; C r (6t+4) and C r (6t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r(6t+4) and C r (6t+5) are the two RS symbols output from delay line 2; C r (6t+6) and C r (6t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to FIG. 5, if 6Q+2≧68, i.e., Q≧11, then there are a total of six RS symbols C output by the convolutional interleaving. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be seen that (6t+5) are from 6 different RS codewords.

[0226] FIG. 16(b) is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 16(b), in a possible implementation, Q=11 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 16(b). The interleaving latency corresponding to the convolutional interleaver is approximately 22*2*3 / 2=66 RS symbols. The convolutional interleaver shown in FIG. 16(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 5. It is not difficult to understand that any RS symbol in the first data streams 0 to 15 and any RS symbol in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, where first data streams 0 to 15 are first data stream subset 0, and first data streams 16 to 31 are first data stream subset 1. Referring to Figure 16(a), No. The six output symbols C are those of an arbitrary data stream r_0 in data stream subset 0 of 1. r_0 (6t-12Q), C r_0 (6t-12Q+1), C r_0 (6t-12Q+1), C r_0 (6t-6Q+3), C r_0 (6t+4), and C r_0 (6t+5), as well as six output symbols C that are of any data stream r_1 in the first data stream subset 1. r_1 (6t-12Q), C r_1 (6t-12Q+1), C r_1 (6t-6Q+2), C r_1 (6t-6Q+3), C r_1 (6t+4), and C r_1 (6t+4) A total of 12 RS symbols, It is not difficult to see that σ is from 12 different RS codewords.

[0227] In this embodiment, possible implementations of the multiplexing shown in Figure 13 are as follows: G = 2, K = 2, and m = 16. Sixteen second data streams are generated, and sixteen 2:1 multiplexing processing modules are included. Any first data stream selected from first data stream subset 0 and any first data stream selected from first data stream subset 1 are used as inputs to the 2:1 multiplexer.

[0228] 17(a) is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(a), the two input data streams of a 2:1 multiplexer i (0≦i≦15) are a first data stream i and a first data stream (i+16). In the figure,

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[0229] 13 of this embodiment is as follows: G=2, K=4, m=8, eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from first data stream subset 0 and any two first data streams selected from first data stream subset 1 are used as inputs to the 4:1 multiplexers.

[0230] 17(b) is a schematic diagram of a third structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(b), multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of 4:1 multiplexer i (0≦i≦7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. In the figure,

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[0231] 13 of this embodiment is as follows: G=2, K=8, m=4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from first data stream subset 0 and any four first data streams selected from first data stream subset 1 are used as inputs to the 8:1 multiplexers.

[0232] 17(c) is a schematic diagram of a fourth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(c), the multiplexed input data streams 0 to 7 of an 8:1 multiplexer i (0≦i≦3) correspond to first data stream i, first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. It should be noted that the multiplexed input data streams 0 through 7 of 8:1 multiplexer i (0≦i≦3) may alternatively correspond to first data stream i, first data stream (i+16), first data stream (i+4), first data stream (i+20), first data stream (i+8), first data stream (i+24), first data stream (i+12), and first data stream (i+28), respectively, i.e., any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets.

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[0233] Inner code encoding is performed separately on 16, 8, or 4 second data streams, with the information bit length of the inner code encoding being 120 bits. Specifically, the inner code encoder adds redundancy separately to a total of 120 bits in 12 consecutive RS symbols in each second data stream to obtain a codeword data stream of the inner code. In one possible embodiment, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, with 8 bits of redundancy added to a total of 120 bits in 12 consecutive RS symbols in each second data stream. In another possible embodiment, inner code encoding is performed using BCH (136, 120), with 16 bits of redundancy added to a total of 120 bits in 12 consecutive RS symbols in each second data stream to obtain a 136-bit codeword.

[0234] After data processing is performed on the inner-code encoded data stream, the data-processed data stream is transmitted to a channel transmission medium. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

[0235] By using the data interleaving and encoding method of embodiment 1, the concatenated code of KP4 RS(544,514)+Hamming(128,120) in the method is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.5E-3, which is close to the optimal performance of the concatenated FEC method.

[0236] Embodiment 2: The application scenario is a 1×800G interface, the information bit length of the inner code encoding is 120 bits, a 2:1, 4:1 or 8:1 multiplexer is used, and lane symbol alignment is used.

[0237] The main difference between the second embodiment and the first embodiment is that in the second embodiment, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

[0238] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. Then, the transmitting-side processing module performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Then, based on the alignment markers, lane reordering is performed on the data of the 32 lanes, so that the data of the 32 lanes can be arranged in a specified sequence. One arrangement sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as FIG. 3(a). Another arrangement sequence is for the first 16 lane data streams to include PCS lane data streams 0 to 15, and the second 16 lanes to include PCS lane data streams 16 to 31, in the 32 lanes output through top-to-bottom "lane reordering." In this case, it should be understood that the specific sequence of the first 16-lane data stream is not limited, and the specific sequence of the second 16-lane data stream is also not limited, i.e., lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

[0239] The 32 lane data streams on which lane rearrangement is performed are sent to a processor designed for convolutional interleaving and multiplexing for interleaving and data sequence irregularity, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing and inner code encoding methods used in this embodiment all use the solution of embodiment 1.

[0240] By using the data interleaving and encoding method of embodiment 2, the concatenated code of KP4 RS(544,514)+Hamming(128,120) in the method is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.5E-3, the performance is comparable to that of the solution of embodiment 1, and the overall latency is lower. However, the solution of embodiment 2 has poorer system burst error tolerance compared to the solution of embodiment 1. This solution is applicable to some scenarios that require lower latency.

[0241] Embodiment 3: The application scenario is a 1×800G interface, the information bit length of the inner code encoding is 160 bits, a 2:1, 4:1 or 8:1 multiplexer is used, and lane deskew is used.

[0242] Based on embodiment 1, in this embodiment, an inner code with a code length of 160 bits is considered, and a newly designed convolutional interleaver is used accordingly.

[0243] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0244] 18(a) is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 18(a), p=4 delay lines are included. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbol, i.e., no delay.

[0245] As shown in Figure 18(a), C r (.) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in lane data stream r currently input to delay line 0, and C r (8t-24Q) and C r (8t-24Q+1) are the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (8t-16Q+2) and C r (8t-16Q+3) are the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r (8t-8Q+4) and C r (8t-8Q+5) are the two RS symbols output from delay line 2; C r (8t+6) and C r (8t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 3, and C r (8t+6) and C r(8t+7) are the two RS symbols output from delay line 3; and so on. Referring to FIG. 5, if 8Q+2≧68, i.e., Q≧9, then there are a total of eight RS symbols, C r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r It can be seen that (8t+7) is from 8 different RS codewords.

[0246] FIG. 18(b) is a schematic diagram of a sixth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 18(b), in a possible implementation, Q=9 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 18(b). The interleaving latency corresponding to the convolutional interleaver is approximately 27*2*4 / 2=108 RS symbols. The convolutional interleaver shown in FIG. 18(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 5. It is not difficult to understand that any RS symbol in the first data streams 0 to 15 and any RS symbol in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, where first data streams 0 to 15 are first data stream subset 0, and first data streams 16 to 31 are first data stream subset 1. Referring to Figure 18(a), No. The eight output symbols C of any data stream r_0 in data stream subset 0 of 1 r_0 (8t-24Q), C r_0 (8t-24Q+1), C r_0(8t-16Q+2), C r_0 (8t-16Q+3), C r_0 (8t-8Q+4), C r_0 (8t-8Q+5), C r_0 (8t+6), and C r_0 (8t+7), as well as the eight output symbols C of any data stream r_1 in the first data stream subset 1. r_1 (8t-24Q), C r_1 (8t-24Q+1), C r_1 (8t-16Q+2), C r_1 (8t-16Q+3),

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[0247] In this embodiment, possible implementations of the multiplexing shown in Figure 13 are as follows: G = 2, K = 2, and m = 16. 16 second data streams are generated, and 16 2:1 multiplexing processing modules are included. Any first data stream selected from first data stream subset 0 and any first data stream selected from first data stream subset 1 are used as inputs to the 2:1 multiplexer. A corresponding specific implementation of the 2:1 multiplexer is shown in Figure 17(a). The two input data streams of 2:1 multiplexer i (0 ≤ i ≤ 15) are first data stream i and first data stream (i + 16). In the figure,

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[0248] In this embodiment, another possible implementation of the multiplexing shown in FIG. 13 is as follows: G=2, K=4, and m=8. Eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from first data stream subset 0 and any two first data streams selected from first data stream subset 1 are used as inputs to the 4:1 multiplexers. A corresponding specific implementation of the 4:1 multiplexers is shown in FIG. 17(b). Multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of 4:1 multiplexer i (0≦i≦7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively; that is, any two consecutive multiplexed input data of the multiplexer are from different first data symbol subsets. In the figure,

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[0249] Another possible implementation of the multiplexing shown in Figure 13 of this embodiment is as follows: G=2, K=8, m=4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from first data stream subset 0 and any four first data streams selected from first data stream subset 1 are used as inputs to the 8:1 multiplexers. A corresponding specific implementation of the 8:1 multiplexers is shown in Figure 17(c). The 0 to 7 multiplexed input data streams of 8:1 multiplexer i (0≦i≦3) correspond to first data stream i, first data stream (i+16), first data stream (i+4), first data stream (i+20), first data stream (i+8), first data stream (i+24), first data stream (i+12), and first data stream (i+28), respectively. In the figure,

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[0250] Inner code encoding is performed separately on 16, 8, or 4 second data streams, with the information bit length of the inner code encoding being 160 bits. Specifically, the inner code encoder adds redundancy separately to a total of 160 bits in 16 consecutive RS symbols in the second data stream to obtain a codeword data stream of the inner code. In one possible embodiment, the inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, with 10 bits of redundancy added to a total of 160 bits in 16 consecutive RS symbols in each second data stream. In another possible embodiment, the inner code encoding is performed using BCH (176, 160), with 16 bits of redundancy added to a total of 160 bits in 16 consecutive RS symbols in each second data stream to obtain a 176-bit codeword. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is transmitted to a channel transmission medium for transmission.

[0251] By using the data interleaving and encoding scheme in this embodiment, when Hamming(170,160) is used as the inner code, the concatenated code of KP4 RS(544,514)+Hamming(170,160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme.When the inner code uses BCH(176,160), the concatenated code of KP4 RS(544,514)+BCH(176,160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

[0252] Embodiment 4: The application scenario is a 1×800G interface, the information bit length of the inner code encoding is 160 bits, a 2:1, 4:1 or 8:1 multiplexer is used, and lane symbol alignment is used.

[0253] The main difference between the fourth embodiment and the third embodiment is that in the fourth embodiment, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

[0254] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. Then, the transmitting-side processing module performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Then, based on the alignment markers, lane reordering is performed on the data of the 32 lanes, so that the data of the 32 lanes can be arranged in a specified sequence. One arrangement sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as FIG. 3(a). Another arrangement sequence is for the first 16 lane data streams to include PCS lane data streams 0 to 15, and the second 16 lanes to include PCS lane data streams 16 to 31, in the 32 lanes output through top-to-bottom "lane reordering." In this case, it should be understood that the specific sequence of the first 16-lane data stream is not limited, and the specific sequence of the second 16-lane data stream is also not limited, i.e., lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

[0255] The 32 lane data streams on which lane rearrangement is performed are sent to a processor designed for convolutional interleaving and multiplexing for interleaving and data sequence irregularity, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing, and inner code encoding methods used in this embodiment all use the solution of embodiment 3.

[0256] By using the data interleaving and encoding method of embodiment 4, the concatenated code of KP4 RS(544,514)+Hamming(160,120) in the method is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.5E-3, the performance is comparable to that of the solution of embodiment 3, and the overall latency is lower. However, the solution of embodiment 4 has poorer system burst error resistance compared to the solution of embodiment 3. This solution is applicable to some scenarios that require lower latency.

[0257] By using the data interleaving and encoding scheme of embodiment 4, when Hamming(170,160) is used as the inner code, the concatenated code of KP4 RS(544,514)+Hamming(170,160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme.When the inner code uses BCH(176,160), the concatenated code of KP4 RS(544,514)+BCH(176,160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme. It should be understood that when the same inner code scheme as the solution of embodiment 3 is used, the performance of the solution of embodiment 4 is the same as that of the solution of embodiment 3, but the solution of embodiment 4 has poor resistance to system burst errors. This solution is applicable to some scenarios that require lower latency.

[0258] Embodiment 5: The application scenario is 2×400G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 2:1, 4:1 or 8:1 multiplexer is used, and lane deskew is used.

[0259] Unlike the first to fourth embodiments, in this embodiment, the host interface is considered to be a 2×400G interface with 100 Gb / s per lane. For details of the interface, please refer to IEEE Std 802.3ck™ / D3.0.

[0260] Specifically, based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 16-lane data streams based on known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. Then, the transmitting-side processing module performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31, lane reorder is performed on the 16-lane data, so that the data of the 16 lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as in FIG. 6.

[0261] The 32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data streams, the data processed data streams are sent to a channel transmission medium for transmission.

[0262] In a possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 5 is the same as that of the solution in embodiment 1, the performance and latency of the concatenated FEC solution will be the same as that of embodiment 1.

[0263] In another possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 5 is the same as that of the solution in embodiment 3, the performance and latency of the concatenated FEC solution is the same as that of embodiment 3.

[0264] Embodiment 6: The application scenario is 2x400G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 2:1, 4:1 or 8:1 multiplexer is used, lane symbol alignment is used, and lane rearrangement is not performed.

[0265] Based on the solution of embodiment 5, embodiment 6 provides an implementation solution with lower latency.

[0266] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(b), the transmitting-side processing module performs alignment marker lock on the 16 lane data streams based on the known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. Then, the transmitting-side processing module performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are directly sent to a designed processor, including convolutional interleaving and multiplexing, for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data streams, the data-processed data streams are transmitted to a channel transmission medium for transmission.

[0267] In a possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 6 is the same as that of the solution in embodiment 2, the performance and latency of the concatenated FEC solution will be the same as that of embodiment 2.

[0268] In another possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 6 is the same as that of the solution in embodiment 4, the performance and latency of the concatenated FEC solution is the same as that of embodiment 4.

[0269] Embodiment 7: The application scenario is a 4×200G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 4:1 or 8:1 multiplexer is used, and lane deskew is used.

[0270] In this embodiment, the host interface is considered to be a 4x200G interface at 100Gb / s per lane. For details of the interface, see IEEE Std 802.3ck™ / D3.0.

[0271] Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channel of 200G, respectively. The transmitting-side processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data of the eight lanes, and the data of the eight lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 7.

[0272] The 32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data streams, the data processed data streams are sent to a channel transmission medium for transmission.

[0273] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0274] 19(a) is a schematic diagram of a seventh structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 19(a), p=2 delay lines are included. The two delay lines include Q storage units and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbol, i.e., no delay.

[0275] As shown in Figure 19(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (4t) and C r (4t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C r (4t+2) and C r(4t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (4t+2) and C r (4t+3) are the two RS symbols output from delay line 1; C r (4t+4) and C r (4t+5) represents two RS symbols in the lane data stream subsequently input to delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are two RS symbols output from delay line 0; and so on. Referring to FIG. 7, if 4Q+2≧136, i.e., Q≧34, then a total of four consecutive RS symbols, Cr(4t-4Q), Cr(4t-4Q+1), C r (4t+2), and C r It can be seen that (4t+3) are from four different RS codewords.

[0276] FIG. 19(b) is a schematic diagram of an eighth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 19(b), in a possible implementation, Q=34 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 19(b). The corresponding interleaving latency is approximately 34*2*2 / 2=68 RS symbols. The convolutional interleaver shown in FIG. 19(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to understand that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=4 first data stream subsets, where first data streams 0 to 7 are first data stream subset 0, first data streams 8 to 15 are first data stream subset 1, first data streams 16 to 23 are first data stream subset 2, and first data streams 24 to 31 are first data stream subset 3.

[0277] In this embodiment, possible implementations of the multiplexing shown in Figure 13 are as follows: G = 4, K = 4, and m = 8. Eight 4:1 multiplexers are included. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. Any first data stream selected from first data stream subset 0, any first data stream selected from first data stream subset 1, any first data stream selected from first data stream subset 2, and any first data stream selected from first data stream subset 3 are used as inputs to the 4:1 multiplexers.

[0278] A corresponding specific implementation of a 4:1 multiplexer is shown in Figure 17(b). Multiplexed Input Data Stream 0, Multiplexed Input Data Stream 1, Multiplexed Input Data Stream 2, and Multiplexed Input Data Stream 3 of 4:1 multiplexer i (0 < i < 7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively. Note that multiplexed Input Data Stream 0, Multiplexed Input Data Stream 1, Multiplexed Input Data Stream 2, and Multiplexed Input Data Stream 3 of 4:1 multiplexer i (0 < i < 7) may alternatively correspond to first data stream i, first data stream (i+8), first data stream (i+16), and first data stream (i+24), respectively. In this embodiment, the multiplexed input data streams shown in Figure 17(b) are used.

number

number

[0279] In this embodiment, another possible implementation of the multiplexing shown in FIG. 13 is as follows: G=4, K=8, and m=4. Four 8:1 multiplexers are included. Each multiplexer multiplexes eight first data streams to obtain one second data stream, generating a total of four second data streams. Any two first data streams selected from first data stream subset 0, any two first data streams selected from first data stream subset 1, any two first data streams selected from first data stream subset 2, and any two first data streams selected from first data stream subset 3 are used as inputs to the 8:1 multiplexers.

[0280] A corresponding specific implementation of an 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of 8:1 multiplexer i (0≦i≦3) correspond to first data stream i, first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively, i.e., any Q=4 consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. It should be noted that multiplexed input data streams 0 through 7 of 8:1 multiplexer i (0≦i≦3) may alternatively correspond to first data stream i, first data stream (i+8), first data stream (i+16), first data stream (i+24), first data stream (i+4), first data stream (i+12), first data stream (i+20), and first data stream (i+28), respectively.

number

number

[0281] The inner code encoding is performed separately on the aforementioned eight or four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain the same performance as embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain the same performance as embodiment 3, and details will not be described herein.

[0282] Embodiment 8: The application scenario is a 4×200G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

[0283] Based on embodiment 7, this embodiment considers the use of a 2:1 multiplexer, and uses a newly designed convolutional interleaver accordingly.

[0284] Specifically, based on the aforementioned schematic diagram of data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channel of 200G, respectively. The transmitting-side processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data of the eight lanes, and the data of the eight lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 7.

[0285] The 32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data streams, the data processed data streams are sent to a channel transmission medium for transmission.

[0286] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. FIG. 16(a) shows the configuration of a convolutional interleaver including p=3 delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

[0287] As shown in Figure 16(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (6t) and C r (6t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and C r (6t-12Q) and C r (6t-12Q+1) are the two RS symbols output from delay line 0; C r (6t+2) and C r (6t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (6t-6Q+2) and C r (6t-6Q+3) are the two RS symbols output from delay line 1; C r (6t+4) and C r (6t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r (6t+4) and C r (6t+5) are the two RS symbols output from delay line 2; C r(6t+6) and C r (6t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to FIG. 7, if 6Q+2≧136, in other words, Q≧23, then there are a total of six RS symbols C output by the convolutional interleaving. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be seen that (6t+5) are from 6 different RS codewords.

[0288] FIG. 20 is a schematic diagram of a ninth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 20, in a possible implementation, Q=23 is selected, and a specific structure of the convolutional interleaver is shown in FIG. 20. The corresponding interleaving latency is approximately 46*2*3 / 2=138 RS symbols. The convolutional interleaver shown in FIG. 20 separately performs convolutional interleaving on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to understand that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=4 first data stream subsets, where first data streams 0 to 7 are first data stream subset 0, first data streams 8 to 15 are first data stream subset 1, first data streams 16 to 23 are first data stream subset 2, and first data streams 24 to 31 are first data stream subset 3.

[0289] In this embodiment, the possible implementation of multiplexing shown in Figure 13 is as follows: G = 4, K = 2, and m = 16. Sixteen 2:1 multiplexers are included, each multiplexer multiplexing two first data streams to obtain one second data stream, generating a total of 16 second data streams. No. Any first data stream selected from each of any two of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3. The two first data streams areIt is used as an input to a 2:1 multiplexer. The corresponding specific embodiment of the 2:1 multiplexer is shown in Fig. 17(a). The multiplexed input data streams 0 and 1 of the 2:1 multiplexer i (0 ≦ i ≦ 15) respectively correspond to the first data stream i and the first data stream (i + 16). In the figure, [Number] represents six consecutive Δ = 6 RS symbols of the multiplexed input data stream j (0 ≦ j ≦ 1) of the 2:1 multiplexer, and the symbols are from six different external code RS codewords. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner for every six RS symbols, that is, the output data sequence is [Number] [[ID=ll]] as shown. The twelve consecutive RS symbols in the output data stream are from twelve different RS codewords. Note that since K < G, when Δ = 1, 2, or 3, the twelve consecutive RS symbols in the second data stream can still be from twelve different RS codes.

[0290] Internal code encoding is separately performed for the above-mentioned sixteen second data streams, and the internal code encoding method of the sixteen second data streams can use the encoding method provided in Embodiment 1 to obtain performance equivalent to that of Embodiment 1. Details are not described in this specification.

[0291] Embodiment 9: The application scenario is a 4 × 200G interface, the information bit length of the internal code encoding is 160 bits, a 2:1 multiplexer is used, and lane despooling is used.

[0292] Based on embodiment 8, in this embodiment, an inner code with a code length of 160 bits is considered, and a newly designed convolutional interleaver is used accordingly.

[0293] Specifically, in this embodiment, the convolutional interleaver structure shown in Figure 18(a) is used, and p = 4 delay lines are included. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbol, i.e., no delay.

[0294] As shown in Figure 18(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and C r (8t-24Q) and C r (8t-24Q+1) are the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (8t-16Q+2) and C r (8t-16Q+3) are the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r (8t-8Q+4) and C r (8t-8Q+5) are the two RS symbols output from delay line 2; C r (8t+6) and Cr (8t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 3, and C r (8t+6) and C r (8t+7) are the two RS symbols output from the delay line 3; C r (8t+8) and C r (8t+9) represents the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C r (8t-24Q+8) and C r (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to FIG. 7, when 8Q+2≧136, in other words, Q≧17, there are a total of eight RS symbols output by convolutional interleaving, C r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), and C r It can be seen that (8t+7) is from 8 different RS codewords.

[0295] Figure 21 is a schematic diagram of the tenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 21, in a possible implementation, Q=17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 21. The corresponding interleaving latency is approximately 51*2*4 / 2=204 RS symbols.

[0296] The convolutional interleaver shown in FIG. 21 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to see that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=4 first data stream subsets, where first data streams 0 to 7 are first data stream subset 0, first data streams 8 to 15 are first data stream subset 1, first data streams 16 to 23 are first data stream subset 2, and first data streams 24 to 31 are first data stream subset 3.

[0297] In this embodiment, the possible implementation of multiplexing shown in Figure 13 is as follows: G = 4, K = 2, and m = 16. Sixteen 2:1 multiplexers are included, each multiplexer multiplexing two first data streams to obtain one second data stream, generating a total of 16 second data streams. No. Any first data stream selected from each of any two of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3. The two first data streams are are used as inputs to a 2:1 multiplexer. A corresponding specific implementation of the 2:1 multiplexer is shown in Figure 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2:1 multiplexer i (0 < i < 15) correspond to first data stream i and first data stream (i + 16), respectively. In the figure,

number

Number

[0298] Inner code encoding is separately performed for the aforementioned 16 second data streams, and the inner code encoding method of the 16 second data streams can use the encoding method provided in Embodiment 3 to obtain performance equivalent to that of Embodiment 3. Details are not described herein.

[0299] Embodiment 10: The application scenario is a 4 × 20G interface, the information bit length of the inner code encoding is 160 bits, and lane symbol alignment is used.

[0300] Based on any one of Embodiments 7 to 9, this embodiment provides a solution for an embodiment with lower latency.

[0301] Based on the aforementioned schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(d), the transmitting-side processing module performs alignment marker lock on the eight lane data streams based on the known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 in this specification may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channels of 200G, respectively. The transmitting-side processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are directly sent to the designated processor, including multiplexing, for processing and then sent to the inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission.

[0302] In a possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 7, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 7, with a lower overall latency. However, the solution of this embodiment has poorer resistance to system burst errors than the solution of embodiment 7. This solution is applicable to some scenarios that require lower latency.

[0303] In another possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 8, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 8, and the overall latency is lower. However, the solution of this embodiment has poorer resistance to system burst errors than the solution of embodiment 8. This solution is applicable to some scenarios that require lower latency.

[0304] In yet another possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 9, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 9, with a lower overall latency. However, the solution of this embodiment has poorer resistance to system burst errors than the solution of embodiment 9. This solution is applicable to some scenarios that require lower latency.

[0305] Embodiment 11: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane deskew is used.

[0306] In this embodiment, the host interface is assumed to be an 8x100G interface with 100Gb / s per lane, and the "100G RS-FEC-Int" mode is used. For details of the interface, please refer to IEEE Std 802.3ck™ / D3.0.

[0307] Based on the aforementioned schematic data processing diagram of the transmitting side processing module shown in FIG. 3(c), the transmitting side processing module performs alignment marker lock for the four lane data stream based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channel of 100G, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering is performed on the data of the four lanes to arrange the data of the four lanes in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as that in FIG. 11. The 32 lane data streams after lane reordering are not convolutionally interleaved but are directly multiplexed to obtain a total of 16 second data streams, which are then sent to the inner code encoder for inner code encoding.After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission.

[0308] See the PCS lane data streams shown in Figure 8. It is not difficult to see that any RS symbol in lane data streams 0 through 3, any RS symbol in lane data streams 4 through 7, any RS symbol in lane data streams 8 through 11, any RS symbol in lane data streams 12 through 15, any RS symbol in lane data streams 16 through 19, any RS symbol in lane data streams 20 through 23, any RS symbol in lane data streams 24 through 27, and any RS symbol in lane data streams 28 through 31 are all from different RS codewords. Because no convolutional interleaving is performed on the lane data streams, lane data streams 0 through 31 are equivalent to the first data streams 0 through 31. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0309] 13 used in this embodiment is as follows: G=8, K=8, m=4, and multiplexing is performed on 32 lane data streams to obtain four second data streams. As the eight input data streams of 8:1 multiplexer i (0≦i≦3), No. one data stream in first data stream subset 0, one data stream in first data stream subset 1, one data stream in first data stream subset 2, one data stream in first data stream subset 3, one data stream in first data stream subset 4, one data stream in first data stream subset 5, one data stream in first data stream subset 6, and one data stream in first data stream subset 7 A total of eight lane data streams is used. A specific embodiment is shown in Figure 17(c). Multiplexer i (0≦i≦3) corresponds to the multiplexed input data streams 0 to 7 of the 8:1 multiplexer using first data stream i, first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively. In the figure,

number

number

[0310] 22 is a schematic diagram of a fifth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 22, multiplexer i (0≦i≦3) corresponds to multiplexed input data streams 0 to 7 of the 8:1 multiplexer using first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28), respectively. In the figure,

number

number

[0311] The inner code encoding is performed separately on the four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain the same performance as embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain the same performance as embodiment 3, and details will not be described herein.

[0312] Embodiment 12: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, a 4:1 multiplexer is used, and lane deskew is used.

[0313] Based on the solution of embodiment 11, this embodiment provides a second low latency implementation solution when a 4:1 multiplexer is used for multiplexing.

[0314] Based on the aforementioned schematic data processing diagram of the transmitting side processing module shown in FIG. 3(a), the transmitting side processing module performs alignment marker lock for the four lane data stream based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channel of 100G, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering is performed on the data of the four lanes so that the data of the four lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in FIG. 11 .

[0315] The 32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data streams, the data processed data streams are sent to a channel transmission medium for transmission.

[0316] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. FIG. 19(a) shows the configuration of a convolutional interleaver including p=2 delay lines. The two delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbol, i.e., no delay.

[0317] As shown in Figure 19(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (4t) and C r (4t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C r (4t+2) and C r (4t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (4t+2) and C r (4t+3) are the two RS symbols output from delay line 1; Cr (4t+4) and C r (4t+5) represents two RS symbols in the lane data stream subsequently input to delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, it can be seen that when 4Q+2 ≥ 272, i.e., Q ≥ 68, the four consecutive RS symbols output via convolutional interleaving, Cr(4t-4Q), Cr(4t-4Q+1), Cr(4t+2), and Cr(4t+3), are from four different RS codewords.

[0318] Figure 23 is a schematic diagram of an eleventh structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 23, in a possible implementation, its Q=68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 23. The corresponding interleaving latency is approximately 68*2*2 / 2=136 RS symbols.

[0319] The convolutional interleaver shown in Figure 23 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in Figure 8. It is not difficult to see that any RS symbol in lane data streams 0 through 3, any RS symbol in lane data streams 4 through 7, any RS symbol in lane data streams 8 through 11, any RS symbol in lane data streams 12 through 15, any RS symbol in lane data streams 16 through 19, any RS symbol in lane data streams 20 through 23, any RS symbol in lane data streams 24 through 27, and any RS symbol in lane data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0320] In this embodiment, the possible implementations of multiplexing shown in Figure 13 are as follows: G = 8, K = 4, and m = 8. Eight 4:1 multiplexers are included, each multiplexer multiplexing four first data streams to obtain one second data stream, generating a total of eight second data streams. No. Any first data stream selected from each of any four of data stream subsets 0 through 7 of 1 The four first data streams areare used as inputs to the 4:1 multiplexer. A specific embodiment is shown in Figure 17(b). The multiplexed input data streams 0 to 3 of the 4:1 multiplexer i (0≦i≦7) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), and the first data stream (i+24), respectively. In the figure,

number

number

[0321] 24 is a schematic diagram of a sixth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 24, multiplexer i (0≦i≦3) uses first data stream i, first data stream (i+8), first data stream (i+16), and first data stream (i+24) to correspond to multiplexed input data streams 0 to 3 of the 4:1 multiplexer, respectively. In the figure,

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[0322] The inner code encoding is performed separately on the aforementioned eight second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain the same performance as embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain the same performance as embodiment 3, and details will not be described herein.

[0323] Embodiment 13: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

[0324] Based on embodiment 12, it is considered that in this embodiment, a 2:1 multiplexer and an inner code with an information length of 120 bits are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are used correspondingly.

[0325] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. FIG. 16(a) shows the configuration of a convolutional interleaver including p=3 delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

[0326] As shown in Figure 16(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (6t) and C r (6t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and C r (6t-12Q) and C r (6t-12Q+1) are the two RS symbols output from delay line 0; C r (6t+2) and C r (6t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (6t-6Q+2) and C r (6t-6Q+3) are the two RS symbols output from delay line 1; C r (6t+4) and C r (6t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r (6t+4) and C r (6t+5) are the two RS symbols output from delay line 2; C r(6t+6) and C r (6t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to FIG. 8, if 6Q+2≧272, in other words, Q≧45, then there are a total of six RS symbols C output by the convolutional interleaving. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be seen that (6t+5) are from 6 different RS codewords.

[0327] Figure 25 is a schematic diagram of the twelfth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 25, in a possible implementation, its Q=45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 25. The corresponding interleaving latency is about 90*2*3 / 2=270 RS symbols.

[0328] The convolutional interleaver shown in Figure 25 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in Figure 8. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0329] In this embodiment, the possible implementations of multiplexing shown in Figure 13 are as follows: G = 8, K = 2, and m = 16. Sixteen 2:1 multiplexers are included, each multiplexer multiplexing two first data streams to obtain one second data stream, generating a total of 16 second data streams. No. Any first data stream selected from each of any two of data stream subsets 0 to 7 of 1 The two first data streams areare used as inputs to the 2:1 multiplexer. A corresponding specific implementation of the 2:1 multiplexer is shown in Figure 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2:1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,

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[0330] The solution for encoding the 16 second data streams output by multiplexing can use the solution of embodiment 1 and obtain performance equivalent to that of embodiment 1, and the details will not be described again in this specification.

[0331] Embodiment 14: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 160 bits, a 2:1 multiplexer is used, and lane deskew is used.

[0332] Based on embodiment 12, it is considered that in this embodiment, a 2:1 multiplexer and an inner code with an information length of 160 bits are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are used correspondingly.

[0333] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. FIG. 18(a) shows a convolutional interleaver configuration including p=4 delay lines. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbol, i.e., no delay.

[0334] As shown in Figure 18(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and C r (8t-24Q) and C r (8t-24Q+1) are the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents the two RS symbols in the lane data stream that are input after delay line 1, and C r (8t-16Q+2) and C r(8t-16Q+3) are the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents the two RS symbols in the lane data stream that are input after delay line 2, and C r (8t-8Q+4) and C r (8t-8Q+5) are the two RS symbols output from delay line 2; C r (8t+6) and C r (8t+7) represents the two RS symbols in the lane data stream that are subsequently input to delay line 3, and C r (8t+6) and C r (8t+7) are the two RS symbols output from the delay line 3; C r (8t+8) and C r (8t+9) represents the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C r (8t-24Q+8) and C r (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to FIG. 8, if 8Q+2≧272, in other words, Q≧34, then there are a total of eight RS symbols C output by the convolutional interleaving. r (8t-24Q), C r (8t-24Q+1), C r (8t-24Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), and C r It can be seen that (8t+7) is from 8 different RS codewords.

[0335] Figure 26 is a schematic diagram of the thirteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 26, in a possible implementation, its Q=34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 26. The corresponding interleaving latency is about 102*2*4 / 2=408 RS symbols.

[0336] The convolutional interleaver shown in Figure 26 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in Figure 8. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0337] In this embodiment, the possible implementations of multiplexing shown in Figure 13 are as follows: G = 8, K = 2, and m = 16. Sixteen 2:1 multiplexers are included, each multiplexer multiplexing two first data streams to obtain one second data stream, generating a total of 16 second data streams. No. Any first data stream selected from each of any two of data stream subsets 0 to 7 of 1 The two first data streams are are used as inputs to the 2:1 multiplexer. A corresponding specific implementation of the 2:1 multiplexer is shown in Figure 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2:1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,

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[0338] The method of performing inner code encoding on the 16 second data streams output by multiplexing can use the inner code encoding method of embodiment 3, and obtain performance equivalent to that of embodiment 3, and the details will not be described again in this specification.

[0339] Embodiment 15: The application scenario is an 8x100G interface, and lane symbol alignment is used.

[0340] Based on any of the embodiments 11 to 14, this embodiment provides a solution for implementation with lower latency.

[0341] Based on the aforementioned schematic data processing diagram of the transmitting-side processing module shown in FIG. 3(b), the transmitting-side processing module performs alignment marker lock on the four lane data streams based on known alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. The transmitting-side processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, which are then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission.

[0342] In this embodiment, when the processor including the convolutional interleaving, multiplexing and inner code encoding is the same as that of the solution of embodiment 11, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 11, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0343] In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those of the solution in embodiment 12, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution in embodiment 12, but the solution in this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0344] In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those of the solution in embodiment 13, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution in embodiment 13, but the solution in this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0345] In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those of the solution in embodiment 14, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution in embodiment 14, but the solution in this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0346] Embodiment 16: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane deskew is used.

[0347] In this embodiment, the host interface is an 8x100G interface with 100Gb / s per lane, and it is assumed that "100G RS-FEC" mode is used. For details of the interface, please refer to IEEE Std 802.3ck™ / D3.0.

[0348] Based on the aforementioned schematic data processing diagram of the transmitting side processing module shown in FIG. 3(a), the transmitting side processing module performs alignment marker lock for the four lane data stream based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channel of 100G, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering is performed on the data of the four lanes so that the data of the four lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in FIG. 9 .

[0349] The 32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data streams, the data processed data streams are sent to a channel transmission medium for transmission.

[0350] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 FEC lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0351] 27(a) is a schematic diagram of a fourteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 27(a), p=2 delay lines are included. The two delay lines include Q storage units and 0 storage units, respectively, and each storage unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0352] As shown in Figure 27(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (2t) represents one RS symbol in the lane data stream currently input to delay line 0, and C r (2t-2Q) is one RS symbol output from delay line 0; C r (2t+1) represents one RS symbol in the lane data stream input after delay line 1, and C r(2t+1) is one RS symbol output from delay line 1; C r (2t+2) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, and C r (2t-2Q+2) is one RS symbol output from delay line 0; and so on. Referring to FIG. 9, when 2Q+1≧136, i.e., Q≧68, two consecutive RS symbols, C r (2t-2Q) and C r It can be seen that (2t+1) are from two different RS codewords.

[0353] Figure 27(b) is a schematic diagram of a fifteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 27(b), in a possible implementation, Q=68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 27(b). The corresponding interleaving latency is approximately 68*2 / 2=68 RS symbols.

[0354] The convolutional interleaver shown in Figure 27(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0355] In this embodiment, the 8:1 multiplexing processing structure of embodiment 11 is used, and four second data streams can be obtained, and all 16 consecutive RS symbols in each second data stream are from 16 different RS code words.

[0356] The inner code encoding is performed separately on the four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain the same performance as embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain the same performance as embodiment 3, and details will not be described herein.

[0357] Embodiment 17: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits, a 4:1 multiplexer is used, and lane deskew is used.

[0358] Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0359] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0360] 28(a) is a schematic diagram of a sixteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 28(a), p=3 delay lines are included. The p=3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 2Q symbols, the delay value of delay line 1 is Q symbols, and the delay value of delay line 1 is 0 symbol, i.e., no delay.

[0361] As shown in Figure 28(a), C r(·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, Cr(3t) represents one RS symbol in the lane data stream currently input to delay line 0, and Cr(3t−6Q) is one RS symbol output from delay line 0; Cr(3t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, and Cr(3t−3Q+1) is one RS symbol output from delay line 1; Cr(3t+2) represents one RS symbol in the lane data stream subsequently input to delay line 2, and Cr(3t+2) is one RS symbol output from delay line 2; Cr(3t+3) represents one RS symbol in the lane data stream subsequently input to delay line 0, and Cr(3t−6Q+3) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, it can be seen that when 3Q+1≧136, i.e., Q≧45, the total three RS symbols output through convolutional interleaving, Cr(3t-6Q), Cr(3t-3Q+2), and Cr(3t+2), are from three different RS codewords.

[0362] Figure 28(b) is a schematic diagram of the seventeenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 28(b), in a possible implementation, Q=45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 28(b). The corresponding interleaving latency is approximately 90*3 / 2=135 RS symbols.

[0363] The convolutional interleaver shown in Figure 28(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0364] In this embodiment, the multiplexing processing structure of embodiment 12 is used, and when Δ=1 or 3, eight second data streams can be obtained, and all 12 consecutive RS symbols in each second data stream are from 12 different RS code words.

[0365] The solution for encoding the eight second data streams output by multiplexing can use the solution of embodiment 1 and obtain performance equivalent to that of embodiment 1, and the details will not be described again in this specification.

[0366] Embodiment 18: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 160 bits, a 4:1 multiplexer is used, and lane deskew is used.

[0367] Based on the solution of embodiment 16, this embodiment provides a solution of an embodiment with a second low latency, in which the length of the inner code information is 160 bits, and a 4:1 multiplexer is used for multiplexing, and a newly designed interleaver and multiplexing are used correspondingly.

[0368] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0369] 29(a) is a schematic diagram of an eighteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 29(a), p=4 delay lines are included. The p=4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 3Q symbols, the delay value of delay line 1 is 2Q symbols, the delay value of delay line 2 is Q symbols, and the delay value of delay line 3 is 0 symbol, i.e., no delay.

[0370] As shown in Figure 29(a), C r(·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (4t) represents one RS symbol in the lane data stream currently input to delay line 0, and Cr(4t-12Q) is one RS symbol output from delay line 0; C r (4t+1) represents one RS symbol in the lane data stream input after delay line 1, and Cr(4t-8Q+1) is one RS symbol output from delay line 1; C r (4t+2) represents one RS symbol in the lane data stream that subsequently enters delay line 2, and Cr(4t-4Q+2) is one RS symbol output from delay line 2; C r (4t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, and C r (4t+3) is one RS symbol output from delay line 3; C r 4t+4) represents one RS symbol in the lane data stream that subsequently enters delay line 0, Cr(4t-12Q+4) is one RS symbol output from delay line 0, and so on. Referring to FIG. 9, if 4Q+1≧136, i.e., Q≧34, then there are a total of four RS symbols, C r (4t-12Q), C r (4t-8Q+1), C r (4t-4Q+2), and C r It can be seen that (4t+3) are from four different RS codewords.

[0371] Figure 29(b) is a schematic diagram of the 19th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 29(b), in a possible implementation, its Q=34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 29(b). The corresponding interleaving latency is approximately 102*4 / 2=204 RS symbols.

[0372] The convolutional interleaver shown in Figure 29(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0373] In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ=1, 2 or 4, eight second data streams can be obtained, and all 16 consecutive RS symbols in each second data stream are from 16 different RS code words.

[0374] The inner code encoding is performed separately on the aforementioned eight second data streams, and the inner code encoding method of the eight second data streams can use the inner code encoding method provided in embodiment 3 to obtain the same performance as embodiment 3. Details will not be described in this specification.

[0375] Embodiment 19: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

[0376] Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0377] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0378] 30(a) is a schematic diagram of a twentieth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 30(a), p=6 delay lines are included. The p=6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 5Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 3Q symbols, the delay value of delay line 3 is 2Q symbols, the delay value of delay line 4 is Q symbols, and the delay value of delay line 5 is 0 symbol, i.e., no delay.

[0379] As shown in Figure 30(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (6t) represents one RS symbol in the lane data stream currently input to delay line 0, and C r (6t-30Q) is one RS symbol output from delay line 0; C r (6t+1) represents one RS symbol in the lane data stream input after delay line 1, and C r (6t-24Q+1) is one RS symbol output from delay line 1; C r (6t+2) represents one RS symbol in the lane data stream that subsequently enters delay line 2, and C r (6t-18Q+2) is one RS symbol output from delay line 2; C r (6t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, and C r (6t-12Q+3) is one RS symbol output from delay line 3; C r (6t+4) represents one RS symbol in the lane data stream that subsequently enters delay line 4, and C r (6t-6Q+4) is one RS symbol output from delay line 4; C r (6t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, and C r (6t+5) is one RS symbol output from delay line 5; C r (6t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, and C r (6t-30Q+6) is one RS symbol output from delay line 0; and so on. Referring to FIG. 9, when 6Q+1≧136, i.e., Q≧23, a total of six RS symbols, C r (6t-30Q), C r(6t-24Q+1), C r It can be seen that (6t-18Q+2) are from 6 different RS codewords.

[0380] Figure 30(b) is a schematic diagram of the 21st structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 30(b), in a possible implementation, its Q=23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 30(b). The corresponding interleaving latency is approximately 23*5*6 / 2=345 RS symbols.

[0381] The convolutional interleaver shown in Figure 30(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0382] In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ=1, 2, 3 or 6, 16 second data streams can be obtained, and all 12 consecutive RS symbols in each second data stream are from 12 different RS code words.

[0383] The inner code encoding is performed separately on the above-mentioned 16 second data streams, and the encoding method of the 16 second data streams can use the inner code encoding method provided in embodiment 1 to obtain the same performance as embodiment 1. Details will not be described in this specification.

[0384] Embodiment 20: The application scenario is an 8×100G interface, the information bit length of the inner code encoding is 160 bits, a 2:1 multiplexer is used, and lane deskew is used.

[0385] Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 160 bits and a 2:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0386] 11 is used for convolutional interleaving, and convolutional interleaving is performed separately on n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0387] 31(a) is a schematic diagram of a 22nd structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 31(a), p=8 delay lines are included. The p=8 delay lines include 7Q storage units, 6Q storage units, 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 7Q symbols, the delay value of delay line 1 is 6Q symbols, the delay value of delay line 2 is 5Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 3Q symbols, the delay value of delay line 5 is 2Q symbols, the delay value of delay line 6 is Q symbols, and the delay value of delay line 7 is 0 symbols, i.e., no delay.

[0388] As shown in Figure 31(a), C r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C r (8t) represents one RS symbol in the lane data stream currently input to delay line 0, and C r (8t-56Q) is one RS symbol output from delay line 0; C r (8t+1) represents one RS symbol in the lane data stream input after delay line 1, and C r (8t-48Q+1) is one RS symbol output from delay line 1; C r (8t+2) represents one RS symbol in the lane data stream that subsequently enters delay line 2, and C r (8t-40Q+2) is one RS symbol output from delay line 2; C r (8t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, and C r (8t-32Q+3) is one RS symbol output from delay line 3; C r(8t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 4, and C r (8t-24Q+4) is one RS symbol output from delay line 4; C r (8t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, and C r (8t-16Q+5) is one RS symbol output from delay line 5; C r (8t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 6, and C r (8t-8Q+6) is one RS symbol output from delay line 6; C r (8t+7) represents one RS symbol in the lane data stream that is subsequently input to delay line 7, and C r (8t+7) is one RS symbol output from delay line 7; C r (8t+8) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, and C r (8t-56Q+8) is one RS symbol output from delay line 0; and so on. Referring to FIG. 9, if 8Q+1≧136, i.e., Q≧17, then there are a total of eight RS symbols C output consecutively via convolutional interleaving. r (8t-56Q), C r (8t-48Q+1), C r (8t-40Q+2), C r (8t-32Q+3), C r (8t-24Q+4), C r (8t-16Q+5), C r (8t-8Q+6), and C r It can be seen that (8t+7) is from 8 different RS codewords.

[0389] Figure 31(b) is a schematic diagram of the 23rd structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 31(b), in a possible implementation, Q=17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 31(b). The corresponding interleaving latency is approximately 17*7*8 / 2=476 RS symbols.

[0390] The convolutional interleaver shown in Figure 31(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, with first data streams 0 to 3 in first data stream subset 0, first data streams 4 to 7 in first data stream subset 1, first data streams 8 to 11 in first data stream subset 2, first data streams 12 to 15 in first data stream subset 3, first data streams 16 to 19 in first data stream subset 4, first data streams 20 to 23 in first data stream subset 5, first data streams 24 to 27 in first data stream subset 6, and first data streams 28 to 31 in first data stream subset 7.

[0391] In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ=1, 2, 3 or 8, 16 second data streams can be obtained, and all 16 consecutive RS symbols in each second data stream are from 16 different RS code words.

[0392] The inner code encoding is performed separately on the above-mentioned 16 second data streams, and the inner code encoding method of the 16 second data streams can use the inner code encoding method provided in embodiment 3 to obtain the same performance as embodiment 3. Details will not be described in this specification.

[0393] Embodiment 21: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, and lane symbol alignment is used.

[0394] Based on the solution in any of embodiments 16 to 20, this embodiment provides an implementation solution with lower latency.

[0395] Based on the aforementioned schematic data processing diagram of the transmitting-side processing module shown in FIG. 3(d), the transmitting-side processing module performs alignment marker lock on the four lane data streams based on known alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. Then, the transmitting-side processing module performs one symbol-based alignment on the 32 lane data streams to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, which are then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission.

[0396] It should be understood that the multiplexing and inner code encoding schemes used in this embodiment both use the solutions provided in any one of embodiments 16 to 20.

[0397] In this embodiment, when the processor including multiplexing and inner code encoding are the same as those of the solution of embodiment 16, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 16, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0398] In this embodiment, when the processor including multiplexing and inner code encoding are the same as those of the solution of embodiment 17, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 17, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0399] In this embodiment, when the processor including multiplexing and inner code encoding are the same as those of the solution of embodiment 18, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 18, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0400] In this embodiment, when the processor including multiplexing and inner code encoding are the same as those of the solution of embodiment 19, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 19, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0401] In this embodiment, when the processor including multiplexing and inner code encoding are the same as those of the solution of embodiment 20, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution of embodiment 20, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

[0402] It should be noted that in some possible implementations, the multiplexing described in the above embodiments may also be replaced by block interleaving for implementation purposes. Hereinafter, a description will be provided with reference to specific embodiments.

[0403] 32(a) is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application. As shown in FIG. 32(a), block interleaving may be performed through m parallel block interleaving modules. Specifically, each block interleaver generates one second data stream after performing block interleaving on K input first data streams, thereby obtaining a total of m second data streams. The manner of selecting the K first data streams to be input to each block interleaver is consistent with the manner of selecting the K input multiplexed data streams to be input to the multiplexer in the above embodiment, and details will not be described again in this specification.

[0404] 32(b) is a schematic diagram of the structure of a block interleaver according to an embodiment of the present application. As shown in FIG. 32(b), the first data stream i k Consecutive ΔRS symbols in are a symbol subset, and S k (.), where 0≦k≦K-1. Therefore, S k (0), S k (1), ..., S k (W) is the first data stream i k represents W consecutive symbol subsets output from the first data stream. Consecutive ΔRS symbols in the second data stream are one symbol subset, denoted by S(.). W symbol subsets ...

Claims

1. 1. A data processing method comprising: performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams to obtain a total of m first data streams, where n=q*t and m=q*s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2, and s is an integer greater than or equal to 1; performing first forward error correction (FEC) encoding on all of the n lane data streams, where every a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 2; wherein every a consecutive symbols in each lane data stream are from a different codeword, and every L1 consecutive symbols in each lane data stream are from at least a different codewords, where L1 = N*a / b, and N represents the length of the codeword, and the t lane data streams comprise a total of t*a symbols, where the a consecutive symbols in each lane data stream are, and the t*a symbols comprise a total of D bits, for Δ bits in each symbol, and D = Δ*t*a, and the D bits are consecutive in any one of the s first data streams, and Δ = M / s, and M represents the number of bits comprised in a symbol; separately performing convolutional interleaving on the m first data streams to obtain m second data streams; A data processing method comprising:

2. 2. The data processing method of claim 1, wherein all d consecutive symbols in each first data stream are from v different codewords, every L2 consecutive symbols in each first data stream are from at least v different codewords, v is exactly divisible by a, L2 = t / s * L1, and d = D / M.

3. 2. The method of claim 1, wherein n=32, 16 lane data streams within odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams within even-numbered lanes of the n lane data streams are from the same codeword, and the data streams within the odd-numbered lanes of the n lane data streams and the data streams within the even-numbered lanes of the n lane data streams are from different codewords.

4. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and in the first data stream obtained by block interleaving, a total of 16 consecutive symbols are two consecutive symbols comprised in each of the eight lane data streams, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and every 544 consecutive symbols are from at least four different codewords; wherein the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords. The method of claim 3, comprising:

5. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, a total of 16 symbols, which are j-th two consecutive symbol groups comprised in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, and j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving the symbols are from at least four different codewords, and every 544 consecutive symbols are from at least four different codewords; the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords.are from different codewords, The method of claim 3, comprising:

6. t=8, s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain the s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and a total of eight symbols, which is a jth symbol included in each of the eight lane data streams, are interleaved by the block interleaving. and j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, and the zeroth, first, second, and third symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the fourth, fifth, sixth, and seventh symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords. The method of claim 3, comprising:

7. 2. The method of claim 1, wherein n=32, 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, 16 consecutive lane data streams sorted at the back of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the back of the n lane data streams are from different codewords.

8. where t=2 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, and two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained by block interleaving, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords; The method of claim 7, comprising:

9. where t=2 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, a jth group of consecutive β bits in the ith lane data stream and a jth group of consecutive β bits in the (i+16)th lane data stream are consecutive in the first data stream obtained by block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords; The method of claim 7, comprising:

10. where t=2 and s=2, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain a (2*i)-th first data stream and a (2*i+1)-th first data stream, wherein 0≦i<16, in the (2*i)-th first data stream, four symbols are consecutive: five bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits; and every 20 consecutive bits in the (2*i)-th first data stream are from four different codewords; and in the (2*i+1)-th first data stream, four symbols are consecutive: two consecutive symbols in the i-th lane data stream and another five bits in each of two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits; and every 20 consecutive bits in the (2*i+1)-th first data stream are from four different codewords. The method of claim 7, comprising:

11. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and in the first data stream obtained by block interleaving, a total of 16 consecutive symbols are two consecutive symbols comprised in each of the eight lane data streams, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and every 544 consecutive symbols are from at least four different codewords; wherein the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords. The method of claim 7, comprising:

12. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, a total of 16 symbols, which are j-th two consecutive symbol groups comprised in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, and j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving. the symbols in the first data stream obtained by block interleaving are from at least four different codewords, every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.are from different codewords, The method of claim 7, comprising:

13. t=8, s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain the s first data streams includes: performing block interleaving on a total of eight lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and a total of eight symbols, which are j-th symbols included in each of the eight lane data streams, are interleaved with the first data stream obtained by the block interleaving; and j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and the zeroth, first, second, and third symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the fourth, fifth, sixth, and seventh symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords. The method of claim 7, comprising:

14. performing convolutional interleaving on a first data stream to obtain a second data stream; delaying one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line has a different number of storage units, the delay line with the fewest number of storage units has 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, each delay line inputs d symbols once and outputs d symbols once, p*d consecutive symbols in the second data stream comprise the d symbols output from the delay lines, and Q is an integer greater than or equal to 1; The method of claim 1 , comprising:

15. performing convolutional interleaving on a first data stream to obtain a second data stream; delaying one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line has a different number of storage units, the delay line with the fewest number of storage units has 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store 4 symbols, symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, each delay line inputs 4 symbols once and outputs 4 symbols once, p*4 consecutive symbols in the second data stream comprise the 4 symbols output from the delay lines, where Q satisfies 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544; The method of claim 1 , comprising:

16. After the step of separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further comprises: separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein information data of length K symbols in each of the coded data streams is from up to K different codewords, where K≧p*4; The method of claim 15 further comprising:

17. performing convolutional interleaving on a first data stream to obtain a second data stream; delaying one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and the number of storage units provided in each delay line is different, the delay line with the fewest number of storage units has 0 storage units, and the difference in the number of storage units between every two adjacent delay lines is Q; 2. The method of claim 1, wherein each storage unit is configured to store 34 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 34 bits input to each delay line once and 34 bits output from each delay line once, and p*34 consecutive bits in one second data stream comprising the 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 68 bits input to each delay line once and 68 bits output from each delay line once, and p*68 consecutive bits in one second data stream comprising the 68 bits output from the delay lines.

18. The method of claim 1, wherein t is 2, 4, or 8.

19. The method of claim 1, wherein s is 1.

20. 1. A data processing apparatus comprising a block interleaver and a convolutional interleaver, the block interleaver is configured to perform block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams, to obtain a total of m first data streams, where n=q*t and m=q*s, where n is an integer greater than 1 and n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2, and s is an integer greater than or equal to 1; first forward error correction (FEC) encoding is performed on all the n lane data streams, and every a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, and n is exactly divisible by b; a is an integer greater than or equal to 2, every a consecutive symbols in each lane data stream are from a different codeword, and every L1 consecutive symbols in each lane data stream are from at least a different codewords, where L1 = N*a / b, and N represents the length of the codeword, the t lane data streams comprise a total of t*a symbols, where the a consecutive symbols in each lane data stream are, the t*a symbols comprise a total of D bits, for Δ bits in each symbol, and D = Δ*t*a, and the D bits are consecutive in any one of the s first data streams, where Δ = M / s, and M represents the number of bits comprised in a symbol; and A data processing apparatus configured to separately perform a convolutional interleaver on said m first data streams to obtain said m second data streams.

21. 21. The data processing apparatus of claim 20, wherein every d consecutive symbols in each first data stream are from v different codewords, and every L2 consecutive symbols in each first data stream are from at least v different codewords, where v is exactly divisible by a, L2 = t / s * L1, and d = D / M.

22. 21. The data processing device of claim 20, wherein n=32, 16 lane data streams in odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams in even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

23. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving, two consecutive symbols comprised in each of the eight lane data streams are 16 consecutive symbols in total, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different code words, and every 544 consecutive symbols are from at least four different code words. wherein the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

23. A data processing apparatus according to claim 22, specifically configured to:

24. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, wherein 0≦i≦3, and in the first data stream obtained by the block interleaving, a total of 16 symbols, which are j-th two consecutive symbol groups included in each of the eight lane data streams, are consecutive, and the j-th two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by the block interleaving, and j≧0, and every 16 consecutive symbols in the first data stream obtained by the block interleaving the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords;are from different codewords, 23. A data processing apparatus according to claim 22, specifically configured to:

25. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream; and a total of eight symbols, where 0≦i≦3 and j-th symbols included in each of the eight lane data streams, are used as the first data stream obtained by the block interleaving. j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

23. A data processing apparatus according to claim 22, specifically configured to:

26. 21. The data processing apparatus of claim 20, wherein n=32, 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, 16 consecutive lane data streams sorted at the back of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the back of the n lane data streams are from different codewords.

27. t=2, s=1, and the block interleaver is performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, and two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained by the block interleaving, and every fourth consecutive symbol in the first data stream obtained by the block interleaving is from four different codewords; 27. A data processing apparatus according to claim 26, specifically adapted to:

28. t=2, s=1, and the block interleaver is performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, a jth group of consecutive β bits in the ith lane data stream and a jth group of consecutive β bits in the (i+16)th lane data stream are consecutive in the first data stream obtained by block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords; 27. A data processing apparatus according to claim 26, specifically adapted to:

29. t=2, s=2, and the block interleaver is performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain a (2*i)-th first data stream and a (2*i+1)-th first data stream, wherein 0≦i<16; four symbols: five bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits, are consecutive in the (2*i)-th first data stream, and every 20 consecutive bits in the (2*i)-th first data stream are from four different codewords; and four symbols: another five bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits, are consecutive in the (2*i+1)-th first data stream, and every 20 consecutive bits in the (2*i+1)-th first data stream are from four different codewords; 27. A data processing apparatus according to claim 26, specifically adapted to:

30. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, where 0≦i≦3, and in the first data stream obtained by block interleaving, a total of 16 consecutive symbols are two consecutive symbols in each of the eight lane data streams, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and every 544 consecutive symbols are from at least four different codewords. the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

27. A data processing apparatus according to claim 26, specifically adapted to:

31. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, wherein 0≦i≦3, and in the first data stream obtained by the block interleaving, a total of 16 symbols, which are j-th two consecutive symbol groups included in each of the eight lane data streams, are consecutive, and the j-th two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by the block interleaving, and j≧0, and every 16 consecutive symbols in the first data stream obtained by the block interleaving. the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords;are from different codewords, 27. A data processing apparatus according to claim 26, specifically adapted to:

32. t=8, s=1, and the block interleaver is To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream; and a total of eight symbols, where 0≦i≦3 and jth symbols included in each of the eight lane data streams, are used as the first data stream obtained by the block interleaving. and j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

27. A data processing apparatus according to claim 26, specifically adapted to:

33. The convolutional interleaver comprises: To obtain one second data stream, one first lane data stream is delayed based on p delay lines, where p is an integer greater than 1, and the number of storage units included in each delay line is different, with the delay line with the fewest number of storage units including 0 storage units, and the difference in the number of storage units between every two adjacent delay lines is Q, and each storage unit is configured to store d symbols, and symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with d symbols input to each delay line once and d symbols output from the delay lines once, and p*d consecutive symbols in the second data stream include the d symbols output from the delay lines, and Q is an integer greater than or equal to 1.

21. A data processing apparatus according to claim 20, specifically configured to:

34. The convolutional interleaver comprises: delaying one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line having a different number of storage units, with the delay line having the fewest number of storage units having 0 storage units, and the difference in the number of storage units between every two adjacent delay lines being Q, each storage unit being configured to store 4 symbols, the symbols in each lane data stream being input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 4 symbols being input to each delay line once and 4 symbols being output from the delay lines once, p*4 consecutive symbols in the second data stream comprising the 4 symbols being output from the delay line, where Q satisfies 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544; 21. A data processing apparatus according to claim 20, configured to:

35. The data processing apparatus further comprises an encoder, wherein after the m second data streams are obtained, the encoder separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein the information data having a length of K symbols in each of the coded data streams is from up to K different codewords, where K≧p*4; 35. A data processing apparatus according to claim 34, configured to:

36. The convolutional interleaver comprises: A first data stream is delayed based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and the number of storage units provided in each delay line is different, the delay line with the smallest number of storage units has 0 storage units, and the difference in the number of storage units between every two adjacent delay lines is Q; 21. The data processing apparatus of claim 20, wherein each storage unit is configured to store 34 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 34 bits input to each delay line once and 34 bits output from each delay line once, and p*34 consecutive bits in one second data stream comprising the 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 68 bits input to each delay line once and 68 bits output from each delay line once, and p*68 consecutive bits in one second data stream comprising the 68 bits output from the delay lines.

37. The data processing device of claim 20, wherein t is 2, 4, or 8.

38. A data processing apparatus as claimed in claim 20, wherein s is 1.

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