Systems and methods for low latency decoding of tail-biting convolutional codes

Abstract

Communication systems that utilize receivers for decoding short block length messages are disclosed. In many embodiments, the receiver includes an antenna for receiving encoded data, via RF signals, a demodulator for obtaining symbols from the RF signal, a demapper for generating symbol metrics, and a parallel list decoder. In several embodiments, the parallel list decoder processes multiple trellis stages simultaneously, enabling efficient decoding of the symbol metrics to obtain received, bits. In certain embodiments, the parallel list decoder divides the decoding trellis into segments, processes these segments independently, and combines them pairwise to form new segments. This parallel processing approach can allow for reduced decoding latency and improved efficiency in handling short block length messages. making it particularly suitable for applications requiring rapid data exchange and low-latency communication.

Description

nd Methods for Low Latency Decoding of Tail-biting Convolutional CodesFIELD OF THE INVENTION

[0001] The present invention relates generally to digital communications and, more specifi-cally, to digital communications involving the transmission of short-block-length messages.BACKGROUND

[0002] Digital communication systems are utilized to transfer data over a communicationchannel, such as (but not limited to) an optical, wired, and / or wireless communicationchannel. The Shannon-Hartley theorem enables a determination of the maximum rate atwhich information can be transmitted over a communication channel of a specified bandwidthin the presence of noise. The theorem establishes Shannon’s channel capacity for such acommunication link, which is a bound on the maximum amount of substantially error-freeinformation per time unit that can be transmitted with a specified bandwidth in the presenceof noise, assuming that the signal power is bounded (i.e. the maximum capacity of thechannel at a given signal-to-noise (SNR) ratio).

[0003] FEC, or channel coding, is a technique that can be used for controlling errors in datatransmission over unreliable or noisy channels. Shannon’s theorem predicts the maximumpossible efficiency that can be achieved by a Forward Error Correction (FEC) code but doesnot provide any insights into how to design such a code. Accordingly, coding theorists haveattempted to develop FECs that can achieve efficiency approaching the Shannon limit.

[0004] Block codes are a category of FEC that work on afixed-size number of bits orsymbols. Practical block codes can generally be hard-decoded in polynomial time based onblock length. Convolutional codes are a type of FEC that typically work on bit or symbolstreams, which can be of arbitrary length and are often soft-decoded using an algorithm suchas (but not limited to) the Viterbi algorithm. A convolutional code that is terminated can beconsidered to be a block code in that it encodes afixed-size block of input data, but the blockcode is generally arbitrary. Types of termination for convolutionalcodes include “tail-biting” and “zero-state termination.”

[0005] During the 1990s, a number of different classes of capacity-approaching codes werediscovered, or in the case of (Low-Density Parity Check) LDPC codes were rediscovered.The use of large block-length capacity-approaching codes significantly increased data ratesthat could be achieved within digital communication systems. Modern linear block codes,such as LDPC and Polar codes, are considered to be one class of “capacity-approaching”codes. A distinction is often drawn between classical or algebraic block codes (e.g. BCH,Golay, Hamming, Reed-Solomon codes) that apply the algebraic properties of finitefieldsand modern linear block codes, such as (but not limited to) LDPC and Polar codes, whichare characterized by bipartite graphs. Turbo codes constitute a second class of capacity-approaching codes that are based upon concatenated convolutional codes. Turbo coding istypically considered to involve an iterated soft-decoding scheme and an FEC that combinestwo or more relatively simple convolutional codes and an interleaver to produce a block codethat can achieve performance approaching the Shannon limit. Thefirst Turbo codes wereparallel concatenated convolution codes and subsequent Turbo codes have also utilized serialconcatenated convolutional codes.SUMMARY OF THE INVENTION

[0006] Parallel list decoders in accordance with various embodiments of the inventionoffer significant advantages for decoding short block length codes, particularly convolutionalcodes and tail-biting convolutional codes (TBCCs). By dividing the decoding trellis intosegments and processing these segments independently before combining them, parallel listdecoders can simultaneously explore multiple potential solutions. This approach can allowfor the efficient processing of multiple trellis stages in parallel, rather than sequentially. Theparallel nature of the decoding process can result in a decoding latency that is proportionalof the block length, making parallel list decoders particularly well-suited forlow-latency applications. A specific benefit of the use of parallel list decoders is their abilityto process stages in parallel such that there is no requirement that trellis stages be processedsequentially.

[0007] In a number of embodiments, the parallel list decoder maintains multiple pathsor edges for each valid source-destination state pair in the trellis, allowing it to consider abroader set of potential solutions. As the decoding process progresses through multiple layers,the number of trellis stages considered decreases at each level, but the decoder retains thebest paths. Additionally, the parallel list decoder can be enhanced by searching neighboringcodewords, further improving its error-correction capabilities. Parallel list decoders can beimplemented using custom circuits or on parallel processing hardware such as (but not limitedto) GPUs. When implemented on parallel processing hardware such as GPUs, these decoderscan achieve significant speed improvements while maintaining high decoding accuracy, makingthem particularly effective for decoding short block length messages in applications requiringrapid data exchange and / or low latency.

[0008] In one embodiment, a transceiver capable of transmitting and receiving shortmessages using low latency decoding is provided. The transceiver includes a tail-bitingconvolutional code encoder for encoding received input data, a mapper for mapping encodeddata to symbols based on a modulation scheme, a modulator for generating a transmit RFsignal, an antenna for receiving an RF signal, a demodulator for demodulating the receivedRF signal to symbols, a demapper for generating symbol metrics, and a decoder for decodingthe symbol metrics to obtain received bits.

[0009] In another embodiment, the decoder of the transceiver is a low latency decoder.

[0010] In a further embodiment, the modulation scheme of the transceiver comprises atleast one of a binary phase shift keyed (BPSK) scheme and a non-return-to-zero (NRZ)scheme.another embodiment, the decoder of the transceiver comprises multiple listdecoders configured to generate lists of most likely sequences.

[0012] In an additional embodiment, the multiple list decoders form a parallel list decoderconfigured to produce a list of likely sequences that are processed in parallel.

[0013] In a still further embodiment, the decoder is a parallel list decoder configured toprocess multiple trellis stages in parallel.

[0014] In still another embodiment, the parallel list decoder is configured to divide adecoding trellis into segments, process the segments independently, and combine the processedsegments in pairs to form new segments.

[0015] In a yet further embodiment, processing each segment comprises generating edgesfor all valid source and destination state pairs and selecting a set of edges having best metricsfor each pair.

[0016] In yet another embodiment, the parallel list decoder is configured to repeat theprocessing and combining of segments until a single segment remains.

[0017] In an additional embodiment, the parallel list decoder is further configured to selecta best path from the single remaining segment as a survivor path.

[0018] In a still yet further embodiment, the parallel list decoder is configured to recon-struct a decoding estimate by tracing back state transitions of the survivor path in reverseorder.

[0019] In still yet another embodiment, the parallel list decoder is configured to maintainmultiple edges for each valid source-destination state pair.

[0020] In a further embodiment again, the parallel list decoder is configured to maintain asingle edge for each valid source-destination state pair.

[0021] In yet another embodiment again, the parallel list decoder is further configured tosearch neighboring tail-biting codewords of estimates produced by the decoder.

[0022] In an additional embodiment again, searching neighboring tail-biting codewordsa list of offset codewords with monotonically increasing Hamming weightsto construct a list of neighboring codewords through XOR operations with the list of offsetcodewords.

[0023] In a still further embodiment again, the TBCC has a message length K given byK=ν × 2l, where ν is a number of memory elements in the encoder and l is an integer.

[0024] In still another embodiment again, the demapper is configured to generate at leastone of log likelihood ratios, Euclidean distances, and Hamming distances as the symbolmetrics.

[0025] In a yet further embodiment again, the decoder is configured to have a decodinglatency proportional to a log of a block length of the received input data.

[0026] In yet another embodiment again, the decoder is implemented using parallel pro-cessing hardware.

[0027] In an additional embodiment, the parallel processing hardware comprises a graphicsprocessing unit (GPU).

[0028] In one embodiment, a method of decoding short block length messages is provided.The method includes receiving a signal comprising data encoded using a short blocklengthcode, demodulating the signal to obtain symbols, generating a sequence of symbol metricsbased on the demodulated symbols, and decoding the sequence of symbol metrics using aparallel list decoder to obtain a sequence of received bits, where the parallel list decoderprocesses multiple trellis stages in parallel.

[0029] In another embodiment, decoding the sequence of symbol metrics comprises dividinga decoding trellis into segments, processing the segments independently, and combining theprocessed segments in pairs to form new segments.

[0030] In a further embodiment, processing each segment comprises generating edges forall valid source and destination state pairs and selecting a set of edges with best metrics foreach pair.embodiment, the method further includes repeating the processing andcombining of segments until a single segment remains.

[0032] In an additional embodiment, the method further includes selecting a best pathfrom the single remaining segment as a survivor path.

[0033] In a still further embodiment, the method further includes reconstructing a decodingestimate by tracing back state transitions of the survivor path in reverse order.

[0034] In still another embodiment, the parallel list decoder maintains multiple edges ateach valid source-destination state pair.

[0035] In a yet further embodiment, the parallel list decoder maintains a single edge ateach valid source-destination state pair.

[0036] In yet another embodiment, the method further includes searching neighboringcodewords of estimates produced by the parallel list decoder.

[0037] In a further additional embodiment, searching neighboring codewords comprisesusing a list of offset codewords with monotonically increasing Hamming weights to constructa list of neighboring codewords through XOR operations with the list of offset codewords.

[0038] In another additonal embodiment, the parallel list decoder has a decoding latencyproportional to a log of a block length of the encoded data.

[0039] In still yet another embodiment, the parallel list decoder is implemented usingparallel processing hardware.

[0040] In a still yet further embodiment, the parallel processing hardware comprises agraphics processing unit (GPU).

[0041] In yet another embodiment again, generating the sequence of symbol metricscomprises generating at least one of log likelihood ratios, Euclidean distances, and Hammingdistances.

[0042] In an additional embodiment again, the encoded data is encoded using a convolu-tional code.further additional embodiment again, the encoded data is encoded using atail-biting convolutional code.

[0044] In yet another embodiment again, a receiver for decoding short block length mes-sages is provided. The receiver includes an antenna configured to receive a radio frequency(RF) signal comprising encoded data, a demodulator coupled to the antenna and configuredto demodulate the RF signal to obtain symbols, a demapper coupled to the demodulator andconfigured to generate a sequence of symbol metrics based on the demodulated symbols, anda parallel list decoder coupled to the demapper and configured to decode the sequence ofsymbol metrics to obtain a sequence of received bits, where the parallel list decoder processesmultiple trellis stages in parallel.

[0045] In a further embodiment, the parallel list decoder is further configured to divide adecoding trellis into segments, process the segments independently, and combine the processedsegments in pairs to form new segments.

[0046] In another embodiment, the parallel list decoder is further configured to generateedges for all valid source and destination state pairs and select a set of edges with best metricsfor each pair.

[0047] In an additional embodiment, the parallel list decoder is further configured toiteratively process and combine segments until a single segment remains.

[0048] In a still further embodiment, the parallel list decoder is further configured to selecta best path from the single remaining segment as a survivor path.

[0049] In still another embodiment, the parallel list decoder is further configured toreconstruct a decoding estimate by tracing back state transitions of the survivor path inreverse order.

[0050] In a further embodiment again, the parallel list decoder is configured to maintainmultiple edges for each valid source-destination state pair.

[0051] In yet another embodiment again, the parallel list decoder is configured to maintaineach valid source-destination state pair.

[0052] In a further additional embodiment, the parallel list decoder is further configuredto search neighboring codewords of estimates produced by the parallel list decoder.

[0053] In another additional embodiment, the parallel list decoder is further configured touse a list of offset codewords with monotonically increasing Hamming weights to construct alist of neighboring codewords through XOR operations with the list of offset codewords.

[0054] In a still yet further embodiment, the parallel list decoder is configured to have adecoding latency proportional to a log of a block length of the encoded data.

[0055] In a still further embodiment again, the parallel list decoder is implemented usingparallel processing hardware.

[0056] In still yet another embodiment again, the parallel processing hardware comprisesa graphics processing unit (GPU).

[0057] In another further additional embodiment, the demapper is configured to generateat least one of log likelihood ratios, Euclidean distances, and Hamming distances as thesymbol metrics.

[0058] In another further embodiment again, the encoded data is encoded using a convolu-tional code.

[0059] In still yet another further embodiment, the encoded data is encoded using atail-biting convolutional code.

[0060] In a still yet further additional embodiment, the receiver further comprises a pro-cessor coupled to the parallel list decoder and configured to process the sequence of receivedbits to extract at least one of control data and application data.

[0061] In one embodiment, a communication system for transmitting and receiving shortblock length messages is provided. The communication system includes a transmitter config-ured to encode input data using a code and transmit a signal based upon the encoded data,and a receiver configured to receive and decode the signal, wherein the receiver employs athat is configured to process multiple trellis stages in parallel.

[0062] In an additional embodiment, the transmitter includes an encoder configured toencode the input data, a mapper configured to map the encoded data to symbols based ona modulation scheme, and a modulator configured to generate an RF signal based on thesymbols.

[0063] In a further embodiment, the receiver further includes an antenna configured toreceive the RF signal, a demodulator coupled to the antenna and configured to demodulatethe RF signal to obtain symbols, and a demapper coupled to the demodulator and configuredto generate a sequence of symbol metrics based on the demodulated symbols. The parallellist decoder is coupled to the demapper and is configured to decode the sequence of symbolmetrics to obtain a sequence of received bits.

[0064] In another embodiment, the parallel list decoder is further configured to divide adecoding trellis into segments, process the segments independently, and combine the processedsegments in pairs to form new segments.

[0065] In a still further embodiment, the parallel list decoder is further configured togenerate edges for all valid source and destination state pairs and select a set of edges withbest metrics for each pair.

[0066] In yet another embodiment, the parallel list decoder is further configured to itera-tively process and combine segments until a single segment remains.

[0067] In an additional embodiment again, the parallel list decoder is further configuredto select a best path from the single remaining segment as a survivor path.

[0068] In a still yet further embodiment, the parallel list decoder is further configuredto reconstruct a decoding estimate by tracing back state transitions of the survivor path inreverse order.

[0069] In still yet another embodiment, the parallel list decoder is configured to maintainmultiple paths for each valid source-destination state pair.further embodiment, the parallel list decoder is configured to maintaina single path for each valid source-destination state pair.

[0071] In yet another further embodiment, the parallel list decoder is further configuredto search neighboring codewords of estimates produced by the parallel list decoder.

[0072] In another additional embodiment, the parallel list decoder is further configured touse a list of offset codewords with monotonically increasing Hamming weights to construct alist of neighboring codewords through XOR operations with the list of offset codewords.

[0073] In a further additional embodiment, the parallel list decoder is configured to havea decoding latency proportional to a log of a block length of the encoded data.

[0074] In another further embodiment again, the parallel list decoder is implemented usingparallel processing hardware.

[0075] In a further additional embodiment again, the parallel processing hardware com-prises a graphics processing unit (GPU).

[0076] In yet another additional embodiment, the demapper is configured to generate atleast one of log likelihood ratios, Euclidean distances, and Hamming distances as the symbolmetrics.

[0077] In still yet another additional embodiment, the encoded data is encoded using aconvolutional code.

[0078] In a still yet further additional embodiment, the encoded data is encoded using atail-biting convolutional code.BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The description and claims will be more fully understood with reference to thefollowingfigures and data graphs, which are presented as exemplary embodiments of theinvention and should not be construed as a complete recitation of the scope of the invention.1 illustrates a communication system that includes various devices that trans-mit short messages in accordance with various embodiments of the invention.

[0081] Fig. 2 illustrates a communication system capable of transmitting and receivingshort messages in accordance with various embodiments of the invention.

[0082] Fig. 3 illustrates a transceiver capable of transmitting and receiving short messagesin accordance with various embodiments of the invention.

[0083] Fig. 4 illustrates a system model that includes an encoder transmitting a convolu-tional code, a channel, and a trellis-based decoder in accordance with various embodimentsof the invention.

[0084] Figs. 5A-J conceptually illustrate construction of a tail-biting trellis path by layersin accordance with various embodiments of the invention.

[0085] Fig. 6 illustrates a performance comparison of a parallel list decoder for threedifferent TBCC codes in accordance with various embodiments of the invention.

[0086] Fig. 7 illustrates a performance comparison of two list decoders against three othertypes of decoders in accordance with various embodiments of the invention.DETAILED DESCRIPTION

[0087] Turning now to the drawings, communication systems and methods that transmitand receive short block-length messages in accordance with various embodiments of theinvention are illustrated. While capacity-approaching codes, such as (but not limited to) LowDensity Parity Check (LDPC) codes, Turbo codes, and Polar codes, can achieve data ratesapproaching the Shannon limit at large block-lengths, the performance of these codes candeteriorate dramatically at short block-lengths. In a number of embodiments, transmitters,and receivers use encoding and modulation techniques that are specifically designed for usewith messages having short block lengths. These messages can be referred to as short messages.In many instances, communication systems can use transmitters and receivers implemented invarious embodiments of the invention that employ tail-biting convolutionalcodes (TBCC). In several embodiments, the receivers perform maximum likelihood (ML)decoding using a low-latency Viterbi decoder. Low-latency Viterbi decoders in accordancewith several embodiments of the invention can be utilized in parallel processing hardwaresuch as graphics processing units (GPUs). In certain embodiments, the low-latency Viterbidecoders exploit the structure of trellis decoders to maximize the number of simultaneousoperations capable of being performed by parallel processing hardware.

[0088] Convolutional codes are typically decoded via the Viterbi algorithm, or the Bahl,Cocke, Jelinek, and Raviv (BCJR) algorithm to minimize symbol error rate. Low delayrequirements have been a limiting factor for Viterbi decoders. Systems and methods inaccordance with many embodiments of the invention implement a very low latency Viterbidecoder that can be used with (but is not limited to use with) TBCCs by leveraging thestructure of the code trellis to pre-compute many operations. The pre-computed steps canthen be used to speed up the decoding process to obtain a decoding latency proportional tothe log of the block length. The lower delay may lead to an increase in the total number ofoperations that are performed. The use of simultaneous operations, however, can partiallycompensate for the additional operations and make the implementation efficient for processorscapable of performing multiple instructions in parallel such as (but not limited to) vectorprocessors and GPUs.

[0089] Low latency list decoders can significantly improve receiver performance. In anumber of embodiments, the receiver includes two list decoders having similar decodingdelays. Employing low latency list decoders within a communication system can enable thesystem to obtain a target performance using a simpler code (e.g. a code that may be moresuitable for the system hardware). In certain embodiments, decoding methods can improve acode performance for the same decoder by modifying the code to be a block code, but notconvolutional code. In selected embodiments, systems may include a list decoder versiondecoder that produces afixed list size at the same delay (provided sufficienthardware) that can contain the second most likely estimate.

[0090] Communication systems and methods of transmitting and receiving data using shortmessages involving the use of low latency decoders in accordance with various embodimentsof the invention are discussed further below.Communication Systems

[0091] Communication systems and methods in accordance with various embodimentsof the invention can be utilized to efficiently transmit short messages. Short messagetransmission can be useful in a variety of circumstances including (but not limited to)control signaling in wireless communication networks, device-to-device communications (e.g.Near Field Communication (NFC), Bluetooth, vehicle-to-vehicle communications), and datatransmissions by Internet of Things (IoT) devices. In many embodiments, the use of lowlatency decoders to decode received data can enable the communication system to achievelower latency than a comparable system employing a conventional decoding process such asthe Viterbi and / or BCJR algorithms.

[0092] A communication system that includes various devices that transmit short messagesin accordance with various embodiments of the invention is illustrated in Fig. 1. Thecommunication system 100 includes a mobile phone 102 capable of communicating witha cell tower 104 that connects the mobile phone 102 to a network 106. In the illustratedembodiment, the sequence of message exchanges between the mobile phone 102 and the celltower 104 includes the exchange of a number of short block-length messages encoded anddecoded in accordance with various embodiments of the invention. In many instances, theshort block-length messages are utilized by the mobile phone 102 to negotiate access to and / ortransmission of data via the network 106. In several embodiments, the short block-lengthmessages are utilized to communicate information via at least one of a Broadcast ControlControl Channel, a Common Control Channel, and / or a Dedicated ControlChannel. Sometimes these messages communicate transmission parameters. As can be readilyappreciated, the specific circumstances and / or the particular channels utilized to transmitand receive short block-length messages encoded in accordance with various embodiments ofthe invention are largely dependent upon the requirements of specific applications.

[0093] The mobile phone 102 can also utilized short block-length messages encoded inaccordance with various embodiments of the invention in short-range wireless communicationswith other devices such as, but not limited to, another mobile phone 108. Mobile phonescan also use short block-length messages encoded in accordance with various embodimentsof the invention to communicate via Near Field Communication (NFC). In the illustratedembodiment, a mobile phone 110 is shown communicating with a payment terminal 112.

[0094] The use of short messages encoded in accordance with various embodiments of theinvention is not limited to mobile phones. Any of a variety of devices capable of wirelesscommunication can encode and / or decode short messages using the techniques describedherein. For example, Fig. 1 illustrates a vehicle 114 communicating with the cell phone tower104 using short messages encoded in accordance with various embodiments of the invention.The vehicle 114 is also capable of utilizing short messages encoded in accordance withvarious embodiments of the invention to perform Vehicle-to-Vehicle (V2V) communicationand / or Vehicle-to-Everything (V2X) communication. As can readily be appreciated, any of avariety of devices can use short block-length messages encoded in accordance with variousembodiments of the invention to communicate via any of a number of wired and / or wirelesscommunication techniques including (but not limited to) NFC, short-range wireless, wirelessLocal Area Network, and / or cellular data network as appropriate to the requirements ofspecific applications.

[0095] While specific communication systems and devices that are capable of decoding shortmessages using low-latency decoders in accordance with various embodiments of the inventionabove with reference to Fig. 1, any of a variety of different communicationsystems and / or communication devices can be utilized to transmit and receive short messagesin accordance with certain embodiments of the invention. For example, communicationsystems in accordance with a number of embodiments of the invention can include medicaldevices, UAVs, and / or any other type of device that can communicate via a wired and / orwireless communication channel. Communication devices, and transmitters and receiversthat can be utilized within communication devices implemented in accordance with variousembodiments of the invention are discussed further below.Communication Devices

[0096] Communication devices in accordance with many embodiments of the invention canincorporate one or more transmitters, one or more receivers and / or one or more transceiversthat are capable of encoding and / or decoding short messages using the techniques describedherein. In many embodiments, the techniques described herein can be utilized to efficientlyexchange control information to negotiate the efficient transmission of longer block-lengthmessages using conventional communication techniques such as (but not limited to) usingLDPC and / or Polar codes with higher order modulation schemes including (but not limitedto) higher-order uniform QAMs and non-uniform capacity-optimized QAMs. In certainembodiments, the techniques described herein are used to transmit control and / or applicationdata. As can readily be appreciated, the specific circumstances in which the efficient trans-mission of short messages is beneficial typically depend upon the requirements of particularapplications.

[0097] A communication system capable of transmitting short messages encoded in accor-dance with various embodiments of the invention is illustrated in Fig. 2. The communicationsystem 200 includes afirst communication device 210 that includes a processor 212, memory214, a transmitter 216, and an antenna 218. While the illustrated embodiment shows the use218, it should readily be appreciated that the techniques described herein areequally applicable to wired communication systems including (but not limited to) opticalcommunication systems.

[0098] In many embodiments, the processor 212 of thefirst communication device 210executes one or more applications stored in memory 214 that cause the transmission of controland / or application data via the transmitter 216. The transmitter is capable of establishinga communication channel and transmitting the control and / or application data. In manyinstances, the transmitted message contains encoded control information utilized to establisha communication channel for communicating application data for the same application and / orother applications. In a number of embodiments, the process of establishing the communi-cation channel involves the use of short messages encoded using the techniques describedherein. In several embodiments, the techniques described herein are used to encode shortblock lengths of application data for transmission via the communication channel. As canreadily be appreciated, the techniques described herein can be utilized to encode some or allof the messages transmitted via the transmitter as appropriate to the requirements of specificapplications.

[0099] A second communication device 220 receives messages transmitted by thefirstcommunication device 210 via an antenna 222. In the illustrated embodiment, the secondcommunication device 220 includes a receiver 224 that employs a low latency decoder imple-mented in accordance with an embodiment of the invention, a processor 226, and memory228. In a number of embodiments the low latency decoder is implemented as a parallellist decoder using parallel processing circuitry that can be a dedicated component (e.g. anASIC or an FPGA) and / or a parallel processor within the processor 226 (e.g. the processor226 includes an application processor, CPU, and a parallel processor, GPU) based uponinstructions contained within memory. In many instances, the receiver receives transmittedmessages and outputs application data that is processed by at least one application executing226 using the machine-readable instructions of the at least one applicationstored in the memory 228. In many instances, the short messages received by the receiver areencoded in accordance with various embodiments of the invention. In certain embodiments,the short messages encoded in this manner are utilized to communicate control information.In a number of embodiments, the short messages encoded in this manner are utilized totransmit application data. As can readily be appreciated, the specific information transmittedvia the short messages is largely dependent upon the requirements of specific applications.

[0100] While specific communication devices capable of communicating using short mes-sages and low latency decoders are described above with reference to Fig. 2, any of a varietyof different communication systems and / or communication devices can be utilized to transmitshort messages via wired and / or wireless communication channels in accordance with variousembodiments of the invention. Furthermore, any of the communication devices described withreference to Fig. 2 can be utilized in any of a variety of communication systems including(but not limited to) the communication systems described above with reference to Fig. 1.Specific processes for encoding short messages for transmission and decoding short messagesusing low latency decoding methods in accordance with various embodiments of the inventionare discussed further below.Short Message Transceivers

[0101] Transceivers, transmitters and receivers capable of transmitting and / or receivingshort messages encoded in accordance with various embodiments can be implemented in avariety of ways. A transceiver capable of transmitting and receiving short messages usinglow latency decoding in accordance with various embodiments of the invention is illustratedin Fig. 3. The transceiver 300 receives data bits and encodes the data bits using a TBCCencoder 302. While a TBCC encoder is shown, it should be readily appreciated that any of avariety of codes and / or encoders can be utilized in accordance with various embodiments of

[0102] The encoded bits output by the TBCC encoder 302 are received by the mapper 306,which maps the encoded bits to symbols in accordance with a specific modulation scheme.Any of a variety of binary modulation schemes can be utilized including (but not limited to)Binary Phase Shift Keyed (BPSK), and / or Non-Return-to-Zero (NRZ) modulation schemes.The symbols output by the mapper 306 are provided to a modulator 308, which, for theapplication to wireless systems, generates an RF signal that can be transmitted via one ormore antennas 312 connected 310 to the modulator 308.

[0103] The antenna 312 can also be connected (310) to a receiver signal path within thetransceiver. The antenna 312 can provide a received RF signal to a demodulator 314, whichcan output a demodulated signal 314 to a demapper 316. The demapper can 316 can generatea sequence of symbol metrics that are provided to a decoder 318. In several embodiments, thesymbol metrics can be log likelihood ratios with respect to each possible symbol. In a numberof embodiments, the symbol metrics can be Euclidean distances with respect to each possiblesymbol. The specific choice of symbol metric may depend on the particular application andcan include (but is not limited to) log likelihood ratios and Hamming distances. In theillustrated embodiment, decoder 318 is a low latency decoder. In several embodiments, thelow latency decoder includes multiple list decoders that each generate a list of the most likelysequences. In this way, the list decoders form a parallel list decoder that can produce a listof likely sequences that are processed in parallel. As can readily be appreciated, the specificimplementation of a low latency decoder used in a receiver implemented in accordance withvarious embodiments of the invention is not limited to the use of multiple list decoders and islargely dependent upon the requirements of specific applications.

[0104] While a variety of different transceiver implementations are described above withreference to Fig. 3, any of a variety of transmitter, receiver and / or transceiver architecturescapable of transmitting and / or receiving short messages encoded in accordance with variousof the invention can be utilized as appropriate to the requirements of specificapplication. Various receivers that employ low latency decoders in accordance with differentembodiments of the invention are discussed further below.Low Latency Viterbi Decoding

[0105] Communication systems in accordance with many embodiments of the inventionemploy codes such as (but not limited to) TBCCs to encode data for transmission and alow latency decoder, such as (but not limited to) a parallel list decoder and / or a decoderimplemented using multiple list decoders, to decode received data. A communication systemincluding a transmitter capable of encoding data for transmission via to a receiver via achannel, where the receiver includes a low latency decoder for decoding the transmitted data,in accordance with an embodiment of the invention is illustrated in Fig. 4.

[0106] In several embodiments, TBCCs can be described by the circuit that implementsthe TBCC in the encoder. In many embodiments, the circuit is afinite-state machine withone or more inputs and one or more outputs. The number of states may be given by thenumber of possible states defined by the number of memory elements ν in the circuit. Inselected embodiments, the code rate is characterized by the number of input and outputstreams, denoted by the parameters k, n, and the number of states is given by 2ν . Theinput information sequence U = U0, U1, ... can be split into two or more streams, dependingon the code parameter k. For every k input symbols the code can produce n output sym-bols, which are then modulated (e.g. to {−1, 1}) to construct the channel symbol sequenceX = X1, X2, .... In various embodiments, the channel model is additive white Gaussiannoise (AWGN). In other embodiments, the channel model can be any of a variety of channelmodels appropriate to the requirements of specific applications including (but not limited to)fading channel models. The received signal can be considered to be the sum of the channelsymbols X1, X2, ... and the noise components W1,W2, ... where Wi ∼ N (0, σ2).embodiments, trellis-based decoders for convolutional codes with a highlevel of parallelism can be implemented that allows for a decoding latency that is a functionof the base 2 log of the message length, the hardware resources available, and the squareof the number of states in a trellis. In selected embodiments, a trellis can be broken intosegments that arefirst processed independently and then combined in pairs into new segments.Processing of a segment may include generating all edges from all valid source and destinationstate pairs. All the edges reaching each pair may be compared and the edge with the bestmetric is selected, in a similar manner as the add compare and select method used in theViterbi algorithm. In many embodiments, the process repeats until the number of remainingsegments is reduced to one, where only the best paths from every state at thefirst stageto the same state at the last stage remain. The best of these paths can be selected as thesurvivor path. In some embodiments, the decoding estimate is recovered by tracing back thestate transitions of the survivor path in the reverse order wherefirst the state and the centerstage are recovered, then the centers of each segment are recovered.

[0108] Figs. 5A-J illustrate a parallel trellis stage decoder for a rate 12TBCC ν = 2 codewith four states and 16 stages in accordance with an embodiment of the invention. Theencoder circuit for this code is similar to the encoder shown in Fig. 4 with two memoryelements. Fig. 5B illustrates half the standard tail-biting trellis with inputs and outputs. Thefull trellis is shown in Fig. 5C. To initialize the decoder, edges connecting every two stagesinstead of every stage may be constructed as shown in the Fig. 5D. This way, each sourcestate at one stage can reach each destination state at the next stage. In many embodiments,the process starts by constructing the double length edges shown in Fig. 5E from the edges inFig. 5D. There may be four such edges connecting each source and destination state pair, onethrough each intermediate state in the previous layer. The processing at level 2 illustrated byFigs. 5E-F may end by selecting the best intermediate state, shown in Fig. 5F. The thirdlayer can repeat the process with four segments remaining, leaving only edges connectingsource stage to the ones at the center and the ones at the center to the statesat the last stage. For the last layer, since tail-biting codes need to start and end at the samestate, only edges connecting states with the same state number may be considered, as shownin Fig. 5I. At the end of the fourth layer illustrated by Fig. 5J, a single edge connecting eachsource state with its counterpart destination state may remain. The best edge connecting asource and destination pair can be selected as the single survivor, which is used to reconstructthe estimate.

[0109] In numerous embodiments, reconstructing the estimate includes tracing back thesurviving path through states in every layer in reverse order. For example, suppose that theselected edge is one starting (and ending) at state two. Fig. 5J may be retraced to determinethe state at the center stage that connected the two four-stage components of the survivingedge. Fig. 5H can be retraced tofind the states at the center of the two segments. In manyembodiments, the retracing process repeats until thefirst layer is reached, and all the statesincluded in the surviving path are recovered. The decoding estimate can be reconstructedusing the input symbols corresponding with the edges connecting every pair of the recoveredstates.

[0110] In several embodiments, parallel list decoders function like a maximum likelihooddecoder. For example, suppose that the state transitions of the maximum likelihood (ML)path through the trellis shown in Fig. 5D. This path may include eight state transitionsdefined by a starting and ending state with the same number and the seven intermediatestates. Consider thefirst two transitions, from the source state at stage zero to a state atstage one and from this state to another state at stage two. In selected embodiments, thenext two transitions take the path to a state at the center stage four through a state atstage three. As illustrated by Fig. 5F, parallel Viterbi algorithms in accordance with someembodiments can discover the best two edges connecting every pair of states in even stages.In several embodiments, the two edges connect the ML path from a state at stage zero to atwo through a state at stage one as illustrated by Fig. 5F. The same processmay happen with edges between stages illustrated by Figs. 5E-F and 5I-J.

[0111] In some embodiments, the new edges form the best path connecting the sourcestate of the ML path with stage four of the ML path and will be also selected at the stageillustrated by Fig. 5H. The same process may be mirrored by the other half of the trellis.Finally, since all the components of the ML path have been selected at the stage illustratedby Fig. 5H, the full path can be reconstructed and selected in the stage illustrated by Figs.5I-J.

[0112] The latency of the algorithm may depend on the code parameters ν and l and thehardware available. For example, suppose that 2l × 23ν computing nodes are available andbroadcasting information across nodes incurs no delay. Then, each of the 22ν source anddestination state pairs active at every level can execute simultaneously. At each node, 2νedges may be constructed with the best one selected. This can be as low as ν time unitsif comparisons are executed using binary search, which could require as many as 2ν unitsper each of the 22ν state pairs. The time to process each layer may be proportional to ν.Each addition at the beginning can take an additional time unit, for a total of l(ν + l) timeunits. The square difference between the modulated output symbols of each edge and thecorresponding received signal segment of length ν may be computed to initialize the edgeswith the log domain transition likelihoods. With the same number of processing nodes,initialization can be performed in less than ν + 2, time units. The rest of the process mayinclude tracing back the path, which may take as little as l time units. Thefinal latency canbe as little as νl+2ν +2l+2 time units. Since K is given by ν ×2l, ν(log2(K)− log2(ν)) maybe obtained. Forfixed ν the latency grows with the log base 2 of the block length. However,the required hardware may increase linearly.

[0113] The lower decoding latency of the parallel decoder can require increased computa-tional complexity relatively to a conventional Viterbi decoder. For example, when K = ν2l,there may be 2ν × 2ν edge source and destination state pairs, and 2ν edges areconstructed for each pair. At each layer i = 1, 2, ... , l − 1, there may be 2l−i active stages,each constructing 23ν edges and selecting the best out of every 2ν .layer has 2νstate pairs. In this example, the total number of edges constructed and compared is then(2l − 2) × 23ν + 22ν . The initial number of edges, as shown in Figs. 5A-J, is ν × 2l × 22ν . Thecomputational complexity order may be O(2l × 23ν). Since K = ν × 2l, the computationalcomplexity can be written as O(Kν× 23ν).

[0114] In contrast, aViterbi algorithm can construct two edges with twoadditions and then compare them at each trellis state. The number of addition operationsmay be given by 2 × ν2l × 2ν . The number of length 1 stages may be K = ν × 2l. Thecomplexity order may be O(ν2l × 2ν) or O(K × 2ν). However, the Viterbi algorithm does notproduce the ML estimate in a single pass. In some embodiments, the algorithm is run 2νtimes to increase ML performance. In practice, sub-optimal methods can be used in prior artsystems like the wrap-around Viterbi algorithm (WAVA). WAVA can involve running theViterbi algorithm more than once and approaching ML performance could take about fouriterations. The complexity of WAVA is of order O(ν2l × 2ν). In contrast, many embodimentshave a processing complexity higher by a factor of 22νν, which increases with ν. The twocomplexities are similar at about ν = 2, andfor larger ν. However, the increasedcomplexity can help with obtaining very low delay, parallel processing, and ML performance.Improving Performance Through Code Selection

[0115] In certain embodiments, parallel trellis stage decoders can support modificationsto the TBCC code to improve performance. Many of the systems described above utilize astarting number of stages that is a power of 2, joined by edges of length ν. This could lead tothe message length K to be of the form ν × 2l for some l. In the example illustrated in Fig.5A where a segment size 10 × 16 of the code generator matrix made up of four 4 × 4 blocks,generator matrix can be constructed by appending another copy to theright with two overlapping rows. To obtain the standard for the generator matrix, thefirsttwo rows may be cut and added to the bottom two rows. Alternatively, the last two inputbits may be appended to the starting rows. In several embodiments, this approach is bettersuited to describe the system because the blocks that comprise the matrix defines the lengthν edges connecting states in two contiguous stages. The entries of the block could vary, andthe blocks can be made larger to implement code lengths other than ν × 2l. The edge lengthsmay be ν + 1, ν + 2, ... , 2ν. A length of 2ν is equivalent to length ν but with the processstarting step ahead illustrated in Fig. 5E. In some embodiments, the decoder architecturemay be based on the length of the edges, the number of stages 2l, and the number of states2ν . As the actual value of the edges does not change the decoder, the entries of the blocksthat define the edges to obtain a different block code may be changed and possibly improveits performance.

[0116] In many embodiments, the modification procedure described above can be usedto construct a decoder for an ν = 3, rate 1 / 2 TBCC code with input length 40. In sev-eral embodiments, a trellis with 8 stages and edge length of 5 can be constructed, and bymodifying the code with the addition of a few entries to the size 8 × 10 blocks defining theedges, an improvement in frame error rate can be obtained. Fig. 6 illustrates a performancecomparison of a parallel list decoder for three different TBCC codes in accordance withvarious embodiments of the invention.

[0117] In certain embodiments, parallel list decoders can be implemented using multiplelist decoders. In many embodiments, encoders mayfirst add a cyclic redundancy check (CRC)sequence to the information sequence and then encode the new sequence with the tail-bitingconvolutional encoder. This can allow the list decoder to detect some errors by checkingthe value of the CRC sequence search for a new estimate when the previous one does notpass the CRC check and is rejected. This approach can reduce the code rate by a factor ofm is the size of the CRC segment added to the information sequence.

[0118] In some embodiments, list decoders produce more than one estimate at each validsource-destination state pair. The number of trellis stages considered at each level of theoriginal process may decrease to half from one level to the next. This is shown in Figs. 5C-Fwith the number of stages decreasing from eight in Fig. 5D to four in Fig. 5F, and from fourin Fig. 5G to two in Fig. 5I and so on. The best two paths at each level can be selected. Inseveral embodiments, the new process adds a new copy of the half-sized system from onelevel to the next. In the circuit illustrated by Figs. 5A-J, at Fig. 5F, there would be twocopies of the process, and the size of the system would be the same as that of Fig. 5E. At Fig.5G, there would be three copies, one that combines on the best edges that reach stages twoand six with the best edges that leave the same stages; one copy that combine the best edgesthat reach stages two and six with the second best edges that leave these stages and one thatcombines the second best edges that reach the same stages with the best edges leaving thestages. From the system with only the best edges, the two best edges may be saved. Of theother two, only the best may be saved. With this approach, the total size of the systemsat each level remains constant. At each state of the last level, there may be a number oftail-biting paths equal to the number of stages the system started with, eight in the exampleof Figs. 5A-J. However, only the best and second-best paths may be among them. The thirdand subsequent best paths may not be guaranteed to be among the paths. If there are 2lstarting stages, with edges of length ν, that is K = ν × 2l, then the output number of pathsat for each state is 2l. The bestsecond best overall path are guaranteed. In selectedembodiments, the third most likely path can be included, except possibly for the case wherethefirst three best paths are from the same source state.

[0119] In several embodiments, a second list decoder version extends thefirst approachdescribed above by searching the neighboring tail-biting codewords of the estimates producedby thefirst list decoder. For this decoder, a list of tail-biting codewords with monotonicallyweights canfirst be constructed using a sieve method. In several em-bodiments, 1024 neighboring TB codewords are obtained. As can readily be appreciated,the specific number and / or method used to obtain the neighboring tail-biting codewords islargely dependent upon the requirements of specific applications.

[0120] After getting all the estimates produced by thefirst list decoder, each of theestimates in accordance with several embodiments is then added to the neighboring TBcodewords through XOR operations, producing 16 × 2ν × 1024 TB codewords in total. Sincethe XOR operation is fast, the overall decoding latency can be very similar to that of theoriginal ML decoder if the original decoder takes the same time at each level, i.e. thefirstlayer does not require splitting the process into two parts. Otherwise, every stage may takeas much time as thefirst. In numerous embodiments, the decoding latency is given by theproduct of the number of layers with the time taken by thefirst layer.

[0121] Exploring additional codewords using linearity in accordance with various em-bodiments of the invention can provide an improvement in the decoding performance . Anexample of the improvement in decoding performance can be appreciated from Fig. 7, whichillustrates a performance comparison of the use of two list decoders to perform a low latencydecoding process similar to the process described above against three other types of decoders.The linearity LVD can improve the error rate by around 0.8 dB at a target FER rate of10−4 and approaches the ML decoding performance of a serial LVD with a gap of 0.4 dB.Increasing the linearity list size can further improve the decoding performance but it canhave a large memory cost.

[0122] In some embodiments, decoders are implemented as neural network models usingPyTorch to leverage the parallel processing capabilities of this framework. In many embodi-ments, input and modulated outputof all of the edges in the trellis are generated and saved inseparate data structures. To compute the log domain square differences metrics for each edge,the modulated edge outputs can be subtracted from the received signal. The difference canand the components of each edge can be summed. From there the processcan proceed in a similar manner to the various processes described above with reference toFigs. 5A-J.

[0123] Simulations of several versions of the disclosed decoders were used to provideperformance plots for parallel trellis stage decoders in Fig. 6 and for parallel trellis stagelist decoders in Fig. 7. The graphs illustrate frame error rate (FER) vs bit energy to noiseenergy ratio in dB, EbN0. In Fig. 6, the performance of three TBCCs with 3, 5 and 6 memoryelements ν and message size of K = 64 for ν = 5, 6 and K = 40 for ν = 3 are illustrated. Thedecoders include 8 stages with initial edge length K / 8. For the 8 state TBCC with ν = 3, amodified code was designed to obtain theof the dotted green line with diamonds.This performance is better than that of the original TBCC code, and the decoder is the same.These results show that the decoder design is suitable for practical implementation in parallelprocessing systems.

[0124] A ν = 5 TBCC with polynomials {53, 75} concatenated with an 8-bit CRC wasused. The trellises have 16 stages and edge length ν. The TBCC input is a 72 bit informationsequence with the 8-bit CRC. The solid orange curve with diamonds is the performance ofthe low latency list decoder alone and the solid magenta line with squares is that of the samelist decoder but with neighborhood search. The performance of the same code without listdecoding, with and without adjusting for the CRC rate loss, is also illustrated. Each listdecoder version improves the performance by about a half of a dB or more and the best isless than a half dB away from the serial list Viterbi.

[0125] Although specific methods of transmitting and receiving short messages using lowlatency Viterbi decoders are discussed above, many different methods of transmitting andreceiving short messages can be implemented in accordance with many different embodimentsof the invention. For example, one of ordinary skill in the art will appreciate that methods ofcommunication described above can be implemented on other platforms as appropriate toof specific applications of embodiments of the invention and are not limitedto the decoding of any specific codes or code structures. It is therefore to be understood thatthe present invention may be practiced in ways other than specifically described, without de-parting from the scope and spirit of the present invention. Thus, embodiments of the presentinvention should be considered in all respects as illustrative and not restrictive. Accordingly,the scope of the invention should be determined not by the embodiments illustrated, but bythe appended claims and their equivalents.

[0126] Additional disclosure can be found in the manuscriptsfiled herewith, which areincorporated by reference in its entirely. The references to additional works made in thefootnotes are incorporated by reference in their entireties. Although the description abovecontains many specificities, these should not be construed as limiting the scope of the inventionbut as merely providing illustrations of some of the presently preferred embodiments of theinvention. Various other embodiments are possible within its scope. Accordingly, the scope ofthe invention should be determined not by the embodiments illustrated, but by the appendedclaims and their equivalents.

Claims

aimed is:

1. A transceiver capable of transmitting and receiving short messages using lowlatency decoding, comprising:a tail-biting convolutional code encoder capable of encoding received input data;a mapper configured to map the encoded input data to symbols based on amodulation scheme;a modulator capable of generating a transmit radio frequency (RF) signal based onthe symbols;an antenna capable of receiving a receive RF signal;a demodulator capable of demodulating the received RF signal to symbols;a demapper configured to generate a sequence of symbol metrics based on thedemodulated symbols; anda decoder capable of decoding the sequence of symbol metrics to obtain a sequenceof received bits.

2. The transceiver of claim 1, wherein the decoder is a low latency decoder.

3. The transceiver of claim 1, wherein the modulation scheme comprises at leastone of a binary phase shift keyed (BPSK) scheme and a non-return-to-zero (NRZ) scheme.

4. The transceiver of claim 1, wherein the decoder comprises multiple listdecoders configured to generate lists of most likely sequences.

5. The transceiver of claim 4, wherein the multiple list decoders form a parallellist decoder configured to produce a list of likely sequences that are processed in parallel.

6. The transceiver of any of claims 1-5, wherein the decoder is a parallel listnfigured to process multiple trellis stages in parallel.

7. The transceiver of claim 6, wherein the parallel list decoder is configured to:divide a decoding trellis into segments;process the segments independently; andcombine the processed segments in pairs to form new segments.

8. The transceiver of claim 7, wherein processing each segment comprises:generating edges for all valid source and destination state pairs; andselecting a set of edges having best metrics for each pair.

9. The transceiver of any one of claims 6-8, wherein the parallel list decoder isconfigured to repeat the processing and combining of segments until a single segmentremains.

10. The transceiver of claim 9, wherein the parallel list decoder is furtherconfigured to select a best path from the single remaining segment as a survivor path.

11. The transceiver of claim 10, wherein the parallel list decoder is configured toreconstruct a decoding estimate by tracing back state transitions of the survivor path inreverse order.

12. The transceiver of any one of claims 6-11, wherein the parallel list decoder isconfigured to maintain multiple edges for each valid source-destination state pair.

13. The transceiver of any one of claims 6-11, wherein the parallel list decoder isconfigured to maintain a single edge for each valid source-destination state pair.

14. The transceiver of any one of claims 6-13, wherein the parallel list decoder isfigured to search neighboring tail-biting codewords of estimates produced bythe decoder.

15. The transceiver of claim 14, wherein searching neighboring tail-bitingcodewords comprises:using a list of offset codewords with monotonically increasing Hamming weights toconstruct a list of neighboring codewords through XOR operations with the list of offsetcodewords.

16. The transceiver of any of claims 1-15, wherein the TBCC has a messagelength K given by K=ν × 2l, where ν is a number of memory elements in the encoder andl is an integer.

17. The transceiver of any one of claims 1-16, wherein the demapper isconfigured to generate at least one of log likelihood ratios, Euclidean distances, andHamming distances as the symbol metrics.

18. The transceiver of any one of claims 1-17, wherein the decoder is configuredto have a decoding latency proportional to a log of a block length of the received inputdata.

19. The transceiver of any one of claims 1-18, wherein the decoder isimplemented using parallel processing hardware.

20. The transceiver of claim 19, wherein the parallel processing hardwarecomprises a graphics processing unit (GPU).

21. A method of decoding short block length messages, comprising:iving a signal comprising data encoded using a short blocklength code;demodulating the signal to obtain symbols;generating a sequence of symbol metrics based on the demodulated symbols;decoding the sequence of symbol metrics using a parallel list decoder to obtain asequence of received bits, where the parallel list decoder processes multiple trellis stages inparallel.

22. The method of claim 21, wherein decoding the sequence of symbol metricscomprises: dividing a decoding trellis into segments;processing the segments independently; andcombining the processed segments in pairs to form new segments.

23. The method of claim 22, wherein processing each segment comprises:generating edges for all valid source and destination state pairs; andselecting a set of edges with best metrics for each pair.

24. The method of claim 23, further comprising repeating the processing andcombining of segments until a single segment remains.

25. The method of claim 24, further comprising selecting a best path from thesingle remaining segment as a survivor path.

26. The method of claim 25, further comprising reconstructing a decodingestimate by tracing back state transitions of the survivor path in reverse order.

27. The method of any one of claims 21-26, wherein the parallel list decodermaintains multiple edges at each valid source-destination state pair.

28. The method of any one of claims 21-26, wherein the parallel list decodermaintains a single edge at each valid source-destination state pair.

29. The method of any one of claims 21-28, further comprising searchingneighboring codewords of estimates produced by the parallel list decoder.

30. The method of claim 29, wherein searching neighboring codewords comprises:using a list of offset codewords with monotonically increasing Hamming weights toconstruct a list of neighboring codewords through XOR operations with the list of offsetcodewords.

31. The method of any one of claims 21-30, wherein the parallel list decoder hasa decoding latency proportional to a log of a block length of the encoded data.

32. The method of any one of claims 21-31, wherein the parallel list decoder isimplemented using parallel processing hardware.

33. The method of claim 32, wherein the parallel processing hardware comprisesa graphics processing unit (GPU).

34. The method of any one of claims 21-33, wherein generating the sequence ofsymbol metrics comprises generating at least one of log likelihood ratios, Euclideandistances, and Hamming distances.

35. The method of any one of claims 21-34, wherein the encoded data is encodedusing a convolutional code.

36. The method of any one of claims 21-34, wherein the encoded data is encodedusing a tail-biting convolutional code.

37. A receiver for decoding short block length messages comprising:an antenna configured to receive a radio frequency (RF) signal comprising encodeddata; ademodulator coupled to the antenna and configured to demodulate the RF signalto obtain symbols;a demapper coupled to the demodulator and configured to generate a sequence ofsymbol metrics based on the demodulated symbols; anda parallel list decoder coupled to the demapper and configured to decode thesequence of symbol metrics to obtain a sequence of received bits, where the parallel listdecoder processes multiple trellis stages in parallel.

38. The receiver of claim 37, wherein the parallel list decoder is furtherconfigured to:divide a decoding trellis into segments;process the segments independently; andcombine the processed segments in pairs to form new segments.

39. The receiver of claim 38, wherein the parallel list decoder is furtherconfigured to:generate edges for all valid source and destination state pairs; andselect a set of edges with best metrics for each pair.

40. The receiver of claim 39, wherein the parallel list decoder is furtherto iteratively process and combine segments until a single segment remains.

41. The receiver of claim 40, wherein the parallel list decoder is furtherconfigured to select a best path from the single remaining segment as a survivor path.

42. The receiver of claim 41, wherein the parallel list decoder is furtherconfigured to reconstruct a decoding estimate by tracing back state transitions of thesurvivor path in reverse order.

43. The receiver of any one of claims 37-42, wherein the parallel list decoder isconfigured to maintain multiple edges for each valid source-destination state pair.

44. The receiver of any one of claims 37-42, wherein the parallel list decoder isconfigured to maintain a single edge for each valid source-destination state pair.

45. The receiver of any one of claims 37-44, wherein the parallel list decoder isfurther configured to search neighboring codewords of estimates produced by the parallellist decoder.

46. The receiver of claim 45, wherein the parallel list decoder is furtherconfigured to:use a list of offset codewords with monotonically increasing Hamming weights toconstruct a list of neighboring codewords through XOR operations with the list of offsetcodewords.

47. The receiver of any one of claims 37-46, wherein the parallel list decoder isconfigured to have a decoding latency proportional to a log of a block length of theencoded data.

48. The receiver of any one of claims 37-47, wherein the parallel list decoder isimplemented using parallel processing hardware.

49. The receiver of claim 48, wherein the parallel processing hardware comprisesa graphics processing unit (GPU).

50. The receiver of any one of claims 37-49, wherein the demapper is configuredto generate at least one of log likelihood ratios, Euclidean distances, and Hammingdistances as the symbol metrics.

51. The receiver of any one of claims 37-50, wherein the encoded data is encodedusing a convolutional code.

52. The receiver of any one of claims 37-50, wherein the encoded data is encodedusing a tail-biting convolutional code.

53. The receiver of any one of claims 34-48, further comprising a processorcoupled to the parallel list decoder and configured to process the sequence of received bitsto extract at least one of control data and application data.

54. A communication system for transmitting and receiving short block lengthmessages, comprising:a transmitter configured to encode input data using a code and transmit a signalbased upon the encoded data; anda receiver configured to receive and decode the signal, wherein the receiver employsa parallel list decoder that is configured to process multiple trellis stages in parallel.

55. The communication system of claim 54, wherein the transmitter comprises:an encoder configured to encode the input data;a mapper configured to map the encoded data to symbols based on a modulationscheme; anda modulator configured to generate an RF signal based on the symbols.

56. The communication system of claim 55, wherein:the receiver further comprises:an antenna configured to receive the RF signal;a demodulator coupled to the antenna and configured to demodulate the RFsignal to obtain symbols; anda demapper coupled to the demodulator and configured to generate asequence of symbol metrics based on the demodulated symbols; andthe parallel list decoder is coupled to the demapper and is configured to decode thesequence of symbol metrics to obtain a sequence of received bits.

57. The communication system of any of claims 54 - 57, wherein the parallel listdecoder is further configured to:divide a decoding trellis into segments;process the segments independently; andcombine the processed segments in pairs to form new segments.

58. The communication system of claim 57, wherein the parallel list decoder isfurther configured to:generate edges for all valid source and destination state pairs; andct a set of edges with best metrics for each pair.

59. The communication system of claim 58, wherein the parallel list decoder isfurther configured to iteratively process and combine segments until a single segmentremains.

60. The communication system of claim 59, wherein the parallel list decoder isfurther configured to select a best path from the single remaining segment as a survivorpath.

61. The communication system of claim 60, wherein the parallel list decoder isfurther configured to reconstruct a decoding estimate by tracing back state transitions ofthe survivor path in reverse order.

62. The communication system of any one of claims 54-61, wherein the parallellist decoder is configured to maintain multiple paths for each valid source-destinationstate pair.

63. The communication system of any one of claims 54-61, wherein the parallellist decoder is configured to maintain a single for each valid source-destination state pair.

64. The communication system of any one of claims 54-63, wherein the parallellist decoder is further configured to search neighboring codewords of estimates producedby the parallel list decoder.

65. The communication system of claim 64, wherein the parallel list decoder isfurther configured to:use a list of offset codewords with monotonically increasing Hamming weights tolist of neighboring codewords through XOR operations with the list of offsetcodewords.

66. The communication system of any one of claims 54-65, wherein the parallellist decoder is configured to have a decoding latency proportional to a log of a blocklength of the encoded data.

67. The communication system of any one of claims 54-66, wherein the parallellist decoder is implemented using parallel processing hardware.

68. The communication system of claim 67, wherein the parallel processinghardware comprises a graphics processing unit (GPU).

69. The communication system of any one of claims 54-58, wherein thedemapper is configured to generate at least one of log likelihood ratios, Euclideandistances, and Hamming distances as the symbol metrics.

70. The communication system of any one of claims 54-59, wherein the encodeddata is encoded using a convolutional code.

71. The communication system of any one of claims 54-59, wherein the encodeddata is encoded using a tail-biting convolutional code.

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