Calculating and displaying predicted overlapping features in IC designs based on predicted manufacturing contours.

Abstract

Some embodiments provide a method for calculating and displaying minimum overlaps of semiconductor layer interfaces, such as metal vias and metal contacts. The method leverages a machine-trained network (e.g., a trained neural network) to rapidly but accurately predict the contours of features manufactured over a range of process variations. The method also models the layer-to-layer misregistration of semiconductor process manufacturing. The combined set of information (from the machine-trained network and from the modeling) is used by the method to calculate minimum overlapping shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlapping shapes to obtain an accurate calculation of via or contact resistance.

Description

[Technical field]

[0001] The present disclosure relates to the calculation and display of predicted overlapping features in an IC design based on a predicted manufacturing contour. [Background technology]

[0002] Among the biggest challenges in chip scaling are contacts and interconnects. As interconnects become more compact at each process node, this negatively impacts RC (resistance-capacitance) delay (and therefore timing, maximum operating frequency, etc.) in integrated circuit (IC) designs. Transistor devices have traditionally scaled well, for example, by moving from planar field-effect transistor (FinFET) devices. However, contacts and interconnects are shrinking as devices shrink, which results in a significant increase in resistance.

[0003] Figure 1 shows an example of interconnects 102, contacts 104, and transistors 106 at various nodes. Transistor devices (Front-End-of-LINE (FEOL) devices) and IC interconnects Back End Of Line (BEOL) are connected by a contact layer called middle-of-line (MOL) where the contacts are formed. Contacts are typically three-dimensional structures with small gaps that are filled with a conductive material such as tungsten. The tungsten structure, called a tungsten plug, is sandwiched between a liner material (titanium) and a barrier layer (titanium nitride). This entire structure is called a contact.

[0004] At the 16nm / 14nm process node, the volume of tungsten conductor material is relatively small. Thus, electrical signals flow through a relatively small amount of conductive metal, causing a significant increase in contact resistance. The electrical resistance of an object is a measure of its resistance to the flow of electric current and is therefore related to the difficulty of passing electric current through a conductor (such as a contact). Contact resistance becomes more problematic at each process node.

[0005] An interconnect is a structure that electrically connects two or more circuit elements (such as transistors) to each other. Modern integrated circuits in state-of-the-art process geometries currently have at least in the range of 9-12 metal (copper) layers. Each layer contains several wire structures, and wires on different layers are electrically connected with vias.

[0006] FIG. 2 shows some examples of interconnect layers 200. Copper interconnects in IC designs are typically fabricated using a dual damascene process in which a low-k dielectric material is deposited on the surface of the device. The low-k dielectric material insulates one device layer from another. Vias and trenches are then patterned and the resulting structure is etched to form the vias and trenches. FIG. 3 shows an example of a dual damascene manufacturing process 300 with etched vias 302 and trenches 304.

[0007] FIG. 4 shows an example of an interconnect line width 400 that has had to scale in size as transistor sizes shrink in modern processes. This has resulted in substantially increased resistance (towards the left side of the graph in the figure). Over the past decade, interconnect dimensions have continued to scale along with transistor devices, resulting in an increase in overall wire length (a several-fold increase from the 90 nm node) coupled with increased resistance and capacitance from thinner wires that are spaced closer together. Foundries have been able to reduce the contribution of resistance to RC delay by increasing the aspect ratio (effectively the height) of the interconnects (resulting in increased coupling capacitance), but resistance is becoming an increasingly difficult problem to solve.

[0008] Figure 5 shows an example of the major issues for 10nm / 7nm process nodes: BEOL performance / area / cross-scaling, and the difficulties at various process nodes. Smaller process nodes are shown on the right, and the y-axis is plotted in logarithmic scale. Figure 5 shows how interconnect RC delays increased by orders of magnitude from 90nm to 7nm, even though transistor delays decreased by less than an order of magnitude.

[0009] A large portion of the RC delay can be attributed to the via resistance, which increases significantly as the wire width decreases. Figure 6 shows an example of the relationship between the via resistance of both a standard via and a chamfered via as a function of the critical dimension of the metal layer.

[0010] An important goal in IC manufacturing is to precisely align the various layers of a wafer, which represents good overlay. For example, a transistor gate on one layer needs to be connected to an interconnect wire on another layer through a contact on another layer. They must all be aligned on top of each other. Such alignment is not perfect in a true manufacturing process, so there are tolerances built into the design rules, both in geometry and performance characteristics. To scale standard cells smaller at each node, the overlay accuracy (alignment) must also scale with the feature size. Metrology system vendors ASML and KLA-Tencor have recently introduced new overlay metrology systems to address the increased precision required for lines, cuts, and other features on each layer. At 10 / 7nm, there are 80 or more masking layers, compared to 40 at 28nm. If these masking layers are not measured accurately, the features that are patterned, deposited, and etched may not align from one layer to the next. The job of the overlay metrology system is to detect undesired shifts in position between layers, as well as process variations. This is an important measurement because overlay failures can affect the performance and yield of a chip, as well as its reliability in the field. However, with each new node, the alignment process becomes much more challenging. Even with these recent advances in metrology systems, overlay / misalignment problems still remain in today's IC manufacturing.

[0011] Multi-patterning for smaller geometry processes makes overlay / alignment issues even more severe. Many of the most difficult alignment challenges exist when layers (masks) need to be aligned to self-aligned quadruple patterning (SAQP) with lower levels in the interconnect stack. As the pitch of the SAQP layers is so small, there is an increased challenge of aligning the edges of higher interconnect levels to the pitch of those lower levels. This complex process becomes significantly more difficult as the process scales from 7nm to 5nm.

[0012] Via resistance can further increase as a function of such process layer misregistration unless specific steps are taken to oversize the vias. For non-oversized vias, the increase in via resistance due to misregistration can be as much as 150%. For oversized vias, the increase in via resistance can be reduced to 10-20%, but is still non-zero.

[0013] In addition to contact and via resistance issues that can affect IC performance (e.g., maximum operating frequency), via misalignment issues pose reliability issues: reducing the via contact area to the connected metal line can degrade electromigration (EM) lifetime due to increased local current density (current density increases as via overlap area decreases).

[0014] Design rules have become more stringent and complex to try to mitigate the issues mentioned above (as shown in Figure 7). Even with design rules that offer some degree of protection, IC designers need to be able to visualize and understand the interconnect resistance and reliability issues in the context of their specific IC design. In a design rule waiver scenario, if the designer can have true visualization of the actual overlap on a per-via instance basis, the designer may be in a position to modify the design layout to improve many of these issues, leading to a higher performing design, improved reliability, or both.

[0015] General purpose IC design rules must be somewhat pessimistic / conservative in nature to accommodate a wide variety of designs since it is not known a priori which polygons will be adjacent to other polygons during IC layout, and therefore the rules must be able to accommodate nearly all possibilities.

[0016] On the other hand, standard cell designers (e.g., SRAM designers) have traditionally been able to take advantage of “DRC waivers” due to the extreme regularity of their designs (e.g., each SRAM cell is surrounded on all sides by identical or nearly identical dummy cells at the periphery of the memory array). This regularity means that it is known a priori which polygons are adjacent to other polygons, and therefore the rules can be somewhat “relaxed”, allowing for tighter packing of polygons compared to what is allowed by the restrictive rules. Packing cells tightly makes more sense when they are repeated many times, and therefore these waivers are often negotiated between the designer and the foundry / fab. Even a very small reduction in bitcell (or any other type of cell that is used highly repetitively, such as a cell in a standard cell library) area can result in exceptionally large improvements in chip density and area reduction at the chip level. Traditionally, efforts have been made in other design areas to use DRC waivers with regularly structured designs / fabrics to result in improved packaging density and / or improved manufacturing yields. Here, the regularity enforced by the design fabric has resulted in some relaxation of the design rule constraints, however this approach is somewhat inflexible as it requires significant regularity to be imposed on the design fabric, thus reducing options for the design and layout engineer. Summary of the Invention

[0017] Some embodiments provide a method for calculating and displaying minimum overlaps of semiconductor layer interfaces, such as metal vias and metal contacts. The method leverages a machine-trained network (e.g., a trained neural network) to rapidly but accurately predict the contours of features manufactured over a range of process variations. The method also models the layer-to-layer misregistration of semiconductor process manufacturing. The combined set of information (from the machine-trained network and from the modeling) is used by the method to calculate minimum overlapping shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlapping shapes to obtain an accurate calculation of via or contact resistance.

[0018] The method of some embodiments also helps the IC designer intuitively understand exactly how to arrive at the final overlapping shape. The method of some embodiments provides a passive animation scheme that is presented in a manner similar to a video file playback. Additionally or alternatively, the method of some embodiments provides a dynamic animation scheme that is also presented in a video-like manner, but allows the user to continue to manipulate the layout editor, for example to perform operations (e.g., design editing operations, view operations such as zoom and pan) on the target shape, while the layout editor (e.g., router) itself is used to dynamically display the animation.

[0019] The method of some embodiments extends the animation with a baseline of perfectly aligned images between the misaligned images to provide a static visual frame of reference to allow the animation details to be better understood by the layout engineer (e.g., overlaying the animation on top of the IC design layout defined by the layout editor). The animation allows the layout engineer to visualize the effects of process fabrication layer misalignment while simultaneously visualizing the fabricated process wafer contour in a variation-aware manner, helping them intuitively understand how the minimum overlapping shapes are obtained.

[0020] Due to the dynamic nature of the computed shapes being scheduled and redrawn by the layout editor, the method of some embodiments can redraw the shapes at the same level of granularity as the design shapes, providing the designer with the clearest picture, even when highly zoomed in at low zoom height levels. The method of some embodiments also provides several higher level layout editing tasks that leverage computation to optimize the layout for improved overlap area, reduced metal via and metal contact resistance, and improved long term reliability. The method uses highly parallel computing architectures (such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs)), thereby improving throughput compared to conventional means.

[0021] The method of some embodiments provides the layout designer with enough information to visualize the contact and via overlap on a contact-by-contact or via-by-via basis so that the layout can be modified to further improve the overlap and minimize resistance. The method also extends the concept and application of DRC exempt design to more arbitrary design scenarios (e.g., custom IC designs) during design layout time, effectively simplifying the design rules for the layout designer and improving the resulting design yield and manufacturability. Some embodiments achieve this without compromising layout flexibility, i.e., without forcing the layout designer to use a small number of pre-defined layout templates.

[0022] Some embodiments use machine learning processes to present designers with a "WYSIWYG" (What You See Is What You Get) paradigm for contacts / vias and metal overlap. These embodiments enable interactive design updates while visualizing the expected manufactured silicon results in real time. In particular, some embodiments use machine-trained neural networks to predict the shape of the wafer contour for metal, contact, and via geometries along with their process variations (inner and outer contours) after a particular manufacturing stage of the manufacturing process used to produce an IC based on the design layout.

[0023] Combining such a machine-trained network with other described aspects of the method of some embodiments allows for the calculation of IC designs with minimum contact or via metal overlap areas in the presence of both process variations and mask misalignment during semiconductor manufacturing. The method of some embodiments presents the minimum overlap area to the circuit designer in the context of the circuit design itself and within the tools used to generate the circuit design. Furthermore, to allow the designer to understand how the minimum overlap area is obtained in the context of a particular integrated circuit design, the method of some embodiments allows the designer to make layout modifications specific to that design to improve the minimum overlap area and thus reduce the contact or via metal resistance, improve operating frequency, and also improve reliability. By providing the designer with sufficient information, the method allows the designer to locally optimize contacts and vias on a per-contact or per-via instance basis with layout modifications as a function of the surrounding design features.

[0024] Those skilled in the art will appreciate that other embodiments are implemented differently. For example, some embodiments do not use machine-trained networks to generate contours of manufactured features over a range of process variations, but rather generate these contours by other programmatic or algorithmic methods. Others only model semiconductor process manufacturing interlayer misregistration in the predicted overlap features they present, without considering contour variations due to manufacturing process variations. Alternatively, still other embodiments do not consider interlayer misregistration in the predicted overlap features, but rather only consider contour variations due to manufacturing process variations.

[0025] The above "Summary" is intended to serve as a brief introduction of some embodiments of the present invention. It is not intended to be an introduction or summary of all inventive subject matter disclosed herein. The following "Description of the Invention" and the "Drawings" referenced in the "Description of the Invention" further describe not only the embodiments described in the "Summary of the Invention" but also other embodiments. Therefore, in order to understand all embodiments described herein, the "Summary of the Invention", the "Description of the Invention", the "Drawings", and the "Claims" must be thoroughly considered. Furthermore, the claimed subject matter is not limited by the illustrative details in the "Summary of the Invention", the "Description of the Invention", and the "Drawings". [Brief description of the drawings]

[0026] The novel features of the invention are set forth in the appended claims. However, for purposes of illustration, certain embodiments of the invention are set forth in the following drawings. [Figure 1] 1 shows an example of interconnects, contacts, and transistors at various nodes. [Diagram 2] Some examples of interconnect layers are shown. [Diagram 3] 1 illustrates an example of a dual damascene manufacturing process with etched vias and trenches. [Figure 4]Illustrates an example of interconnect line widths that have had to be scaled in size as transistor sizes shrink in modern processes. [Diagram 5] An example of BEOL performance / area / cross-scaling, which are the major issues for 10nm / 7nm process nodes, and the difficulties at various process nodes is given. [Figure 6] 1 shows an example of the relationship between via resistance for both regular and chamfered vias as a function of the critical dimension of the metal layer. [Figure 7] Shows the growth of design rules. [Figure 8] 1 shows an example of curvilinearization of a Manhattan shape by a manufacturing process. [Figure 9] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 10] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 11] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 12] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 13] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 14] 1 shows an example of multiple contours being generated and displayed for metal, contact, and via features. [Figure 15] 13-14 show the process for generating the derived contours. [Figure 16] 13 illustrates the use of a neural network to infer manufactured shape tiles from rasterized CAD data input tiles, illustrating the operation of the neural network portion of the process in some embodiments. [Figure 17]13 illustrates the use of multiple neural networks to infer the shape tiles produced in another embodiment. [Figure 18] 15 shows an example of a further zoomed-in view of the design space highlighted within the rectangle of FIG. 14. [Figure 19] 19 shows an even more zoomed in and highly detailed view of the metal / contact intersection corresponding to the box in FIG. [Figure 20] 1 illustrates a process used in some embodiments to calculate minimum overlapping shapes of a multi-layer interface having components on multiple layers. [Figure 21] 21 shows a process that provides one way of implementing the process of FIG. 20. [Figure 22] 22 shows a process illustrating one of the steps of FIG. 21. [Diagram 23] 1 shows a table listing the misregistration translations applied to each layer in some embodiments. [Figure 24] 1 shows a table listing the misregistration translations applied to each layer in some embodiments. [Diagram 25] 1 shows a table listing the misregistration translations applied to each layer in some embodiments. [Figure 26] 1 shows an example of one misalignment configuration that illustrates the non-overlapping area due to misalignment. [Figure 27] 13 shows an example of a dynamic ruler measurement of a selected minimum overlap area polygon width. [Figure 28] 13 illustrates an example of a dynamic display of minimum overlay area polygon properties including area. [Figure 29] An example of the initially drawn contact polygon, only the inner contour of the fabricated contact and metal, and the minimum metal / contact overlap are shown. [Diagram 30] 1 illustrates an example of a graphical user interface for configuring a minimum overlap calculation that is provided to assist a user in the task of configuring the operations to be performed in some embodiments. [Diagram 31]1 illustrates a process for looping video-like animation using still images. [Diagram 32] 1 illustrates the process by which an image sequence is generated. [Diagram 33] 13 illustrates an example of misaligned contours for metal and contact features showing nominal contours, inner contours, and outer contours with all three sets of contours rendered. [Diagram 34] Presents a set of GUI controls that can make it easy to specify exactly which contours to show. [Diagram 35] GUI controls such as forward, reverse, and fast forward / rewind buttons are shown for fine control over the sequence of such scheduled animations. [Diagram 36] By taking the minimum overlapping polygon of the Metal 1 via layer interface together with the minimum overlapping polygon of the Metal 2 via layer interface and assuming an "approximately" cylindrical shape, an example of a routing structure is shown in which a 3D via shape can be calculated for the via. [Figure 37] 1 conceptually illustrates an electronic system in which some embodiments of the present invention may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and explained. However, it will be apparent to one of ordinary skill in the art that the invention is not limited to the described embodiments, and that the invention may be practiced without some of the specific details and examples described.

[0028] Some embodiments provide a method for calculating and displaying minimum overlaps of semiconductor layer interfaces, such as metal vias and metal contacts. The method uses a machine-trained network (e.g., a trained neural network) to rapidly yet accurately generate multiple contours of features manufactured over a range of process variations. The method also models the layer-to-layer misregistration of semiconductor process manufacturing. The combined set of information (from the machine-trained network and from the modeling) is used by the method to calculate minimum overlapping features at multiple layer interfaces. The method in some embodiments then uses the minimum overlapping features to obtain an accurate calculation of via or contact resistance.

[0029] Some embodiments use machine learning processes (such as the deep neural network processes disclosed in U.S. Patent Application Publication No. 2022 / 0128899, incorporated herein by reference) to present designers with a "What You See Is What You Get" (WYSIWYG) paradigm for contacts / vias and metal overlap. These embodiments enable interactive design updates while visualizing the expected manufactured silicon results in real time. In particular, some embodiments use machine-trained neural networks (such as the neural networks disclosed in U.S. Patent Application Publication No. 2022 / 0128899) to predict the shape of the manufactured wafer contour for metal, contact, and via shapes along with their process variations (inner and outer contours).

[0030] The predicted shapes of the contours represent the expected shapes of those contours after a particular manufacturing stage of a manufacturing process used to manufacture an IC based on the design layout, which may be a stage that results in the final manufactured IC or an earlier stage, such as a wafer simulation stage, as further described in co-filed U.S. patent application entitled "Leveraging Concurrency to Improve Interactivity with an EDA Tool," docket number D2S.P0007.

[0031] Combining such a machine-trained network with other described aspects of the method of some embodiments allows for the calculation of IC designs with minimum contact or via metal overlap areas in the presence of both process variations and mask misalignment during semiconductor manufacturing. The method of some embodiments presents the minimum overlap area to the circuit designer in the context of the circuit design itself and within the tools used to generate the circuit design. Furthermore, to allow the designer to understand how the minimum overlap area is obtained in the context of a particular integrated circuit design, the method of some embodiments allows the designer to make layout modifications specific to that design to improve the minimum overlap area and thus reduce the contact or via metal resistance, improve operating frequency, and also improve reliability. By providing the designer with sufficient information, the method allows the designer to locally optimize contacts and vias on a per-contact or per-via instance basis with layout modifications as a function of the surrounding design features.

[0032] Those skilled in the art will appreciate that other embodiments are implemented differently. For example, some embodiments do not use machine-trained networks to generate contours of manufactured features over a range of process variations, but rather generate these contours by other programmatic or algorithmic methods. Others only model semiconductor process manufacturing interlayer misregistration in the predicted overlap features they present, without considering contour variations due to manufacturing process variations. Alternatively, still other embodiments do not consider interlayer misregistration in the predicted overlap features, but rather only consider contour variations due to manufacturing process variations.

[0033] Before describing more detailed embodiments, we will describe the generation of multiple contours corresponding to multiple variations of manufacturing process parameters. Most IC designs today are generated with straight-line features using Manhattan routing, or sometimes 45-degree routing. When these designs are manufactured, the features deposited on the substrate are no longer Manhattan. In other words, the features deposited on the substrate during manufacturing become very curvilinear due to manufacturing realities, especially in modern process geometries.

[0034] 8 shows an example showing a linear shape being modeled by three sets of curved contours, which in some embodiments are generated by one or more machine-trained networks. The linear shapes in this example are identified by cross-hatched lines. In this example, the cross-hatched linear / Manhattan shape is overlaid with three sets of curved lines having three different appearances, such as three different colored contours (e.g., green for the inner contour, dark blue for the nominal contour, and purple for the outer counter).

[0035] The cross-hatched linear shapes represent different color masks for metal layers, e.g., cross-hatching from right to left for a blue mask and cross-hatching from left to right for a red mask. The three sets of curved manufactured contours shown correspond to one manufacturing process extreme (e.g., inner contour for maximum variation), nominal process conditions (e.g., nominal contour for nominal variation), and another manufacturing process extreme (e.g., outer contour for minimum variation). The manufacturing process variations resulting in multiple contours (inner, nominal, outer) combined with the process layer misregistration problem make it difficult for designers to understand how much actual via or contact overlap exists based on a via-by-via or contact-by-contact instance, and therefore difficult to predict how best to design the layout for maximum overlay with minimum contact / via resistance and best reliability. The generation of such contours through the use of machine trained networks is further described in the above-incorporated U.S. Patent Application Publication No. 2022 / 0128899.

[0036] 9-14 show an example of generated and displayed contours for metal, contact, and via shapes. This example refers to a standard cell 900 in FIG. 9. The standard cell 900 is from a standard cell library. The diagram in FIG. 9 presents multiple design layers (also called interconnect layers or metal layers) of an IC that correspond to multiple wiring layers (including a substrate layer) of the IC. As shown, the standard cell 900 includes a polysilicon layer 902 (displayed on the display screen in a first color, e.g., green), a metal layer 904 (displayed in a second color, e.g., dark blue), a contact layer 906 represented by a small square, and a pin layer 908 (displayed in a different design, e.g., dark blue square with a stippled "X"). N and P implant layers are also seen with diagonal stipples and colors (displayed in a third and fourth color, e.g., orange and yellow).

[0037] 10 shows a standard cell 900 showing only the metal, pin, and contact layers, along with the cell boundary. This figure shows the same standard cell where only a subset of the layers are visible (contact, metal, and pin layers). The standard cell boundary box is also visible in a different color (e.g., light blue). The focus of some embodiments is the interconnect stack, including contact layers when available.

[0038] FIG. 11 shows an example of the fabricated contours of the metal 1 layer of standard cell design 900 superimposed on the design. Even at this high zoom level, it is clear that the corners of the metal features have been rounded during fabrication, resulting in more complex shapes compared to the purely rectilinear shapes of FIG. 10. Although not apparent from this level of zoom, in some embodiments, there are three contours in the image of each metal feature that correspond to the inner, nominal, and outer contours fabricated on the silicon wafer. These inner, nominal, and outer contours become more apparent in later views where lower advanced zoom levels are developed.

[0039] FIG. 12 shows an example of the fabricated contours of a contact layer superimposed on the metal and contact layers of a standard cell design 900. The fabricated contours are shown as black circles. Again, at this particular zoom level, the distinction between the inner contour, nominal contour, and outer contour is not clear, but will become clear in later figures. The contact shape 1206 in some embodiments is not fabricated as a square as originally drawn (e.g., in FIG. 10), but instead is fabricated with rounded corners, resulting in a final shape that appears circular (especially if the corners are highly rounded). In this particular figure, the metal layer contours are not shown, and instead the linear shapes of the designer-drawn layout are shown.

[0040] 13 shows an example of the fabricated contours of the metal 1 and contact layers of a standard cell design superimposed on the design. The fabricated shapes are again curvilinear, as is apparent from the figure. As shown, the fabricated shapes of the contact and metal 1 layers are perfectly aligned with the original design shapes and with each other, which does not reflect the reality of manufacturing where such perfect alignment rarely occurs.

[0041] FIG. 14 shows a lower elevation zoomed-in view 1400 of a portion of the design that generally corresponds to the rectangular highlighted area 1302 in FIG. 13. Here, the inner, nominal, and outer contours of both the metal 1 layer features and the contact layer features are now seen as dashed lines with a thin line thickness. In some embodiments, the minimum overlapping polygon 1402 for each metal / contact location is shown as a thick dashed line. In some embodiments, a contact refers to a multi-layer interface that connects a portion of a circuit element on an IC substrate with one or more lower metal layers (e.g., metal layer 1) to form a circuit element (e.g., to form a transistor), a via refers to an interconnect line (e.g., a line representing a wire) on a different metal layer and a multi-layer interface that connects an upper layer interconnect line to a circuit element, and a metal refers to an interconnect that connects to a contact or a via.

[0042] FIG. 15 illustrates a process 1500 for generating the contours from which FIGS. 13-14 were derived. As illustrated, the layout editing software first saves (at 1505) a copy of the design. Then, at 1510, a manufacturing software process launches, acquires licenses, biases up the metal / contact / via layers of the design (increases the size by expanding each polygon edge by a certain amount), and converts the design to a rasterized format (converts from the geometry domain of the layout editing tool to the raster domain, i.e., pixelated image format). The pixelated image is then cropped into a number of smaller tiles.

[0043] At 1515, a deep learning software process is launched and uses the trained deep learning model to predict the shape that will appear on the wafer after fabrication. The process loads its neural network with its weights and generates a matching set of tiles that correspond to the input design. It then reconstructs these tiles to form a pixelated image of the manufactured design shape.

[0044] At 1520, the manufacturing software process (1) starts again, (2) contours the reconstructed pixel image to determine the exact curved manufacturing shape contour, and then (3) etches down the predicted contour design so that it can be viewed and manipulated in the geometry domain utilized by the layout editing software. The deep learning inference process is effectively repeated for multiple sets of process conditions such that minimum (inner), nominal, and maximum (outer) corner images are obtained. At 1525, the manufacturing software process determines whether it has processed the design components for all colors. If so, process 1500 ends. If not, process 1500 returns to 1510 to repeat the operations for another set of components of another color.

[0045] The process of FIG. 15 is simplified to facilitate description and understanding of the process from a high-level view. As shown, its performance in terms of elapsed time is relatively poor. A more complex alternative, involving manufacturing software processes and deep learning software processes running in parallel on multiple servers, can significantly increase throughput. Such an alternative is described in detail in U.S. Provisional Patent Application No. 63 / 283520 and a co-filed U.S. patent application having docket number D2S.P0007, entitled "Leveraging Concurrency to Improve Interactivity with an EDA Tool." The provisional application No. 63 / 283520 and the co-filed non-provisional patent application (docket number D2S.P0007) are incorporated herein by reference.

[0046] 16 shows an example of the use of a neural network to infer manufactured feature tiles from rasterized CAD data input tiles. This example illustrates the operation of the neural network portion of process 1500 in some embodiments, where a single neural network is used to infer multiple output tiles at once, corresponding to different sets of process conditions. For example, the output tiles in some embodiments represent wafer images at process nominal conditions in addition to wafer images at process extremes.

[0047] 17 illustrates the use of multiple neural networks to infer manufactured feature tiles in another embodiment, where multiple trained neural networks are used to infer output tiles, with each neural network trained to generate tiles corresponding to a different set of process conditions. For example, the output tiles from the various networks in some embodiments each represent wafer images at process nominal conditions in addition to process extremes.

[0048] Returning now to the discussion of the fabricated contours of the metal, contact and via layers, a further zoomed-in view 1800 of the design area highlighted within rectangle 1404 in FIG. 14 is shown in FIG. 18. Here, the inner, nominal and outer contours of the circular fabricated contact shape, as well as the larger metal "finger" shapes, are clearly visible. It is also clear that the metal / contact minimum overlap shape (shown as a thick dashed line in a first color, e.g., red) is even smaller in area than the inner contour of the contact shape itself (shown as a thin dashed line in a second color, e.g., blue), as will be explained later. Looking closely at the area marked by the gray box in the figure, it appears clear that the inner, nominal and outer contours of the metal shape are nearly identical to the corresponding contours of the contact shape.

[0049] Figure 19 shows an even more zoomed-in, highly detailed view 1900 of the metal / contact intersection, corresponding to box 1802 of Figure 18, including details of the originally drawn polygon, the fabricated contour, and the minimum metal / contact overlap. In this view, the inner contour of the metal "finger" shape is nearly coincident with the (circular) inner contour of the contact shape, which reflects reality when these semiconductor layers are perfectly aligned during fabrication. However, due to misalignment problems inherent in real-world fabrication, this is rarely, if ever, the case.

[0050] Without the benefit of some embodiments, it would be difficult or impossible for a circuit designer to envision or predict the inner / nominal / outer contour resulting from any individual metal / contact intersection, given that the details of the fabricated contour actually vary as a function of adjacent features in the design. For example, a metal feature fabricated in isolation will result in a different contour than one fabricated in close proximity to another. The same is true for contacts or vias. Given this, it is even more difficult for a designer to envision the minimum metal / contact (or metal / via) overlap area, and therefore accurately predict the resistance of that portion of the interconnect stack. Small geometry process interconnects are known to suffer from high resistance at the metal / via or metal / contact interfaces, and therefore it is important that these are tightly controlled.

[0051] To guarantee a minimum overlap area and a corresponding maximum overlap resistance, design rules typically exist for designers to overlap metal or via polygon shapes by a certain amount when drawing the metal shapes. However, for designers working in design rule waiver scenarios, it is desirable to know exactly what the minimum overlap shape is so that the exact manufactured overlap area (and corresponding resistance value) can be calculated as a function of the actual circuit layout and the circuit layout modified until these values ​​are within tolerance.

[0052] In order to accurately calculate the minimum overlap for any given metal / contact or metal / via intersection (and therefore the corresponding resistance value), the contours of the fabricated metal and contact / via shapes must be known, taking into account neighborhood / proximity effects. In some embodiments, these contours are first determined by a trained neural network, such as the network detailed in U.S. Patent Application Publication No. 2022 / 0128899. A brief overview of the process by which this is accomplished is presented with respect to FIGS. 15-17. In some embodiments, the known contours can then be used to calculate the minimum overlap.

[0053] While it is possible to calculate the overlap shape using all available contours, some embodiments perform the overlap calculation more efficiently (e.g., for maximum process variation) using only the inner contours and ignoring process conditions corresponding to the outer or nominal contours. FIG. 20 shows a process 2000 used in some embodiments to calculate the minimum overlap shape of a multilayer interface having components on multiple layers. The process 2000 starts by determining a contour for each layer of a layer pair by using a trained neural network (at 2005). For each translation value in the translation table, the inner contour is translated (at 2010) by the translation value relative to the layer in (x,y). The process collects (at 2015) all translated layer contour polygons and intersects (at 2020) all translated layer contour polygons via a Boolean AND operation to obtain the minimum overlap shape of a multilayer interface having components on multiple layers. After 2020, the process ends.

[0054] Figure 21 shows a process 2100 that provides one manner for performing the process 2000 of Figure 20. As shown, the process selects (at 2105) a layer that is traversed by a multi-layer interface (e.g., a metal contact or metal via) having components on multiple layers. Next, the process determines (at 2110) the inner contours of various semiconductor shapes. At 2115, the process applies a series of mathematical translation transformations, one for each translation value in a table of translation values.

[0055] In a translation transformation, all points in an object are moved in a straight line in the same direction. The size, shape, and orientation of the image are the same as the original object. Same orientation means that the object and the image face the same direction. With each such translation value, the process translates (at 2120) the inner contour, or "slides" it by a particular amount in a particular direction, and all such translated contours are collected.

[0056] Next, at 2125, the process determines whether all translation values ​​have been exhausted for a particular layer. If so, the process determines (at 2130) whether another layer in the pair should be investigated, and the process is repeated. Thus, the translation operations model the outcome of various possible misregistrations in the manufacturing process. After the last layer is exhausted, all translated shape contours are collected, and the process intersects (at 2135) via a Boolean operation to calculate the minimum overlap area, taking into account all misregistrations. After 2135, the process ends.

[0057] Some of the embodiments described above calculate the shape of the overlapping area by using an inner contour, while other embodiments use a nominal contour and / or an outer contour as described above. Other embodiments generate multiple overlapping shapes by intersecting multiple sets of contours (e.g., one shape by intersecting the inner contour, another by intersecting the nominal contour, and yet another by intersecting the outer contour). For each of these shapes, these embodiments perform a process similar to process 2100 of FIG. 21.

[0058] 22 shows a process 2200 illustrating step 2135 of process 2100. As shown, the process moves (at 2205) to a first layer (L1) and sets (at 2210) a first set of translated contours for the first layer as initial results. The process then moves (at 2215) to a second layer (L2) and retrieves (at 2220) the next set of translated contours for the second layer L2. The initial results from 2210 are then subjected (at 2225) to a Boolean AND operation with each set of translated contours for the second layer.

[0059] This process is repeated until it determines (at 2230) that there are no more translated contours for the second layer. The process then determines (at 2235) whether there is another set of translated contours for the first layer. If so, the process returns to retrieve (at 2240) the next translation for the first layer and performs (at 2245) a Boolean AND operation of the result with each set of translated contours for the first layer and continues the operation. If not, the process 2200 ends.

[0060] In this way, all combinations of translated inner contours for the first and second layers are explored and Boolean ANDed together to generate the final result. At the end of the process, each of the original polygonal shapes from the initial set of "inner" contours has been reduced to a minimal shape that represents the intersection of all shapes (per shape), such as the one shown in FIG. 19 with the thick dashed line (displayed in a first color, e.g., red).

[0061] During the process of FIG. 21, the inner contour of each manufactured layer shape is calculated and "misaligned" within known misalignment limits known for the manufacturing process of that layer. A representative number of such possible misalignments is calculated, as listed in a misalignment table 2300 of FIG. 23, described further below, and the layer contours are translated in the (x,y) directions by the corresponding misalignment amounts accordingly. All manufactured shapes on any given layer are assumed to be misaligned in the same way due to printing biases in the manufacturing process. Thus, the misalignment can be applied to all inner contour shapes of a given layer via the same affine transformation with translation in the X and / or Y directions.

[0062] In some embodiments, the misalignment translations applied to each layer are listed in table 2300 of FIG. 23. Here, the maximum misalignment is assumed to be up to 2 nm in either the X or Y direction, and the four rows in the table correspond to misaligning the layers by the maximum misalignment amount (2 nm) in each of the four cardinal compass directions (N, E, S, W). The translations can be applied in any order, but it is best to perform or collect them in a clockwise or counterclockwise direction, for example within the order shown in the table. The reason for this will become more clear below when the results of such operations are presented to the user via a sequence of animations. Having a smooth order of reorientations in a circular fashion, rather than an arbitrary or "jerky" fashion, improves the user experience and reduces the cognitive burden when viewing the animation.

[0063] In other embodiments, the misalignment translations applied to each layer are listed in table 2400 in FIG. 24, where the maximum alignment is assumed to be a maximum of 2 nm in either the X or Y direction, and the four rows in the table correspond to misaligning the layers by the maximum misalignment amount (2 nm) in each of the four ordinal compass directions (NE, SE, SW, NW). For even more accurate representation, additional values ​​in some embodiments can be included in the table, where the contours are misaligned in both the X and Y directions at once, instead of just one direction at a time. Again assuming a maximum misalignment of 2 nm in either the X or Y direction independently, the resulting table 2500 is shown in FIG. 25, where misalignments in both the four cardinal (primary) compass directions and the four ordinal compass directions are included.

[0064] In some embodiments, different misalignments can be investigated for different pairs of interconnect layers, and in some embodiments, different misalignments can be investigated for different x-axis and y-axis directions. The misalignment in some embodiments is defined relative to the z-axis, which is the vertical axis along which the metal layers are stacked on top of the substrate layers and on top of each other.

[0065] The intersection of the misaligned polygons for calculating the minimum overlap is calculated by a Boolean AND operation in some embodiments using any of a variety of algorithms. Some standard algorithms that can be used to calculate the resulting clipped polygon given a translated inner contour polygon include the Greiner-Hormann clipping algorithm and the Sutherland-Hodgman clipping algorithm. These algorithms are applied layer by layer sequentially. If only two layers are involved, only a single layer intersection is performed, but if multiple layers are involved (e.g., M1-Via1-M2), an intersection operation is performed at each layer interface (e.g., M10-Via1) and (Via1-M2). Figure 26 shows a graphical example of such a Boolean layer AND operation.

[0066] FIG. 26 shows an example 2600 of one misalignment configuration illustrating the non-overlapping area due to misalignment. Here, the inner metal contour is shown translated to the left by the maximum misalignment amount. The inner contact layer contour is shown translated by a different amount (one of the possible combinations). By ANDing the two translated layers together (intersection operation), the non-overlapping circled area 2602 is effectively removed, thus "clipping" the minimum overlap shape on the right edge, as indicated by the large white arrow. Other edges are also "clipped" by this operation, but are not shown in the figure for simplicity.

[0067] A minimum overlapping polygon is generated for each layer interface, and all overlapping polygons for a particular layer interface are assigned to a dedicated Layer Purpose Pair (LPP) in a layout editor such as Synopsys's Custom Compiler or Cadence's Virtuoso for displaying the results. LPPs can be thought of as physical or other design entities used as visual representations of different types of information, such as mask geometry and interconnects in a schematic. Each unique layer purpose pair has its own associated color, highlighting, menus, and design objects. A visual example of different LPPs in use is shown in FIG. 9, where different colors and stipple patterns associated with these LPPs were used to indicate various design layers, such as polysilicon, metal 1, contacts, etc.

[0068] By dynamically generating minimum overlapping polygons on a dedicated LPP in the layout editor for a given design and storing these polygons within or alongside the regular polygons that represent the design database itself, it is possible for the layout editor tool to render the minimum overlapping polygons along with the polygons of the design cells themselves (polygons drawn by the designer) and have the overlapping polygons dynamically redrawn by the layout editor software at the correct zoom levels as the user interacts with the design via zoom and pan operations in the user interface. Examples of the results of these dynamic redraw operations are shown in Figures 11-14, 19, and 20. For each zoom / pan viewport presented in the figures, the minimum overlapping polygons are simultaneously drawn at the same resolution as the other design views.

[0069] In some embodiments, the minimum overlapping polygons are drawn using LPPs that are drawn above / after the regular design polygons and the contours of the metal and via / contact layers. In some embodiments, a stipple pattern is used that effectively makes the minimum overlapping polygons semi-transparent even if drawn with an opacity value of 100%. In other embodiments, the contours and / or the minimum overlapping polygons are drawn using opacity values ​​less than 100%, making them appear semi-transparent despite the stipple pattern.

[0070] In some embodiments, various interactive user operations are possible on the minimum overlap contour displayed in the layout editor. For example, it is possible to select an overlapping shape and query its properties such as bounding box, location of individual polygon vertices, etc. Figure 27 shows an example of a dynamic ruler measurement 2702 of a selected minimum overlap area polygon width. Measurements such as inserting a dynamic ruler measure the distance between a point or edge on the minimum overlap contour and an adjacent shape in the design.

[0071] FIG. 28 shows an example of dynamic display of minimum overlay area polygon properties including area. By dynamically hovering the mouse near an overlapping shape, the shape is highlighted (e.g., in bright yellow) and a semi-transparent (or opaque) information balloon 2802 can dynamically appear after a short delay, displaying the outline shape's properties (its constituent points, overall bounding box, etc.). In some embodiments, the (maximum) resistance of the minimum overlay polygon is further calculated and displayed either in the property editor, the dynamic information balloon, or both, based on the polygon's area and other information in the technology file (material the contact / via is made of, its height, resistivity, etc.). The presented information allows the designer to modify the layout (e.g., to decrease the maximum resistance and increase the minimum overlapping area) and repeat the analysis process for validation.

[0072] In some embodiments, only the inner contours of the various layers included in the overlay are shown. Figure 29 shows an example of the originally drawn contact polygon 2902, only the inner contours of the fabricated contacts and metal 2904, and the minimum metal / contact overlap 2906. In this figure, the originally drawn metal shapes are not shown, nor are the nominal or outer contours of the fabricated shapes of either the contacts or the metal.

[0073] While it is most important to consider the case of minimum overlap (as this results in the maximum resistance that is important for circuit performance), it is also important for the designer to know the range of possible overlap values ​​for each contour area. This can be used to determine the resistance range (minimum, nominal, and maximum resistance values) for any given contact or via. The technique for determining minimum overlap in the presence of manufacturing variations, neighborhood effects, and manufacturing layer misregistration can also be used to calculate nominal overlap. In this situation, instead of using the minimum contours in the process of FIG. 20, the nominal contours are used in their place. The resulting area and contact / via resistance calculations then represent the "typical" or nominal case in terms of process variations, in the presence of the same manufacturing misregistration. Similarly, the outer contours can be substituted to calculate the maximum overlap area (and its associated resistance), thus establishing the minimum resistance for each contact / via instance in the presence of manufacturing process variations and layer misregistration.

[0074] FIG. 30 illustrates an example of a graphical user interface 3000 for configuring a minimum overlap calculation, provided to assist a user in the task of configuring operations to be performed in some embodiments. The user interface 3000 includes a checkbox 3002 to enable / disable the entire process of generating a minimum shape overlap after the contours have been determined (e.g., by using a separate GUI control such as a push button to initiate and display such contours). The interface 3000 includes a control 3004 that allows a maximum misalignment value to be specified in nanometers. The user interface 3000 also includes several mutually exclusive controls 3006-3012 that indicate how the misalignment translation transformation should be performed, effectively allowing the user to select between one of any number of translations of any magnitude and in any direction via input of (1) the default major compass points table of FIG. 23, (2) the default ordinal compass points table of FIG. 24, (3) the 8 default major+ordinal compass points table of FIG. 25, or (4) a custom value table.

[0075] The custom value table allows the user to enter their own values, adding new rows or deleting existing rows as necessary, and setting the values ​​of the alignment X and Y parameters differently for each row. In some embodiments, different magnitudes of the misalignment translation vector are also entered here (e.g., the figure shows the user entering values ​​corresponding to a maximum misalignment value of 3 nm in any of the eight compass directions). In some embodiments, different directions from the cardinal and ordinal compass points are also entered, and the number of rows includes any positive integer. A standard table editing interface, familiar to those skilled in the art of GUI design, is also used here.

[0076] While displaying (and interacting with) the minimum overlap area polygon is useful for circuit designers to understand the causes of contact / via resistance, it would be even more useful to further assist the designer in intuitively understanding exactly how to arrive at those overlap shapes. Such understanding can help the designer modify the design layout to achieve the desired overlap shapes (and corresponding resistance values). This is especially true for designers working in design rule waiver scenarios, who have more freedom to modify the design layout to achieve minimum resistance and therefore maximum device performance, but also true for designers working in standard DRC enforcement flows.

[0077] By better understanding the reasons for exactly what the minimum overlap shape is, a designer can do a better (or faster) job of modifying the design layout. In particular, if a designer can understand exactly how each edge of the minimum overlap area polygon was determined for a particular contact or via of interest, the designer can be in the best position to modify the layout to move that edge further outward, thus increasing the minimum overlap area.

[0078] Some embodiments use several different methods to present this understanding to the user, including looped video-like animation and dynamic interactive animation generation, in which a sequence of still images is generated to show the manufactured design features "moving" smoothly through a range of motion selected to represent the misalignment.

[0079] FIG. 31 shows an animation process 3100 for looping video-like animation using still images. First, the process generates (at 3105) a sequence of images or screenshots, in each of which the design shape is "wobbled" out of position, i.e., purposely displaced by one of the translations in the translation table. When the video is played in a loop, the playback process advances (at 3110) to the next image in the sequence, renders that image (at 3115), and then pauses (at 3120) to allow the user to understand what has happened. After the pause, the process continues with the next image in the sequence. When the list of images is exhausted, the process "loops" back to the starting image. As previously discussed in the discussion of generating displaced translation transformations, when presenting these images, it is best to do so in a manner in which the displacedness is applied in a "cyclical" manner rather than in some arbitrary or "jerky" manner. This reduces the cognitive burden on the user when watching the animation and makes learning easier. A sequence of overlapping images (such as the overlapping shapes of Figures 26 and 27, or overlapping images generated by overlaying the contours shown in Figures 18 and 19) are presented to the user, with some "frames" in the sequence showing a portion of a valid via or contact shape cropped to its minimum value.

[0080] In some embodiments, the translations are extended by adding additional translations to the sequence, which effectively "move" the layer shapes back to their unaligned (i.e., perfectly centered) positions. The frames generated in this manner are rendered between the misaligned frames, so that the user experiences the shapes moving as if they were misaligned, then all perfectly aligned ("move" back out of alignment), then disaligned again to a different misaligned position, and so on. This intervening unaligned (centered) frames further helps the user form a better mental image of the animation sequence, since the animation reversal provides a static reference point between each animation frame, thus providing better visual continuity and reducing confusion.

[0081] In some embodiments, standard video playback controls are provided that allow the user to simply play the animation sequence in a loop, pause (pause) the video, or resume the video. In some embodiments, the user can also control the playback speed and / or direction (i.e., the user can reverse the order in which the animations are shown). This can allow the user to more easily focus on a particular cropping event, determine which contour edge is responsible for the crop, and therefore determine which edge to move by editing the corresponding layout shape(s), perhaps by modifying the shape size, position, or both.

[0082] FIG. 32 illustrates a process 3200 in which an image sequence is generated. As illustrated, the process moves (at 3205) to a first layer (L1), translates (at 3210) all layer L1 shapes by the next translation amount, renders the screen, and captures an image. Then, the process moves (at 3215) to a second layer (L2), retrieves (at 3220) the next translation value for the second layer. Then, the process translates (at 3225) all layer L2 shapes by the next translation amount, renders the screen, and captures an image. The process repeats until it determines (at 3230) that there are no more translation values ​​for the second layer. Then, the process determines (at 3235) whether there is another translation value for the first layer. If so, the process goes back and retrieves (at 3240) the next translation value for the first layer. The process repeats until it determines (at 3235) that there are no more translation values ​​for the first layer. After 3235 the process ends.

[0083] The process has an outer loop and an inner loop that ensures that all combinations of translation events are iterated through, translating (sliding) the contour shape for each translation amount, rendering the layout, and then capturing a screenshot after each translation event. Each screenshot captured is added to a sequence. The process starts with the first translation value of the first layer, then proceeds through each translation value of the second layer. It then returns to the first layer, translates the first layer by the second translation specified in the table, and then proceeds again through each of the translations of the second layer, thus enumerating all combinations.

[0084] One advantage of the animation method using static screenshots is that it can be automatically rendered and saved as a "movie" in a common video file format, and thus visualized outside the layout editing tool itself. For example, a video capture of the animation in some embodiments can be saved to an animated GIF image (.gif file) or in a movie format such as a .mov or .mp3 file, and then embedded in a presentation, etc.

[0085] However, this approach does not allow for the user to actually dynamically pan and zoom around the movie image to see the shapes at higher resolution, as is typically performed by a layout engineer in an interactive layout editor. It is desirable for a user of a layout editor to be able to zoom and pan to any area of ​​the layout of interest and have the shapes dynamically redrawn according to an animation sequence. For example, a user may wish to zoom in, zoom in again, and zoom in a third time before panning left twice to see a particular contact or via interface in great detail, along with only its immediate neighboring metal shapes. It would also be beneficial if the user could perform design edits between different renderings of the animation.

[0086] Thus, in some embodiments, an interactive, dynamic approach is used to animate a sequence of events, where the layout editor uses an animation process (its own or a separate program) to pick out the contours to be animated, and an event is scheduled in the near future (e.g., 1 / 3 seconds) to render those contours using the next translation in the extended sequence of translations. Before that scheduled event occurs, in some embodiments, the user continues to use the layout editor in its normal way, e.g., zooming and panning around the design.

[0087] When it is time to process the event, the layout editor displays the next rendering in an animation, which is generated by the layout editor's or other program's animation process applying the next translation vector in the extended sequence to the shapes. Any previously drawn shapes are erased and the newly positioned shapes are drawn (according to the current misalignment translation value). The layout editor then "refreshes" or redraws the graphics screen with the new rendering, and another animation event is scheduled in the near future before the editor is allowed to return to its event loop. Again, before the next scheduled animation event occurs, in some embodiments the user chooses to interact with the layout tool, zoom, pan, hover the mouse over an object of interest, select or highlight an object, perform a design editing operation, etc. When the next scheduled animation event is processed, the previously drawn outline shapes are erased and repositioned and redrawn according to the next misalignment vector value in the sequence.

[0088] In some embodiments, the sequence of translations is augmented with translations that "return" the translated shapes to their perfectly aligned positions, thus establishing a stable frame of reference for a user watching or interacting with the animation sequence. For the generation of a video-like sequence of still images, these "return" events are inserted between the regular animation sequence of events. Thus, in some embodiments, a first event is scheduled in which one of the layers is offset by a certain misalignment vector value.

[0089] Once processed and rendered by the layout editor, the next scheduled event will "undo" or "revert" the misalignment, presenting the user with a static, non-moving reference. The next scheduled event after that will then misalign the layers again. Between events (either normal misalignment events or the special "revert" events), the user is still free to interact with the tools in the normal way, performing zoom and pan operations, etc. In some embodiments, the animated shapes presented are limited to the inner contours only. This form allows the user to best understand how the "clipping" to the final, minimum overlapping shape occurs without undue visual clutter.

[0090] In some embodiments, the animated shape presented includes inner, nominal, and outer contours all at the same time. Figure 33 shows an example of misaligned contours for metal and contact shapes, showing the nominal, inner, and outer contours, with all three sets of contours rendered. The large right-pointing arrow 3302 indicates a clipping event, where the right side of the minimum overlapping via / contact polygon is clipped by the metal inner contour. A second clipping event is indicated by the large downward arrow 3304, where the bottom edge of the minimum overlapping polygon is effectively clipped by the bottom of the via / contact shape's inner contour. The inner metal and contact contours involved in the clipping event for this particular misalignment combination are also annotated in the figure.

[0091] Not all misalignment value translations result in clipping events, i.e., not all translations contribute to the final minimum overlapping polygon shape, and some of the relatively sparse subset of translations that result in clipping events will be "overlooked" by a user quickly scanning the sequence. Thus, in some embodiments, arrow polygons such as the one shown in Figure 33 are dynamically generated and added to the layout as the animated outline shape itself is drawn, but only when a clipping event is present, in order to draw the user's attention to the clipping event.

[0092] In some embodiments, advanced interactive "playback" controls are provided to the user, allowing the scheduled sequence of animation events to be paused, continued, or "played" in reverse order. First, the playback speed is affected by a user-specified "frame delay" or frame interval. In addition, after first viewing the entire sequence of animation events to "establish the big picture," in some embodiments the method allows the user, via GUI controls, to select to have the event sequence filtered to only clipping events, such that animation translation events that do not result in clipping events are not even scheduled / displayed.

[0093] In other embodiments, the complete sequence of events continues to be scheduled according to the original schedule, but allows the user to choose at any time to advance to the next event or to "fast forward" to the next clipping event. The user can also choose whether to see an interactive animation sequence in which only some or all of the nominal, inner, and outer contours are shown. Figure 34 shows a set of GUI controls that can facilitate the specification of exactly which contours are shown. Figure 35 shows GUI controls such as forward, reverse, and fast forward / rewind buttons (to the next / previous clipping event, respectively) for fine control of such scheduled animation sequences.

[0094] In some embodiments, the method calculates (and intuitively displays) the minimum overlap area of ​​the metal and via / contact layer interfaces. The areas calculated in this way can be used to determine the corresponding maximum resistance (upper limit) value. Figure 36 shows an example of a routing structure where a 3D via shape can be calculated for a via by taking the minimum overlap polygon of the Metal 1 via layer interface together with the minimum overlap polygon of the Metal 2 via layer interface and assuming a "near" cylindrical shape. The shape is generated with a height specified in the process technology file for the via layer, whose top has the minimum overlap polygon of the Metal 2 via interface and whose bottom has the minimum overlap polygon of the Metal 1 via interface.

[0095] When the inner contour is used to calculate the minimum overlap shape, the "narrowest" approximately cylindrical shape with the maximum via resistance is determined. In some embodiments, it is also useful for the designer to know what the "nominal" or "minimum" via resistance is. In this case, it is contemplated to calculate the overlap shape with respect to the nominal or outer contour, respectively, rather than the inner contour. By knowing the resistance range, i.e., the typical upper and lower limits of the contact or via resistance, the designer can make some circuit design or layout tweaks to best take them into account in the final circuit performance.

[0096] Some flows in some embodiments include modifying the circuit layout to provide greater overlap, optimizing the circuit layout, and changing from a straight line design to a curved design. As previously mentioned, modifying the circuit layout to provide greater overlap requires changing the location or size of metal, via, and / or contact polygons. The designer can optimize the layout for each individual via / contact, for example, to create greater overlap for a particular via instance that is known to be problematic due to excessive resistance.

[0097] In some embodiments, certain vias / instances are found to result in significantly larger overlaps than some of their neighbors. This method allows the designer to be more "aggressive" with the layout in these areas, thus reducing the overlap area somewhat, in a tradeoff that improves some other layout metric. For example, vias or metal shapes are moved slightly in some embodiments to provide more space for some other important route nearby. Certain automated tools that take advantage of this include, for example, intelligent compaction algorithms.

[0098] Linear shapes cannot be simply manufactured as depicted due to limitations caused by the laws of physics. On the other hand, curved shapes in some embodiments are depicted very close to the curved shapes that are actually manufactured. The target shape is now manufactured with reduced variability, since it is now initially curved and therefore easier to create an optimal mask. The resulting manufactured inner and outer contours are now closer to the nominal contour than in the case of a linear shape. The corresponding minimum / maximum resistance values ​​are closer to the nominal resistance, i.e., the spread or variance of the resistance is correspondingly smaller. This in turn results in improved overlap areas, reduced resistance, and improved long-term reliability. Thus, the ability to know the exact manufactured contours and associated resistance values ​​of the curved shapes allows the designer to target specific via or contact instances that are drawn in curved form.

[0099] Many of the above features and applications are implemented as a software process specified as a set of instructions recorded on a computer-readable storage medium (also referred to as a computer-readable medium). When these instructions are executed by one or more processing unit(s) (e.g., one or more processors, processor cores, or other processing units), these instructions cause the processing unit(s) to perform the actions indicated in the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, etc. Computer-readable media does not include carrier waves and electronic signals that pass wirelessly or over wired connections.

[0100] As used herein, the term "software" is meant to include applications stored on magnetic storage devices or firmware resident in read-only memory that can be loaded into memory for processing by a processor. Also, in some embodiments, multiple software inventions can be implemented as subparts of a larger program while remaining separate software inventions. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination of separate programs that together implement a software invention described herein is within the scope of the invention. In some embodiments, the software program, when installed to operate on one or more electronic systems, defines one or more specific machine implementations that execute and perform the operations of the software program.

[0101] 37 conceptually illustrates an electronic system 3700 in which some embodiments of the present invention are implemented. The electronic system 3700 may be a computer (e.g., a desktop computer, a personal computer, a tablet computer, a server computer, a mainframe, a blade computer, etc.), a phone, a PDA, or any other type of electronic device. As illustrated, the electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. Specifically, the electronic system 3700 includes a bus 3705, a processing unit(s) 3710, a system memory 3725, a read-only memory 3730, a permanent storage device 3735, input devices 3740, and output devices 3745.

[0102] The bus 3705 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the electronic system 3700. For example, the bus 3705 communicatively connects the processing unit(s) 3710 to the read-only memory (ROM) 3730, the system memory 3725, and the permanent storage device 3735. From these various memory units, the processing unit(s) 3710 retrieves instructions to execute and data to process in order to perform the processes of the present invention. The processing unit(s) may be a single processor or a multi-core processor in different embodiments.

[0103] The ROM 3730 stores static data and instructions required by the processing unit(s) 3710 and other modules of the electronic system. The permanent storage device 3735, on the other hand, is a read-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the electronic system 3700 is turned off. Some embodiments of the invention use mass storage devices (such as magnetic or optical disks and their corresponding disk drives) as the permanent storage device 3735.

[0104] In other embodiments, a removable storage device (such as a floppy disk, flash drive, etc.) is used as the permanent storage device. Like the permanent storage device 3735, the system memory 3725 is a read-write memory device. However, unlike the storage device 3735, the system memory is a volatile read-write memory, such as a random access memory. The system memory stores some of the instructions and data that the processor needs at run time. In some embodiments, the processes of the present invention are stored in the system memory 3725, the permanent storage device 3735, and / or the read-only memory 3730. From these various memory units, the processing unit(s) 3710 retrieves the instructions to execute and the data to process in order to execute the processes of some embodiments.

[0105] The bus 3705 also connects to input devices 3740 and output devices 3745. The input devices allow a user to communicate information and select commands to the electronic system. The input devices 3740 include alphanumeric keyboards and pointing devices (also called "cursor control devices"). The output devices 3745 display images generated by the electronic system. Output devices include printers and display devices such as cathode ray tubes (CRT) or liquid crystal displays (LCD). Some embodiments include devices such as touch screens that function as both input and output devices.

[0106] 37, the bus 3705 also couples the electronic system 3700 to a network 3765 via a network adapter (not shown). As such, the computer can be part of a network of computers (such as a local area network ("LAN"), a wide area network ("WAN"), or an intranet), or a network of networks such as the Internet. Any or all of the components of the electronic system 3700 may be used in conjunction with the present invention.

[0107] Some embodiments include electronic components such as microprocessors, storage, and memory that store computer program instructions on machine-readable or computer-readable media (alternatively referred to as computer-readable storage media, machine-readable media, or machine-readable storage media). Some examples of such computer-readable media include RAM, ROM, read-only compact discs (CD-ROM), recordable compact discs (CD-R), rewritable compact discs (CD-RW), read-only digital versatile discs (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini SD cards, micro SD cards, etc.), magnetic and / or solid-state hard drives, read-only and recordable Blu-Ray® discs, extra-high density optical discs, any other optical or magnetic media, and floppy disks. The computer-readable medium can store a computer program executable by at least one processing unit and including a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as that produced by a compiler, and files containing high-level code that are executed by a computer, electronic component, or microprocessor using an interpreter.

[0108] While the above description primarily refers to microprocessors or multi-core processors executing software, some embodiments are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on the circuit itself.

[0109] As used herein, the terms "computer," "server," "processor," and "memory" all refer to electronic or other technological devices. These terms exclude people or groups of people. For purposes of this specification, the terms display or display mean display on an electronic device. As used herein, the terms "computer-readable medium," "computer-readable mediums," and "machine-readable medium" are entirely limited to tangible, physical objects that store information in a form that is readable by a computer. These terms exclude any wireless signals, wired download signals, and any other ephemeral or transitory signals.

[0110] Although the present invention has been described with reference to numerous specific details, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the spirit of the present invention. For example, some figures conceptually illustrate processes. Certain operations of these processes may not be performed in the exact order shown and described. Certain operations may not be performed in one continuous sequence of operations, and different specific operations may be performed in different embodiments. Furthermore, processes may be implemented using several sub-processes or as part of a larger macro process. Thus, those skilled in the art will appreciate that the present invention should not be limited by the illustrative details set forth above, but should instead be defined by the appended claims.

Claims

1. 1. A method for designing a semiconductor circuit, comprising: generating a design layout having multiple interconnect layers and multi-layer interfaces connecting components on different interconnect layers; generating, for each of a plurality of said multi-layer interfaces, a predicted minimum overlapping shape that will be generated after a manufacturing stage of a manufacturing process used to produce a semiconductor circuit from said design layout; providing a representation of the predicted minimum overlapping shapes to aid in evaluation of the design layout; and A method comprising:

2. 2. The method of claim 1, further comprising: performing design rule checks based on the predicted minimum overlapping shapes.

3. The method of claim 1 , wherein the multi-layer interface comprises at least one of a metal via interface and a metal contact interface.

4. 2. The method of claim 1 , wherein generating the minimal overlapping shapes comprises using a machine trained network to generate a predicted shape for each interface on each layer connected by the interface.

5. using the machine trained network includes using the machine trained network to identify a plurality of contours for each interface on each layer; The method of claim 4 , wherein each contour represents a shape of the interface for a particular variation of a parameter of the manufacturing process.

6. The method of claim 5 , wherein the plurality of contours includes a first set of contours associated with a maximum variation of a manufacturing process parameter and a second set of contours associated with a minimum variation of the manufacturing process parameter.

7. The method of claim 6 , wherein the plurality of contours further comprises a third set of contours associated with nominal variations of the manufacturing process parameters.

8. The method of claim 5 , wherein the plurality of contours includes a first set of contours associated with a maximum variation of a manufacturing process parameter and a second set of contours associated with a nominal variation of the manufacturing process parameter.

9. The method of claim 5 , wherein the machine trained network generates a plurality of outputs representative of process variations associated with the plurality of contours.

10. 2. The method of claim 1 , wherein generating the minimum overlapping shape comprises generating the overlapping shape by identifying, for at least one particular multilayer interface, at least one misregistration between at least two different portions of the particular multilayer interface on at least two different layers that the multilayer interface traverses.

11. 1. An electronic design automation (EDA) method for generating predicted overlap shapes of multi-layer interfaces of an integrated circuit (IC) design, comprising: generating an IC design having at least two defined shapes of the multi-layer interface on at least two layers of the IC design; receiving data from a designer specifying how to model a misregistration between the two layers; using the received data to misalign the two IC design layers, thereby misaligning the two defined features of the multi-layer interface; generating the predicted overlap shape of the multi-layer interface from the two misaligned defined shapes; presenting the predicted overlap shape for display on a display screen; and The EDA method comprises:

12. 12. The EDA method of claim 11, wherein the two defined features are a first pair of later defined features that predict how a second pair of earlier defined features of the multilayer interface will appear after a subsequent manufacturing step.

13. using a machine trained network to generate at least the first pair of subsequently defined shapes from the second pair of previously defined shapes; The EDA method of claim 12 , wherein the machine trained network generates the predicted first pair of shapes by taking into account deformations produced during the subsequent manufacturing stages.

14. The EDA method of claim 13 , wherein the machine trained network further accounts for variations in a manufacturing process associated with the subsequent manufacturing stage.

15. 12. The EDA method of claim 11, wherein the predicted overlap shape is presented to enable the designer to evaluate the feasibility of manufacturing an IC based on the design.

16. receiving the data includes providing a set of tools within a graphical user interface (GUI) to enable the designer to provide data specifying how to model the misregistration between the two layers; The EDA method of claim 11 , wherein the set of UI tools provides the designer with a representative selection of misalignment translation values ​​for misaligning the two layers.

17. 20. The EDA method of claim 16, wherein the representation uses vector directions corresponding to a plurality of compass directions and a user-specified maximum misalignment value.

18. The EDA method of claim 17 , wherein the plurality of compass directions are four cardinal compass directions.

19. The EDA method of claim 17 , wherein the plurality of compass directions are four ordinal compass directions.

20. 20. The EDA method of claim 17, wherein the plurality of compass directions are four cardinal compass directions and four ordinal compass directions.

21. 1. A machine-readable medium storing a program for execution by at least one processing unit, comprising: A machine-readable medium, the program comprising a set of instructions for carrying out the method according to any one of claims 1 to 20.

22. A system comprising means for carrying out the method according to any one of claims 1 to 20.

Images