Heat Dissipation System for Electronic Devices

Abstract

An integrated device package is disclosed. The integrated device package may include a carrier and a cap bonded to the carrier. The carrier and cap at least partially define a cavity configured to receive a coolant. The integrated device package may include an inorganic material layer disposed on at least a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap may be directly bonded to the carrier without an intervening adhesive. The integrated device package may include an integrated device die disposed within the cavity and bonded to the carrier. The integrated device die may be directly bonded to the carrier without an intervening adhesive.

Description

[Technical field]

[0001] The present invention relates to heat dissipation in microelectronics.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 305,112, filed January 31, 2022, which is incorporated by reference in its entirety for all purposes. [Background technology]

[0003] An integrated device package can contain electrical components (e.g., integrated device dies and passive components such as inductors, resistors, and capacitors). The electrical components generate heat during operation. Some high performance applications require high power components that generate significant amounts of heat. It can be critical to transfer and remove the generated heat from the package to sustain reliable operation. Therefore, there is a continuing need for improved heat dissipation / transfer systems for electronic devices and integrated device packages. Summary of the Invention

[0004] An integrated device package is disclosed. The integrated device package may include a carrier and a cap bonded to the carrier. The carrier and cap at least partially define a cavity configured to receive a coolant. The integrated device package may include an inorganic material layer disposed on at least a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap may be directly bonded to the carrier without an intervening adhesive. The integrated device package may include an integrated device die disposed within the cavity and bonded to the carrier. The integrated device die may be directly bonded to the carrier without an intervening adhesive.

[0005] Specific embodiments will now be described with reference to the following drawings, which are provided by way of illustration and not by way of limitation. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional side view of a cooling system configured to dissipate heat generated by an integrated device die attached to a package substrate. [Diagram 2] FIG. 1 is a cross-sectional side view of an integrated device package according to one embodiment. [Diagram 3] FIG. 2 is a cross-sectional side view of an integrated device package with a flow disruption structure according to one embodiment. [Figure 4] FIG. 2 is a cross-sectional side view of a cooling system including a heat sink coupled to a cap according to one embodiment. [Diagram 5] FIG. 1 is a cross-sectional side view of a cooling system with a circulation pipe according to an embodiment. [Figure 6] FIG. 1 is a cross-sectional side view of a cooling system including a heat sink and a circulation pipe according to one embodiment. [Figure 7] FIG. 1 illustrates a cross-sectional side view of a cooling system including a thermoelectric element coupled to a cap according to one embodiment. [Figure 8] 1 illustrates a cross-sectional side view of a cooling system including a thermoelectric element coupled to a die, according to one embodiment. [Figure 9] FIG. 2 is a cross-sectional side view of a cooling system including a thermoelectric element coupled to a die and a circulation pipe, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] 1 is a schematic cross-sectional side view of a cooling system 1 configured to dissipate heat generated by an integrated device die (a first chip 112 and a second chip 114) attached to a package substrate 110. The cooling system 1 includes a first thermally conductive material (TIM) 116, a heat spreader 118, a second TIM 120, and a liquid pipe 122 containing a coolant 124. As shown by arrows in FIG. 1, heat generated by the first chip 112 and the second chip 114 is transferred to the liquid pipe 122 through the first TIM 116, the heat spreader 118, and the second TIM 120. The first TIM 116, the heat spreader 118, and the second TIM 120 can be said to have a lower heat dissipation efficiency than the liquid pipe 122. Therefore, it may be desirable to move the liquid pipe 122 closer to the first chip 112 and the second chip 114 to improve the effectiveness of heat transfer away from the chips 112, 114 and / or to eliminate the first TIM 116, the heat spreader 118, and the second TIM.

[0008] Various embodiments disclosed herein allow the coolant to be in contact (e.g., in direct thermal and / or physical contact) with a heat source, such as the first chip 112 and the second chip 114. In such embodiments, heat generated by the heat source may be dissipated more efficiently as compared to transferring the heat to the first TIM 116, the heat spreader 118, and the second TIM 120, and finally to the liquid pipe 122. For example, the heat generated by the heat source may be dissipated directly by the liquid pipe 122. However, if the coolant 124 is provided in direct contact with the heat source, the coolant 124 may damage the heat source (e.g., the first chip 112 and the second chip 114). For example, if an integrated device die is mounted on a package substrate and the coolant is provided in direct contact with the integrated device die, the coolant may seep or ooze at or near the interface between the integrated device die and the package substrate, such as between the solder balls for a flip-chip mounted device.

[0009] Various embodiments of the present invention relate to a heat dissipation system for an integrated device package. In various embodiments, a heat generating element (e.g., an integrated device die) may be bonded to a carrier using a hybrid direct bonding technique. Two or more elements (e.g., integrated device dies, wafers, etc.) may be stacked or bonded together to form a bonded structure. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked in the bonded structure.

[0010] In some embodiments, the elements (e.g., semiconductor element and carrier) are directly bonded to one another without an adhesive. In various embodiments, a non-conductive (e.g., semiconductor or inorganic dielectric) of a first element can be directly bonded to a corresponding non-conductive field region (e.g., semiconductor field region or inorganic dielectric field region) of a second element without an adhesive. In various embodiments, a conductive feature or region (e.g., metal pad) of a first element can be directly bonded to a corresponding conductive feature or region (e.g., metal pad) of a second element without an adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element may be directly bonded to the corresponding non-conductive material of the second element using adhesive-free bonding techniques, such as those disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference in its entirety for all purposes. In other applications, the non-conductive material of the first element may be directly bonded to the conductive material of the second element in a bonded structure such that the conductive material of the first element is intimately coupled to the non-conductive material of the second element. Suitable dielectrics for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, or carbon, such as silicon carbide, silicon oxycarbonitride, low-k dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon. Such carbon-containing ceramic materials may be considered inorganic materials, despite the presence of carbon, as opposed to primarily hydrocarbon materials. In some embodiments, the dielectric does not include a polymeric material, such as an epoxy, resin, or molding material. Additional examples of hybrid direct bonding can be found throughout U.S. Pat. No. 11,056,390, which is incorporated by reference for all purposes and is incorporated herein in its entirety.

[0011] In various embodiments, direct bonds can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. For example, chemical mechanical polishing (CMP) can be used to polish the non-conductive bonds 112a, 112b. The polished bonding surface can have a roughness of less than 30 Å rms. For example, the bonding surface can have a roughness in the range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. The bonding surfaces can be cleaned and exposed to plasma and / or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after or during activation (e.g., during the plasma and / or etch process). Without being bound by theory, in some embodiments, an activation process may be performed to break chemical bonds at the bonding surface, and a termination process may provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding. In some embodiments, activation and termination may be provided in the same step, for example, a surface may be activated and terminated using a plasma or a wet etchant. In other embodiments, the bonding surface may be terminated in a separate process to provide additional chemical species, which may then be used for direct bonding. In various embodiments, the termination chemical species may include nitrogen. Additionally, in some embodiments, the bonding surface may be exposed to fluorine. For example, one or many fluorine peaks may appear near the layers and / or bonding interface. Thus, in a direct bonded structure, the bonding interface between two non-conductive materials may comprise a very smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface.Additional examples of activation and / or end group treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes. The roughness of the polished bonding surface may be slightly rougher (e.g., in the range of about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or in some cases rougher) after the activation process.

[0012] In various embodiments, the contact pads of the first element may also be directly bonded to the corresponding conductive contact pads of the second element. For example, direct hybrid bonding techniques may be used to provide conductor-conductor direct bonds along bond interfaces that include covalently directly bonded dielectric inter-dielectric (dielectric-dielectric) surfaces that have been pretreated as described above. In various embodiments, conductor-conductor (e.g., conductive feature-conductive feature) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference and incorporated herein in its entirety for all purposes. The bond structures described herein may also be useful for direct metal bonding without non-conductive region bonding, or other bonding techniques.

[0013] In some embodiments, the non-conductive (e.g., dielectric) bonding regions (e.g., inorganic dielectric surfaces) can be pretreated and directly bonded to each other without an intervening adhesive as described above. The conductive contact features (which may be surrounded by a non-conductive dielectric field region) can also be directly bonded to each other without an intervening adhesive. In some embodiments, the contact features can be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layer, respectively, such as by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, such as by 2 nm to 20 nm or by 4 nm to 10 nm. The non-conductive bonding layers can be directly bonded to each other without an adhesive at room temperature in some embodiments, after which the bonded structure can be annealed. During annealing, the contact pads can expand relative to the non-conductive bonding regions and contact each other to form a metal-metal (intermetal) direct bond. The bonding structure can be annealed at an annealing temperature of greater than 250°C. For example, the annealing temperature may be greater than 300° C. or 350° C. The annealing temperature may be determined at least in part based on the material of the conductive contact pads, the mismatch of the coefficient of thermal expansion (CTE) between the conductive contact pads and the non-conductive bonding areas, and the gap between the conductive contact pads. Advantageously, the use of adhesive-free surface (surface-to-surface) direct bonding technology, such as "ZIBOND®" and / or hybrid bonding technology, such as Direct Bond Interconnect, or DBI® technology, commercially available from Adair, Inc., San Jose, Calif., allows for a high density of pads connected across the direct bond interface (e.g., with a small or fine pitch for a regular array). In various embodiments, the contact pads may be made of copper, although other metals may be suitable.

[0014] Thus, in a direct bonding process, a first element can be directly bonded to a second element without an intervening adhesive. In some configurations, the first element can be a singulated element, such as a singulated integrated device die. In other configurations, the first element can be a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can be a singulated element, such as a singulated integrated device die. In other configurations, the second element can be a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein can be applied to a wafer-to-wafer (W2W) bonding process, a die-to-die (D2D) bonding process, or a die-to-wafer (D2W) bonding process. In a wafer-to-wafer (W2W) process, two or more wafers can be directly bonded together (e.g., direct hybrid bonding) and then singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush with one another and may include indicia indicative of a common singulation process for the bonded structure (e.g., saw marks if a saw singulation process is used).

[0015] As described herein, the first and second elements can be directly bonded together without adhesive, which is different from the deposition process and results in a structurally different interface compared to deposition. In one application, the width of the first element in the bonded structure is approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure is different from the width of the second element. Similarly, the width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements may be comprised of non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure may include defect areas along the bond interface where nanoscale voids (nanovoids) exist. The nanovoids may form due to activation (e.g., exposure to plasma) of the bonding surface. As mentioned above, the bond interface may include a concentration of material resulting from activation and / or the final chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface. The nitrogen peak can be detected using a secondary ion mass spectrometer. In various embodiments, for example, a nitrogen-terminated treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can replace the hydrolyzed (OH-terminated) surface with NH2 molecules, resulting in a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond includes a covalent bond, which is stronger than a van der Waals bond. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness.

[0016] FIG. 2 is a cross-sectional side view of an embodiment of an integrated device package 2. The integrated device package 2 may include a carrier 10, a first die 12 attached to the carrier 10, a second die 14 attached to the carrier 10, and a cap 16 coupled to the carrier 10. The carrier 10 and the cap 16 may at least partially define a cavity 18 that contains the first die 12 and the second die 14. The cavity 18 is configured to receive a coolant (not shown). The cap 16 may include openings (e.g., a coolant inlet 20 and a coolant outlet 22) for supplying or removing the coolant to or from the cavity 18. The coolant may comprise any suitable refrigerant material. For example, the coolant may include a fluid coolant, such as a liquid coolant (e.g., a dielectric liquid) or a gas (e.g., air or an inert gas). In some embodiments, the coolant may have a thermal conductivity of at least 0.1 W / mK at a temperature of 20° C. For example, the coolant may have a thermal conductivity of at least 0.5 W / mK at a temperature of 20° C. In some embodiments, the thermal conductivity of the coolant may be in the range of 0.1 W / mK to 10 W / mK, in the range of 0.1 W / mK to 5 W / mK, in the range of 0.1 W / mK to 3 W / mK, in the range of 0.5 W / mK to 5 W / mK, or in the range of 0.5 W / mK to 3 W / mK at a temperature of 20° C.

[0017] In some embodiments, the carrier 10 may include an inorganic material layer 24. The inorganic material layer 24 may be part of the carrier 10 or may be a separate layer at least partially disposed on the carrier 10. In some embodiments, the inorganic material layer 24 may serve as a non-conductive bonding layer to which the cap 16 and / or the die 12, 14 may be directly bonded (e.g., directly hybrid bonded). In such embodiments, at least a portion of the inorganic material layer 24 may be disposed between the carrier 10 and the die 12, 14. The inorganic material layer 24 may prevent or reduce contamination of the bonding interface between the die 12, 14 and the carrier 10 by the coolant. Thus, the inorganic material layer 24 may include any suitable protective layer, such as silicon oxide, silicon nitride, titanium nitride, or any other suitable direct bonding material described herein. In some embodiments, the protective layer may comprise a multi-layer protective coating. In some embodiments, inorganic material layer 25 may also be provided on the surfaces of first and second die 12, 14. In some embodiments, inorganic material layer 25 may be made of the same or substantially the same material as inorganic material layer 24. In some embodiments, carrier 10 may be made of a semiconductor device, such as an interposer, an integrated device die, or other device. In other embodiments, carrier 10 may be made of a packaging substrate (e.g., a printed circuit board (PCB)). In some embodiments, carrier 10 may be attached to and / or electrically coupled to a packaging substrate (not shown). Inorganic material layer 24 may have a thickness in the range of 10 nm to 5 μm, in the range of 10 nm to 1 μm, or in the range of 50 nm to 1 μm.

[0018] In some embodiments, the first die 12 and / or the second die 14 may comprise a memory die (e.g., a dynamic random access memory (DRAM) die), a logic die, a sensor die, a microelectromechanical system (MEMS) die, a processor die (e.g., a graphics processing unit (GPU) die), or any other type of semiconductor device. In some embodiments, the first die 12 and / or the second die 14 may be directly bonded to the carrier 10 without an intervening adhesive, such as by any one or more of the direct bonding techniques described above. For example, the first die 12 may have a conductive feature 26 directly bonded to a corresponding conductive feature 27 of the carrier 10 and a non-conductive region 28 directly bonded to a corresponding non-conductive region 29 (e.g., the inorganic material layer 24) of the carrier 10. In other embodiments, the first die 12 and / or the second die 14 may be flip-chip attached to the carrier 10 with an adhesive, such as a solder (not shown). In some embodiments, the distance d between the conductive feature 26 and the edge of the first die 12 may be in the range of 100 μm to 500 μm, in the range of 200 μm to 500 μm, in the range of 300 μm to 500 μm, in the range of 100 μm to 400 μm, in the range of 100 μm to 300 μm, or in the range of 200 μm to 400 μm.

[0019] Although the first and second die 12, 14 are shown to be bonded to the carrier 10, another embodiment may have only one die bonded to the carrier 10. In some other embodiments, the integrated device package 2 may have three or more die bonded to the carrier 10. In some embodiments, multiple die may be stacked on the carrier 10. In some embodiments, the first die 12 and / or the second die 14 may comprise an active die or a passive die.

[0020] The cap 16 may be made of any suitable material, such as silicon, glass, ceramic, plastic, metal, etc. In some embodiments, the cap 16 may be directly bonded to the carrier 10 without an intervening adhesive, such as by any one or more of the direct bonding techniques described above. In other embodiments, the cap 16 may be bonded to the carrier 10 by an adhesive, such as by glue or solder. In some embodiments, the cap 16 and the carrier 10 may have corresponding metal portions, and the metal portions of the cap 16 and the carrier 10 may be bonded in any suitable manner as disclosed herein. During operation of a cooling or heat dissipation system utilizing the integrated device package 2, the cavity 18 may be at least partially filled with a fluid coolant (not shown), which may include a liquid coolant or a gas coolant. In some embodiments, the cavity 18 may be completely filled with the coolant. In some embodiments, the width w of the legs of the cap 16 may be in the range of 100 μm to 500 μm, 200 μm to 500 μm, 300 μm to 500 μm, 100 μm to 400 μm, 100 μm to 300 μm, or 200 μm to 400 μm. The coolant inlet 20 and the coolant outlet 22 of the cap 16 may be coupled, for example, to a system (not shown) for driving the coolant. The locations of the coolant inlet 20 and the coolant outlet 22 may be selected based at least in part on the location of the heat generating components (e.g., the first and second dies 12, 14) and / or the hydrodynamic characteristics of the coolant within the cavity 18.

[0021] In some embodiments, portions within cavity 18 configured to be exposed to the fluid coolant (e.g., the inner side and / or upper walls of cap 16 and surfaces of first die 12 and / or second die 14, surfaces of carrier 10) may be covered with an organic or inorganic (but possibly thermally conductive) protective coating. In such cases, the fluid coolant may directly contact the protective coating (e.g., inorganic material layer 25).

[0022] When the first and second dies 12, 14 are directly bonded (e.g., directly hybrid bonded) to the carrier 10 as described above, the electrical connections between the first and second dies and the carrier 10 may be protected. For example, the bonding interface between the first and second dies 12, 14 and the carrier 10 may prevent or reduce the coolant from seeping, penetrating, or leaking into the bonding interface, thereby protecting the circuitry within the first and second dies 12, 14. When the cap 16 is directly bonded to the carrier 10 as described above, it may prevent or reduce the coolant from leaking out of the cavity 18 to the outside of the cavity 18. The inorganic material layer 25 on the surface of the first and second dies 12, 14 may protect the first and second dies 12, 14 from being damaged by the coolant. In some embodiments, the inorganic material layer 25 may at least partially encapsulate the first and second dies 12, 14. For example, the inorganic material layer 25 may encapsulate only a portion of the first die 12 or the second die 14. For another embodiment, the inorganic material layer 25 may completely encapsulate the first and / or second die 12, 14. The inorganic material layer 25 may be relatively thin so that heat can be transferred from the first and second die 12, 14 to the coolant without significant loss. For example, the inorganic material layer 25 may have a thickness in the range of 10 nm to 5 μm, 10 nm to 1 μm, or 50 nm to 1 μm. In some embodiments, the inorganic material layer 25 may have a thickness less along the sidewalls of the first die 12 or the second die 14 than along the top side of the first die 12 or the second die 14.

[0023] In some embodiments, the first and / or second die 12, 14 may include an arrester (not shown). The arrester may include a physical cavity configured to absorb leaked or seeped coolant or an absorbent material that absorbs leaked or seeped coolant and prevents or mitigates the coolant from leaking into the bonding interface. Similarly, the cap 16 may include an arrester (not shown) configured to increase the reliability of the seal between the cap 16 and the carrier 10. The arrester may prevent or mitigate the coolant from leaking outside the cavity 18.

[0024] 3 is a cross-sectional side view of an embodiment of an integrated device package 2′. Unless otherwise noted, the components in FIG. 3 may be the same or substantially the same as the same components disclosed herein, such as the components in FIG. 2. The integrated device package 2′ may be substantially the same as the integrated device package 2 shown in FIG. 2, except that the integrated device package 2′ includes a flow impeding structure 32. For example, protrusions may be provided within the cavity 18 on the inner surface of the cap 16 and / or on the surfaces of the first and second dies 12, 14. In some embodiments, the flow impeding structure 32 may also be provided on the surfaces of the carrier 10 within the cavity 18. In some embodiments, the flow impeding structure 32 may be formed by removing at least a portion of the first and second dies 12, 14 and / or the cap 16. During operation of a cooling or heat dissipation system utilizing the integrated device package 2′, a coolant may flow within the cavity 18. The flow impediment structure 32 may impede the flow of the coolant to facilitate the transfer of heat generated by the first and second dies 12, 14 to the coolant.

[0025] 4-9 are schematic cross-sectional side views of various embodiments of cooling systems 3, 4, 5, 6, 7, 8. FIGS. 4-9 show a heat source 34 having a die 36 mounted on a carrier 10 and a plurality of stacked dies 38 mounted on the carrier 10, a cap 16 coupled to the carrier 10, a coolant 40 disposed within a cavity 18 and contained within the cavity 18 at least partially defined by the carrier 10 and the cap 16, and a package substrate 42 to which the carrier 10 is attached. In some embodiments, the die 36 and the plurality of stacked dies 38 may be directly bonded (e.g., directly hybrid bonded) to the carrier 10 as disclosed herein. The package substrate 42 may be attached to a larger system or device (not shown), for example, by a plurality of solder balls 44. In the illustrated embodiment, the stacked dies 38 may comprise a plurality of memory dies and the die 36 may comprise a processor die configured to communicate with the stacked dies 38. In some embodiments, the memory dies may be direct bonded (e.g., direct hybrid bonded) as disclosed herein. Any combination of the principles and advantages disclosed herein may be used.

[0026] The cap 16 of the cooling system 3 shown in FIG. 4 includes a heat sink 46 (multiple fins) and a fan 48. The heat sink 46 can dissipate heat generated by the heat source 34 from the cooling system 3. In some embodiments, the coolant 40 can be contained within the cavity 18. In the embodiment shown in FIG. 4, the fluid coolant 40 can be contained within the cavity 18 such that during operation, the coolant does not flow in or out of the cavity, but instead remains within the cavity 18. The heat sink 46 can remove heat from the coolant 40, and the fan 48 provides convective heat transfer from the heat sink 46.

[0027] The cap 16 of the cooling system 4 shown in FIG. 5 has a fluid or coolant inlet 20 and a fluid or coolant outlet 22. A circulation pipe 52 may be coupled to the coolant inlet 20 and outlet 22. The coolant inlet 20 may be configured to carry the coolant 40 into the cavity 18, and the coolant outlet 22 may be configured to remove the coolant 40 from the cavity 18. A heat sink 54 (multiple fins) may be coupled to the circulation pipe 52. A coolant driver 56 may be provided in a flow path within the circulation pipe 52. The coolant driver 56 may comprise a pump. The coolant driver 56 may drive the coolant 40 through the circulation pipe 52 into and / or out of the cavity 18. In some embodiments, as with the cooling system 3 of FIG. 4, the cooling system 4 may further include a fan (not shown). As shown in FIG. 6, the cooling system 5 may utilize both a heat sink 46 and a heat sink 54.

[0028] As shown in FIG. 7, the cooling system 6 may include a thermoelectric element 62, such as a thermoelectric or Peltier effect element, coupled to the cap 16. A voltage may be applied to the thermoelectric element 62 to facilitate heat transfer from one side of the thermoelectric element 62 to the other side of the thermoelectric element 62. The thermoelectric element 62 may convert heat transferred to the thermoelectric element 62 into a voltage, thereby reducing the temperature of the coolant 40 in the cavity. The cooling system 6 may further include a heat sink 46 coupled to the cap 16. In the illustrated embodiment, a portion of the thermoelectric element 62 is disposed between the cap 16 and the heat sink 46.

[0029] As shown in FIG. 8, the cooling system 7 may include a thermoelectric element 72 coupled to a die 36 (e.g., a graphics processing unit die, or GPU die) and a thermoelectric element 74 positioned between a die 38a (e.g., a logic die) and a die 38b (a DRAM die). The side of the thermoelectric element 72 coupled to the die 36 may be a hot side, and the other side of the thermoelectric element 72 may be a cold side. The thermoelectric elements 72, 74 may be configured to transfer heat from the die 36, 38 to the coolant 40. Additional examples of incorporating thermoelectric elements into direct bonded structures are shown and described throughout U.S. patent application Ser. No. 18 / 067,655, filed Dec. 16, 2022, entitled THERMOELECTRIC COOLING FOR DIE PACAGES, which is incorporated herein by reference in its entirety for all purposes.

[0030] As shown in Figure 9, the cooling system 8 may utilize the heat sink 54 shown in Figure 5 together with the thermoelectric elements 72, 74 shown in Figure 8. The cooling system 8 may include a thermoelectric element 72 on the die 36, a thermoelectric element 74 between the die 38a (e.g., a logic die) and the die 38b (e.g., a DRAM die), and a circulation pipe 52 in fluid communication with the cavity 18.

[0031] Any suitable combination of the principles and advantages disclosed herein may be used. For example, any suitable combination of the features illustrated in Figures 2-9 may be embodied together in a cooling system.

[0032] In one aspect, an integrated device package is disclosed. The integrated device package may include a carrier and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity configured to receive a coolant. The integrated device package may include an inorganic material layer disposed on at least a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant.

[0033] In one embodiment, the package further comprises an integrated device die disposed within the cavity and bonded to the carrier. The carrier may comprise an interposer. The carrier may comprise a printed circuit board (PCB). The cap may comprise silicon, glass, plastic, or metal. The cap may be bonded to the carrier by glue, eutectic, or solder. The inorganic material layer may further be disposed on the integrated device die. The integrated device die may be directly bonded to the carrier. The integrated device die may have conductive features and non-conductive regions. The conductive features may be directly bonded to corresponding conductive features of the carrier, and the non-conductive regions may be directly bonded to corresponding non-conductive regions of the carrier. A distance between the conductive features of the integrated device die and an edge of the integrated device die may be between 50 μm and 500 μm. The non-conductive regions of the carrier may comprise an inorganic material layer. The integrated device die may be a momery die or a logic die. The package may further include a second integrated device die stacked on the integrated device die. The integrated device die may be configured to contact a coolant. The cap may have a coolant inlet and a coolant outlet. The coolant may be configured to flow from the coolant inlet to the coolant outlet of the cavity. The coolant inlet and the coolant outlet may be coupled to a pump. The legs of the cap bonded to the carrier may have a width in the range of 100 μm to 5 mm. The coolant may include a liquid or a gas. The cap may include a heat sink including a plurality of fins. The package may further include a flow impeding structure on an inner surface of the cap configured to impede the flow of the coolant over the integrated device die or within the cavity. The package may further include a thermoelectric element coupled to the cap or the integrated device die. The package may further include a second integrated device die disposed within the cavity. The second integrated device die may be directly bonded to the carrier. The second integrated device die may be stacked on the integrated device die.

[0034] In one embodiment, a coolant is disposed within the cavity at least during operation of the integrated device package, and at least a portion of the inorganic material layer is in contact with the coolant at least during operation of the integrated device package.

[0035] An integrated device package is disclosed that may include a carrier and a cap bonded to the carrier. The carrier and cap at least partially define a cavity configured to receive a fluid coolant. The integrated device package may include an opening configured to convey the fluid coolant into the cavity or to remove the fluid coolant from the cavity. The integrated device package may include an integrated device die directly bonded to the carrier while disposed within the cavity.

[0036] In one embodiment, the package may further include an inorganic material layer disposed over at least a portion of the carrier, the inorganic material layer configured to contact a fluid coolant.

[0037] In one embodiment, the carrier includes an interposer.

[0038] In one embodiment, the carrier comprises a printed circuit board (PCB).

[0039] In one embodiment, the cap comprises silicon, glass, plastic, or metal.

[0040] In one embodiment, the cap is directly bonded to the carrier without an intervening adhesive.

[0041] In one embodiment, the cap is bonded to the carrier by glue or solder.

[0042] In one embodiment, the package further comprises an inorganic material layer disposed over the integrated device die.

[0043] In one embodiment, the integrated device die has conductive features and non-conductive regions, the conductive features can be direct bonded to corresponding conductive features of the carrier and the non-conductive regions can be direct bonded to corresponding non-conductive regions of the carrier, and the distance between the conductive features and the edge of the integrated device die can be between 100 μm and 500 μm.

[0044] In one embodiment, the integrated device die is a memory die or a logic die.

[0045] In one embodiment, the integrated device die is configured to contact a coolant.

[0046] In one embodiment, the package further comprises a second opening. The opening may comprise a fluid inlet configured to convey the fluid coolant into the cavity and the second opening may comprise a fluid outlet configured to remove the fluid coolant from the cavity. The cap may comprise a fluid inlet and a fluid outlet. The fluid coolant may be configured to flow from the coolant inlet to the coolant outlet of the cavity. The coolant inlet and the coolant outlet may be coupled to a pump.

[0047] In one embodiment, the legs of the cap that are bonded to the carrier have a width in the range of 100 μm to 5 mm.

[0048] In one embodiment, the coolant comprises a liquid or a gas.

[0049] In one embodiment, the cap has a heat sink including a number of fins.

[0050] In one embodiment, the package further comprises a flow impeding structure disposed on an inner surface of the cap configured to impede the flow of coolant over the integrated device die or within the cavity.

[0051] In one embodiment, the package further comprises a thermoelectric element coupled to the cap or to the integrated device die.

[0052] In one embodiment, the package further comprises a second integrated device die disposed within the cavity, the second integrated device die may be direct bonded to the carrier, or the second integrated device die may be stacked on the integrated device die.

[0053] In one aspect, a heat dissipation system is disclosed. The heat dissipation system may include a carrier and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity. The heat dissipation system may include a fluid coolant contained within the cavity and an integrated device die directly bonded to the carrier while disposed within the cavity.

[0054] In one embodiment, the heat dissipation system further comprises an inorganic material layer disposed over at least a portion of the carrier, the inorganic material layer being in contact with the fluid coolant.

[0055] In one embodiment, the carrier includes an interposer.

[0056] In one embodiment, the carrier comprises a printed circuit board (PCB).

[0057] In one embodiment, the cap comprises silicon, glass, plastic, or metal.

[0058] In one embodiment, the cap is directly bonded to the carrier without an intervening adhesive.

[0059] In one embodiment, the cap is bonded to the carrier by glue or solder.

[0060] In one embodiment, the heat dissipation system further includes an inorganic material layer disposed over the integrated device die.

[0061] In one embodiment, the integrated device die is direct bonded to the carrier. The integrated device die has conductive features and non-conductive regions. The conductive features may be direct bonded to corresponding conductive features of the carrier and the non-conductive regions may be direct bonded to corresponding non-conductive regions of the carrier. A distance between the conductive features and an edge of the integrated device die may be between 50 μm and 500 μm. The non-conductive regions of the carrier may include an inorganic material layer.

[0062] In one embodiment, the integrated device die is a memory die or a logic die.

[0063] In one embodiment, the integrated device die is configured to contact a coolant.

[0064] In one embodiment, the cap has a fluid inlet and a fluid outlet. The fluid coolant can flow from the coolant inlet to the coolant outlet of the cavity. The heat dissipation system can further include a pump coupled to the coolant inlet and the coolant outlet, the pump configured to drive the fluid coolant. The heat dissipation system of claim 63.

[0065] In one embodiment, the legs of the cap that are bonded to the carrier have a width in the range of 100 μm to 5 mm.

[0066] In one embodiment, the coolant comprises a liquid or a gas.

[0067] In one embodiment, the cap has a heat sink including a number of fins.

[0068] In one embodiment, the heat dissipation system further includes a flow impeding structure disposed on an inner surface of the cap configured to impede the flow of coolant over the integrated device die or within the cavity.

[0069] In one embodiment, the heat dissipation system further includes a thermoelectric element coupled to the cap or the integrated device die.

[0070] In one embodiment, the heat dissipation system further includes a second integrated device die disposed within the cavity. The second integrated device die may be directly bonded to the carrier. The second integrated device die may be stacked on the integrated device die.

[0071] In one aspect, a method of making an integrated device package is disclosed. The method includes providing a carrier and bonding a cap to the carrier. The carrier and cap at least partially define a cavity that receives a fluid coolant at least during operation of the integrated device package. The method may include direct bonding an integrated device die to the carrier. The integrated device die may be disposed within the cavity.

[0072] In one embodiment, the method further includes forming a fluid inlet configured to convey a fluid coolant into the cavity and forming a fluid outlet configured to remove the fluid coolant from the cavity. The method may further include supplying the fluid coolant into the cavity. Supplying the fluid coolant may comprise passing the fluid coolant through the fluid inlet.

[0073] In one aspect, an integrated device package is disclosed. The integrated device package may include a carrier and a cap bonded to the carrier. The carrier and cap at least partially define a cavity that receives a fluid coolant at least during operation of the integrated device package. The integrated device package may include an integrated device die bonded to the carrier and disposed within the cavity. At least a portion of the integrated device die is in contact with the fluid coolant at least during operation of the integrated device package. The integrated device package may include an inorganic material layer disposed on at least a portion of the carrier. At least one of the cap and the integrated device die is directly bonded to the carrier without an intervening adhesive.

[0074] In one aspect, an integrated device package is disclosed. The integrated device package may include a carrier with a first conductive feature and a first non-conductive region. The integrated device package may include a cap bonded to the carrier. The carrier and the cap at least partially define a cavity configured to receive a fluid coolant. The integrated device package may include an opening configured to convey the fluid coolant into the cavity or remove the fluid coolant from the cavity. The integrated device package may include an integrated device die with a second conductive feature and a second non-conductive region. The integrated device die is disposed within the cavity. The second conductive feature is direct bonded to the first conductive feature of the carrier and the second non-conductive region is direct bonded to the first non-conductive region of the carrier.

[0075] In one embodiment, the distance between the conductive features of the integrated device die and the edge of the integrated device die is between 50 μm and 500 μm.

[0076] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are either directly connected to each other or connected to each other by one or more intermediate elements. Additionally, the terms "herein," "above," "below," and words of similar import as used herein refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above Detailed Description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0077] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0078] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. 1. An integrated device package comprising: having a carrier, a cap directly bonded to the carrier without an intervening adhesive, the carrier and the cap at least partially defining a cavity configured to receive a coolant; An integrated device package comprising an inorganic material layer disposed on at least a portion of the carrier, at least a portion of the inorganic material layer being exposed to the cavity and configured to contact the coolant.

2. 2. The integrated device package of claim 1, further comprising an integrated device die disposed within said cavity and bonded to said carrier.

3. The integrated device package of claim 2 , wherein the carrier comprises an interposer.

4. The integrated device package of claim 2 , wherein the carrier comprises a printed circuit board (PCB).

5. The integrated device package of claim 2 , wherein the cap is made of silicon, glass, plastic, or metal.

6. 3. The integrated device package of claim 2, wherein the cap is bonded to the carrier by glue, eutectic, or solder.

7. The integrated device package of claim 2 , wherein the inorganic material layer is further disposed on the integrated device die.

8. 3. The integrated device package of claim 2, wherein the integrated device die is directly bonded to the carrier.

9. 9. The integrated device package of claim 8, wherein the integrated device die has conductive features and non-conductive regions, the conductive features being directly bonded to corresponding conductive features of the carrier, and the non-conductive regions being directly bonded to corresponding non-conductive regions of the carrier.

10. The integrated device package of claim 9 , wherein the distance between the conductive feature of the integrated device die and the edge of the integrated device die is between 50 μm and 500 μm.

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