Read offset compensation in a read operation of a memory device - Patents.com

Abstract

A memory controller coupled to a memory device including an array of memory cells, each memory cell having two memory cells corresponding to N bits of data. N The memory controller is coupled to the memory device and, upon execution of the instruction, sets the memory cell to one of two states, N being an integer greater than 1, and the array of memory cells is divided into one or more units. N The method is configured to obtain from the memory device a number P of memory cells in one of the plurality of units that are in one or more programmed states of the states, calculate a compensated read voltage having an offset from a default read voltage based on the number P, and provide to the memory device the compensated read voltage for a read operation performed on a selected one of the memory cells in the one of the plurality of units.

Description

[Technical field]

[0001] The present disclosure relates to memory devices and their operation. [Background technology]

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory allows various operations such as read, program (write), and erase. For NAND flash memory, erase operations can be performed at the block level, while program or read operations can be performed at the page level. Summary of the Invention [Means for solving the problem]

[0003] In one embodiment, the memory system includes a memory device and a memory controller. The memory device includes an array of memory cells and peripheral circuits. Each memory cell stores two N-bit data. N A memory controller is configured to set a read voltage to one of the states, N being an integer greater than 1, and the array of memory cells being divided into one or more units. A peripheral circuit is coupled to the memory cells and configured to perform a read operation on a selected one of the memory cells in one of the units. A memory controller is coupled to the memory device and configured to control the memory device to perform a read operation using a compensated read voltage having an offset from a default read voltage by sending an instruction to the peripheral circuit. The offset is 2 N It correlates with the number P of memory cells in the unit that are in one or more of the programmed states.

[0004] In some implementations, the offset is associated with a unit and is updated after the number P of memory cells in the unit is changed.

[0005] In some implementations, the offset is updated periodically.

[0006] In some implementations, the update period is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0007] In some implementations, the number P is obtained through a verify read operation configured to count the number P of memory cells in the unit.

[0008] In some implementations, the memory controller includes: N The method is configured to select one or more of the programmed states of the states and determine a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states, the verify voltage being equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0009] In some implementations, two N The number of the selected one or more programmed states is 1, and the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of a memory cell corresponding to the unselected state among the states.

[0010] In some implementations, the peripheral circuitry includes a word line driver configured to apply a verify voltage to at least some of the memory cells in the unit via the word lines.

[0011] In some implementations, the memory controller includes a digital signal processor configured to count a number P after a verify voltage is applied to at least a portion of the memory cells in the unit.

[0012] In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is 2 N The average number of memory cells in one or more selected pages that are in one or more of the programmed states.

[0013] In some implementations, the controller includes an offset corresponding to the number P and a processor configured to obtain the offset through a lookup operation by looking up a first mapping table between the offset and the number P.

[0014] In some implementations, the memory controller includes a first register configured to store the first mapping table.

[0015] In some implementations, the memory controller includes a digital signal processor configured to calculate a numerical difference ΔP between the number P and a default number P′, where the default number P′ is 2 N The number of memory cells in a unit that are in one or more of the programmed states.

[0016] In some implementations, the memory controller includes a processor configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

[0017] In some implementations, the memory controller includes a second register configured to store the second mapping table.

[0018] In some implementations, the memory controller includes a third register configured to store the default number P'.

[0019] In some implementations, the processor is configured to adjust, for memory cells in the unit, an offset based on a default threshold voltage of the memory cells.

[0020] In some implementations, the adjusted offsets of the memory cells in a unit are positively correlated with the default threshold voltages of the memory cells.

[0021] In some implementations, the memory controller includes a fourth register configured to store the offset obtained by the processor.

[0022] In some implementations, the processor is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[0023] In another aspect, a memory controller is coupled to a memory device including an array of memory cells, each memory cell having two corresponding N bits of data. N The memory controller is coupled to the memory device and, upon execution of the instruction, outputs from the memory device one or more of the following: N The method is configured to obtain a number P of memory cells in one of the plurality of units that are in one or more programmed states of the states, calculate a compensated read voltage having an offset from a default read voltage based on the number P, and provide the compensated read voltage to the memory device for a read operation performed on a selected one of the memory cells in the one of the plurality of units.

[0024] In some implementations, the offset is associated with a unit and is updated after the number P of memory cells in the unit is changed.

[0025] In some implementations, the offset is updated periodically, hi some implementations, the update period is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0026] In some implementations, the memory controller includes a processor configured to control the memory device to count the number P of memory cells in the unit by performing a verify read operation.

[0027] In some implementations, the processor N and configuring to select one or more programmed states from among the states and determine a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states, the verify voltage being equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0028] In some implementations, two N The number of the selected one or more programmed states is 1, and the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of a memory cell corresponding to the unselected state among the states.

[0029] In some implementations, the memory controller includes a digital signal processor configured to count a number P after a verify voltage is applied to at least a portion of the memory cells in the unit.

[0030] In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is 2 N The average number of memory cells in one or more selected pages that are in one or more of the programmed states.

[0031] Some implementations include an offset corresponding to the number P, and a processor configured to obtain the offset through a lookup operation by looking up a first mapping table between the offset and the number P.

[0032] In some implementations, the memory controller includes a first register configured to store the first mapping table.

[0033] In some implementations, the memory controller includes a digital signal processor configured to calculate a numerical difference ΔP between the number P and a default number P′, where the default number P′ is 2 N The number of memory cells in the unit that are in one or more of the programmed states.

[0034] In some implementations, the memory controller includes a processor configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

[0035] In some implementations, the memory controller includes a second register configured to store the second mapping table.

[0036] In some implementations, the memory controller includes a third register configured to store the default number P'.

[0037] In some implementations, the processor is configured to adjust, for memory cells in the unit, an offset based on a default threshold voltage of the memory cells.

[0038] In some implementations, the adjusted offsets of the memory cells in a unit are positively correlated with the default threshold voltages of the memory cells.

[0039] In some implementations, the memory controller includes a fourth register configured to store the offset obtained by the processor.

[0040] In some implementations, the processor is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[0041] In yet another embodiment, a memory device includes an array of memory cells and peripheral circuitry. Each memory cell stores two N-bit data corresponding to the N-bit data. N The array of memory cells is configured to be set to one of the states, N being an integer greater than 1, and the array of memory cells is divided into one or more units. The peripheral circuitry is coupled to the memory cells and configured to perform a read operation on a selected one of the memory cells in one of the units using a compensated read voltage having an offset from a default read voltage. The offset is between 2 N It correlates with the number P of memory cells in the unit that are in one or more of the programmed states.

[0042] In some implementations, the offset is associated with a unit and is updated after the number P of memory cells in the unit is changed.

[0043] In some implementations, the offset is updated periodically.

[0044] In some implementations, the update period is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0045] In some implementations, the number P is obtained through a verify read operation configured to count the number P of memory cells in the unit.

[0046] In some implementations, the peripheral circuitry includes two N and selecting one or more of the programmed states of the states and determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states, the verify voltage being equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0047] In some implementations, two N The number of the selected one or more programmed states is 1, and the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is 2 N The state is higher than the threshold voltage of a memory cell corresponding to the unselected state.

[0048] In some implementations, the peripheral circuitry includes a word line driver configured to apply a verify voltage to at least some of the memory cells in the unit via the word lines.

[0049] In some implementations, the peripheral circuitry includes a calculator configured to calculate the number P after a verify voltage is applied to at least some of the memory cells in the unit.

[0050] In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is 2 N The average number of memory cells in one or more selected pages that are in one or more of the programmed states.

[0051] In some implementations, the peripheral circuit includes an offset corresponding to the number P, and control logic configured to obtain the offset through a lookup operation by looking up a first mapping table between the offset and the number P.

[0052] In some implementations, the peripheral circuit includes a first register configured to store the first mapping table.

[0053] In some implementations, the peripheral circuitry includes a calculator configured to calculate a numerical difference ΔP between the number P and a default number P′, where the default number P′ is 2 N The number of memory cells in the unit that are in one or more of the programmed states.

[0054] In some implementations, the control logic is configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

[0055] In some implementations, the peripheral circuit includes a second register configured to store the second mapping table.

[0056] In some implementations, the peripheral circuitry includes a third register configured to store the default number P'.

[0057] In some implementations, the processor is configured to adjust the offset for memory cells in the unit based on a default threshold voltage of the memory cells.

[0058] In some implementations, the adjusted offsets of the memory cells in a unit are positively correlated with the default threshold voltages of the memory cells.

[0059] In some implementations, the peripheral circuit includes a fourth register configured to store the offset obtained by the processor.

[0060] In some implementations, the control logic is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

[0061] In yet another embodiment, two N-bit data are N A method is disclosed for reading a memory device including an array of memory cells configured to be set to one of two states, N being an integer greater than 1, the array of memory cells being divided into one or more units, and the method comprising: N The method includes obtaining a number P of memory cells in the unit that are in one or more programmed states of the states, calculating a compensated read voltage having an offset from a default read voltage, and performing a read operation using the compensated read voltage on selected memory cells of the memory cells in the unit.

[0062] In some implementations, after calculating the compensated read voltage, the method further includes updating the offset after the number P of memory cells in the unit is changed.

[0063] In some implementations, the offset is updated periodically.

[0064] In some implementations, the update period is less than or equal to the minimum interval between two adjacent programming operations performed on the unit.

[0065] In some implementations, the number P of memory cells in the unit is calculated by performing a verify read operation.

[0066] In some implementations, the step of performing a verify read operation includes: Nselecting one or more of the programmed states of the states and determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states, wherein the verify voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected one or more states.

[0067] In some implementations, two N The number of the selected one or more programmed states is 1, and the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is 2 N It is higher than the threshold voltage of a memory cell corresponding to the unselected state among the states.

[0068] In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is 2 N The average number of memory cells in one or more selected pages that are in one or more of the programmed states.

[0069] In some implementations, calculating the compensated read voltage with the offset includes looking up an offset corresponding to the number P and a first mapping table between the offset and the number P.

[0070] In some implementations, the first mapping table is stored in a first register.

[0071] In some implementations, calculating the compensated read voltage with offset includes calculating a numerical difference ΔP between the number P and a default number P′, where the default number P′ is 2 N The number of memory cells in the unit that are in one or more of the programmed states.

[0072] In some implementations, the step of calculating the compensated read voltage with the offset further includes looking up an offset corresponding to the number difference ΔP, and a second mapping table between the offset and the number difference ΔP.

[0073] In some implementations, the second mapping table is stored in a second register.

[0074] In some implementations, the default number P' is stored in a third register.

[0075] In some implementations, after calculating the compensated read voltage with the offset, the method further includes adjusting the offset based on a default threshold voltage of the memory cell.

[0076] In some implementations, the adjusted offsets of the memory cells in a unit are positively correlated with the default threshold voltages of the memory cells.

[0077] In some implementations, the method further includes storing the adjusted offset in a fourth register.

[0078] In some implementations, determining the compensated read voltage includes obtaining an offset from a fourth register and calculating the compensated read voltage by adding the offset to a default read voltage.

[0079] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the disclosure and enable one skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0080] [Figure 1] FIG. 1 illustrates a trend in threshold voltage distribution of a memory device after charge loss, according to some aspects of the present disclosure. [Figure 2A] FIG. 2 illustrates a diagram showing storage times of blocks in a memory device in accordance with some aspects of the present disclosure. [Figure 2B] FIG. 2 illustrates a relationship between storage time and threshold voltage distribution of a memory device, in accordance with some aspects of the present disclosure. [Figure 3A] FIG. 1 illustrates the amount of time incurred by a read operation without error recovery. [Figure 3B] FIG. 1 illustrates the amount of time incurred by a read operation with error recovery. [Figure 3C] FIG. 2 illustrates an example of the amount of time incurred by a read operation in accordance with some aspects of the present disclosure. [Figure 4] FIG. 1 is a block diagram of a system having a memory device in accordance with some aspects of the present disclosure. [Figure 5A] FIG. 2 illustrates a memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 5B] FIG. 1 illustrates a solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram illustrating a memory device including peripheral circuits in accordance with some aspects of the present disclosure. [Figure 7] FIG. 1 is a block diagram illustrating a memory device including a memory cell array and peripheral circuits in accordance with some aspects of the disclosure. [Figure 8] FIG. 1 is a block diagram illustrating a memory system including a host, a memory controller, and a memory device in accordance with some aspects of the present disclosure. [Figure 9A] FIG. 2 is a block diagram illustrating a memory controller coupled to a memory cell array in accordance with some aspects of the present disclosure. [Figure 9B] FIG. 2 is a block diagram illustrating another memory controller coupled to a memory cell array in accordance with some aspects of the present disclosure. [Figure 10A] FIG. 13 illustrates the relationship between verify voltage and threshold voltage distribution without charge loss. [Figure 10B] FIG. 1 illustrates the relationship between verify voltage and threshold voltage distribution with charge loss. [Figure 11] FIG. 11 is a diagram showing a first mapping table. [Figure 12] FIG. 13 shows a plot of programming state offset versus number of memory cells P. [Figure 13] FIG. 13 shows a table of offsets for each unit. [Figure 14A] FIG. 13 illustrates the relationship between verify voltage and threshold voltage distribution without charge loss. [Figure 14B] FIG. 1 illustrates the relationship between verify voltage and threshold voltage distribution with charge loss. [Figure 15] 1 is a flowchart of a method for read offset compensation based on a number P of memory cells according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0081] Aspects of the present disclosure will now be described with reference to the accompanying drawings.

[0082] In general, terms may be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood as conveying a singular use or as conveying a plural use, depending at least in part on the context. Furthermore, the term "based on" is not necessarily intended to convey an exclusive set of factors, but instead may allow for the presence of additional factors not necessarily explicitly recited, depending at least in part on the context.

[0083] By utilizing charge trapping technology, memory devices such as NAND flash memory devices can store more than one bit of information in each memory cell in multiple states to increase storage capacity and reduce cost per bit. In a program operation of a memory device employing charge trapping technology, data can be programmed (written) into a multi-level cell (MLC) block, such as a trip-level cell (TLC) block, a quad-level cell (QLC) block, or a penta-level cell (PLC), which significantly increases programming speed. Referring to FIG. 1, the threshold voltage distribution of a block is reduced due to charge loss, and memory cells in different program states experience different degrees of charge loss. The reduction in threshold voltage distribution causes error bits and, if the charge loss is severe, causes read error recovery. A read offset is provided to compensate for the charge loss. For example, a first offset is added to the default read voltage to compensate for the change in threshold voltage distribution. This approach is largely ineffective because the charge loss is closely related to the period after the data is written. 2A and 2B, the durations of different blocks are not statistically maintained but change dynamically, so the read offset cannot compensate for the charge loss of all blocks and cannot avoid read errors.

[0084] FIG. 3A illustrates a first period t R and a second period t for transferring data to the memory controller. XER FIG. 3B shows a diagram of the length of time caused by a read operation with error recovery, including a first period t R and the second period t XER In addition to the read error, there is a third period t during which the memory controller and hardware prepare to try again after a read error. 0V The actual time caused by the read operation of the memory block having charge loss is a first period tR , the second period t XER , and the third period t 0V Therefore, the efficiency of the memory system is greatly reduced.

[0085] In order to address one or more of the above-mentioned problems, the present disclosure provides a method for detecting the degree of charge loss in each block, and generating a specially adjusted read offset to compensate for the default read voltage based on the degree of charge loss, thus avoiding read errors, greatly improving the read speed, and reducing the time taken by the read operation of the memory block to a first period t regardless of the charge loss, as shown in FIG. 3C. R , the second period t XER , and the third time t 0V A solution is introduced in which the sum of . By counting the number of memory cells in a programmed state in each block, the degree of charge loss can be detected since the number decreases due to charge loss. Depending on the degree of charge loss detected, the read voltage can be accurately compensated by a tailor-made offset. This solution can detect the charge loss in each block regardless of the cause of the charge loss, i.e., whether the charge loss is caused by time, temperature, program operation, etc., and can accurately compensate the read voltage. The relationship between the offset and the number of memory cells in a programmed state is pre-calculated and stored as a mapping table, so that the offset can be determined immediately after obtaining the number. Since the accumulation of charge loss requires a certain time, the offset is updated periodically rather than calculated before each read operation to balance the efficiency and accuracy of the read operation. The solution of the present disclosure reduces the undesirable effects of charge loss at a low cost and significantly improves the performance of memory devices and memory systems.

[0086] FIG. 4 illustrates a block diagram of a system 100 having a memory device according to some aspects of the disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or other suitable electronic device having storage. As shown in FIG. 4, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit and receive data to and from the memory device 104.

[0087] The memory device 104 may be any memory device disclosed in detail in this disclosure. According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low duty cycle environments such as secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 106 is designed to operate in high duty cycle environments such as SSDs or embedded multi-media-cards (eMMC) used as data storage in mobile devices such as smart phones, tablets, laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104 such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory device 104. Any other suitable functions may be performed by the memory controller 106 as well, such as formatting the memory device 104.Consistent with certain aspects of the present disclosure, in some implementations, the memory controller 106 is configured to fully or partially perform read offset compensation, as described in more detail below.

[0088] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with the external device via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0089] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into various types of end electronic products. In one example shown in FIG. 5A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, and the like. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1). In another example shown in FIG. 5B, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 of FIG. 4). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0090] FIG. 6 illustrates a schematic circuit diagram of a memory device 300 including peripheral circuits according to some aspects of the disclosure. The memory device 300 may be an example of the memory device 104 of FIG. 4. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, in which the memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be either a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0091] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0092] As shown in FIG. 6, each NAND memory string 308 may include a source select gate (SSG) 310 at the source end and a drain select gate (DSG) 312 at the drain end. The SSG 310 and DSG 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314, e.g., a common SL. In other words, according to some implementations, all the NAND memory strings 308 in the same block 304 have an array common source (ACS). The DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 through which data can be read or written via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor comprising the DSG 312) or a non-select voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313, and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor comprising the SSG 310) or a non-select voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

[0093] As shown in FIG. 6, the NAND memory strings 308 can be organized into multiple blocks 304, and each block can have a common source line 314 coupled to, for example, an ACS. In some implementations, each block 304 is the basic data unit of an erase operation. That is, all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source lines 315 coupled to the selected block 304, as well as unselected blocks 304 in the same plane as the selected block 304, can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or more). It is understood that in some examples, the erase operation can be performed at a half-block level, a quarter-block level, or a level having any suitable number of blocks or any suitable portion of a block. The memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit of a program operation. The size of one page 320 in bits may be related to the number of NAND memory strings 308 coupled by the word lines 318 in one block 304. For ease of explanation, the memory cells 306 in one page 320 may be coupled to the same word line 318, and the terms "page" and "word line" may be used interchangeably in this disclosure. However, it is understood that in some examples, the memory cells 306 in one page 320 may be coupled to multiple word lines 318. Each word line 318 may include multiple control gates (gate electrodes) in each memory cell 306 in the respective page 320 and gate lines coupling the control gates.

[0094] As shown in FIG. 6, program operations are performed at the page / word line level for each block 304, and therefore consistent with the scope of the present disclosure. The peripheral circuitry 302 may be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include any suitable analog, digital, and mixed signal circuitry by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313 to facilitate operation of the memory cell array 301. The peripheral circuitry 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 shows peripheral circuits in memory device 104, including page buffer / sense amplifiers 404, column decoder / bit line drivers 406, row decoder / word line drivers 408, voltage generators 410, control logic 412, registers 414, interface 416, and data bus 418. It will be understood that in some examples, additional peripheral circuits not shown in Figure 7 may be included as well.

[0095] The page buffer / sense amplifier 404 can be configured to read and program (write) data to and from the memory cell array 301 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 can store a page of program data (write data) to be programmed into a page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 404 can perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 404 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder / bit line driver 406 can be configured to select one or more NAND memory strings 308 by applying bit line voltages generated from a voltage generator 410, controlled by the control logic 412.

[0096] The row decoder / word line driver 408 can be configured to be controlled by the control logic 412, the select / deselect block 304 of the memory cell array 301, and the select / deselect word line 318 of the block 304. The row decoder / word line driver 408 can be further configured to drive the word line 318 using a word line voltage generated from a voltage generator 410. In some implementations, the row decoder / word line driver 408 can also select / deselect and drive the SSG line 315 and the DSG line 313. As described in more detail below, the row decoder / word line driver 408 is configured to apply a read voltage to the selected word line 318 in a read operation for the memory cells 306 coupled to the selected word line 318.

[0097] The voltage generator 410 may be controlled by the control logic 412 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages supplied to the memory cell array 301. The control logic 412 may be coupled to each of the peripheral circuits mentioned above and configured to control the operation of each of the peripheral circuits. The registers 415 may be coupled to the control logic 412 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each of the peripheral circuits.

[0098] The interface 416 is coupled to the control logic 412 and may function as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 412 and to relay status information received from the control logic 412 to the host. The interface 416 may also be coupled to the column decoder / bit line drivers 406 via a data bus 418 and may function as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 301.

[0099] 8, in accordance with some implementations of the present disclosure, a memory system 500 is provided that includes a plurality of memory devices 104 and a memory controller 106. Each of the memory devices 104 includes an array of memory cells and peripheral circuits, as shown in FIG. 7. The memory cells in the memory devices 104 are MLC, and each memory cell stores 2 N-bit data. NThe memory cell array is configured to be set to one of the states, where N is an integer greater than 1. The array of memory cells is divided into one or more units. The unit can be a physical unit or a logical unit. For example, the unit can be a page or a block based on the physical connection between the memory cells. The unit can also be a group of memory cells in different pages or blocks that operate with the same write operation. The number of memory cells in each unit can be the same or different depending on the actual needs of the storage. In one implementation, the number of memory cells in a unit can be one. The division method of the unit and the number of memory cells in a unit described herein are for illustrative purposes only and should not be construed as limiting the present disclosure. The peripheral circuit is coupled to the memory cell and configured to perform a read operation on a selected one of the memory cells in one of the units.

[0100] The memory controller 106 may be coupled to the memory devices and configured to execute various interface protocols disclosed herein. As shown in FIG. 8, the memory controller 106 may be coupled to one or more memory devices 104 and configured to control cache programming of the memory devices 104. The memory controller 106 may include various interface layers, including but not limited to a peripheral component interconnect express (PCIe) layer 510, a non-volatile memory express (NVMe) layer 520, and / or a NAND controller interface (NFI) layer 530 for interfacing with the host 108 and the memory devices 104. The PCIe layer 510 and / or the NVMe layer 520 may be coupled to one or more processing units 540 (e.g., microcontrollers), which may be configured to implement various memory control functions by executing instructions, for example, in the form of firmware stored in a read-only memory (ROM) 550. The processing unit 540 may be coupled to a dynamic random access memory (DRAM) 570 via a DRAM controller 560. DRAM controller 560 may be configured to store and access data stored in DRAM 570, such as cached new programming data and / or reconstructed current programming data transmitted from memory device 104 to memory controller 106 according to various interface protocols disclosed herein. It is understood that in some examples, DRAM 570 and DRAM controller 560 may be omitted. In other words, memory controller 106 may be a non-DRAM memory controller.

[0101] FIG. 9A illustrates an implementation of the memory controller 106 coupled to the memory cell array 301 via a back-end interface 628. The memory controller 106 includes a processor 622 and a digital signal processor (DSP) 624 coupled to the back-end interface 628. The processor 622 is configured to control the memory cell array 301 to count the number P of memory cells in a unit by performing a verify read operation. The DSP 624 is configured to count the number P after a verify voltage is applied to at least a portion of the memory cells in the unit. The memory controller 106 further includes a register 626 configured to store the first mapping table and an offset. The memory controller 106 further includes a register 626 configured to store the first mapping table and an offset. The number P calculated by the DSP 624 can be stored in a register, for example, the register 626, and the processor 622 can extract the number P from the register. The first mapping table, the number P, and the offset can be stored in the same register or different registers depending on the size of the register. In the current implementation, the first mapping table is stored in a first register and the offset is stored in a fourth register.

[0102] In one implementation of the present disclosure, the memory controller 106 is configured to control the memory device 104 to perform a read operation using a compensated read voltage having an offset from a default read voltage by sending an instruction to the peripheral circuit. NThe number of memory cells in the unit that are in one or more programmed states of the states is correlated with P. A TLC unit is used as an example in the current implementation (N=3), and each TLC unit has 8 states. Other MLC units, such as QLC units and PLC units, can also be used in this disclosure. For a QLC unit, N=4, the memory cells in the QLC unit have 16 states, and 15 of the 16 states are programmed states. For a PLC unit, N=5, the memory cells in the QLC unit have 32 states, and 31 of the 32 states are programmed states. This disclosure can be applied to any MLC unit, regardless of the number of states the unit has.

[0103] Referring to FIG. 10A, after data is programmed into the memory device, the number of memory cells in each state of the eight states is approximately the same. The default read voltages of memory cells in different states are set to the margin between adjacent states. Take state L7 as an example, the default read voltage of memory cells in state L7 is equal to or less than the minimum threshold voltage of memory cells in state L7 and is greater than the maximum threshold voltage of memory cells in state L6. FIG. 10B shows the threshold voltage distribution in the same unit after a period of time in the memory device. As the threshold voltage decreases, the number of memory cells in each state of the eight states changes slightly, but the default read voltage of the read operation remains at the original level. In a situation where the default read voltage is equal to the minimum threshold voltage of memory cells in state L7, the read operation completes with the distribution shown in FIG. 10A and fails with the distribution shown in FIG. 10B. Referring to FIG. 3B, when the read operation fails, an error recovery is triggered to adjust the read voltage. This process may take time because the degree of threshold voltage decrease varies from unit to unit. The more the threshold voltage deviates from the default read voltage, the longer it takes to recover from the error. A fixed offset does not solve this problem.

[0104] To save time spent on error recovery, it is necessary to accurately compensate for the charge loss of each memory unit. That is, the offset needs to be specifically tailored for each unit based on the duration of each read operation after the unit is programmed. Since the charge loss accumulates and changes over time, the offset is updated periodically to accurately compensate for the charge loss. The charge loss is relatively slow compared to the speed and frequency of read operations. For example, the threshold voltage of a memory cell is not affected until a certain amount of accumulated lost charge, which may take a month or more. Therefore, it is not necessary to update the offset after every read operation. In this implementation, the offset may be updated periodically after a program operation. In some implementations, the update period is less than or equal to the minimum interval between two adjacent programming operations performed on the unit. For example, the offset is updated monthly after a write operation.

[0105] The number of memory cells P in the unit is obtained by a verify read operation using a verify voltage. To determine the verify voltage, N One or more programmed states are selected from the states, and a default range of threshold voltages corresponding to the selected state or states is extracted. The verify voltage must be equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected state or states so that minor charge loss can be detected.

[0106] In this implementation, 2 N The number of the selected one or more programmed states is 1, i.e., the minimum threshold voltage of the default range of threshold voltages corresponding to the selected states is 2 N10A and 10B, eight states can be stored in the TLC unit, with L0 being the erased state and L1 through L7 being the seven programmed states. The highest level, L7, is selected and the corresponding L7 verify voltage is equal to the minimum threshold voltage of L7. In a verify read operation, a verify voltage is applied to at least some of the memory cells in the unit via the word lines 318 driven by the word line driver 408. In other MLC units, such as the QLC unit, sixteen states can be stored in the QLC unit, with L0 being the erased state and L1 through L15 being the fifteen programmed states. The highest level, L15, can be selected and the corresponding L15 verify voltage is equal to the minimum threshold voltage of L15.

[0107] The principle of the verify read operation is to view the MLC unit as a single-level cell (SLC) unit, i.e., the memory cells whose threshold voltage is higher than the verify voltage are in the first state and data "0" is fed back, and the memory cells whose threshold voltage is lower than the verify voltage are in the second state and data "1" is fed back. Assuming an ideal situation where there is no charge loss in the memory device, the number of memory cells in the first state should not change over time. However, in reality, when the charge in the memory cells is detrapped, the threshold voltage distribution shifts to the left, as shown in Figure 1. Thus, when a verify read operation is performed on the memory device, the number of memory cells in the first state decreases. The more charge is lost, the fewer the number of memory cells in the first state. In this way, the degree of charge loss can be accurately detected and the offset can be specifically adjusted to accurately compensate for the charge loss. The first and second states are distinguished by the verify voltage of the verify read operation. By setting the verify voltage, the two N One or more of the programmed states can be selected. Typically, the highest level memory cell is selected to improve the speed and accuracy of the verify read operation, e.g., level 7 for TLC devices and level 15 for QLC devices. Once the verify voltage is determined, it is fixed and will not be changed for the next verify read operation.

[0108] When the L7 verify voltage is applied to the unit immediately after the program operation is finished, the number of memory cells P in state L7 is equal to the default number P'. Because there is a scrambler that randomizes the data pattern in each program operation, the number of memory cells in each of the eight states is close. For example, an 18 kB NAND page has a total of 18 x 1024 x 8 = 147456 bits, and the number of memory cells in each of the eight states is 147456 / 8 = 18432 bits. For a unit containing one page, the number of memory cells in each of the eight states is 18432 x 1 = 18432 bits. For a unit containing four pages, the number of memory cells in each of the eight states is 18432 x 4 = 73728 bits. For a unit containing eight pages, the number of memory cells in each of the eight states is 18432 x 8 = 147456 bits. In this implementation, taking a unit containing 4 pages as an example, immediately after the unit is programmed, the number P of memory cells in state L7 is equal to the default number P' of memory cells in state L7, ie, 73728 bits.

[0109] Over time, more electrons are detrapped on the cells due to the loss of charge. Thus, the threshold voltage distribution shifts downwards; that is, L7 shifts leftwards, and the number of cells P decreases. After the L7 verify voltage is applied to at least some of the memory cells in the unit, the number P is counted by the digital signal processor of the memory controller. As the threshold voltage distribution shifts leftwards, as shown in FIG. 10B, under the same verify voltage, the number P of memory cells in L7 becomes less than the default number P'. To address the offset to compensate for the charge loss, the processor 622 sends an instruction to the memory cell array 301 via the back-end interface 628 to control the memory cell array 301 to count the number P of memory cells in the L7 state by performing a verify read operation. The verify voltage used in the verify read operation is ascertained by the processor 622 as described above, i.e., the minimum threshold voltage of memory cells in the L7 state.

[0110] After the verify read operation is completed, the DSP 624 counts the number P. In one embodiment, the DSP 624 is coupled to a page buffer of the memory cell array 301 via a back-end interface 628. For memory cells coupled to the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in a register 626, and the total current generated under the verify voltage can be tested by the page buffer, and the number of memory cells in L7 is proportional to the current tested by the page buffer.

[0111] In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is 2 N P is the average number of memory cells in one or more selected pages that are in one or more programmed states of the state. The verify read operation is performed page by page. That is, memory cells driven by the same bit lines are verified in the same verify read operation. For a unit containing multiple pages, the verification efficiency can be improved by sampling some of the pages instead of the whole page. For example, unit 1 contains 1024 pages that are written in the same write operation, and performing verify read operations on all 1024 pages is time consuming. Since the charge loss is strongly related to the period after the last write operation, pages in the same unit have a similar amount of charge loss. Therefore, to obtain the number P, it is reasonable to sample a few of the 1024 pages. For example, one page was selected to perform the verify read operation. In other implementations, two or more pages can be selected to perform the verify read operation, and the number P can be obtained by averaging the number of memory cells in the selected states in the selected pages to reduce errors.

[0112] After the number P is confirmed, the processor 622 can obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table can be stored in a first register of the registers 626. The first mapping table can also be stored in a static random access memory (SRAM). FIG. 11 shows an example of the first mapping table, where M corresponds to the number P. That is, when P is 2 N where M is the number of memory cells in the unit that are in one or more of the programmed states, P is the number of memory cells in the unit that are in one or more of the programmed states, and P is the number of memory cells in the selected page that are in one or more of the programmed states. N Where M is the number of memory cells in one or more of the programmed states of the unit, M is the number of memory cells in a selected page of the unit. In this implementation, only some, but not all, of the pages in the unit are selected to perform a verify read operation, and M is 2 N In another implementation, all pages in the unit are selected to perform a verify read operation, and M is equal to 2 N M is the number of memory cells in the unit that are in one or more programmed states of the L7 state. In this implementation, M is the number of memory cells in the selected page that are in the L7 state immediately after the selected page is programmed, i.e., 18432. The degree of charge loss is divided into eight stages, from D0 to D7, based on the number of P counted by the DSP 624. As shown in FIG. 11, if the number P is 18340 and is less than M,

[0113]

number

[0114] If it is larger, the degree of charge loss corresponding to 18340 is small at D0, and there is no need to adjust the default read voltage. The offset should be 0. If the number P is

[0115]

number

[0116] Smaller

[0117]

number

[0118] If the number P is greater than 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120 mV must be applied to the memory cells in the L7 state.

[0119]

number

[0120] Smaller

[0121]

number

[0122] If the number P is greater than 3072, then the degree of charge loss corresponding to 3072 is D5, and an offset of -300 mV must be applied to the memory cells in the L7 state.

[0123]

number

[0124] If it is less than 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too serious to be compensated for, and the data stored in the unit needs to be rearranged.

[0125] For memory cells with the same degree of charge loss, the higher the threshold voltage of the memory cell, the more serious the threshold drop. Therefore, the offset needs to be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell. For example, for a charge loss of D2 degree, the offset of the memory cell in the L7 state should be -120mV, the offset of the memory cell in the L4 state should be -60mV, and the offset of the memory cell in the L1 state should be -20mV. The relationship between the offset of the memory cell in different states and the charge loss degree is shown in Figure 12. For other MLC devices, such as QLC devices, the relationship between the offset of the memory cell in various states and the charge loss degree shows a similar trend to that shown in Figure 12.

[0126] After the offset of the unit is obtained, it is stored in an index table as shown in FIG. 13. Since the degree of charge loss of different units is different, the offset of different units is also different. For example, the degree of charge loss of unit 1 is D0, which means that the memory cells of unit 1 do not experience charge loss, and the offset of each memory cell of unit 1 is 0. The degree of charge loss of unit 2 is D5, which means that the memory cells of unit 2 experience serious but non-fatal charge loss, and an offset is required. Referring to FIG. 13, for the memory cells of unit 2, the offset of the memory cells of level 1 is −130 mV, the offset of the memory cells of level 3 is −200 mV, and the offset of the memory cells of level 7 is −300 mV. If the degree of charge loss of the unit is D7, this means that the memory cells in the unit experience serious and fatal charge loss, and data may not be read correctly, like unit 3, and the data of unit 3 needs to be relocated. The index table of FIG. 13 is stored in a register or SRAM, and is periodically updated by performing a verify read operation. Each read operation accesses the index table to obtain the corresponding offset, thus avoiding read errors, and thus the time required to access the index table is negligible, greatly improving the efficiency of the memory device.

[0127] FIG. 9B illustrates another implementation of the present disclosure, in which a numerical difference ΔP between a number P and a default number P′ is calculated. The default number P′ is 2 NThe number of memory cells in the unit that are in one or more programmed states of the state. As described above, for a unit including 4 18 kB NAND pages, the number of memory cells P in state L7 is equal to the default number P' of memory cells in state L7, i.e., 73728 bits. In this embodiment, the processor 622 is configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP. The second mapping table is stored in a second register of the registers 626, and the default number P' is stored in a third register of the registers 626. The memory controller 106 further includes a calculator 629 coupled to the processor 622 and the DSP 624. The calculator 629 is configured to calculate the number difference ΔP based on the default number P' stored in the third register and the number P obtained by the DSP 624. The number difference ΔP is then transmitted to the processor 622, which determines the offset based on the number difference ΔP and the second mapping table. The numerical difference ΔP used in this implementation has the same function as the number P in the above implementation, that is, it reflects the charge loss due to the change in the numerical value in the selected state. Although the approaches to calculate the numerical difference ΔP and the number P are different, both can be realized in multiple ways. The implementations described above are exemplary and should not be construed as limiting the present disclosure.

[0128] 14A and 14B show some implementations of the present disclosure in which four programmed states are selected instead of one to reflect the change in the number P. The verify voltage is set as the minimum threshold voltage of memory cells in all states from L4 to L7, i.e., the minimum threshold voltage of memory cells in state L4. Memory cells in states L4 to L7 are in the first state, and data "0" is fed back when the verify voltage is applied. When the threshold voltage distribution shifts due to charge loss, the number P of memory cells under the verify voltage decreases, as shown in FIG. 14B. Therefore, the offset can be specially adjusted based on the number P. The verify read operation is the same as that described above, and is not repeated here.

[0129] The memory system of the present disclosure can detect the exact degree of charge loss and specifically adjust the offset to compensate for the charge loss in the read operation. Thus, error recovery is avoided and the time required for each read operation is greatly saved. The performance of the memory system is greatly improved.

[0130] 9A and 9B show different implementations of the memory controller 106 coupled to a memory cell array 301 of memory cells as shown in FIG. 7. Each memory cell stores two N The memory cells are set to one of the states, where N is an integer greater than 1, and the array of memory cells is divided into one or more units.

[0131] In FIG. 9A, a memory controller 106 is coupled to a memory device to address the above-mentioned problem. The memory controller 106 is coupled to a memory cell array 301, and upon execution of an instruction, the memory controller 106 reads two or more data from the memory cell array 301. NThe memory controller 106 is configured to: obtain a number P of memory cells in one of the plurality of units that are in one or more programmed states of the states; calculate a compensated read voltage having an offset from a default read voltage based on the number P; and provide the compensated read voltage to the memory device for a read operation performed on a selected one of the memory cells in the one of the plurality of units. Referring to FIG. 9A, the memory controller 106 includes a processor 622 and a DSP 624 coupled to a back-end interface 628. The processor 622 is configured to control the memory cell array 301 to count the number P of memory cells in the unit by performing a verify read operation. The DSP 624 is configured to count the number P after the verify voltage is applied to at least a portion of the memory cells in the unit. The memory controller 106 further includes a register 626 configured to store a first mapping table and an offset. The first mapping table and the offset can be stored in the same register or different registers depending on the size of the register. In this implementation, the first mapping table is stored in a first register and the offset is stored in a fourth register. 9B, the memory controller further includes a calculator 629 coupled to the processor 622 and the DSP 624. The numerical difference ΔP is then sent to the processor 622, and an offset is determined based on the numerical difference ΔP and the second mapping table. The numerical difference ΔP used in this implementation has the same function as the numerical value P in the above implementation, that is, it reflects the charge loss due to the change in numerical value in the selected state.

[0132] FIG. 9B illustrates another implementation of the present disclosure, in which a numerical difference ΔP between a number P and a default number P′ is calculated. The default number P′ is 2 NThe number P′ is the number of memory cells in the unit that are in one or more programmed states of the state. The processor 622 is configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP. The second mapping table is stored in a second register of the registers 626, and the default number P′ is stored in a third register of the registers 626. The memory controller 106 further includes a calculator 629 coupled to the processor 622 and the DSP 624. The calculator 629 is configured to calculate the number difference ΔP based on the default number P′ stored in the third register and the number P obtained by the DSP 624. The number difference ΔP is then sent to the processor 622, and the offset is determined based on the number difference ΔP and the second mapping table. The number difference ΔP used in this implementation has the same function as the number P in the above implementation, that is, it reflects the charge loss due to the change in the number in the selected state. Although the approaches to calculate the number difference ΔP and the number P are different, both can be realized in multiple ways. The above-described implementations are illustrative and should not be construed as limiting the disclosure.

[0133] In some implementations of the present disclosure, an offset that can accurately compensate for charge loss can be provided by the memory device without the involvement of a memory controller. As shown in FIG. 7, the memory device 104 includes an array 301 of memory cells and peripheral circuits 302. Each memory cell stores 2 N bits of data corresponding to the N bits of data. N A peripheral circuit 302 is coupled to the memory cells and configured to perform a read operation on selected ones of the memory cells of the unit using a compensated read voltage having an offset from a default read voltage. The offset is 2 N It correlates to the number P of memory cells in the unit that are in one or more of the programmed states.

[0134] Taking a TLC device as an example, referring to FIG. 10A and FIG. 10B, eight states can be stored in a TLC unit, with L0 being the erased state and L1 to L7 being the seven programmed states. In this embodiment, N The number of the selected one or more programmed states is one, that is, the minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is 2 N The L7 verify voltage is higher than the threshold voltage of the memory cell corresponding to the unselected state of the state. The highest level, L7, is selected and the corresponding L7 verify voltage is equal to the minimum threshold voltage of L7. In a verify read operation, a verify voltage is applied to at least some of the memory cells in the unit via the word lines 318 driven by the word line driver 408. When the L7 verify voltage is applied to the unit immediately after the program operation is finished, the number of memory cells P in the L7 state is equal to the default number P'. The number of memory cells in each state of the eight states is close because there is a scrambler that randomizes the data pattern in each program operation. For example, an 18kB NAND page has a total of 18×1024×8=147456 bits, and the number of memory cells in each state of the eight states is 147456 / 8=18432 bits. For a unit containing one page, the number of memory cells in each state of the eight states is 18432×1=18432 bits. For a unit containing four pages, the number of memory cells in each state of the eight states is 18432×4=73728 bits. For a unit containing 8 pages, the number of memory cells in each of the 8 states is 18432×8=147456 bits. In this embodiment, taking a unit containing 4 pages as an example, immediately after the unit is programmed, the number P of memory cells in state L7 is equal to the default number P′ of memory cells in state L7, which is 73728 bits.

[0135] Over time, more electrons are detrapped on the cell due to the loss of charge. Thus, the threshold voltage distribution shifts down, i.e., L7 shifts left, and the number of cells P decreases. After the L7 verify voltage is applied to at least some memory cells in the unit, the number P is counted by the calculator in the peripheral circuit 302. As shown in FIG. 10B, as the threshold voltage distribution shifts left, under the same verify voltage, the number P of memory cells in L7 becomes less than the default number P'. To address the offset to compensate for the charge loss, the control logic 412 sends an instruction to the memory cell array 301 to control the memory cell array 301 to count the number P of memory cells in the L7 state by performing a verify read operation. The verify voltage used in the verify read operation is confirmed by the control logic 412 as described above, i.e., the minimum threshold voltage of memory cells in the L7 state.

[0136] After the verify read operation is completed, the page buffer counts a number P. For memory cells coupled to the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in a register 414, and the total current generated under the verify voltage can be tested by the page buffer, and the number of memory cells in L7 is proportional to the current tested by the page buffer. In some implementations, each unit of the one or more units includes one or more pages, and the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is calculated as follows: NP is the average number of memory cells in one or more selected pages that are in one or more programmed states of the state. The verify read operation is performed page by page, i.e., memory cells driven by the same bit lines are verified in the same verify read operation. For a unit that contains multiple pages, sampling a portion of the page instead of the entire page improves the verification efficiency. For example, unit 1 contains 1024 pages that are written in the same write operation, and performing verify read operations on all 1024 pages is time consuming. Since the charge loss is strongly related to the period after the last write operation, pages in the same unit have a similar amount of charge loss. Therefore, to obtain the number P, it is reasonable to sample a few pages out of the 1024 pages. For example, one page was selected to perform the verify read operation. In other implementations, two or more pages can be selected to perform the verify read operation, and the number P can be obtained by averaging the number of memory cells in the selected states in the selected pages to reduce errors.

[0137] After the number P is confirmed, the control logic 412 can obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table is stored in a first register of the registers 414. FIG. 11 shows an example of the first mapping table, where M is 2 N M is the number of memory cells in one of the multiple units that are in one or more programmed states of the multiple units. In this implementation, M is the number of memory cells in the unit that are in the L7 state immediately after the unit is programmed, i.e., 18432. The degree of charge loss is divided into eight stages, from D0 to D7, based on the number P counted by the page buffer. As shown in FIG. 11, when the number P is smaller than M,

[0138]

number

[0139] If the number P is greater than 18340, the charge loss corresponding to 18340 is D0, which is small, so there is no need to adjust the default read voltage and the offset should be 0.

[0140]

number

[0141] Smaller

[0142]

number

[0143] If the number P is greater than 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120 mV must be applied to the memory cells in the L7 state.

[0144]

number

[0145] Smaller

[0146]

number

[0147] If the number P is greater than 3072, then the degree of charge loss corresponding to 3072 is D5, and an offset of -300 mV must be applied to the memory cells in the L7 state.

[0148]

number

[0149] For the smaller 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too serious to be compensated for, so the data stored in the unit needs to be rearranged.

[0150] For memory cells with the same degree of charge loss, the higher the threshold voltage of the memory cell, the more serious the threshold drop. Therefore, the offset needs to be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell. For example, for a charge loss of about D2, the offset of the memory cell in the L7 state should be -120mV, the offset of the memory cell in the L4 state should be -60mV, and the offset of the memory cell in the L1 state should be -20mV. The relationship between the offset and the charge loss degree of memory cells in various states is shown in Figure 12. For other MLC devices, such as QLC devices, the relationship between the offset and the charge loss degree of memory cells in various states shows a similar trend to that shown in Figure 12.

[0151] After the offset of the unit is obtained, it is stored in an index table as shown in FIG. 13. Since the degree of charge loss of different units is different, the offset of different units is also different. For example, the degree of charge loss of unit 1 is D0, which means that the memory cells of unit 1 do not experience charge loss, and the offset of each memory cell of unit 1 is 0. The degree of charge loss of unit 2 is D5, which means that the memory cells of unit 2 experience serious, but not fatal, charge loss, and an offset is required. Referring to FIG. 13, for the memory cells of unit 2, the offset of the memory cells of level 1 is −130 mV, the offset of the memory cells of level 3 is −200 mV, and the offset of the memory cells of level 7 is −300 mV. If the degree of charge loss of the unit is D7, this means that the memory cells in the unit experience serious and fatal charge loss, and data may not be read correctly, like unit 3, and the data of unit 3 needs to be relocated. The index table of FIG. 13 is stored in a register or SRAM, and is periodically updated by performing a verify read operation. For each read operation, the index table is accessed to obtain the corresponding offset, which avoids read errors, and therefore the time required to access the index table is negligible, greatly improving the efficiency of the memory device.

[0152] In another implementation of the present disclosure, a numerical difference ΔP between the number P and a default number P′ is calculated. The default number P′ is calculated by multiplying the number P by 2 after the program operation is completed. NThe number of memory cells in the unit that are in one or more programmed states among the states. As described above, for a unit including 4 18 kB NAND pages, the number P of memory cells in state L7 is equal to the default number P' of memory cells in state L7, i.e., 73728 bits. In this implementation, the control logic 412 is configured to obtain the offset through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP. The second mapping table is stored in a second register of the registers 414, and the default number P' is stored in a third register of the registers 414. The control logic 412 further includes a calculator configured to calculate the number difference ΔP based on the default number P' stored in the third register and the obtained number P. The number difference ΔP is then used to determine an offset based on the number difference ΔP and the second mapping table. The number difference ΔP used in this implementation has the same function as the number P in the above implementation, i.e., reflects the charge loss due to a change in the value in the selected state. Although the approaches to calculate the number difference ΔP and the number P are different, both can be realized in multiple ways. The implementations described above are exemplary and should not be construed as limiting the present disclosure.

[0153] 15 illustrates a flowchart of a method 1500 for operating a memory device according to some aspects of the disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 104. Memory device 104 has two N-bit data corresponding to one N-bit data. N15 includes an array 301 of memory cells configured to be set to one of N states, where N is an integer greater than 1, and the array 301 of memory cells is divided into one or more units. The method 1500 may be implemented by peripheral circuits 302, such as row decoder / word line driver 408, voltage generator 410, control logic 412, and registers 414. The method 1500 may be implemented by memory controller 106, such as processor 622, DSP 624, and registers 626. It is understood that the operations illustrated in the method 1500 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations as well. Additionally, some operations may be performed simultaneously or in a different order than that illustrated in FIG.

[0154] Referring to FIG. 15, the method 1500 begins with operation 1502. N The number P of memory cells in the unit that are in one or more programmed states of the states is obtained. Taking a TLC device as an example, referring to FIG. 10A and FIG. 10B, eight states can be stored in a TLC unit, with L0 being the erased state and L1 to L7 being the seven programmed states. In this embodiment, N The number of the selected one or more programmed states is 1, i.e., the minimum threshold voltage of the default range of threshold voltages corresponding to the selected states is 2 NThe L7 verify voltage is higher than the threshold voltage of the memory cell corresponding to the unselected state of the state. The highest level, L7, is selected and the corresponding L7 verify voltage is equal to the minimum threshold voltage of L7. In a verify read operation, a verify voltage is applied to at least some of the memory cells in the unit via the word lines 318 driven by the word line driver 408. When the L7 verify voltage is applied to the unit immediately after the program operation is finished, the number of memory cells P in the L7 state is equal to the default number P'. The number of memory cells in each state of the eight states is close because there is a scrambler that randomizes the data pattern in each program operation. For example, an 18kB NAND page has a total of 18×1024×8=147456 bits, and the number of memory cells in each state of the eight states is 147456 / 8=18432 bits. For a unit containing one page, the number of memory cells in each state of the eight states is 18432×1=18432 bits. For a unit containing four pages, the number of memory cells in each state of the eight states is 18432×4=73728 bits. For a unit containing 8 pages, the number of memory cells in each of the 8 states is 18432×8=147456 bits. In this implementation, take a unit containing 4 pages as an example, and immediately after the unit is programmed, the number P of memory cells in state L7 is equal to the default number P′ of memory cells in state L7, which is 73728 bits.

[0155] Over time, more electrons are detrapped on the cells due to charge loss. Thus, the threshold voltage distribution shifts down, i.e., L7 shifts left, and the cell number P decreases. After the L7 verify voltage is applied to at least some memory cells in the unit, the number P is counted. As the threshold voltage distribution shifts left, under the same verify voltage, the number P of memory cells in L7 becomes less than the default number P', as shown in FIG. 10B. To address the offset and compensate for the charge loss, a verify read operation is performed. The verify voltage used in the verify read operation is confirmed as above, i.e., the minimum threshold voltage of memory cells in the L7 state.

[0156] Upon completion of the verify read operation, the page buffer counts a number P. For memory cells coupled to the same bit line, the number of memory cells and the current generated by each memory cell in the L7 state are stored in a register. The total current generated under the verify voltage can be tested in the page buffer, and the number of memory cells in L7 is proportional to the current tested in the page buffer. In some implementations, each unit of the one or more units includes one or more pages, and a verify read operation is performed on one or more selected pages of the one or more pages, and the number P is calculated as 2 N P is the average number of memory cells in one or more selected pages that are in one or more programmed states of the state. The verify read operation is performed page by page, i.e., memory cells driven by the same bit lines are verified in the same verify read operation. For a unit containing multiple pages, sampling a portion of the page instead of the entire page improves the verification efficiency. For example, unit 1 contains 1024 pages that are written in the same write operation, and performing verify read operations on all 1024 pages is time consuming. Since the charge loss is strongly related to the period after the last write operation, pages in the same unit have a similar amount of charge loss. Therefore, to obtain the number P, it is reasonable to sample a few pages out of the 1024 pages. For example, one page was selected to perform the verify read operation. In other implementations, two or more pages can be selected to perform the verify read operation, and the number P can be obtained by averaging the number of memory cells in the selected state in the selected pages to reduce errors.

[0157] The method 1500 proceeds to operation 1504 as shown in FIG. 15, where a compensated read voltage having an offset from a default read voltage is obtained. After the number P is identified, the offset is obtained through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P. The first mapping table is stored in a first register of the registers. FIG. 11 shows an example of the first mapping table, where M corresponds to the number P. That is, when P is 2 N where M is the number of memory cells in the unit that are in one or more of the programmed states, P is the number of memory cells in the unit, and P is 2 N Where M is the number of memory cells in a selected page of a unit that are in one or more of the programmed states, M is the number of memory cells in a selected page of a unit. In this implementation, only some, but not all, of the pages in a unit are selected to perform a verify read operation, and M is 2 N M is the number of memory cells in a selected page in one of the multiple units that are in one or more programmed states. In another implementation, all pages in the unit are selected to perform a verify read operation, and M is 2 N M is the number of memory cells in the unit that are in one or more of the programmed states of the state. In this implementation, M is the number of memory cells in the selected page that are in the L7 state immediately after the selected page is programmed, i.e., 18432. The degree of charge loss is divided into eight stages, from D0 to D7, based on the number of P counted by the page buffer. As shown in FIG. 11, when the number P is smaller than M,

[0158]

number

[0159] If the number P is greater than 18340, the degree of charge loss corresponding to 18340 is D0, which is small, there is no need to adjust the default read voltage, and the offset should be 0.

[0160]

number

[0161] Smaller

[0162]

number

[0163] If the number P is greater than 14240, the degree of charge loss corresponding to 14240 is D2, and an offset of -120 mV must be applied to the memory cells in the L7 state.

[0164]

number

[0165] Smaller

[0166]

number

[0167] If the number P is greater than 3072, then the degree of charge loss corresponding to 3072 is D5, and an offset of -300 mV must be applied to the memory cells in the L7 state.

[0168]

number

[0169] If it is less than 1120, the degree of charge loss corresponding to 3072 is D7, which means that the charge loss of the unit is too serious to be compensated for, and the data stored in the unit needs to be rearranged.

[0170] For memory cells with the same degree of charge loss, the higher the threshold voltage of the memory cell, the more serious the threshold drop. Therefore, the offset needs to be adjusted based on the default threshold voltage of the memory cell, and the adjusted offset of the memory cell in the unit is positively correlated with the default threshold voltage of the memory cell. For example, for a charge loss of about D2, the offset of the memory cell in the L7 state should be -120mV, the offset of the memory cell in the L4 state should be -60mV, and the offset of the memory cell in the L1 state should be -20mV. The relationship between the offset and the charge loss degree of memory cells in various states is shown in Figure 12. For other MLC devices, such as QLC devices, the relationship between the offset and the charge loss degree of memory cells in various states shows a similar trend to that shown in Figure 12.

[0171] In another implementation of the present disclosure, a numerical difference ΔP between the number P and a default number P′ is calculated. The default number P′ is calculated by multiplying the number P by 2 after the program operation is completed. NThe offset is the number of memory cells in the unit that are in one or more programmed states among the states. As mentioned above, for a unit containing 4 18 kB NAND pages, the number P of memory cells in state L7 is equal to the default number P' of memory cells in state L7, i.e., 73728 bits. In this implementation, the offset is obtained through a lookup operation by looking up an offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP. The second mapping table is stored in a second register among the plurality of registers, and the default number P' is stored in a third register among the plurality of registers. A number difference ΔP is then calculated based on the default number P' stored in the third register and the obtained number P. The number difference ΔP is then used to determine an offset based on the number difference ΔP and the second mapping table. The number difference ΔP used in this implementation has the same function as the number P in the above implementation, i.e., it reflects the charge loss due to a change in the number in the selected state. Although the approaches to calculate the number difference ΔP and the number P are different, both can be realized in multiple ways. The above-described implementations are illustrative and should not be construed as limiting the disclosure.

[0172] The method 1500 continues with operation 1506, as shown in FIG. 15, where a read operation is performed using the compensated read voltage on selected ones of the memory cells in the unit.

[0173] By considering the MLC units as single-level cell (SLC) units and performing a verify read operation to confirm the actual charge loss of a particular unit, the present disclosure can confirm a customized offset to compensate for the default read voltage of the read operation. Error recovery is avoided and the time taken for each read operation is significantly saved. The performance of the memory system is significantly improved.

[0174] The foregoing description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0175] The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0176] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The subject matter described in this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with one another in a manner consistent with the scope of the present disclosure. [Explanation of symbols]

[0177] 100 Systems 104 Memory Devices 106 Memory Controller 108 Host 202 Memory Card 204 Memory card connector 206 SSD 208 SSD Connector 300 Memory Devices 301 Memory Cell Array 302 Peripheral Circuit 304 Block 306 Memory Cells 308 NAND memory strings 310SSG 312DSG 313 DSG line 314 Source Line 315 SSG Line 316 bit lines 318 Word Line 320 pages Page 404 Buffer / Sense Amplifier 406 Column Decoder / Bit Line Driver 408 Row Decoder / Word Line Driver 410 Voltage Generator 412 Control Logic 414 Register 416 Interface 418 Data Bus 500 Memory System 510 Peripheral Component Interconnect Express (PCIe) layer 520 Non-Volatile Memory Express (NVMe) Tier 530 NAND Controller Interface (NFI) Layer 540 Processing Unit 550 Read-Only Memory (ROM) 560 DRAM Controller 570 Dynamic Random Access Memory (DRAM) 622 processor 624 Digital Signal Processor (DSP) 626 Register 628 Backend Interface 629 Calculator

Claims

1. 1. A memory system comprising: An array of memory cells, each of which stores two bits of data corresponding to one N-bit data. Ｎ an array of memory cells configured to be set to one of states, N being an integer greater than 1, the array of memory cells being divided into one or more units; a peripheral circuit coupled to the memory cell and configured to perform a read operation on a selected one of the memory cells in a unit of the plurality of units; a memory device including: a memory controller coupled to the memory device and configured to control the memory device to perform the read operation using a compensated read voltage having an offset from a default read voltage by sending an instruction to the peripheral circuit; Equipped with The offset is Ｎ correlated with the number P of memory cells in the unit that are in one or more of the programmed states; Memory system.

2. 2. The memory system of claim 1, wherein the offset is associated with the unit and is updated after the number P of memory cells in the unit changes.

3. The memory system of claim 2 , wherein the offset is updated periodically.

4. 4. The memory system of claim 3, wherein an update period is less than or equal to a minimum interval between two adjacent programming operations performed on said unit.

5. 2. The memory system of claim 1, wherein the number P is obtained through a verify read operation configured to count the number P of memory cells in the unit.

6. The memory controller, 2 Ｎ Selecting one or more of the programmed states of the states; determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states; It is structured as follows: the verify voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected state or states; 6. The memory system of claim 5.

7. 2 Ｎ the number of the selected one or more programmed states is one, The minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is Ｎ higher than the threshold voltage of a memory cell corresponding to a non-selected state among the states, 7. The memory system of claim 6.

8. 7. The memory system of claim 6, wherein the peripheral circuitry comprises a word line driver configured to apply the verify voltage to at least some of the memory cells in the unit via a word line.

9. 9. The memory system of claim 8, wherein the memory controller comprises a digital signal processor configured to count the number P after the verify voltage is applied to at least a portion of the memory cells in the unit.

10. Each unit of the one or more units includes one or more pages, the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is Ｎ 6. The memory system of claim 5, wherein the average number of memory cells in the one or more selected pages that are in one or more of the programmed states of states.

11. 2. The memory system of claim 1, wherein the controller comprises a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

12. 12. The memory system of claim 11, wherein the memory controller comprises a first register configured to store the first mapping table.

13. The memory controller includes a digital signal processor configured to calculate a numerical difference ΔP between the number P and a default number P′, the default number P′ being equal to or smaller than the two numbers P and P′ after a program operation is completed. Ｎ 2. The memory system of claim 1, wherein the number of memory cells in the unit that are in the one or more programmed states of states.

14. 14. The memory system of claim 13, wherein the memory controller comprises a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

15. 15. The memory system of claim 14, wherein the memory controller comprises a second register configured to store the second mapping table.

16. 15. The memory system of claim 14, wherein the memory controller comprises a third register configured to store the default number P'.

17. 17. The memory system of claim 11, wherein the processor is configured to adjust the offset for memory cells in the unit based on default threshold voltages of the memory cells.

18. 20. The memory system of claim 17, wherein the adjusted offsets of the memory cells in the unit are positively correlated with the default threshold voltages of the memory cells.

19. 15. The memory system of claim 11 or 14, wherein the memory controller comprises a fourth register configured to store the offset obtained by the processor.

20. 20. The memory system of claim 19, wherein the processor is configured to obtain the offset from a fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

21. A memory controller coupled to a memory device having an array of memory cells, each memory cell storing two memory cells corresponding to one N-bit data. Ｎ a first state, N being an integer greater than one, the array of memory cells being divided into one or more units, the memory controller being coupled to the memory device, When the command is executed, From the memory device, Ｎ obtaining a number P of memory cells in one of the plurality of units that are in one or more programmed states; Calculating a compensated read voltage having an offset from a default read voltage based on the number P; providing the compensated read voltage to the memory device for a read operation performed on a selected one of the memory cells in a unit of the plurality of units; It is configured as follows: Memory controller.

22. 22. The memory controller of claim 21, wherein the offset is associated with the unit and is updated after the number P of memory cells in the unit is changed.

23. 23. The memory controller of claim 22, wherein the offset is updated periodically.

24. 24. The memory controller of claim 23, wherein an update period is less than or equal to a minimum interval between two adjacent programming operations performed on the unit.

25. 22. The memory controller of claim 21, further comprising a processor configured to control the memory device to count the number P of memory cells in the unit by performing a verify read operation.

26. The processor, 2 Ｎ Selecting one or more of the programmed states of the states; determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states; It is structured as follows: the verify voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected state or states; 26. The memory controller of claim 25.

27. 2 Ｎ the number of the selected one or more programmed states is one, The minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is Ｎ higher than the threshold voltage of a memory cell corresponding to a non-selected state among the states, 27. The memory controller of claim 26.

28. 28. The memory controller of claim 27, wherein the memory controller comprises a digital signal processor configured to count the number P after the verify voltage is applied to at least a portion of the memory cells in the unit.

29. Each unit of the one or more units includes one or more pages, the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is Ｎ 26. The memory system of claim 25, wherein the average number of memory cells in the one or more selected pages that are in one or more of the programmed states of states.

30. 22. The memory controller of claim 21, comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

31. 31. The memory controller of claim 30, wherein the memory controller comprises a first register configured to store the first mapping table.

32. The memory controller includes a digital signal processor configured to calculate a numerical difference ΔP between the number P and a default number P′, the default number P′ being equal to or smaller than the two numbers P and P′ after a program operation is completed. Ｎ 22. The memory controller of claim 21, wherein the number of memory cells in the unit that are in the one or more programmed ones of states.

33. 33. The memory controller of claim 32, comprising a processor configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

34. 34. The memory controller of claim 33, wherein the memory controller comprises a second register configured to store the second mapping table.

35. 34. The memory controller of claim 33, wherein the memory controller comprises a third register configured to store the default number P'.

36. 34. The memory controller of claim 30 or claim 33, wherein the processor is configured to adjust the offset for memory cells in the unit based on default threshold voltages of the memory cells.

37. 37. The memory controller of claim 36, wherein the adjusted offsets of the memory cells in the unit are positively correlated to the default threshold voltages of the memory cells.

38. 34. The memory controller of claim 30 or claim 33, wherein the memory controller comprises a fourth register configured to store the offset obtained by the processor.

39. 39. The memory controller of claim 38, wherein the processor is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

40. 1. A memory device comprising: An array of memory cells, each of which stores two bits of data corresponding to one N-bit data. Ｎ an array of memory cells configured to be set to one of states, N being an integer greater than 1, the array of memory cells being divided into one or more units; a peripheral circuit coupled to the memory cell and configured to perform a read operation on a selected one of the memory cells in a unit of the plurality of units using a compensated read voltage having an offset from a default read voltage; Equipped with The offset is Ｎ correlated with the number P of memory cells in the unit that are in one or more of the programmed states; Memory device.

41. 41. The memory device of claim 40, wherein the offset is associated with the unit and is updated after a number P of memory cells in the unit changes.

42. 42. The memory device of claim 41, wherein the offset is updated periodically.

43. 43. The memory device of claim 42, wherein an update period is less than or equal to a minimum interval between two adjacent programming operations performed on the unit.

44. 41. The memory device of claim 40, wherein the number P is obtained through a verify read operation configured to count the number P of memory cells in the unit.

45. The peripheral circuit is 2 Ｎ Selecting one or more of the programmed states of the states; determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states; It is structured as follows: the verify voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected state or states; 45. The memory device of claim 44.

46. 2 Ｎ the number of the selected one or more programmed states is one, The minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is Ｎ higher than the threshold voltage of a memory cell corresponding to a non-selected state among the states, 46. ​​The memory device of claim 45.

47. 46. ​​The memory device of claim 45, wherein the peripheral circuitry comprises a word line driver configured to apply the verify voltage to at least some of the memory cells in the unit via a word line.

48. 48. The memory device of claim 47, wherein the peripheral circuitry comprises a calculator configured to calculate the number P after the verify voltage is applied to at least a portion of the memory cells in the unit.

49. Each unit of the one or more units includes one or more pages, the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is Ｎ an average number of memory cells in the one or more selected pages that are in one or more of the programmed states; 45. The memory device of claim 44.

50. 41. The memory device of claim 40, wherein the peripheral circuitry comprises control logic configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number P and a first mapping table between the offset and the number P.

51. 51. The memory device of claim 50, wherein the peripheral circuitry comprises a first register configured to store the first mapping table.

52. The peripheral circuitry includes a calculator configured to calculate a numerical difference ΔP between the number P and a default number P′, the default number P′ being equal to or smaller than the two numbers P and P′ after a program operation is completed. Ｎ 51. The memory device of claim 50, wherein the number of memory cells in the unit that are in the one or more programmed ones of states.

53. 53. The memory device of claim 52, wherein the control logic is configured to obtain the offset through a lookup operation by looking up the offset corresponding to the number difference ΔP and a second mapping table between the offset and the number difference ΔP.

54. 54. The memory device of claim 53, wherein the peripheral circuitry comprises a second register configured to store the second mapping table.

55. 54. The memory device of claim 53, wherein the peripheral circuitry comprises a third register configured to store the default number P'.

56. 54. The memory device of claim 50 or claim 53, wherein the control logic is configured to adjust the offset, for memory cells in the unit, based on default threshold voltages of the memory cells.

57. 57. The memory device of claim 56, wherein the adjusted offsets of the memory cells in the unit are positively correlated to the default threshold voltages of the memory cells.

58. 54. A memory device according to claim 50 or claim 53, wherein the peripheral circuitry comprises a fourth register configured to store an offset obtained by the control logic.

59. 60. The memory device of claim 58, wherein the control logic is configured to obtain the offset from the fourth register and calculate the compensated read voltage by adding the offset to the default read voltage.

60. 2 corresponding to one N-bit data Ｎ 16. A method for reading a memory device comprising an array of memory cells configured to be set to one of a set of states, N being an integer greater than 1, the array of memory cells being divided into one or more units, the method comprising: 2 Ｎ obtaining a number P of memory cells in the unit that are in one or more of the programmed states; calculating a compensated read voltage having an offset from a default read voltage; performing a read operation on selected ones of the memory cells in the unit using the compensated read voltage; A method comprising:

61. 61. The method of claim 60, further comprising: after calculating the compensated read voltage, updating the offset after a number P of memory cells in the unit is changed.

62. 62. The method of claim 61 , wherein the offset is updated periodically.

63. 63. The method of claim 62, wherein an update period is less than or equal to a minimum interval between two adjacent programming operations performed on the unit.

64. 61. The method of claim 60, wherein the number P of memory cells in the unit is calculated by performing a verify read operation.

65. said step of performing a verify read operation further comprising: 2 Ｎ selecting one or more programmed states of the states; determining a verify voltage to be used in the verify read operation based on a default range of threshold voltages corresponding to the selected one or more states; Including, the verify voltage is equal to a minimum threshold voltage of the default range of threshold voltages corresponding to the selected state or states; 65. The method of claim 64.

66. 2 Ｎ the number of the selected one or more programmed states is one, The minimum threshold voltage of the default range of threshold voltages corresponding to the selected state is Ｎ higher than the threshold voltage of a memory cell corresponding to a non-selected state among the states, 66. The method of claim 65.

67. Each unit of the one or more units includes one or more pages, the verify read operation is performed on one or more selected pages of the one or more pages, and the number P is Ｎ 65. The method of claim 64, wherein the average number of memory cells in the one or more selected pages that are in one or more of the programmed states.

68. 67. The method of claim 66, wherein calculating the compensated read voltage with the offset comprises: looking up the offset corresponding to the number P, and a first mapping table between the offset and the number P.

69. 69. The method of claim 68, wherein the first mapping table is stored in a first register.

70. The step of calculating the compensated read voltage having the offset includes the step of calculating a difference ΔP between the number P and a default number P′, and the default number P′ is equal to or smaller than the difference ΔP between the number P and a default number P′ after a program operation is completed. Ｎ 67. The method of claim 66, wherein the number of memory cells in the unit that are in the one or more programmed ones of states.

71. 71. The method of claim 70, wherein calculating the compensated read voltage with the offset further comprises: looking up the offset corresponding to the number difference ΔP, and a second mapping table between the offset and the number difference ΔP.

72. 72. The method of claim 71, wherein the second mapping table is stored in a second register.

73. 72. The method of claim 71, wherein the default number P' is stored in a third register.

74. 72. The method of claim 67 or claim 71, further comprising, after calculating the compensated read voltage having the offset, adjusting the offset based on a default threshold voltage of the memory cell.

75. 75. The method of claim 74, wherein the adjusted offsets of the memory cells in the unit are positively correlated with the default threshold voltages of the memory cells.

76. 75. The method of claim 74, further comprising storing the adjusted offset in a fourth register.

77. determining the compensated read voltage, obtaining the offset from the fourth register; calculating the compensated read voltage by adding the offset to the default read voltage; 77. The method of claim 76, comprising:

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