Thermal sensors for integrated circuits

Abstract

A thermal sensor for an integrated circuit includes a proportional to absolute temperature (PTAT) circuit including an n-type MOS transistor and providing a first voltage, and a voltage generator circuit including a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and / or the second voltage. In another aspect, the integrated circuit has a power routing mechanism that provides a power supply core voltage (VDDCORE) to operate functional circuits on the integrated circuit. One or more local thermal sensors are disposed on the integrated circuit. Each local thermal sensor includes a PTAT circuit having a MOS transistor and uses the power supply core voltage to generate a temperature dependent voltage that varies independently of variations in the power supply core voltage.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 303,674, entitled "Local Voltage Thermal Sensor," filed on January 27, 2022, and U.S. Patent Application No. 17,750,637, entitled "Thermal Sensor for Integrated Circuit," filed on May 23, 2022, the contents of both of which are incorporated herein by reference.

[0002] The present invention relates to the field of thermal sensors for integrated circuits. [Background technology]

[0003]

[0003] An integrated circuit (IC) can include analog and digital electronic circuits on a flat semiconductor substrate such as a silicon wafer. Modern electronic circuit designs using ICs are low-cost and high-performance by using photolithography techniques to print tiny transistors on the substrate, creating complex circuits of billions of transistors in an extremely small area. ICs are produced on assembly lines in factories called foundries that commercialize the production of ICs such as complementary metal-oxide-semiconductor (CMOS) ICs. Digital ICs contain billions of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), which are arranged in functional and / or logic units on the wafer. Data paths interconnecting the functional units transfer data values ​​between the functional units. Each unit has a power supply, associated on power, off power, standby power, etc.

[0004]

[0004] Digital ICs implement many CMOS-based sub-circuits, and each sub-circuit has an associated OFF configuration. During the OFF configuration, power may still be consumed by the sub-circuit devices, for example, often referred to as static power consumption. The static (or leakage) power of all the sub-circuits in an IC is summed up and can be referred to as the total IC static power.

[0005]

[0005] In digital ICs, sub-threshold leakage can be considered as a parasitic leakage in an ideal no current state. Conversely, in micro-power analog circuits, weak inversion is an efficient region of operation and sub-threshold is a useful transistor mode around which circuit functions can be designed. It is therefore desirable to measure or track leakage current and other operating characteristics such as temperature of functional units or ICs.

[0006]

[0006] In a semiconductor IC, it is desirable to sense the local temperature at various locations within the IC. For this purpose, a temperature sensor may be embedded in the IC. The temperature sensor can be used to protect the IC from overheating. For example, the temperature sensor can shut down the IC if the temperature exceeds a threshold. It is therefore desirable for the temperature sensor to be as accurate and reliable as possible. Digital Thermal Sensors (DTS) are commonly used and are usually based on diodes. The power requirements of a DTS are high and to provide power to it, this typically requires a V CC A power supply. Therefore, the IC has a V CC A dedicated conductive path is required from the A pin to the DTS, so implementing multiple DTSs in this manner is complex, expensive, and power consuming.

[0007]

[0007] PCT International Publication No. WO2021 / 019539A1, assigned to the assignee of the present application, proposes the use of multiple spaced apart ring oscillator (ROSC) circuits, each of which operates at a frequency that varies with temperature. One ROSC circuit is in close proximity to a semiconductor (diode-based) temperature sensor, and the oscillation frequency of this ROSC circuit is used to determine the temperature of the distal ROSC circuit. Nevertheless, at least one diode-based temperature sensor is required for accuracy.

[0008]

[0008] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative and not exhaustive. Other limitations of the related art will become apparent to those of ordinary skill in the art upon reading the specification and studying the drawings. Summary of the Invention

[0009]

[0009] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods that are intended to be illustrative and explanatory rather than limiting in scope.

[0010] In one aspect, a thermal sensor for an integrated circuit is provided. The thermal sensor includes a proportional to absolute temperature (PTAT) circuit including two series-connected n-type MOS transistors configured to receive a first current source output and provide a first voltage, a voltage generator circuit including a p-type MOS transistor configured to provide a second voltage, a reference voltage generation circuit configured to generate a reference voltage based on the first voltage and the second voltage, and an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first voltage and / or the second voltage. Optional features related to this aspect are detailed below and may be provided in any combination.

[0011] In an embodiment, the reference voltage generating circuit includes a first voltage-to-current circuit configured to convert a first voltage to a first current, and a second voltage-to-current circuit configured to convert a second voltage to a second current. The reference voltage generating circuit is advantageously configured to generate a reference voltage based on a combination of the first current and the second current.

[0012]

[0012] In an embodiment, each of the first and second voltage-current circuits includes an amplifier circuit configured to receive an input voltage (which may be, for example, a first or second voltage) at a first input and provide an output voltage, and a follower circuit including a follower current source (source or drain) controlled by the output voltage of the amplifier circuit and providing a follower current to a resistor coupled to ground. The voltage across the resistor can provide the follower output voltage. For example, the follower current source may include a MOS transistor having a first signal terminal coupled to a power supply voltage, a gate configured to receive an output voltage from the amplifier circuit, and a second signal terminal configured to provide the follower output voltage. The second signal terminal is connected to ground via a resistor (as at least a part of the resistor). Advantageously, the amplifier circuit is configured to receive the follower output voltage at a second input.

[0013]

[0013] In an embodiment, the reference voltage generating circuit further includes a first combiner current source (e.g., including a first combiner transistor having a first signal terminal coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a second signal terminal coupled to the common point) controlled by the output voltage of the amplifier circuit (of the first voltage-current circuit) and providing a first combiner current to the common point, a second combiner current source (e.g., including a second combiner transistor having a first signal terminal coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the second voltage-current circuit, and a second signal terminal coupled to the common point) controlled by the output voltage of the amplifier circuit (of the second voltage-current circuit) and providing a second combiner current to the common point, and a common resistor connecting the common point to ground. The reference voltage is output at the common point. Optionally, the width of the first combiner transistor is different from the width of the second combiner transistor.

[0014]

[0014] In an embodiment, the PTAT circuit further includes a first current source controlled by the output voltage of the amplifier circuit of the first voltage-current circuit, the first current source configured to provide the first current source output to the series-connected n-type MOS transistor. Additionally or alternatively, the PTAT circuit further includes a first p-type current source transistor having a source connected to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide the first current source output to the series-connected n-type MOS transistor. Additionally or alternatively, the voltage generator circuit further includes a second current source controlled by the output voltage of the amplifier circuit (optionally of the first voltage-current circuit), the second current source configured to provide the second current source output to the p-type MOS transistor of the voltage generator circuit. Additionally or alternatively, the voltage generator circuit further includes a second p-type current source transistor having a source connected to the power supply voltage, a gate coupled to the gate of the first p-type current source transistor and / or the gate of the MOS transistor of the first voltage-to-current circuit, and a drain configured to provide a second current source output to the p-type MOS transistor.

[0015]

[0015] In an embodiment, the thermal sensor further includes a sense voltage generating circuit including a sense voltage current source controlled by an output of the amplifier circuit (of the first or second voltage-current circuit) and configured to provide a sense voltage current to the selectable resistor. The sense voltage current source may include a MOS transistor having a first signal terminal coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit or the gate of the MOS transistor of the second voltage-current circuit, and a second signal terminal connected to ground through the selectable resistor. The voltage across the selectable resistor (at the second signal terminal) is provided as the output sense voltage.

[0016]

[0016] In an embodiment, the series-connected n-type MOS transistors of the PTAT circuit include a first n-type MOS transistor having a source connected to ground and a drain connected to a common point, and a second n-type MOS transistor. The second n-type MOS transistor has a source connected to the common point and a drain connected to the gate of the first n-type MOS transistor and the gate of the second n-type MOS transistor. The drain of the second n-type MOS transistor is further configured to receive the first current source output, and the first voltage is provided to the common point. Additionally or alternatively, the p-type MOS transistor of the voltage generator circuit has a drain and a gate connected to ground and a source configured to receive the second current source output and provide a second voltage.

[0017] In an embodiment, the at least one thermal output signal includes a thermal trip signal, and the output circuit includes a thermal trip circuit configured to generate the thermal trip signal by comparing a threshold voltage with a sense voltage based on the first voltage and / or the second voltage. The threshold voltage is generated from a reference voltage. Optionally, the threshold voltage is generated by applying the reference voltage to a resistive divider, the resistive divider including a selectable resistor to allow selection of the threshold voltage.

[0018] In an embodiment, the at least one thermal output signal includes a digital thermal signal, and the output circuit includes an analog-to-digital converter configured to convert a sensed voltage based on the first voltage and / or the second voltage into the digital thermal signal. The analog-to-digital converter generates the digital thermal signal using a reference voltage. Optionally, the analog-to-digital converter includes a sigma-delta modulator.

[0019]

[0019] In an embodiment, the thermal sensor further comprises a calibration circuit. The calibration circuit includes a calibration voltage generation circuit including a resistive voltage divider, to which the power supply voltage is applied and whose resistance is selectable to generate a configurable calibration voltage. The calibration circuit also includes a switching circuit. The switching circuit is advantageously configured to selectively apply, in a first configuration, a reference voltage at the analog signal input of the analog-digital converter and a calibration voltage at the reference input of the analog-digital converter, in a second configuration, a sense voltage at the analog signal input of the analog-digital converter and a calibration voltage at the reference input of the analog-digital converter, and in a third configuration, a sense voltage at the analog signal input of the analog-digital converter and a reference voltage at the reference input of the analog-digital converter.

[0020] In another aspect (which may be combined with any other aspect disclosed herein), an integrated circuit is provided that includes a power routing mechanism that provides a power supply core voltage (VDDcore) for operating functional circuits on the integrated circuit, and one or more local thermal sensors disposed on the integrated circuit, each local thermal sensor including a proportional to absolute temperature (PTAT) circuit including MOS transistors and configured to generate at least one temperature dependent voltage using the power supply core voltage that varies independently of variations in the power supply core voltage.

[0021]

[0021] Features of other aspects may be optionally applied to this aspect. For example, in an embodiment, each of the one or more local thermal sensors includes a PTAT circuit configured to generate a first temperature dependent voltage of the at least one temperature dependent voltage using n-type MOS transistors, a voltage generator circuit configured to generate a second temperature dependent voltage of the at least one temperature dependent voltage using p-type MOS transistors, and a reference voltage generation circuit configured to generate a reference voltage independent of variations in temperature and / or power supply core voltage using the first and second temperature dependent voltages.

[0022]

[0022] In another aspect (which may be combined with other aspects), a method of operating a thermal sensor on an integrated circuit is provided. The method includes obtaining a first voltage using two series-connected n-type MOS transistors receiving a first current source output, obtaining a second voltage using a p-type MOS transistor, generating a reference voltage using the first voltage and the second voltage, and generating at least one thermal output signal based on the reference voltage together with the first voltage and / or the second voltage. Features of the other aspects may be optionally applied to this aspect. Optional features related to this aspect are detailed below and may be provided in any combination.

[0023]

[0023] In an embodiment, the step of generating a reference voltage using the first voltage and the second voltage includes converting the first voltage to a first current using a first MOS transistor mechanism, converting the second voltage to a second current using a second MOS transistor mechanism, and combining the first current and the second current. The reference voltage is generated by passing the combined first and second currents through a resistor. Advantageously, the method further includes calibrating the reference voltage by configuring one or more of the first MOS transistor mechanism, the second MOS transistor mechanism, and the resistor.

[0024]

[0024] In an embodiment, the method further comprises generating a sense voltage by converting the first voltage or the second voltage into a sense current using a MOS transistor arrangement. The sense voltage is generated by passing the sense current through a resistor. The method further comprises calibrating the sense voltage by configuring the resistor. Advantageously, the thermal output signal is generated based on the sense voltage.

[0025]

[0025] In an embodiment, the step of generating at least one thermal output signal includes applying a sensed voltage based on the first voltage or the second voltage to an analog-to-digital converter to generate a digital thermal signal. And the method may further include calibrating the thermal output signal by generating a calibration voltage by applying a power supply voltage to a resistive divider having a selectable resistance and selecting the resistance according to the power supply voltage, providing a reference voltage at an analog signal input of the analog-to-digital converter and the calibration voltage at a reference input of the analog-to-digital converter, reading the thermal output signal as a first calibrated output, providing a sensed voltage at an analog signal input of the analog-to-digital converter and the calibration voltage at a reference input of the analog-to-digital converter, reading the thermal output signal as a second calibrated output, and determining a calibration value based on the first and second calibrated outputs.

[0026] In an embodiment, the step of generating at least one thermal output signal includes generating a thermal trip signal by comparing a threshold voltage with a sense voltage based on the first voltage and / or the second voltage. The threshold voltage is generated by applying a reference voltage to a resistive divider having a selectable resistance. Also, the method may further include calibrating the thermal trip signal by setting the selectable resistance.

[0027]

[0027] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by study of the following detailed description and with reference to the drawings. [Brief description of the drawings]

[0028]

[0028] Exemplary embodiments are shown in the reference drawings. Dimensions of components and features shown in the drawings are generally chosen for convenience and clarity of presentation and are not necessarily drawn to scale. The same reference numbers are used wherever the same features are shown. The drawings are listed below.

[0029] [Figure 1]

[0029] FIG. 1 shows a circuit diagram of an existing diode-based temperature sensor for an IC. [Diagram 2]

[0030] FIG. 1 shows a circuit diagram of an existing diode-based reference voltage generator for an IC. [Diagram 3]

[0031] 1 shows a schematic block diagram of a local voltage temperature sensor mechanism. [Figure 4A]

[0032] A circuit for obtaining a proportional-to-absolute-temperature (PTAT) voltage is shown. [Figure 4B]

[0033] A circuit diagram for generating a PTAT current in an IC is shown using the circuit of Figure 4A. [Diagram 5]

[0034] 4C shows a circuit diagram based on the circuit of FIG. 4B illustrating providing another voltage based on the PTAT voltage. [Figure 6]

[0035] According to the block diagram of FIG. 3, a circuit diagram for generating a reference voltage that can be independent of temperature is shown. [Figure 7]

[0036] According to the block diagram of FIG. 3, a schematic circuit for generating a thermal trip signal is shown. [Figure 8]

[0037] 1 shows a schematic diagram of an auxiliary circuit for calibration of the generated reference voltage; [Figure 9]

[0038] 1 shows an exemplary plot of PTAT voltage versus temperature after calibration. [Figure 10]

[0039] 1 shows a schematic block diagram of a local voltage temperature sensor mechanism according to an alternative design. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030]

[0040] Disclosed herein is a thermal sensor for a semiconductor IC, a semiconductor IC including a local thermal sensor, and a method for operating the same.

[0031]

[0041] However, for comparison, we first refer to FIG. 1, which shows a circuit diagram of an existing conventional diode-based temperature sensor for an IC. Two diode arrays are implemented by PNP transistors Q1 and Q2. This is connected to the core power supply voltage V DDCORE Unique V generated as a multiple of DD power supply voltage. This circuit can be used for a wide range of core power supply voltages. Calibration is required to compensate for diode ideality factor, amplifier offset, and random effects. The PTAT current is given by: According to the Shockley diode equation, n represents the transistor size ratio and kT / q is the thermal voltage of the diode (PN junction) (V T ) is shown.

[0032]

number

[0033] where k is the Boltzmann constant, T is the temperature, and q is the electron charge.

[0034]

[0042] The rate of change of VBE (base-emitter voltage) with respect to temperature (δVBE / δT) is -1.286mV / ℃. Therefore, VBE or I PTAT can be used to sense the temperature. This is called remote diode sensing.

[0035]

[0043] An analog-to-digital converter (ADC) converts an analog current (I PTAT) or voltage (e.g., VBE or ΔVBE) into a digital reading. A temperature indication can be generated directly from the VBE, which is used to compare with a threshold to identify a catastrophic condition. The threshold may require calibration. The ADC reading is referenced to a temperature-independent reference voltage V REF Refers to.

[0036]

[0044] Referring now to Figure 2, a schematic diagram of an existing diode-based reference voltage generator for an IC is shown. The output current I O is given by the following equation. The first term (ΔVBE / R0) increases with increasing temperature, and the second term (VBE / R1) decreases with increasing temperature. Therefore, by carefully selecting the resistor values, I O and the resulting VREF(I O ·R3) can be made temperature invariant.

[0037]

number

[0038]

[0045] Remote diode sensing is sensitive to power supply voltage drops in the reference voltage generation and / or distribution. The number of remote diode sensors is usually limited by the ADC input stage leakage current. The accuracy of the sensors without calibration is typically stated to be ±7°C, but with calibration it can be as low as ±1°C. The size of the sensors is also large (typically 8000 to 30000 μm 2 ).

[0039]

[0046] As briefly mentioned above, disclosed herein is a thermal sensor for a semiconductor IC, a semiconductor IC including a local thermal sensor, and a method for operating the same. The thermal sensor is based on a MOS-based proportional to absolute temperature (PTAT) circuit (NMOS-based) and / or a voltage generator (PMOS-based). Furthermore, the sensor uses a temperature independent reference voltage (VREF) generator, in particular as a reference voltage for a sigma-delta (modulator) analog-to-digital converter (ADC) and / or to generate a threshold voltage for a thermal trip circuit. The PTAT circuit includes two series-connected NMOS transistors arranged to receive a current source output and provide a temperature dependent voltage that can be converted to a PTAT current. The size of the sensor is therefore small. Thus, multiple local voltage temperature sensors can be provided. Advantageously, the thermal sensor output can be independent of power supply voltage variations and therefore can be independent of the core power supply voltage V DDCORE The thermal sensor can be powered by a 32-bit 100-V power supply. This simplifies the power supply routing compared to existing diode-based sensors. The power supply advantageously supports multiple power performance modes, e.g., high voltage / high frequency and low voltage / low frequency. Since IC temperature changes over time, a thermal sensor can be used to determine the power performance mode (voltage / frequency pair) based on the current measured temperature.

[0040]

[0047] Providing a stable thermal sensor output using a PTAT circuit advantageously uses a reference voltage that is independent of variations in the power supply voltage. This can be provided using two complementary temperature dependent voltage generator circuits: one based on n-type MOSFETs (NMOS) and providing an output signal with a positive correlation to temperature, and the other based on p-type MOSFETs (PMOS) and providing an output signal with a negative correlation to temperature. The output signal of each circuit is typically a current derived from the generated voltage. The two output signals can be used together to generate a stable reference voltage.

[0041]

[0048] Generally, and according to one aspect, a power supply core voltage (VDD CORE) can be considered. The power supply core voltage is typically used to provide circuitry for generating functional output of the IC, such as CPU / GPU functionality. One or more local thermal sensors are disposed on the integrated circuit, each of which includes a proportional to absolute temperature (PTAT) circuit including MOS transistors and configured to use the power supply core voltage to generate at least one temperature dependent voltage that varies independently of variations in the power supply core voltage. The use of a MOS-based PTAT circuit allows for the provision of a local voltage temperature sensor with small size but high accuracy (compared to diode-based sensors). The at least one temperature dependent voltage can be used to select an operating mode of the power supply circuitry of the IC. This aspect can be combined with any other aspect disclosed herein or implemented as a method, such as a method of providing, manufacturing, and / or operating such an IC.

[0042]

[0049] Advantageously, each of the one or more local thermal sensors includes a PTAT circuit configured to generate a first temperature dependent voltage (typically a voltage having a positive correlation with temperature) of the at least one temperature dependent voltage using n-type MOS transistors, a voltage generator circuit configured to generate a second temperature dependent voltage (typically a voltage having a negative correlation with temperature) of the at least one temperature dependent voltage using p-type MOS transistors, and a reference voltage generation circuit configured to generate a reference voltage independent of temperature and / or power supply core voltage variations using the first and second temperature dependent voltages. By matching the magnitude of the correlation between the first voltage and temperature to the magnitude of the correlation between the second voltage and temperature (the two correlations have opposite signs), the reference voltage can be independent of temperature variations. The first voltage is also advantageously independent of the power supply core voltage. By adjusting the second voltage generation, the reference voltage can be set to be independent of power supply core voltage variations (i.e., a high Power Supply Rejection Ratio (PSRR)).

[0043]

[0050] Also in general terms, according to another aspect, there is provided a thermal sensor for an integrated circuit comprising: a proportional to absolute temperature (PTAT) circuit including two series-connected n-type MOS transistors configured to receive a first current source output and provide a first voltage (e.g., of a type known to provide a PTAT signal), a voltage generator circuit including a p-type MOS transistor configured to provide a second voltage, a reference voltage generation circuit configured to generate a reference voltage based on the first voltage and the second voltage, and an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first voltage and / or the second voltage.

[0044]

[0051] According to another (corresponding) aspect, a method for operating a thermal sensor on an integrated circuit can be considered, the method including obtaining a first voltage using two series-connected n-type MOS transistors receiving a first current source output, obtaining a second voltage using a p-type MOS transistor, generating a reference voltage using the first and second voltages, and generating at least one thermal output signal based on the reference voltage together with the first and / or second voltages.

[0045]

[0052] These thermal sensor and method aspects may be combined with any other aspects disclosed herein and have additional optional features (which may also be applicable to other aspects), which are discussed further below after discussing implementation details according to certain embodiments.

[0046]

[0053] Reference is now made to Figure 3, which illustrates a schematic block diagram of a thermal sensor (also referred to herein as a Local Voltage Temperature Sensor "LVTS") according to the present disclosure. The sensor comprises an NMOS PTAT circuit 10 for generating a first temperature dependent voltage 15, a PMOS circuit 20 (voltage generator circuit) for generating a second temperature dependent voltage 25, a first voltage-current (V / I) circuit 31 for generating a first (PTAT) current 33 from the first temperature dependent voltage 15, a second voltage-current (V / I) circuit 32 for generating a second current 34 from the second temperature dependent voltage 25, a reference voltage generation circuit 40 for generating a (temperature independent) reference voltage 45 from the first (PTAT) current 33 and the second current 34, and an output signal generation circuit (output circuit) 50. The reference voltage generating circuit 40 advantageously sums the first (PTAT) current 33 and the second current 34 to generate a high power supply rejection ratio (PSRR) reference voltage 45. The output signal generating circuit 50 receives as inputs a thermal sense voltage 44 based on either the first temperature dependent voltage 15 or the second temperature dependent voltage 25 (selectable using a multiplexer 43) and a reference voltage 45. As shown, the output signal generating circuit 50 also receives an external reference voltage (EXT VREF) 47 generated by an external reference voltage generating circuit 46 (and used to calibrate the thermal sensor) and the second temperature dependent voltage 25. In other implementations, the thermal sense voltage may be based on a combination of the first temperature dependent voltage 15 and the second temperature dependent voltage 25. The output signal generating circuit 50 generates a digital thermal signal output 66 (e.g., a temperature measurement) and optionally also generates a thermal trip signal output 77 (each of which may be generally referred to as a thermal output signal). Calibration data can be acquired during test and fused inside the IC to aid in generating the output signal.

[0047]

[0054] Exemplary implementations of NMOS PTAT circuit 10, PMOS circuit 20, V / I circuit 31 / 32, and reference voltage generation circuit 40 are discussed further below. NMOS PTAT circuit 10 and PMOS circuit 20 each provide a linear output voltage over a wide range of temperatures (e.g., −40° C. to 125° C.). First temperature dependent voltage 15 has a positive correlation with temperature, and second temperature dependent voltage 25 has a negative correlation with temperature.

[0048]

[0055] 3, the output signal generating circuit 50 comprises a digital thermal signal output circuit 60 that generates a digital thermal signal output 66, and optionally a catastrophic thermal trip circuit 70 that generates a thermal trip signal output 77. The output signal generating circuit 50 further comprises a first selector 51 that selects between the external reference voltage (EXT VREF) 47 and the thermal sensing voltage 44, and a second selector 52 that selects between the external reference voltage (EXT VREF) 47 and the (temperature independent) reference voltage 45.

[0049]

[0056] The digital thermal signal output circuit 60 includes a selectable (optional) unity gain buffer (UGB) 61, a measurement bypass selector 62, a measurement selector 63, a sigma-delta (ΣΔ) ADC 64, and a register (flip-flop) 65. The UGB 61 receives the output of the first selector 51, and the output of the UGB and the output of the first selector 51 are provided as separate inputs to the measurement bypass selector 62. The output of the measurement bypass selector 62 and the VDD / 4 signal are provided as separate inputs to the measurement selector 63, and the output of the measurement selector 63 is provided as a sampling input to the ADC 64. The measurement selector 63 selects between a temperature measurement and a voltage measurement. If the output of the measurement bypass selector 62 is provided to the ADC 64, a temperature measurement is performed. If the VDD / 4 signal is provided to the ADC 64, the output is a voltage measurement. The VDD signal is divided (by 4 in this example) before being provided to the ADC 64. This is because the VDD voltage value is higher than the reference voltage (VREF).

[0050]

[0057] The ADC 64 also receives the output of the second selector 52 as a reference voltage input and a clock signal 67 as a clock input. The output of the ADC 64 is provided to a register 65 which also receives the clock signal 67 as a clock input. The output of the register 65 is provided as a digital thermal signal (output) 66. The sigma-delta ADC 60 converts the value of its input voltage to a digital output which is sampled and accumulated in the LVTS control logic (not shown), optionally resulting in a 12-bit digital output.

[0051]

[0058] The catastrophic thermal trip circuit 70 includes a UGB 71, a reference bypass selector 72, an adjustable resistive divider 74 that generates a threshold signal (VCAT) 75 set by a configuration signal (cat_threshold[7:0]) 73, and a comparator (CMP) 76 that compares the second temperature dependent voltage 25 (alternatively, the thermal sensing voltage 44 can be used) with the threshold signal 75 to generate a thermal trip signal output 77.

[0052]

[0059] The following table details optional parameter specifications for the LVTS based on our designs and simulations.

[0053] [Table 1]

[0054]

[0060] In practice, it should be understood that the LVTS can certainly operate over a wider voltage and / or temperature range, either without modification to the configuration or with modifications that would be readily understood by one of ordinary skill in the art.

[0055]

[0061] Furthermore, the area of ​​the LVTS is actually 2000 to 10000 μm 2 (For example, 4000 μm 2 Below, 6000μm 2 Below, 8000μm 2 Below, 10000μm 2This is a significant area savings compared to typical diode-based thermal sensors, which typically occupy areas of tens of thousands of square microns.

[0056]

[0062] With respect to temperature measurement accuracy, this may actually be within ±0.8°C, and more specifically within ±0.6°C, ±0.4°C, ±0.2°C, or ±0.1°C. Similarly, catastrophic trip accuracy may actually be within ±2.0°C, and more specifically within ±1.7°C, ±1.5°C, ±1.3°C, or ±1.0°C. It should be noted that there is a trade-off between speed and accuracy; that is, temperature measurement (e.g., using the digital thermal signal output circuit 60) is slower (because an ADC is used) but more accurate, whereas catastrophic tripping may be faster but less accurate (because an ADC is not used and therefore reaction to a catastrophic temperature may be faster).

[0057]

[0063] Concerning the sampling rate of the LVTS, the listed frequency range of 5 MHz to 50 MHz is given only as an example of frequencies that, on the one hand, are significantly slower with respect to the IC's clock frequency (which may be in the GHz range) and therefore consume less power, and, on the other hand, are fast enough to provide a reasonable number of samples (temperature measurements) per second in the most common situations. IC manufacturers may of course choose to operate the LVTS at frequencies beyond the range listed in the table (for example frequencies in the range of 1 MHz to 1 GHz) to suit other situations or needs.

[0058]

[0064] Specific implementations will be considered further below, but generalized meanings will be mentioned further below.

[0059] PTAT circuit

[0065] Reference is now made to FIG. 4A, which shows a circuit for obtaining the PTAT voltage. This circuit is known, for example, from "A low-voltage CMOS bandgap reference" (Vittoz et al, IEEE Journal of Solid-State Circuits vol. 14.3 (1979), pp. 573-579). It may be used, for example, as part of an LVTS as shown in FIG. 3, as will be discussed further below. It is connected to a current source (I O ) 100 and a MOS transistor arrangement 110. The MOS transistor arrangement 110 includes two series-connected n-type MOS (NMOS) transistors with a common gate connection. One end of the transistor arrangement 110 (in the configuration shown this is the source of a first transistor 111 of size W1) is connected to ground and the other end of the transistor arrangement 110 (in the configuration shown this is the drain of a second transistor 112 of size W2) is connected to the current source 100 and the common gate connection.

[0060]

[0066] The MOS transistors 111, 112 are assumed to be operating in subthreshold mode. They generate a temperature dependent output voltage, denoted as Vn(T), at the midpoint between the series connected transistors, where the drain of one transistor is connected to the source of the other. The temperature dependent output voltage Vn(T) is given by the following equation: According to the Shockley diode equation, kT / q is the thermal voltage (V T ) The temperature dependent output voltage Vn(T) is therefore positively correlated to temperature and is independent of the power supply voltage.

[0061]

number

[0062] Vgs1 is the gate-source voltage of transistor 111, Vgs2 is the gate-source voltage of transistor 112, k is Boltzmann's constant, T is temperature, and q is the electron charge.

[0063]

[0067] A similar arrangement can be implemented using p-type MOS (PMOS) transistors. In that case, the end of the transistor arrangement connected to the common gate connection is the same end connected to ground, rather than the end connected to the current source. However, this configuration of the PTAT circuit is not commonly used, as it has an output that can depend on the power supply voltage. The output voltage of a circuit based on PMOS transistors has a negative correlation to temperature.

[0064]

[0068] Reference is now made to FIG. 4B, which shows a circuit diagram for generating a PTAT current in an IC using the circuit of FIG. 4A. As mentioned above, this circuit may be used, for example, as part of an LVTS as shown in FIG. 3, as will be discussed further below. Clearly shown is the NMOS transistor mechanism 110 of FIG. 4A which generates a temperature dependent output voltage (Vn(T)) 115. The current source is connected to the power supply voltage V DDCOREThe power supply is provided by a PMOS transistor 105 (first p-type current source transistor) connected to a power supply (supplied by a suitable power routing arrangement, only one end of which is shown diagrammatically). More generally, the PMOS transistor 105 (first p-type current source transistor) may replace or form part of a first current source, which may include multiple transistors and / or any other necessary electronic elements. Also shown in this arrangement is a voltage-to-current (V / I) circuit 31. This includes a differential amplifier 120 having a first input (+) and a second input (-) and forming an amplifier circuit, a V / I circuit PMOS transistor 130, and a V / I circuit resistor 132. The gate of the V / I circuit PMOS transistor 130 is connected to the gate of the current source PMOS transistor 105. The source of the V / I circuit PMOS transistor 130 is connected to a power supply voltage and the drain is connected to one end of a resistor 132 at a common point 135. The other end of the resistor 132 is connected to ground. More generally, the V / I circuit transistor 130 may replace or form part of a V / I current source (typically controlled by a first current source), which may include multiple transistors and / or any other necessary electronic elements. Thus, the V / I circuit PMOS transistor 130 is configured in a follower circuit configuration (in this case a common source circuit, but alternative follower circuits may be used instead, with one of the source and drain referred to as a first signal terminal and the other referred to as a second signal terminal, and a source follower circuit or a drain follower circuit may be used depending on the configuration). A first positive input of the differential amplifier 120 is connected to the PTAT output voltage (Vn(T)) 115 (which is effectively the input to the V / I circuit 31), and a second negative input of the differential amplifier 120 is connected to a common point 135 (the follower output).

[0065]

[0069] Thus, the V / I circuit 31 generates a PTAT current In(T), which flows from the drain of the V / I circuit PMOS transistor 130 through common point 135 to resistor 132. Also shown is another PMOS transistor 140, which is discussed further below.

[0066] PTAT Voltage Expansion

[0070] Reference is made to FIG. 5, which shows a circuit diagram based on the circuit of FIG. 4B, illustrating providing another voltage (which may be referred to as a sense voltage and may be used, for example, as a thermal sense voltage 44 as discussed with reference to FIG. 3 above) based on the PTAT voltage. This is an extension of the circuit of FIG. 4B, and the same reference numbers are used where similar features are shown. Additional features of this circuit (which may be referred to as a sense voltage generation circuit) may also be used as part of the LVTS, but this is not shown in the more detailed circuit diagram below. However, it will be understood that this circuit may be used in addition to (or instead of) the implementations described herein.

[0067]

[0071] The further PMOS transistor 140 has a source (first signal terminal) connected to the power supply voltage and a gate connected to the gate of the current source PMOS transistor 105 and the gate of the V / I circuit PMOS transistor 130. Therefore, the current flowing from the drain (second signal terminal) of the further PMOS transistor 140 has the same behavior over temperature as the PTAT current In(T) flowing from the drain of the V / I circuit PMOS transistor 130. However, the current flowing from the drain of the further PMOS transistor 140 may have a different amplitude depending on the size ratio (r) between the further PMOS transistor 140 and the PMOS transistor 130. Typically, the size ratio is greater than 1 to change the level and range of the output sense voltage Vx(T) relative to Vn(T).

[0068]

[0072] The drain of another PMOS transistor 140 is connected to an adjustable resistor (Rn) 142 controlled by a (e.g. 4-bit) digital configuration input X[3:0]. And the voltage ("extended voltage" or output sense voltage) 145, Vx(T), at the drain of the other PMOS transistor 140 is the PTAT voltage, Vx(T)=r*Rn / R·(Vn(T)), so that the scale is controlled by the size ratio (r) and adjustment of the resistor (Rn) 142.

[0069]

[0073] This voltage, which may be referred to as the extended voltage or output sense voltage, may be used to provide an output from the sensor, as discussed further below. The term Vx(T) is used to indicate temperature dependence, but the same voltage may equally be referred to as Vx. More generally, another PMOS transistor 140 may replace or form part of a sense voltage generator current source (typically controlled by a first current source and / or a V / I current source), which may include multiple transistors and / or any other necessary electronic elements.

[0070] Reference voltage generation

[0074] It is highly desirable to have a temperature invariant reference voltage to provide an output from the sensor. This can be provided by using two temperature dependent circuits, one using NMOS transistors (specifically the PTAT circuit discussed above) and the other using PMOS transistors. Although the PMOS temperature dependent circuit can be designed similarly to the NMOS temperature dependent circuit, a different design is proposed with certain advantages, as discussed below.

[0071]

[0075] Referring now to Figure 6, there is shown a circuit diagram for generating a reference voltage that can be independent of temperature, in accordance with the block diagram of Figure 3. This also uses the circuit of Figure 4B, and where the same features as in the previous figures are illustrated, the same reference numbers have been used.

[0072]

[0076] A PMOS transistor arrangement 210 is shown as discussed above. The current is provided by a current source PMOS transistor 205 (a second p-type current source transistor) driven by a current generated by an NMO transistor structure as discussed below. More specifically, the current source PMOS transistor 205 may be substituted for or form part of a second current source, which may include multiple transistors and / or any other necessary electronic elements. The PMOS transistor arrangement 210 includes a PMOS transistor 211 of size W1, providing a temperature dependent output voltage Vp(T) 215. The current density of the PMOS transistor 211 is determined by its size such that the transistor operates in the sub-threshold region. In sub-threshold operation, the source-gate voltage (V sg The device current can be described by the following equation, which demonstrates a direct negative correlation between V and temperature: SD represents the source-drain voltage, and V th represents the device (transistor) threshold voltage, and I D represents the drain current, and I O (T) represents the temperature dependent output voltage source current.

[0073]

number

[0074]

[0077] Thus, the output voltage 215 of the PMOS transistor mechanism 210 is inversely proportional to temperature, but may not be as linear and voltage supply independent as the temperature dependent output voltage (Vn(T)) 115 of the NMOS transistor mechanism 110 .

[0075]

[0078] Current source PMOS transistor 205 has its source connected to a power supply voltage and its drain connected to PMOS transistor mechanism 210 (specifically the source of PMOS transistor 211) to provide the drive current. The gate of current source PMOS transistor 205 is connected to the gate of current source PMOS transistor 105, so that the current supplied to PMOS transistor mechanism 210 is based on the current supplied to NMOS transistor mechanism 110. If the sizes of current source PMOS transistor 105 and current source PMOS transistor 205 are the same, these currents may be the same. Advantageously, the sizing of current source PMOS transistor 205 is adjustable or trimmable so that the current can be appropriately configured.

[0076]

[0079] Also shown is a second voltage-to-current (V / I) circuit 32 which is very similar to the V / I circuit 31 discussed above. The V / I circuit 32 includes a differential amplifier 220, a V / I circuit PMOS transistor 230, and a V / I circuit resistor 232. The gate of the V / I circuit PMOS transistor 230 is connected to the gate of the current source PMOS transistor 205. The source of the V / I circuit PMOS transistor 230 is connected to a power supply voltage and the drain is connected to one end of a resistor 232. The other end of the resistor 232 is connected to ground. The positive input of the differential amplifier 220 is connected to the temperature dependent output voltage (Vp(T)) 215 and the negative input of the differential amplifier 220 is connected to the drain of the V / I circuit PMOS transistor 230. More generally, V / I circuit PMOS transistor 230 may be replaced by or form part of a second V / I current source (typically controlled by a second current source), which may include multiple transistors and / or any other necessary electronic elements.

[0077]

[0080] The reference voltage generating circuit 40 comprises a first PMOS transistor (first combiner transistor) 150, a second PMOS transistor (second combiner transistor) 250, and a common resistor 152. The sources (first signal terminal in this configuration) of the first PMOS transistor 150 and the second PMOS transistor 250 are both connected to a power supply voltage, and their drains (second signal terminal in this configuration) are both connected to a common point 155. One end of the common resistor 152 is also connected to the common point 155. The other end of the common resistor 152 is connected to ground. If NMOS transistors are used as combiner transistors, their drains can be the first signal terminal and their sources can be the second signal terminal.

[0078]

[0081] The gate of the first PMOS transistor 150 is connected to the gate of the current source PMOS transistor 105 and to the gate of the V / I circuit PMOS transistor 130. The first PMOS transistor 150 is sized such that the current flowing from its drain is a first multiple (m) of the PTAT current In(T) from the NMOS transistor arrangement 110. More generally, the first PMOS transistor 150 may replace or form part of a first combiner current source (typically controlled by the first current source and / or the V / I current source), which may include multiple transistors and / or any other necessary electronic elements, and the transistor sizing may be applied to one or more transistors of the current source. The gate of the second PMOS transistor 250 is connected to the gate of the current source PMOS transistor 205 and to the gate of the V / I circuit PMOS transistor 230. The second PMOS transistor 250 is sized such that the current flowing from its drain is a second multiple (n) of the PTAT current Ip(T) from the PMOS transistor arrangement 210. More generally, the second PMOS transistor 250 can replace or form part of a second combiner current source (typically controlled by a second current source and / or a second V / I current source) that may include multiple transistors and / or any other necessary electronic elements, and the transistor sizing can be applied to one or more transistors of the current source. Thus, the current flowing through the common point 155 is the sum of the currents from the drains of the first PMOS transistor 150 and the second PMOS transistor 250. This current flows through the common resistor 152, generating a voltage at the common point 155. This voltage is the reference voltage 45.

[0079] Catastrophic Trip Signal Generator

[0082] Reference is now made to Figure 7 which shows a schematic circuit (thermal trip circuit) 70 for generating a thermal trip signal 75 according to the block diagram of Figure 3. It uses as inputs an external voltage Vx(T) 145 and a reference voltage 45. A further input is a trip calibration signal 71, as will be discussed below.

[0080]

[0083] The circuit includes a resistive voltage divider 72 and a comparator 74. The resistive voltage divider is used to divide down the reference voltage 45, constituted by an 8-bit trip calibration signal X[7:0] 71. This generates a threshold voltage 73.

[0081]

[0084] The threshold voltage 73 provides a first (positive) input to the comparator 74, and the extended voltage Vx(T) 145 provides a second (negative) input to the comparator 74. The output of the comparator provides the thermal trip signal CAT 75. The thermal trip signal 75 is thus a binary signal. It can be used for additional control of part or all of the IC. For example, in response to the thermal trip signal 75 indicating a catastrophic temperature (i.e., a temperature higher than a predetermined threshold), one or more operating characteristics (e.g., operating frequency, voltage, etc.) of part or all of the IC can be modified (e.g., reduced) or all or all of the IC can be shut down to prevent damage to that part or all of the IC due to overheating. Implementation of such responses to a catastrophic trip signal already exists in many conventional ICs and will not be discussed in detail herein.

[0082] Digital Thermal Signal Calibration

[0085] Reference is now made to Figure 8, which illustrates a schematic of an auxiliary circuit for calibration of the digital thermal signal. Although such a circuit is not shown diagrammatically in Figure 3, it will be understood that this circuit, or additional features disclosed therein, may be used in addition to (e.g., in combination with) or as an alternative to the implementations disclosed elsewhere herein. The sigma-delta ADC 64 has a signal input 161 and a reference input 162. It uses the voltage on the reference input 162 to generate a digital thermal signal 65 that matches the voltage on the signal input 161.

[0083]

[0086] As part of the auxiliary circuit, a calibration voltage 310 is generated. This is accomplished using a resistor divider that includes a first resistor 301 and a second adjustable resistor 302. The first resistor 301 is connected to the power supply voltage V DDCOREThe adjustable resistor 302 is set by a configuration signal 303. In this embodiment, the configuration signal 303 is, for example, a 4-bit signal X[3:0]. A calibration voltage V_cal 310 is output to a common point 306 between the first resistor 301 and the second resistor 302. In a practical implementation, the configuration signal 303 is set to a V_cal voltage between 750 mV and 950 mV. DDCORE V_cal can be set to maintain approximately 300mV for

[0084]

[0087] As shown in FIG. 8, a selector mechanism (switching circuit) controls the inputs provided to the signal input 161 and the reference input 162 of the ADC 64. It includes two selectors: a first selector 320 with two inputs (0,1) and whose output is controlled by a first select signal 325, and a second selector 330 with two inputs (0,1) and whose output is controlled by a second select signal 335. The first select signal 325 and the second select signal 335 can be considered as a 2-bit mode input Mode[1:0]. The calibration voltage 310 is connected to the 0 port of the first selector 320, and the reference voltage 45 is connected to the 1 port of the first selector 320 and the 0 port of the second selector 330. The extension voltage Vx(T) 145 is connected to the 1 port of the second selector 330.

[0085]

[0088] During normal operation, the first select signal 325 is configured to select one port of the first selector 320 and the second select signal 335 is configured to select one port of the second selector 330 (Mode[1:0]=[1,1]). As a result, the sigma-delta ADC 64 receives the extended voltage Vx(T) 145 at its (analog) signal input 161 and the reference voltage 45 at its reference input 162. The ADC 64 therefore uses the reference voltage 45 to generate a digital thermal signal 65 that corresponds to the extended voltage Vx(T) 145.

[0086]

[0089] Three different options are used during calibration. The first calibration mode is when Mode[1:0]=[0,0], the second calibration mode is when Mode[1:0]=[0,1], and the third calibration mode (which corresponds to the normal operating mode) is when Mode[1:0]=[1,1]. The option Mode[1:0]=[1,0] is not used. Those skilled in the art will understand how to calibrate an ADC using these modes.

[0087]

[0090] Reference is now made to FIG. 9, which shows an exemplary plot of PTAT voltage (specifically Vx(T)) versus temperature after calibration (an exemplary reference voltage is 350 mV). The 12-bit ADC output (SDO), which provides the digital thermal signal 65, is calibrated to be at its maximum value (4096) when Vx(T) is equal to the reference voltage. At other temperatures (e.g., T cal_low , T cal_high ) to calibrate the digital thermal signal within its linear range. Also, obtain another set of calibration values ​​at the minimum sensor operating temperature (T low ) and maximum sensor operating temperature (T high ) is also read to check linearity.

[0088]

[0091] Returning to the general sense discussed above, various optional features and / or implementation characteristics may be considered in accordance with one or more of the aspects, which will now be discussed in more detail.

[0089]

[0092] For example, the reference voltage generation circuit may include a first voltage-to-current circuit configured to convert a first voltage to a first current, which may further include a second voltage-to-current circuit configured to convert a second voltage to a second current, and the reference voltage generation circuit may be configured to generate the reference voltage based on a combination of the first current and the second current. The combination of the currents may be achieved by directing the currents to a common node and summing the currents.

[0090]

[0093] Advantageously, each of the first and second voltage-current circuits includes an amplifier circuit (which may be a buffer or an operational amplifier) ​​configured to receive an input voltage (e.g. the first or second voltage) at a first (positive) input and provide an output voltage, and a follower circuit including a follower current source controlled by the output voltage of the amplifier circuit and providing a follower current to a resistor coupled to ground. The follower current source may include a MOS transistor having a first signal terminal (drain or source) coupled to the power supply voltage, a gate configured to receive the output voltage from the amplifier circuit, and a second signal terminal (source or drain) configured to provide the follower output voltage. The second signal terminal is connected to ground via a resistor. The amplifier circuit is configured to receive a source voltage at a second (negative) input.

[0091]

[0094] The reference voltage generating circuit optionally further includes a first combiner current source controlled by the output voltage of the amplifier circuit (of the first voltage-current circuit) and providing a first combiner current to the common point, a second combiner current source controlled by the output voltage of the amplifier circuit (of the second voltage-current circuit) and providing a second combiner current to the common point, and a common resistor (or resistor) connecting the common point to ground, and the reference voltage is output at the common point. For example, the first combiner current source may include a first combiner transistor having a first signal terminal (drain or source) coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a second signal terminal (source or drain) coupled to the common point. The second combiner current source may include a second combiner transistor having a first signal terminal (drain or source) coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the second voltage-current circuit, and a second signal terminal (source or drain) coupled to the common point.

[0092]

[0095] Alternatively, this may be optionally understood as generating a reference voltage using a first voltage and a second voltage. This is done by converting the first voltage into a first current, for example using a first MOS transistor arrangement, converting the second voltage into a second current, for example using a second MOS transistor arrangement, and combining the first current and the second current. The reference voltage is generated by passing the combined first and second currents through a resistor. Also, the reference voltage can be calibrated by configuring one or more of the first MOS transistor arrangement, the second MOS transistor arrangement, and the resistor.

[0093]

[0096] Thus, the reference voltage can be calibrated or adjusted by sizing the first and / or second combiner transistors and / or by selecting or configuring the common resistor. Advantageously, the width of the first combiner transistor is different from the width of the second combiner transistor. This allows the reference voltage to be adjusted.

[0094]

[0097] In an implementation, the PTAT circuit further includes a first current source controlled by the output voltage of the amplifier circuit (of the first voltage-current circuit), the first current source configured to provide the first current source output to the series-connected n-type MOS transistors (NMOS transistor arrangement). To this end, the first current source may include a first p-type current source transistor having a source connected to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide the first current source output to the series-connected n-type MOS transistors (NMOS transistor arrangement). This allows the first p-type current source transistor to provide a current to the series-connected n-type MOS transistors of the PTAT circuit.

[0095]

[0098] In an implementation, the voltage generator circuit further includes a second current source controlled by the output voltage of the amplifier circuit (of the first voltage-current circuit, since this may improve the linearity of the second voltage with respect to temperature), the second current source being configured to provide the output of this second current source to the p-type MOS transistor of the voltage generator circuit. In another sense, the voltage generator circuit may further include a second p-type current source transistor having a source connected to the power supply voltage and a drain configured to provide the output of the second current source to the p-type MOS transistor. In an embodiment, the gate of the second p-type current source transistor is coupled to the gate of the first p-type current source transistor and / or to the gate of the MOS transistor of the first voltage-current circuit. Thus, the current supplied to the p-type MOS transistor of the voltage generator circuit may be based on the current supplied to the series-connected n-type MOS transistor.

[0096]

[0099] Optionally, a sense voltage generating circuit is further provided, comprising a sense voltage current source controlled by an output of the amplifier circuit (of the first or second voltage-current circuit) and configured to provide a sense voltage current to a selectable resistor. The voltage across the selectable resistor is provided as an output sense voltage. The sense voltage current source may include a MOS transistor having a first signal terminal (drain or source) coupled to the power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit or the gate of the MOS transistor of the second voltage-current circuit, and a second signal terminal (source or drain) connected to ground via the selectable resistor. The voltage of the second signal terminal is provided as an output sense voltage. In other words, the sense voltage can be generated by converting the first voltage or the second voltage into a sense current, for example, using a MOS transistor mechanism. The sense voltage is generated by passing the sense current through a resistor. Also, the sense voltage can be calibrated by configuring the resistor. Instead of each of the first voltage and / or the second voltage, the respective output sense voltage may be used. For example, a thermal output signal may be generated based on the sense voltage.

[0097]

[0100] The series connected n-type MOS transistors of the PTAT circuit may include a first n-type MOS transistor having a source connected to ground and a drain connected to a common point, and a second n-type MOS transistor. The second n-type MOS transistor has a source connected to the common point and a drain connected to the gate of the first n-type MOS transistor and the gate of the second n-type MOS transistor. The drain of the second n-type MOS transistor may be further configured to receive the first current source output. A first voltage is provided to the common point.

[0098]

[0101] The p-type MOS transistor of the voltage generator circuit may have a drain and a gate connected to ground, and a source configured to receive the second current source output and provide the second voltage.

[0099]

[0102] The at least one thermal output signal may include a thermal trip signal. The output circuit may also include a thermal trip circuit configured to generate the thermal trip signal by comparing a threshold voltage with a sense voltage based on the first voltage and / or the second voltage. The threshold voltage is advantageously generated from a reference voltage (and may be based on the configuration signal). For example, the threshold voltage is generated by applying the reference voltage to a resistive divider, the resistive divider including a selectable resistor to allow selection of the threshold voltage. Thus, the resistive divider advantageously provides or outputs the threshold voltage.

[0100]

[0103] The at least one thermal output signal may include a digital thermal signal. The output circuit may also include an analog-to-digital converter configured to convert a sensed voltage based on the first voltage and / or the second voltage into a digital thermal signal. The analog-to-digital converter advantageously generates the digital thermal signal using a reference voltage. In an implementation, the analog-to-digital converter includes a sigma-delta modulator.

[0101]

[0104] Additionally, a calibration circuit can be provided. The calibration circuit includes a calibration voltage generation circuit including a resistive voltage divider, to which a power supply voltage is applied and a resistance of the resistive voltage divider is selectable to generate a configurable calibration voltage. The calibration circuit also includes a switching circuit configured to selectively apply a reference voltage at the analog signal input of the analog-to-digital converter and a calibration voltage at the reference input of the analog-to-digital converter in a first configuration, a sense voltage at the analog signal input of the analog-to-digital converter and a calibration voltage at the reference input of the analog-to-digital converter in a second configuration, and a sense voltage at the analog signal input of the analog-to-digital converter and a reference voltage at the reference input of the analog-to-digital converter in a third configuration.

[0102]

[0105] In other words, at least one thermal output signal can be generated by applying a sensed voltage based on the first voltage or the second voltage to an analog-to-digital converter to generate a digital thermal signal. The thermal output signal can be calibrated by applying a power supply voltage to a resistive divider having a selectable resistance, generating a calibration voltage by selecting the resistance according to the power supply voltage, providing a reference voltage to an analog signal input of the analog-to-digital converter and the calibration voltage to a reference input of the analog-to-digital converter, reading the thermal output signal as a first calibrated output, providing a sensed voltage to an analog signal input of the analog-to-digital converter and the calibration voltage to a reference input of the analog-to-digital converter, reading the thermal output signal as a second calibrated output, and determining a calibration value based on the first and second calibrated outputs.

[0103]

[0106] In another approach, the at least one thermal output signal may include a thermal trip signal. The thermal trip signal may be generated by comparing a threshold voltage to a sensed voltage based on the first voltage and / or the second voltage. The threshold voltage is generated by applying a reference voltage to a resistive divider having a selectable resistance. The thermal trip signal may also be calibrated by setting the selectable resistance.

[0104]

[0107] Reference is now made to FIG. 10, which shows a schematic block diagram of a local voltage temperature sensor mechanism according to an alternative design according to the present disclosure. It is similar to FIG. 3, and the same reference numbers are used where the same features are illustrated. Variations on the implementation (or others) of FIG. 3 have been contemplated herein, which can equally be used for the design of FIG. 10 (or equivalently, the changes to FIG. 3 shown in FIG. 10 can be applied to other designs disclosed herein). Additionally, an external voltage input or port 400 (for receiving a voltage from outside the thermal sensor) is provided, along with a configurable (or programmable) voltage divider 410. The output signal generating circuit 50 is replaced with an output signal generating circuit 450 having the same digital thermal signal output circuit 60 but a different catastrophic thermal trip circuit 470. The circuit of the catastrophic thermal trip circuit 470 for generating the thermal trip signal output 77 is the same as that shown in FIG. 3.

[0105]

[0108] Rather than coupling the VDD / 4 signal to the second input of the measurement selector 63, an input from an external voltage port 400 is coupled and the voltage signal is measured to provide a digital measurement voltage at the digital thermal signal output 66. A configurable voltage divider 410 (VDD / K) can be used to reduce the voltage supplied to the measurement selector 63 depending on whether it is greater than or equal to a reference voltage (VREF), so that the divided voltage can be less than VREF for any value of the external voltage.

[0106]

[0109] Further, the catastrophic thermal trip circuit 470 is provided with a second comparator 420. The second comparator 420 compares the output of the configurable voltage divider 410 with a threshold signal (VCAT) 75 and provides a droop signal output 430. Thus, the second comparator 420 can be used to detect voltage droop of the voltage at the external signal input 400. Note that the threshold signal (VCAT) 75 provided to the second comparator 420 is generated based on a reference voltage 45 VREF generated by the thermal sensor. Therefore, this voltage is stable over temperature and has a high PSRR.

[0107]

[0110] Typically, the thermal sensor may further include an external voltage input for receiving a signal from outside the thermal sensor and for providing a measurement voltage. The output circuit may also be configured (after receiving the measurement voltage from the external voltage input) to generate at least one voltage measurement output (possibly as an alternative to the at least one thermal output signal, e.g., such that the at least one thermal output signal includes the at least one voltage measurement output). The voltage measurement output is advantageously based on the measurement voltage and a reference voltage. The measurement voltage may be provided by applying the signal received at the external voltage input to a resistive voltage divider. In other words, the external voltage input may include a resistive voltage divider for dividing the signal received at the external voltage input and thereby providing the measurement voltage.

[0108]

[0111] In an embodiment, the at least one voltage measurement output and / or the at least one thermal output signal may comprise a digital voltage signal. The output circuit may also include an analog-to-digital converter configured to convert the measurement voltage to a digital voltage signal. The analog-to-digital converter generates the digital voltage signal using a reference voltage. A selector may be provided to select whether to provide a sensed voltage based on the first voltage and / or the second voltage to the analog-to-digital converter or to provide the measurement voltage. In this manner, the same analog-to-digital converter may be used to selectively output a digital thermal signal or a digital voltage signal.

[0109]

[0112] Additionally or alternatively, the at least one voltage measurement output and / or the at least one thermal output signal may include a voltage droop signal. The output circuit may also include a droop detection circuit configured to generate the voltage droop signal by comparing the measurement voltage with a threshold. The threshold voltage is generated from a reference voltage. The droop detection circuit may share circuit elements (e.g., a threshold voltage generator) with the thermal trip circuit. Typically, a second comparator is provided to enable the voltage droop signal and the thermal trip signal to be output simultaneously. Alternatively, a selector may be provided to select whether to provide a sense voltage based on the first voltage and / or the second voltage to an analog-to-digital converter or to measure the measurement voltage. The signal comparator may also be used to selectively output a digital thermal signal or a digital voltage signal.

[0110] General points

[0113] Throughout this disclosure, various embodiments of the invention may be presented in a range format. It will be understood that the description in range format is merely for convenience and brevity and should not be construed as an indefinite limitation on the scope of the invention. Thus, the description of a range should be considered to have specifically disclosed all possible subranges and individual numerical values ​​within that range. For example, the description of a range such as 1-6 should be considered to have specifically disclosed subranges such as 1-3, 1-4, 1-5, 2-4, 2-6, 3-6, etc., as well as individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. This is true regardless of the breadth of the range.

[0111]

[0114] Similarly, recitation of a decimal range, such as, for example, 0.6 to 1.1, should be considered to have specifically disclosed smaller ranges, such as, for example, 0.6 to 0.9, 0.7 to 1.1, 0.9 to 1, 0.8 to 0.9, 0.6 to 1.1, 1 to 1.1, etc., as well as individual numbers within that range, such as, for example, 0.7, 1, and 1.1.

[0112]

[0115] Whenever a numerical range is given herein, it is intended to include any recited numbers (fractional or integer) within the given range. The terms "ranging / ranges between" a first designated number and a second designated number, and "ranging from" a first designated number to a second designated number, are used interchangeably herein and are intended to include the first and second designated numbers and all fractional and integer numbers therebetween.

[0113]

[0116] In this description, any numerical value should be interpreted as meaning a deviation of up to 20% from that value (i.e., ±20%). Similarly, when a numerical range is given, a broader range of up to 20% is meant (10% greater than and 10% less than the stated range).

[0114]

[0117] In this description, when a physical element is described as being "for" performing a particular action (e.g., a "circuit for performing X"), and similarly, when a physical element is described as actively performing a particular action (e.g., a "circuit performs X"), it is intended that each physical element is configured to (and "adapted to") perform that particular action.

[0115]

[0118] In the description and claims of this application, the words "comprise," "include," and "have" and their forms do not necessarily limit the elements in the list with which they are associated. Moreover, in the event of a conflict between this application and a document incorporated herein by reference, it is intended that the present application shall control.

[0116]

[0119] It should be noted that for clarity of reference in this disclosure, the use of nouns as common nouns, proper nouns, named nouns, etc. is not intended to imply that embodiments of the invention are limited to a single embodiment. Some embodiments of the invention can be described using many configurations of the disclosed components, while other configurations can be derived from these embodiments in various configurations.

[0117]

[0120] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. Of course, it will be appreciated that the development of any such actual implementation will involve many implementation-specific decisions to achieve the developer's particular goals, such as compliance with application- and business-related constraints, and that these particular goals will vary from implementation to implementation and from developer to developer. It will be further appreciated that such a development effort will be complex and time-consuming, but will nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0118]

[0121] It is expected that those skilled in the art will be able to easily practice the present invention based on the teachings of the present disclosure. It is believed that the description of the various embodiments provided herein provides sufficient insight and details of the present invention to enable those skilled in the art to practice the present invention. Moreover, it is specifically contemplated that the various features and embodiments of the present invention described above may be used alone and in various combinations.

[0119]

[0122] Conventional and / or current circuit design and layout tools can be used to implement the invention. The specific embodiments described herein, particularly the various thicknesses and compositions of the various layouts, are illustrative of example embodiments and should not be considered to limit the invention to the selection of such specific implementations. Thus, multiple examples can be provided for components described herein as a single example.

[0120]

[0123] Although circuits and physical structures are generally assumed, it is fully appreciated that in modern semiconductor design and manufacturing, physical structures and circuits may be embodied in a computer-readable descriptive form suitable for use in subsequent design, testing, or manufacturing stages, and in semiconductor integrated circuits manufactured thereby. Thus, patent claims directed to conventional circuits or structures, consistent with their specific language, may be read in computer-readable encoding and representations thereof, whether embodied in a medium or combined with suitable reading equipment, to enable the manufacture, testing, or design improvement of the corresponding circuits and / or structures. Structures and functionality presented as separate components in the exemplary configurations may be implemented as combined structures or components. The present invention is envisioned to include circuits, systems of circuits, associated methods, and computer-readable medium encodings of such circuits, systems, and methods, all as described herein and as defined in the appended claims. As used herein, a computer-readable medium includes at least a disk, tape, or other magnetic medium, optical medium, semiconductor medium (e.g., flash memory cards, ROM), or electronic medium, and a network, wired, wireless, or other communications medium.

[0121]

[0124] The foregoing detailed description describes only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended to be illustrative and not limiting. Variations and modifications of the embodiments disclosed herein may be made based on the description herein without departing from the scope and spirit of the present invention. Only the following claims, including all equivalents, are intended to define the scope of the present invention. In particular, while some embodiments are described in the context of a particular PTAT circuit, the teachings of the present disclosure are believed to be advantageous for use with other types of MOS-based PTAT circuits. Other types of circuits and / or techniques for generating a reference voltage from a PTAT signal may also be contemplated. For example, a PMOS voltage generator circuit may be substituted for the PTAT circuit in some embodiments, possibly with corresponding changes to the current source transistor mechanism. If an extended voltage (or output sense voltage) is used as an input to the circuit, this may be substituted with any sense voltage based on the first voltage and / or second voltage (as appropriate), including directly with the first and / or second voltage, for example as shown by the thermal sense voltage 44 in FIG. 3. Other types of V / I circuits and current coupling circuits may be considered in the particular implementation described. The particular circuits, sizing, and number of bits of signals are merely for illustration. LVTS in this disclosure refers to the current supply core voltage VDD CORE It has been shown that the power supply is provided by V CORE , V DD , V DDq Other options for this voltage are possible, including LVTS, LVTS+, LVTS+, or others. Advantageously, the power supply voltage used to power the LVTS may also power other functional circuits on the IC. Additionally, the techniques described herein may be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may fall within the scope of the invention, as defined in the following claims.

[0122]

[0125] Embodiments of the invention may be used to manufacture, produce, and / or fabricate integrated circuits and / or products based on integrated circuits.

[0123]

[0126] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0124]

[0127] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions shown in the block diagrams may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or may be executed in the reverse order, depending on the functionality required. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or acts or executes a combination of special-purpose hardware and computer instructions.

[0125]

[0128] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, and to enable those skilled in the art to understand the embodiments disclosed herein.

[0126]

[0129] The present disclosure may include systems, methods, and / or computer program products. The computer program products may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0127]

[0130] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be construed as a signal that is transitory in nature, such as electric waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a wave guide or other transmission medium (e.g., light pulses through a fiber optic cable), or electrical signals transmitting through wires. Conversely, computer-readable storage media are non-transitory (or non-volatile) media.

[0128]

[0131] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing / processing device or to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and transfers the computer readable program instructions to a computer readable storage medium within each computing / processing device for storage.

[0129]

[0132] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages. The one or more programming languages ​​include object oriented programming languages ​​such as Java, Smalltalk, C++, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter situation, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to carry out aspects of the invention.

[0130]

[0133] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0131]

[0134] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, whereby the instructions executed by the processor of the computer or other programmable data processing apparatus produce means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions can also be stored on a computer readable storage medium, whereby the computer, programmable data processing apparatus, and / or other device can be directed to function in a particular manner, whereby the computer readable storage medium on which the instructions are stored constitutes an article of manufacture containing instructions implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0132]

[0135] The computer readable program instructions may also be loaded into a computer, other programmable data processing apparatus, and / or other device to execute a series of operational steps on the computer, other programmable apparatus, or other device to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0133]

[0136] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or may be executed in the reverse order, depending on the functionality required. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or acts or executes a combination of special-purpose hardware and computer instructions.

[0134]

[0137] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, and to enable those skilled in the art to understand the embodiments disclosed in this specification. Those skilled in the art will recognize that combinations and sub-combinations of specific features disclosed in this specification may also be provided, even if not explicitly described.

Claims

1. a proportional to absolute temperature (PTAT) circuit including two series-connected n-type MOS transistors configured to receive the first current source output and provide a first voltage; a voltage generator circuit including a p-type MOS transistor configured to provide a second voltage; a reference voltage generating circuit configured to generate a reference voltage based on the first voltage and the second voltage; an output circuit configured to generate at least one thermal output signal based on the first voltage and / or the second voltage as well as the reference voltage; A thermal sensor for an integrated circuit comprising:

2. The reference voltage generating circuit includes: a first voltage-to-current circuit configured to convert the first voltage into a first current; a second voltage-to-current circuit configured to convert the second voltage into a second current; 2. The thermal sensor of claim 1, wherein the reference voltage generation circuit is configured to generate the reference voltage based on a combination of the first current and the second current.

3. Each of the first and second voltage-current circuits comprises: an amplifier circuit configured to receive an input voltage at a first input and to provide an output voltage; a follower circuit including a follower current source controlled by the output voltage of the amplifier circuit and providing a follower current to a resistor coupled to ground, the voltage across the resistor providing a follower output voltage; 3. The thermal sensor of claim 2, wherein the amplifier circuit is configured to receive the follower output voltage at a second input.

4. The reference voltage generating circuit further comprises: a first combiner current source controlled by the output voltage of the amplifier circuit and providing a first combiner current to a common point; a second combiner current source controlled by the output voltage of the amplifier circuit and providing a second combiner current to the common point; 4. The thermal sensor of claim 3, further comprising a common resistor connecting said common point to ground, said reference voltage being output at said common point.

5. the PTAT circuit further includes a first current source controlled by the output voltage of the amplifier circuit of the first voltage-current circuit, the first current source configured to provide the first current source output to the series connected n-type MOS transistors; the PTAT circuit further includes a first p-type current source transistor having a source connected to a power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide the first current source output to the series connected n-type MOS transistor; the voltage generator circuit further includes a second current source controlled by the output voltage of the amplifier circuit of the first voltage-current circuit, the second current source configured to provide a second current to the p-type MOS transistor of the voltage generator circuit; and / or 5. The thermal sensor of claim 3 or claim 4, wherein the voltage generator circuit further comprises a second p-type current source transistor having a source connected to a power supply voltage, a gate coupled to the gate of the first p-type current source transistor and / or the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide an output of a second current source to the p-type MOS transistor of the voltage generator circuit.

6. 6. The thermal sensor of claim 3, further comprising a sense voltage generation circuit including a sense voltage current source controlled by the output of the amplifier circuit and configured to provide a sense voltage current to a selectable resistor, the voltage across the selectable resistor being provided as an output sense voltage.

7. The series-connected n-type MOS transistors of the PTAT circuit include a first n-type MOS transistor having a source connected to ground and a drain connected to a common point; a second n-type MOS transistor having a source connected to the common point and a drain connected to a gate of the first n-type MOS transistor and a gate of the second n-type MOS transistor, the drain of the second n-type MOS transistor further configured to receive the first current source output, and the first voltage being provided to the common point; and / or 7. The thermal sensor of claim 1, wherein the p-type MOS transistor of the voltage generator circuit has a drain and a gate connected to ground, and a source configured to receive a second current source output and provide the second voltage.

8. 8. A thermal sensor as described in any one of claims 1 to 7, wherein the at least one thermal output signal includes a thermal trip signal, and the output circuit includes a thermal trip circuit configured to generate the thermal trip signal by comparing a threshold voltage with a detection voltage based on the first voltage and / or the second voltage, the threshold voltage being generated from the reference voltage.

9. 9. The thermal sensor of claim 8, further comprising a resistive divider, the threshold voltage being generated by applying the reference voltage to the resistive divider, the resistive divider including a selectable resistor to enable selection of the threshold voltage.

10. 10. The thermal sensor of claim 1, wherein the at least one thermal output signal comprises a digital thermal signal, and the output circuit comprises an analog-to-digital converter configured to convert a detection voltage based on the first voltage and / or the second voltage into the digital thermal signal, the analog-to-digital converter generating the digital thermal signal using the reference voltage.

11. The thermal sensor of claim 10 , wherein the analog-to-digital converter comprises a sigma-delta modulator.

12. The calibration circuit further comprises: a calibration voltage generation circuit including a resistive voltage divider to which a power supply voltage is applied, the resistance of the resistive voltage divider being selectable to generate a configurable calibration voltage; A switching circuit comprising: In a first configuration, the reference voltage at an analog signal input of the analog-to-digital converter and the calibration voltage at a reference input of the analog-to-digital converter are In a second configuration, the sense voltage at the analog signal input of the analog-to-digital converter and the calibration voltage at the reference input of the analog-to-digital converter are In a third configuration, the sense voltage at the analog signal input of the analog to digital converter and the reference voltage at the reference input of the analog to digital converter are a switching circuit configured to selectively apply 12. The thermal sensor of claim 10 or 11, comprising:

13. an external voltage input configured to receive a voltage from outside the thermal sensor and providing a measurement voltage; 13. The thermal sensor of claim 1, wherein the output circuit is further configured to generate at least one voltage measurement output, the voltage measurement output being based on the measurement voltage and the reference voltage.

14. 1. An integrated circuit comprising: a power routing mechanism that provides a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit; one or more local thermal sensors disposed on the integrated circuit, each local thermal sensor including a proportional to absolute temperature (PTAT) circuit including a MOS transistor, and configured to use the power supply core voltage to generate at least one temperature dependent voltage that varies independently of variations in the power supply core voltage; 1. An integrated circuit comprising:

15. Each of the one or more local thermal sensors a PTAT circuit configured to generate a first temperature dependent voltage of the at least one temperature dependent voltage using an n-type MOS transistor; a voltage generator circuit configured to generate a second temperature dependent voltage of the at least one temperature dependent voltage using p-type MOS transistors; a reference voltage generation circuit configured to generate a reference voltage using the first and second temperature dependent voltages, the reference voltage being independent of variations in temperature and / or the power supply core voltage; 15. The integrated circuit of claim 14, comprising:

16. 16. The integrated circuit of claim 15, further comprising an output circuit configured to generate at least one thermal output signal based on the reference voltage together with the first temperature dependent voltage and / or the second temperature dependent voltage.

17. The reference voltage generating circuit includes: a first voltage-to-current circuit configured to convert the first temperature dependent voltage into a first current; a second voltage-to-current circuit configured to convert the second temperature dependent voltage into a second current; 17. The integrated circuit of claim 15 or 16, comprising: a reference voltage generation circuit configured to generate the reference voltage based on a combination of the first current and the second current.

18. Each of the first and second voltage-current circuits comprises: an amplifier circuit configured to receive an input voltage at a first input and to provide an output voltage; a follower circuit including a follower current source controlled by the output voltage of the amplifier circuit and providing a follower current to a resistor coupled to ground, the voltage across the resistor providing a follower output voltage; 20. The integrated circuit of claim 17, comprising: a first input of said amplifier circuit configured to receive said follower output voltage at a second input of said amplifier circuit.

19. The reference voltage generating circuit further comprises: a first combiner current source controlled by the output voltage of the amplifier circuit and providing a first combiner current to a common point; a second combiner current source controlled by the output voltage of the amplifier circuit and providing a second combiner current to the common point; 20. The integrated circuit of claim 18, further comprising: a common resistor connecting said common point to ground, said reference voltage being output at said common point.

20. the PTAT circuit further includes a first current source controlled by the output voltage of the amplifier circuit of the first voltage-current circuit, the first current source configured to provide a first current source output to the series connected n-type MOS transistors; the PTAT circuit further includes a first p-type current source transistor having a source connected to a power supply voltage, a gate coupled to the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide a first current source output to the series connected n-type MOS transistor; the voltage generator circuit further includes a second current source controlled by the output voltage of the amplifier circuit of the first voltage-current circuit, the second current source configured to provide a second current source output to the p-type MOS transistor of the voltage generator circuit; and / or 20. The integrated circuit of claim 18 or 19, wherein the voltage generator circuit further comprises a second p-type current source transistor having a source connected to a power supply voltage, a gate coupled to the gate of the first p-type current source transistor and / or to the gate of the MOS transistor of the first voltage-current circuit, and a drain configured to provide a second current source output to the p-type MOS transistor.

21. 21. The integrated circuit of claim 18, further comprising a sense voltage generation circuit including a sense voltage current source controlled by the output of the amplifier circuit and configured to provide a sense voltage current to a selectable resistor, the voltage across the selectable resistor being provided as an output sense voltage.

22. The series-connected n-type MOS transistors of the PTAT circuit include a first n-type MOS transistor having a source connected to ground and a drain connected to a common point; a second n-type MOS transistor having a source connected to the common point and a drain connected to a gate of the first n-type MOS transistor and a gate of the second n-type MOS transistor, the drain of the second n-type MOS transistor further configured to receive a first current source output, and the first temperature dependent voltage is provided to the common point; and / or 22. The integrated circuit of claim 15, wherein the p-type MOS transistor of the voltage generator circuit has a drain and a gate connected to ground, and a source configured to receive a second current source output and provide the second temperature dependent voltage.

23. 23. The integrated circuit of claim 15, wherein the at least one thermal output signal includes a thermal trip signal, and the output circuit includes a thermal trip circuit configured to generate the thermal trip signal by comparing a threshold voltage with a detection voltage based on the first temperature-dependent voltage and / or a second temperature-dependent voltage, the threshold voltage being generated from the reference voltage.

24. 24. The integrated circuit of claim 23, wherein the threshold voltage is generated by applying the reference voltage to a resistive divider, the resistive divider including a selectable resistor to allow selection of the threshold voltage.

25. 25. The integrated circuit of claim 15, wherein the at least one thermal output signal comprises a digital thermal signal, and the output circuit comprises an analog-to-digital converter configured to convert a sensed voltage based on the first temperature dependent voltage and / or the second temperature dependent voltage into the digital thermal signal, the analog-to-digital converter generating the digital thermal signal using the reference voltage.

26. 26. The integrated circuit of claim 25, wherein the analog-to-digital converter comprises a sigma-delta modulator.

27. The calibration circuit further comprises: a calibration voltage generation circuit including a resistive voltage divider to which a power supply voltage is applied, the resistance of the resistive voltage divider being selectable to generate a configurable calibration voltage; A switching circuit comprising: In a first configuration, the reference voltage at an analog signal input of the analog-to-digital converter and the calibration voltage at a reference input of the analog-to-digital converter are In a second configuration, the sense voltage at the analog signal input of the analog-to-digital converter and the calibration voltage at the reference input of the analog-to-digital converter are In a third configuration, the sense voltage at the analog signal input of the analog to digital converter and the reference voltage at the reference input of the analog to digital converter are a switching circuit configured to selectively apply 27. An integrated circuit according to claim 25 or claim 26, comprising:

28. an external voltage input configured to receive a voltage from outside the thermal sensor and providing a measurement voltage; 28. The integrated circuit of claim 15, wherein the output circuit is further configured to generate at least one voltage measurement output, the voltage measurement output being based on the measurement voltage and the reference voltage.

29. 1. A method of operating a thermal sensor on an integrated circuit, comprising: obtaining a first voltage using two series-connected n-type MOS transistors receiving a first current source output; obtaining a second voltage using a p-type MOS transistor; generating a reference voltage using the first voltage and the second voltage; generating at least one thermal output signal based on the first voltage and / or the second voltage together with the reference voltage; The method includes:

30. generating a reference voltage using the first voltage and the second voltage, converting the first voltage into a first current using a first MOS transistor arrangement; converting the second voltage into a second current using a second MOS transistor arrangement; combining the first current and the second current, wherein the reference voltage is generated by passing the combined first and second currents through a resistor; 30. The method of claim 29, wherein the method further comprises calibrating the reference voltage by configuring one or more of the first MOS transistor mechanism, the second MOS transistor mechanism, and the resistor.

31. generating a sense voltage by converting the first voltage or the second voltage into a sense current using a MOS transistor arrangement, the sense voltage being generated by passing the sense current through a resistor; calibrating the sense voltage by configuring the resistor; 31. The method of claim 29 or claim 30, further comprising: wherein the thermal output signal is generated based on the sensed voltage.

32. The step of generating at least one thermal output signal includes applying a sense voltage based on the first voltage or the second voltage to an analog-to-digital converter to generate a digital thermal signal, the method comprising: generating a calibration voltage by applying a power supply voltage to a resistive divider having a selectable resistance and selecting the resistance in accordance with the power supply voltage; providing the reference voltage at an analog signal input of the analog to digital converter and the calibration voltage at the reference input of the analog to digital converter and reading the thermal output signal as a first calibration output; providing the sense voltage at the analog signal input of the analog to digital converter and the calibration voltage at the reference input of the analog to digital converter and reading the thermal output signal as a second calibrated output; determining a calibration value based on the first and second calibration outputs; 32. The method of any one of claims 29 to 31, further comprising calibrating the thermal output signal by:

33. The step of generating at least one thermal output signal includes generating a thermal trip signal by comparing a threshold voltage to a sense voltage based on the first voltage and / or the second voltage, the threshold voltage being generated by applying the reference voltage to a resistive divider having a selectable resistance, the method comprising: calibrating the thermal trip signal by setting the selectable resistor; 33. The method of any one of claims 29 to 32, further comprising:

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