Laterally gated two-dimensional electron gas field-effect transistor.

Abstract

The invention relates to a two-dimensional electron gas field effect transistor, called TEGFET, comprising a drain (3), a source (4) and at least one channel (6) contained in a heterostructure formed by a stack of at least two semiconductor layers (21, 22). The TEGFET comprises at least two lateral gates (5) arranged on either side of the at least one channel, each lateral gate (5) being arranged opposite one side of the at least one channel, said side of the at least one channel having a smaller dimension of the at least one channel, called the thickness of the at least one channel, extending along the axis (8) of the stack of at least two semiconductor layers and perpendicular to the length of the at least one channel. The TEGFET does not comprise a gate located below or above the at least one channel with respect to an axis perpendicular to a plane, called the channel plane, in which the at least one channel extends between the source and the drain, said channel plane being perpendicular to the thickness of the at least one channel.

Description

[Technical field]

[0001] The present invention belongs to the technical field of two-dimensional electron gas field effect transistors, also called TEGFETs. The principle of operation of a field effect transistor is to modulate the current flowing between the source and drain by changing the voltage applied between the gate and source of the transistor. In the case of a TEGFET, the modulation of the source-drain current is achieved by modulating the electron density of the two-dimensional electron gas. The two-dimensional electron gas is confined in a channel of a heterostructure.

[0002] TEGFETs are characterized by a high electron transport rate and are therefore ideal for use in high frequency devices. TEGFETs are also used in high power applications, for example in GaN-based devices or components.

[0003] The present invention relates in particular, but not exclusively, to high frequency transistors, and is particularly applicable to all existing types of TEGFETs, particularly, but not exclusively, to III-V and III-VN TEGFETs. [Background technology]

[0004] In view of the above mentioned fields of application of TEGFETs, their reliability is a crucial criterion.

[0005] Prior art TEGFETs operate by modifying the density and / or geometric distribution of charge carriers in the channel by spreading a two-dimensional electron gas across the entire width of the channel.

[0006] This is especially true for nano-sized transistors. This type of transistor is characterized by a channel length facing the gate, where the conductivity is modulated and / or controlled, for example for a nanowire or nanostructure, typically of the order of a few hundred nanometers, generally less than 300 nm. In this case, the channel length is generally shorter than, equal to or comparable to the mean free path of the electrons in the channel, which is typically of the order of 40 nanometers for gallium arsenide (GaAs) and of the order of a hundred nanometers for gallium nitride (GaN) at room temperature. Furthermore, the transport of electrons in the channel in this type of transistor is ballistic and governed by quantum physics.

[0007] This type of quantum-sized transistor therefore has a lower power rating due to the nanometer size of the channel.

[0008] Most prior art TEGFETs have an upper gate located vertically above the channel with respect to the plane formed by the two-dimensional electron gas, allowing the source-drain current to be controlled by modulating the electron density of the two-dimensional gas by an electric field perpendicular to the two-dimensional electron gas. Application of an electric field perpendicular to the two-dimensional electron gas depletes the two-dimensional electron gas over the entire width of the channel by reducing or increasing the carriers depending on the type and / or architecture of the field effect transistor, thus changing the conductivity of the channel.

[0009] Prior art TEGFETs have several drawbacks, including, by way of non-limiting examples, gate leakage current, interface defects, and gate embrittlement.

[0010] Gate leakage currents are a key indicator of the state of devices. They reveal their future degradation. Improving reliability means reducing leakage currents, which are also a source of electronic noise, i.e. "generation-recombination" and 1 / frequency (f) noise.

[0011] Interface defects refer to defects at the semiconductor-gate interface and / or at the dielectric-gate interface when a dielectric is placed to reduce leakage current. These defects contribute to trapping effects such as transconductance frequency dispersion, collapse of DC drain characteristics, gate and drain transients, and microwave power limitations.

[0012] The gate fragility is due, on the one hand, to the fragility of the oxides or crystals between the gate and the gas, and, on the other hand, to the fact that the gate is deposited on the surface of the semiconductor without being diffused. The fact that it is simply deposited makes it extremely sensitive to electrostatic shocks.

[0013] The present invention aims to at least partially overcome the drawbacks of the prior art devices.

[0014] A further object of the present invention is to -overcomes the shortcomings of prior art devices; and / or - the current-voltage characteristics are reliable and repeatable, and / or the drain-source current IDS is approximately constant and / or has a saturation curve that is independent or only slightly dependent on the drain-source voltage VDS; and / or for a given voltage VDS, the current IDS changes significantly or substantially when the gate bias voltage VGS is changed, and therefore the TEGFET can be operated by varying the voltage VGS; and / or -Low or no gate leakage current, and / or Characteristics are reliable and repeatable over the temperature range of -300 to 1.5 Kelvin, and / or -Immunity or low susceptibility to interference from the local environment and electromagnetic or ionizing radiation, and / or The present invention provides a TEGFET that can be used for high power applications. Summary of the Invention

[0015] For this purpose, a two-dimensional electron gas field effect transistor (TEGFET) is proposed, which comprises a drain, a source and at least one channel contained in a heterostructure formed by a stack of at least two semiconductor layers, preferably at least two separate layers or layers of different composition. The at least one channel connects the source and the drain along its longest dimension, called the length of the at least one channel.

[0016] The TEGFET comprises at least two lateral gates arranged on either side of the at least one channel, each lateral gate being arranged opposite one side of the at least one channel, the side of the at least one channel comprising or extending along a smaller dimension of the at least one channel, referred to as the thickness of the at least one channel, the thickness extending along an axis of the stack of at least two semiconductor layers and perpendicular to the length of the at least one channel.

[0017] Preferably, the TEGFET does not comprise a gate located below or above the at least one channel with respect to an axis perpendicular to a plane, referred to as the channel plane, in which the at least one channel extends between a source and a drain, said channel plane being perpendicular to the thickness of the at least one channel and / or perpendicular to the stacking axis of the at least two semiconductor layers and / or parallel to the length of the at least one channel.

[0018] Preferably, "side of at least one channel" means a face or surface or interface. Preferably, the side of at least one channel extends through or includes the thickness and length of at least one channel.

[0019] Preferably, at least one of the side gates faces a side of the at least one channel opposite to a side facing by at least one other of the side gates.

[0020] Preferably, the source and drain are contained in or belong to the same TEGFET layer. Preferably, the layer containing the drain and source also contains at least one channel.

[0021] Preferably, the electrical conductivity of at least one channel and / or the electron density of the two-dimensional gas is modulated and / or controlled preferably exclusively by the at least two lateral gates.

[0022] Preferably, the at least two lateral gates are arranged to modulate and / or control the electrical conductivity of at least one channel and / or the electron density of the two-dimensional gas.

[0023] Preferably, the TEGFET modulates and / or controls the electrical conductivity of at least one channel and / or the electron density of the two-dimensional gas without a gate located below or above the channel.

[0024] Preferably, the two-dimensional electron gas is contained and confined within at least one channel, the channel plane being preferably parallel to the plane of extent of the two-dimensional gas.

[0025] Preferably, the two-dimensional electron gas extends between an interface between the source and the stack of at least two semiconductor layers, preferably lying in a plane parallel to the stacking axis perpendicular to the channel plane, and an interface between the drain and the stack of at least two semiconductor layers, preferably lying in a plane parallel to the stacking axis perpendicular to the channel plane. Preferably, the two-dimensional electron gas does not extend into the source or drain.

[0026] Preferably, the channel extends to the source and the drain.

[0027] Preferably, the length of the at least one channel corresponds to the maximum dimension of the at least one channel and / or the maximum distance separating two ends, preferably opposite ends, of the at least one channel.

[0028] "Channel plane" means a plane perpendicular to the thickness of at least one channel.

[0029] Preferably, the thickness of the at least one channel is less than both the length and width of the at least one channel. The thickness of the at least one channel may be defined as the smallest dimension of the at least one channel and / or as the smallest distance separating two, preferably opposite, faces of the at least one channel.

[0030] The TEGFET may comprise an even number of lateral gates. The TEGFET may comprise three or more lateral gates. The TEGFET may comprise a series of adjacent lateral gates extending along an axis connecting the source to the drain located on either side of at least one channel. Two adjacent lateral gates in a series of lateral gates may be separated by a trench or a recess. The lateral gates in a series of lateral gates may be aligned two by two along an axis perpendicular to the axis connecting the source to the drain and perpendicular to the stacking axis.

[0031] Preferably, at least one channel has two opposing sides, more preferably two parallel sides.

[0032] Preferably, the at least one channel has a width extending along an axis connecting two sides of the at least one channel.

[0033] Preferably, the width of at least one channel extends along an axis contained in the channel plane, and / or along an axis perpendicular to the axis connecting the drain to the source, and / or along an axis perpendicular to the length of at least one channel, and / or along an axis perpendicular to the thickness of at least one channel.

[0034] Preferably, the thickness of the at least one channel is less than the length of the at least one channel.

[0035] Preferably, the TEGFET comprises two separate lateral gates. Even more preferably, each of the two lateral gates is in particular independent of the other of the two lateral gates. Even more preferably, the two lateral gates have no common portion.

[0036] Preferably, the two side gates are symmetric. Preferably, the two side gates are symmetric with respect to at least one channel.

[0037] Preferably, the two lateral gates are made of, comprise or consist of a semiconductor material. Preferably, the semiconductor material comprises metal atoms, preferably diffused metal atoms. Preferably, the semiconductor material or the part or portions of the semiconductor material comprising diffused metal atoms constitute an ohmic contact.

[0038] Preferably, the two lateral gates and the channel are physically and / or spatially distinct elements or components or structures or layers or materials.

[0039] Preferably, the two lateral gates are arranged on either side of at least one channel with respect to an axis joining the source and drain.

[0040] Preferably, the two lateral gates extend primarily in a plane in which the at least one channel extends.

[0041] The TEGFET may have a single channel.

[0042] Preferably, the TEGFET may comprise two channels, even more preferably three channels, more preferably four channels, even more preferably five channels. Preferably, the channel planes of the TEGFET channels are parallel to each other. Preferably, the TEGFET channels form a stack along a stacking axis of at least two semiconductor layers.

[0043] Preferably, a lateral face of at least one channel of one of the two side gates is parallel to a lateral face of at least one channel of the other of the two side gates.

[0044] Preferably, the width of the face of each lateral gate flanking at least one channel corresponds to or is equal to, and preferably is greater than, the thickness of the at least one channel.

[0045] The length of the side face of at least one channel of each side gate may be defined as the maximum dimension of said face and / or the maximum distance between two ends, preferably opposite ends, of said face.

[0046] Preferably, the width of the face at the side of the at least one channel of each side gate is less than the length of said face, which may be defined as the smallest dimension of said face and / or the smallest distance between two ends, preferably opposite ends, of said face.

[0047] Preferably, none of the at least two lateral gates contacts or has a common portion or interface with the drain and source.

[0048] The larger dimensions of the at least two lateral gates may extend primarily perpendicular or parallel to the axis joining the gate and the drain.

[0049] Preferably, the conductivity of the at least one channel is modulated and / or controlled over a portion or parts of the at least one channel. Preferably, the conductivity of the at least one channel is modulated and / or controlled over a segment of the at least one channel. Even more preferably, the segment of the at least one channel whose conductivity is modulated and / or controlled corresponds to a portion or parts of the at least one channel that extend over only a portion of the width and / or the entire length and / or the entire thickness of the at least one channel.

[0050] Preferably, the segment of at least one channel, whose conductivity is modulated and / or controlled, corresponds to a portion or part of at least one channel extending over a portion or part of the length of at least one channel. "A portion of the length of at least one channel" can be interpreted as meaning a distance along the axis connecting the source and drain or the axis of the length of at least one channel that is equal to or less than the length of at least one channel. More preferably, the distance or dimension along the axis connecting the source and drain of the segment of at least one channel, whose conductivity is modulated and / or controlled, is equal to the length of a face of one of at least two lateral gates flanking at least one channel, or the length of each of the faces of the lateral gates flanking at least one channel.

[0051] The portion or parts of at least one channel whose conductivity is modulated and / or controlled can be defined as the portion or parts of a TEGFET that allows for controlled blocking and / or preferably controlled circulation of carriers between the drain and source.

[0052] The width of at least one channel may vary along an axis connecting the source to the drain.

[0053] Preferably, the terms "side", "lateral" or "lateral" define or designate a position or location relative to an axis connecting the drain to the source.

[0054] Preferably, the horizontal axis may be taken to mean an axis that lies in the plane of the channel, perpendicular to the axis joining the source and drain, and perpendicular to the thickness of at least one channel.

[0055] Preferably, the at least two lateral gates extend along a stacking axis of the at least two semiconductor layers on either side of each channel in the at least one channel, or along an axis perpendicular to the channel plane. Preferably, the at least two lateral gates extend along a stacking axis of the at least two semiconductor layers from an outer surface of the TEGFET to the at least one channel, or along an axis perpendicular to the channel plane. Preferably, the at least two lateral gates extend beyond each of the at least one channel along the stacking axis of the at least two semiconductor layers and along a direction connecting an upper outer surface of the at least two lateral gates to the at least one channel.

[0056] Preferably, none of the side gates contacts or has a common portion or interface with at least one channel.

[0057] Preferably, the TEGFET is arranged, and even more preferably the at least two lateral gates are arranged, to modulate and / or modify and / or vary the potential in at least one channel along an axis known as the transverse axis, contained in the channel plane and perpendicular to the axis connecting the source and drain. Preferably, the TEGFET is arranged, and even more preferably the at least two lateral gates are arranged, to modulate and / or modify and / or vary the potential in at least one channel along the transverse axis by polarizing the at least two lateral gates with respect to the source.

[0058] Preferably, the modulation and / or modification and / or lateral variation of the electrical potential within the at least one channel preferably has the effect of modifying the electrical potential across one or more portions or sections of the width of the at least one channel and / or generating a potential gradient laterally within the at least one channel.

[0059] Preferably, the modulation and / or modification and / or lateral variation of the electric potential in at least one channel has the effect of modulating, modifying or changing the electron density and / or drain-source current density and / or saturation current of the two-dimensional gas along the lateral axis in at least one channel.

[0060] Preferably, like prior art FETs, a TEGFET according to the invention is arranged so that the potential in at least one channel varies along the channel axis.

[0061] Furthermore, according to the invention, the TEGFET, preferably the at least two lateral gates, are arranged such that the potential is maximum at the center of the at least one channel when the two gates are at the same potential relative to the source. Preferably, according to the invention, the TEGFET, preferably the at least two lateral gates, are arranged such that the potential is zero on one or both sides of the at least one channel when one or both gates are at the same potential as the source.

[0062] Preferably, the TEGFET comprises a dielectric disposed between each of the at least two lateral gates and the at least one channel, or separating each of the lateral gates from the at least one channel.

[0063] Preferably, a dielectric means a body or medium having dielectric properties. The effect of the dielectric is to insulate the lateral gate from at least one channel.

[0064] Even more preferably, there is no contact or common part or interface between the at least one lateral gate and the at least one channel, and even more preferably, the placement of a dielectric between each of the two lateral gates and the at least one channel contributes to and / or has the effect of and / or allows for modulating and / or modifying and / or changing the electrical potential in the at least one channel along the lateral axis.

[0065] Preferably, the TEGFET comprises at least one channel-dielectric interface that is opposite, facing, contiguous or contiguous, preferably directly contiguous, to an interface between the dielectric and one, more than one, or preferably each, of the at least two lateral gates.

[0066] Preferably, the interface between the at least one channel and the dielectric and the interface between the at least one channel and a lateral gate of the at least two lateral gates under consideration are, respectively, a wall or face or side or surface of the at least one channel and a wall or face or side or surface of the lateral gate under consideration.

[0067] The interface between the at least one channel and the dielectric and the interface between the at least one channel and a considered one of the at least two side gates may be a common wall or a common face or a common side or a common surface between the at least one channel and the dielectric and between the at least one channel and a considered one of the at least two side gates, respectively.

[0068] Preferably, the dielectric is arranged in the form of a trench or recess.

[0069] Preferably, the dielectric is recessed.

[0070] Preferably, the recess defines a volume extending between one of the at least two side gates and the at least one channel.

[0071] Preferably, the recess is bounded in the transverse direction, along an axis parallel to the width of the at least one channel, by a face or surface of at least one channel located opposite or facing a face of the at least two lateral gates considered, and by a face of the at least one channel of the lateral gate considered. In this case, preferably, the interface between the at least one channel and the dielectric is formed by a face of the at least one channel facing the face of the corresponding lateral gate. Even more preferably, in this case, the interface between the dielectric and the corresponding lateral gate is formed by a face of the at least one channel of the corresponding lateral gate considered.

[0072] Preferably, the recess comprises or contains a gas.

[0073] In other words, the dielectric may be a gas.

[0074] The gas contained or enclosed in the recess may be air.

[0075] Preferably, the recess does not contain or consist of a solid material.

[0076] Preferably, at least two lateral gates, more preferably each lateral gate, comprises and / or is formed and / or consists of one or more semiconductor materials or one or more layers of semiconductor materials.

[0077] Preferably, at least two lateral gates, more preferably each lateral gate, comprises and / or consists of and / or is formed from and / or consists of a semiconductor material or a stack of one or more semiconductor materials.

[0078] Preferably, the semiconductor material constituting the at least two lateral gates comprises metal atoms diffused into the semiconductor material, preferably comprising metal atoms diffused into the semiconductor material.

[0079] Preferably, the drain, the source and the at least two lateral gates each comprise a metal layer forming a separate electrical contact. Preferably, the metal layer of the drain, the metal layer of the source and the metal layer of the at least two lateral gates are located on the upper outer surfaces of the drain, the source and the at least two lateral gates, respectively. Preferably, the metal layers and the upper outer surfaces of the drain, the source and the at least two lateral gates at least partially, preferably only partially, constitute the upper outer surface of the TEGFET.

[0080] The thickness of the metal layer is preferably 10 to 500 nm. Preferably, the metal layer includes and / or consists of a eutectic. Preferably, the eutectic includes and / or consists of gold, germanium, and nickel.

[0081] Preferably, the TEGFET according to the invention is arranged and / or capable of modulating and / or modifying and / or varying the potential of at least one channel along a transverse axis. Preferably, the TEGFET according to the invention is arranged and / or capable of modulating and / or modifying and / or varying the electron density of the two-dimensional gas and / or the current density of the two-dimensional electron gas along a transverse axis, preferably over a portion, more preferably only over a portion, of the width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged and / or capable of applying a constant potential over the entire width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged and / or capable of varying the electron density and / or the current density of the two-dimensional gas uniformly over the entire width of the at least one channel.

[0082] Preferably, the at least two lateral gates, more preferably each of the lateral gates, are arranged to modulate and / or modify and / or vary the potential of at least one channel along a transverse axis. Preferably, the at least two lateral gates, preferably each of the lateral gates, are arranged and / or are capable of modulating and / or modifying and / or varying the electron density of the two-dimensional electron gas, preferably non-uniformly, across the width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged and / or is not capable of applying a constant potential across the entire width of the at least one channel. Preferably, the at least two lateral gates, even more preferably each of the lateral gates, are not arranged and / or are not capable of generating a depletion and / or current density of the two-dimensional electron gas uniformly across the entire width of the at least one channel.

[0083] Preferably, the TEGFET according to the present invention, preferably the arrangement of the two lateral gates, more preferably the arrangement of the two lateral gates, is not arranged and / or is not capable of converting the two-dimensional electron gas into a one-dimensional electron gas.

[0084] Preferably, in contrast to prior art nanometer-scale FETs, whose operation consists in depleting the channel of electrons uniformly across the entire width of the channel in order to modulate the channel's conductivity, a TEGFET in accordance with the present invention does not deplete the two-dimensional electron gas uniformly across the entire width of at least one channel, but rather produces a non-uniform modulation of electron density and current across the entire width of the at least one channel.

[0085] For this purpose, preferably the ratio between the width of the at least one channel and the mean free path of the electrons in the at least one channel, and / or the ratio between the length of the segment of at least one channel facing at least two lateral gates, the conductivity of which is modulated and / or controlled, and the mean free path of the electrons in the at least one channel, and / or The ratio between the length of at least two lateral gates, preferably the minimum length in case of a change in length, and the mean free path of the electrons in at least one channel is greater than 10, preferably greater than 25, even more preferably greater than 50, even more preferably greater than 60, even more preferably greater than 70, even more preferably greater than 80, even more preferably greater than 90, and particularly advantageously greater than 100.

[0086] Preferably, the length of the at least two side gates is taken to mean the dimension of the at least two side gates in a direction parallel to the length of the at least one channel.

[0087] Also, the width of at least one channel and / or the length of the segment of at least one channel facing at least two side gates whose conductivity is modulated and / or controlled and / or the length of the at least two side gates is preferably greater than 0.5 μm, more preferably 1.25 μm, more preferably 2.5 μm, more preferably 3 μm, more preferably 3.5 μm, more preferably 4 μm, more preferably 4.5 μm, and most preferably all between 0.5 μm and 5 μm.

[0088] In contrast to prior art nanometer FETs, the electron transport in at least one channel of the TEGFET according to the invention is diffusive, i.e. the electrons are subjected to inelastic impacts and their movement is controlled by the mean free path of the electrons. However, the inventors of the present invention have observed that at least one micrometer-sized channel according to the invention allows the implementation of a TEGFET. Moreover, surprisingly, the TEGFET according to the invention has properties comparable to or even superior to those of prior art nanometer-sized TEGFETs (which operate with ballistic conduction of electrons in the channel).

[0089] Preferably, the ratio between the width of the at least one channel and the mean free path of the electrons in the at least one channel, and / or the ratio between the length of the segment of at least one channel facing at least two lateral gates, the conductivity of which is modulated and / or controlled, and the mean free path of the electrons in the at least one channel, and / or The ratio between the length of at least two side gates and the mean free path of electrons in at least one channel causes the potential and / or conductivity of the electron gas to vary non-uniformly across the width of the at least one channel. Thus, in accordance with the invention, equipotentials are observed at the sides of the at least one channel, i.e., at the side edges of the at least one channel, and the drain-source current is zero, or substantially zero. It is also found that the drain-source current flows primarily in a central part or portion of the at least one channel.

[0090] Furthermore, according to the invention, a width of at least one channel on the scale of at least one micrometer also has the effect of increasing the power of the TEGFET.

[0091] Preferably, one of the lateral gates may be electrically connected to the source.

[0092] Preferably, one of the side gates is electrically connected to the source, ensuring that the side gate connected to the source has the same potential as the source.

[0093] A method is also proposed for modulating the conductivity of at least one channel of a two-dimensional electron gas field effect transistor, known as a TEGFET, comprising the steps of applying a potential difference between a source and a drain of the TEGFET. applying the same potential difference between at least one lateral gate of the TEGFET, for example a first of at least two lateral gates arranged on either side of at least one channel of the TEGFET, and the source of the TEGFET; and / or applying the same potential on one or each of the lateral gates and the source of the TEGFET, and / or applying a potential difference between at least one of the lateral gates of the TEGFET, for example a second or second lateral gate arranged on either side of at least one channel of the TEGFET, or between each of the lateral gates of the TEGFET and the source of the TEGFET; Further includes:

[0094] At least one channel connects the source and drain of the TEGFET along the larger dimension of the at least one channel, known as the length of the at least one channel.

[0095] A TEGFET does not comprise a gate located below or above at least one channel with respect to an axis perpendicular to the plane of extension of the at least one channel between the source and the drain, known as the channel plane. extending along an axis of a stack of at least two semiconductor layers forming a heterostructure including at least one channel; and Extending perpendicular to the length of at least one channel Perpendicular to the smaller dimension of the at least one channel, referred to as the thickness of the at least one channel.

[0096] The step of applying the same potential or potential difference between at least two lateral gates and the source and / or the step of applying the same potential or potential difference between at least one lateral gate and at least one other lateral gate may comprise modulating and / or modifying and / or varying the potential of the at least one lateral gate relative to the potential of the source and / or the potential of the at least one lateral gate relative to the potential of the at least one other lateral gate.

[0097] Preferably, the method for modulating the conductivity of at least one channel of a TEGFET does not include a step of uniformly modulating and / or modifying and / or varying the electrical potential in the at least one channel and / or the electron density and / or current density of the two-dimensional gas across the entire width of the at least one channel.

[0098] Preferably, the method for modulating the conductivity of at least one channel of a TEGFET does not include a step consisting of applying a constant potential across the entire width of the at least one channel.

[0099] Preferably, the method for modulating the conductivity of at least one channel comprises the step of modulating and / or modifying and / or changing the potential and / or conductivity in at least one channel along an axis known as the transverse axis, which is contained in the channel plane and perpendicular to the axis connecting the source and drain, by applying the same potential difference between at least one of the lateral gates and the source and / or applying the same potential difference between one or each of the lateral gates and the source and / or applying a potential difference between at least one or each of the lateral gates and the source.

[0100] The step of modulating and / or modifying and / or varying the electrostatic potential in at least one channel along the horizontal axis may further comprise modulating and / or modifying and / or varying the potential of at least two lateral gates relative to the source potential and / or the potential of at least one lateral gate relative to the potential of at least one other lateral gate.

[0101] The step of modulating and / or modifying and / or varying the potential of at least two lateral gates relative to the source potential and / or the potential of at least one lateral gate relative to the potential of at least one other lateral gate may modulate and / or modify and / or vary or have the effect of modulating and / or modifying and / or varying the electrostatic potential in at least one channel along the horizontal axis.

[0102] Preferably, the step of spatially modulating and / or modifying and / or varying the electrostatic potential in at least one channel along a transverse axis has the effect of modulating and / or modifying and / or varying the drain-source current and / or saturation current of the TEGFET.

[0103] A method for modulating the conductivity of at least one channel may comprise the step of non-uniformly modulating and / or modifying and / or varying the electrical potential and / or the conductivity of the two-dimensional electron gas in at least one channel across a width of the at least one channel, preferably only a portion of the width of the at least one channel, by applying the same potential difference between at least one lateral gate and the source, and / or applying the same potential difference between one or each of the lateral gates and the source, and / or applying a potential difference between at least one or each of the lateral gates and the source, and / or the width of the at least one channel extends along an axis perpendicular to the length of the at least one channel and perpendicular to the thickness of the at least one channel.

[0104] The step of modulating and / or modifying and / or varying the electron density of the two-dimensional gas over only a portion of the width of the at least one channel may further comprise modulating and / or modifying and / or varying the potential of at least two lateral gates relative to a source potential and / or the potential of at least one lateral gate relative to a potential of at least one other lateral gate.

[0105] The step of modulating and / or modifying and / or varying the potential of at least two lateral gates relative to the source potential and / or the potential of at least one lateral gate relative to the potential of at least one other lateral gate may or may have the effect of modulating and / or modifying and / or changing the electron density of the two-dimensional gas over at least a portion of the width of the at least one channel.

[0106] Preferably, the process for modulating the conductivity of the at least one channel does not include a step of converting a two-dimensional electron gas into a one-dimensional electron gas.

[0107] The method for modulating the conductivity of a channel of a TEGFET according to the invention is preferably implemented by a TEGFET according to the invention. Preferably, the TEGFET according to the invention is particularly suitable for implementing the method according to the invention, and preferably also specially designed for implementing the method according to the invention. Preferably, the method according to the invention is particularly suitable for implementing by a TEGFET according to the invention, and preferably also specially designed to be implemented by a TEGFET according to the invention. Thus, any feature of the method for modulating the conductivity of a channel of a TEGFET according to the invention can be incorporated in a TEGFET according to the invention, and vice versa.

[0108] According to the invention, a method for manufacturing a TEGFET, preferably a TEGFET according to the invention, is also proposed, said method comprising the steps of: between a first metal layer intended to form an electrical contact and the drain of the TEGFET, and between a second metal layer intended to form an electrical contact and the drain of the TEGFET, and between a third metal layer intended to form an electrical contact and at least two lateral gates of the TEGFET arranged on either side of at least one channel of the TEGFET, The method includes a single annealing step to simultaneously form separate ohmic contacts of the first and second ohmic contacts in a single step.

[0109] Preferably, the first, second and third metal layers are upper outer layers. Preferably, the first, second and third metal layers are arranged on the upper layer of a stack of at least two layers of semiconductor material forming a heterostructure including at least one channel intended to form a drain, a source and at least two lateral gates.

[0110] Preferably, the single annealing step of the method according to the invention is preferably performed along the stacking axis of at least two layers of semiconductor material: a first metal layer in a stack of at least two semiconductor material layers, and a second metal layer in the stack of at least two semiconductor material layers, and A third metal layer in a stack of at least two semiconductor material layers. The drain, source and at least two lateral gates are formed simultaneously in a single step by diffusing metal atoms in the GaN layer.

[0111] The annealing process can be defined as a single step that simultaneously forms ohmic contacts in a single operation.

[0112] Preferably, the first, second and third metal layers are separate and independent layers.

[0113] Preferably, the metal atoms of the metal layer diffuse into the stack of at least two semiconductor material layers forming the drain, the source and especially the at least two lateral gates by a distance of more than 50 nm, preferably 100 nm, even more preferably 150 nm, more preferably 200 nm, even more preferably 250 nm and / or less than 400 nm, even more preferably 350 nm, even more preferably 300 nm. Preferably, the metal atoms of the metal layer diffuse from the upper outer surface of each of the drain, the source and especially the at least two lateral gates along the stack axis of the at least two semiconductor layers.

[0114] Preferably, the metal atoms of the metal layer are introduced from the upper outer surface of the drain, the source and in particular the at least two lateral gates into the stack of at least two layers of semiconductor material. a top outer surface of an upper layer of a stack of at least two semiconductor layers; Channels and It spreads a distance greater than or equal to the distance separating them.

[0115] Preferably, the distance between the upper outer surface of an upper layer of a stack of at least two semiconductor layers and the channel is parallel to the stacking axis and / or perpendicular to a plane known as the channel plane through which the at least one channel between the source and drain extends.

[0116] The TEGFET according to the invention is preferably realized by the manufacturing method according to the invention. Preferably, the manufacturing method according to the invention is particularly suitable for the realization of the TEGFET according to the invention, and preferably is also specially designed for the realization of the TEGFET according to the invention. Therefore, any feature of the manufacturing method according to the invention can be incorporated in the TEGFET according to the invention and vice versa. [Brief description of the drawings]

[0117] Other advantages and features will become apparent from a consideration of the detailed description of the completely non-limiting embodiments and implementations and from the accompanying drawings below.

[0118] [Figure 1a] FIG. 1 is a schematic perspective view of a prior art TEGFET. [Figure 1b] FIG. 1 is a schematic plan view of a prior art TEGFET.

[0119] [Figure 2a] FIG. 1 is a schematic perspective view of one embodiment of a TEGFET according to the present invention. [Figure 2b] FIG. 2a) is a schematic plan view of the embodiment of a TEGFET according to the present invention shown in FIG. 2a).

[0120] [Figure 3a] FIG. 1 is a schematic side view of an embodiment of a TEGFET according to the present invention. [Figure 3b] FIG. 1 is a schematic side view of an embodiment of a TEGFET according to the present invention.

[0121] [Figure 4] FIG. 1 is a schematic side view of one embodiment of a multi-channel TEGFET according to the present invention.

[0122] [Diagram 5] FIG. 1 is a schematic plan view of a TEGFET in which the lateral gate is electrically connected to the source.

[0123] [Figure 6a] FIG. 1 is a schematic perspective view of a channel of a prior art TEGFET in the absence of top gate polarization. [Figure 6b] FIG. 1 is a schematic perspective view of a channel of a prior art TEGFET in the presence of top-gate polarization. [Figure 6c] 1 is a graph showing the progression of drain-source potential in a channel along the horizontal axis of a prior art TEGFET in the presence of an upper gate bias.

[0124] [Figure 7a] FIG. 2 is a schematic perspective view of the channel of a TEGFET according to the invention in the absence of lateral gate polarization. [Figure 7b] FIG. 2 is a schematic diagram of the channel of a TEGFET according to the invention when polarization is present on one or more lateral gates. [Figure 7c] 4 is a graph showing the evolution of the drain-source potential in the channel along the horizontal axis of a TEGFET according to the invention in the presence of polarization of one or more upper gates.

[0125] [Figure 8a] FIG. 2 is a schematic diagram of a TEGFET according to the present invention before an annealing step. [Figure 8b] FIG. 2 is a schematic diagram of a TEGFET according to the present invention after an annealing step.

[0126] [Figure 9a] FIG. 1 is a schematic plan view of a TEGFET according to the present invention. [Figure 9b] FIG. 2 is a schematic plan view of a TEGFET according to the present invention featuring an alternative channel shape.

[0127] [Figure 10a] 9b is a graph showing the change in drain-source current versus drain-source voltage for various gate-source voltages at a temperature of 300 K for the TEGFET shown in FIG. 9a. [Figure 10b] 9b is a graph showing the change in potential in the channel along the horizontal axis at the source end of the channel as a function of drain-source voltage for the 300K TEGFET temperature shown in FIG. 9b. [Figure 10c] 9b is a graph showing the change in potential in the channel along the horizontal axis at the drain end of the channel as a function of drain-source voltage for the 300K TEGFET temperature shown in FIG. 9b.

[0128] [Figure 11]FIG. 9B is a graph showing the variation of drain-source current versus drain-source voltage for various gate-source voltages at a temperature of 300 K for a TEGFET shown in FIG. 9B, which includes a δ-doped layer located at a distance of 2 nm from the GaAs / GaAlAs interface of a TEGFET containing beryllium atoms acting as acceptors at a density of 4.10-10.cm-2.

[0129] [Figure 12] FIG. 9B is a graph showing the variation of drain-source current versus drain-source voltage for various gate-source voltages at a temperature of 1.5 K for the TEGFET shown in FIG. 9B, which includes a δ-doped layer located at a distance of 2.5 nm from the GaAs / GaAlAs interface of the TEGFET, which includes beryllium atoms acting as acceptors at a density of 8.10-10.cm-2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0130] The embodiments described below are in no way limiting, and in particular it is possible to consider variants of the invention that include only selected features of the disclosed features in isolation from the other features disclosed (even if the selection is made in an expression that also includes other features), provided that such selected features are sufficient to provide some technical advantage or to distinguish the invention over the prior art. Such selection includes at least one preferably functional feature without structural details, or has only a portion of structural details, provided that such a portion is sufficient to provide some technical advantage or to distinguish the invention over the prior art.

[0131] 1, a conventional TEGFET from the prior art is shown, comprising a stack of at least two semiconductor layers 21, 22, a drain 3, a source 4, a channel 6 and an upper outer metal gate 50 formed from a metal layer.

[0132] Many prior art TEGFETs include a gate made of metal (commonly known as a Schottky gate) deposited on semiconductor layer 21, without diffusion from the upper outer metal gate 50 into layer 21 and channel 6. Other prior art TEGFETs include a dielectric to electrically insulate the upper outer metal gate 50 from layer 21 and channel 6.

[0133] 2 and 3, an embodiment of a TEGFET 1 according to the invention is presented. The TEGFET 1 according to this embodiment comprises a drain 3, a source 4 and at least one channel 6 (in the embodiment shown, a single channel 6) contained in a heterostructure formed by a stack of at least two semiconductor layers 21, 22. The channel 6 connects the source 4 and the drain 3 along its longest dimension L.

[0134] The TEGFET 1 comprises at least two lateral gates 5, each disposed on either side of at least one channel 6. As shown, the TEGFET 1 comprises two lateral gates 5 on either side of the channel 6. Each of the lateral gates 5 faces a different one of the two side surfaces 7, 71, 72 of the channel 6. The side surfaces 7, 71, 72 of the channel 6 comprise a thickness e of the channel 6, which is the smallest dimension of the channel 6. The thickness e of the channel 6 extends along a stacking axis 8 of the at least two semiconductor layers 21, 22 and extends perpendicular to the length L of the channel 6. Furthermore, the side surfaces 7, 71, 72 of the channel 6 comprise the length L of the channel 6. The side surfaces 7, 71, 72 of the channel 6 are surfaces or interfaces extending along the length L of the channel 6 and the thickness e of the channel 6.

[0135] The TEGFET 1 does not comprise a bottom gate disposed below the channel 6 or a top gate 50 disposed above the channel 6 with respect to an axis 8 perpendicular to the channel plane through which the channel 6 extends. The channel plane is perpendicular to the thickness e of the channel 6. Also, the stacking axis 8 is perpendicular to the channel plane. In other words, the TEGFET 1 according to the invention does not comprise a bottom gate disposed below the channel 6 along the stacking axis 8 or a top gate 50 disposed above the channel 6 along the stacking axis 8. The absence of a top gate avoids all the problems encountered with prior art transistors such as gate leakage current, interface defects and gate brittleness.

[0136] According to this embodiment, the TEGFET 1 comprises a stack of layers, for example, a GaAs substrate, a GaAlAs layer having a thickness of 5 nm to 50 nm, a GaAs layer 22 having a thickness of 10 nm to 100 nm forming a channel, and a GaAlAs layer 21 having a thickness of 50 nm to 300 nm. In this configuration, the channel 6 is located in the GaAs layer at the interface between layers 21 and 22.

[0137] The lateral gate 5 according to the invention, in combination with the absence of a top or bottom gate 50, makes it possible to modulate and / or modify and / or change the potential in the channel 6 along a transverse axis 10, which lies in the channel plane and is perpendicular to the axis connecting the source 4 and the drain 3. Furthermore, the transverse axis 10 is perpendicular to the stack axis 8.

[0138] Unlike prior art TEGFETs with top gate 50 or bottom gate, thus varying the electron density of the two-dimensional electron gas over the entire width, l, of channel 6 as shown in Figures 6a, 6b and 6c, the particular arrangement of TEGFET 1 according to the invention makes it possible to modify and modulate the potential in channel 6 only along transverse axis 10, as shown in Figures 7a, 7b and 7c. Thus, according to the invention, the drain-source saturation current is controlled by varying the current density in channel 6, whereas in top gate 50 or bottom gate TEGFETs it is controlled by uniformly varying the electron density of the two-dimensional electron gas along the entire transverse axis 10.

[0139] A method for modulating the conductivity of the channel 6 of a TEGFET 1 according to the invention is also described. The method comprises the step of applying a potential difference between the source 4 and the drain 3. Furthermore, the method comprises: applying the same potential difference between each lateral gate 5 and source 4, or applying the same potential to one lateral gate 5 and to the source 4 and applying a potential difference between another lateral gate 5 and to the source 4, or applying a potential difference between each lateral gate 5 and the source 4; Further includes:

[0140] The same or different potentials applied between the or each lateral gate 5 and the source 4 may be zero or non-zero.

[0141] Applying the same potential or potential difference between at least one lateral gate 5 and the source 4 and / or applying the same potential or potential difference between at least one lateral gate 5 and another lateral gate 5 has the effect of changing the potential in the channel 6 along the horizontal axis 10.

[0142] The absence of a top gate 50 or a bottom gate in a TEGFET according to the invention means that the method for modulating the conductivity of the channel 6 does not include a step of uniformly varying the density of the two-dimensional electron gas over the entire width l of the channel 6.

[0143] The two lateral gates 5 are made of a semiconductor material. The two lateral gates 5 contain metal atoms diffused into the semiconductor material. According to the illustrated embodiment, the two lateral gates 5 consist of a stack of a GaAs layer 22 having a thickness of 10-100 nm and a GaAlAs layer 21 having a thickness of 50-300 nm. The GaAs / GaAlAs layer stack on the lateral gate 5 contains scattered metal atoms.

[0144] Each of the lateral gates 5 extends along the stacking axis 8 from the upper outer metal layer 9 , 91 and beyond the channel 6 in a direction connecting the upper outer metal layer 9 , 91 to the channel 6 .

[0145] The diffused metal atoms extend from the upper outer metal layer 9 into the layer stack 21 , 22 over a distance of 100-300 nm in the direction connecting the upper outer metal layer 9 , 91 to the channel 6 .

[0146] Also, unlike the upper or lower outer metal gates 50 of the TEGFET in the prior art, the lateral gates 5 according to the invention are made of a semiconductor material containing diffused metal atoms. In addition, the lateral gates 5 according to the invention extend into the structure of the TEGFET 1 along the stacking axis 8, rather than in an outer layer. This improves the mechanical strength of the gate. This also has the advantage of significantly increasing the potential that can be applied before damaging the gate. Finally, it also makes it possible to extend the applied potential beyond the width l of the channel 6, thus obtaining an optimal and uniform electrical effect over the entire width l of the electron gas.

[0147] The drain 3 and source 4 extend along the stack axis 8 from the upper outer metal layer 9, 92 and the upper outer metal layer 9, 93, respectively, in a direction connecting the upper outer metal layer 9, 92 to the channel 6 and connecting the upper outer metal layer 9, 93 to the channel 6, and beyond the channel 6. The diffused metal atoms extend from the upper outer metal layer 9, 92 and the upper outer metal layer 9, 93, respectively, into the stack of layers 21, 22 over a distance of 100-300 nm, and beyond the channel 6 in a direction connecting the upper outer metal layer 9, 92 to the channel 6 and connecting the upper outer metal layer 9, 93 to the channel 6.

[0148] The upper outer metal layer 9, 91, 92, 93 and the diffused metal atoms are a eutectic containing gold, germanium, and nickel.

[0149] According to the invention, none of the lateral gates 5 are in contact with the channel 6 or have a common portion or interface with the channel 6. In addition, the TEGFET 1 comprises a dielectric 11 disposed between each of the lateral gates 5 and the channel 6. The dielectric 11 is preferably in the form of a recess 11. Even more preferably, the dielectric 11 contained in the recess 11 is a gas. In the illustrated non-limiting example, the gas is air. The gas may also be nitrogen or other gases having dielectric properties.

[0150] These features, namely (i) the absence of contact or common parts or interfaces between the lateral gates 5 and the channel 6, (ii) the presence of a dielectric disposed between each of the lateral gates 5, and (iii) the arrangement of the dielectric in the form of a recess, individually contribute to an increased breakdown voltage, reduced leakage current, and improved characteristics of the TEGFET 1.

[0151] Figures 3a) and 3b) show, by way of non-limiting example, two possible configurations of a TEGFET 1 according to the invention. - a heterozygote as shown in Figure 3a), or - Quantum well shown in Fig. 3b) can be limited to.

[0152] In the case of a heterojunction, the channel 6 is located at the interface between two layers 21, 22 of different semiconductors. In this case, the semiconductors constituting layers 21, 22 have different bandgaps but belong to the same family. The channel 6 is therefore located within a semiconductor layer, in this case layer 22, in which the electrons of the two-dimensional gas are trapped and bound to the interface of the heterojunction.

[0153] In the case of a quantum well, the channel 6 is located in a layer 24 of a semiconductor having a small gap, e.g. a gap less than 1 eV, deposited between two layers 23, 25 of the same semiconductor having a large gap, e.g. a gap greater than 1 electron volt (eV).

[0154] The channel plane is parallel to the plane of extension of the interface of a heterojunction or of the layer 24 of small-gap semiconductor in the case of a quantum well.

[0155] 4 shows an arrangement in which the TEGFET 1 comprises multiple channels 6. According to the embodiment shown, the TEGFET 1 comprises three channels 6. The channels are stacked along a stacking axis 8. The channel planes of each channel 6 are parallel to one another. This arrangement is made possible by the use of lateral gates 5 according to the invention. This arrangement has the effect of increasing the current density.

[0156] 5 shows a configuration in which one of the lateral gates of the TEGFET 1 is electrically connected to the source 4. In this configuration, one of the lateral gates 5 and the source 4 are physically connected by the stack of layers 21, 22 and the upper outer metal layers 9, 91, 93. Thus, the source 4 and the lateral gate 5 connected to the source 4 are at the same potential. Furthermore, the diffused metal atoms extend into the portion of the stack of layers 21, 22 that connects the lateral gate 5 connected to the source 4 with the source 4.

[0157] With reference to Figure 8, a method for manufacturing a TEGFET 1 according to the invention is also described. This manufacturing method includes a single annealing step for simultaneously forming all ohmic contacts of the TEGFET 1 in a single step. These include: the upper outer metal layer 9, 92 of the drain 3; the upper outer metal layer 9, 93 of the source 4; the upper outer metal layer 9, 91 of each gate 5; The ohmic contact between the

[0158] Each of the upper outer metal layers 9, 91, 92, 93 is intended to form an electrical contact for connecting the TEGFET 1 to an external power source.

[0159] Prior to the annealing step, the method may include depositing, for example by evaporation, metal layers 9, 91, 92, 93 on the upper external surfaces of the drain 3, source 4 and lateral gate 5, respectively.

[0160] The annealing temperature is 300-450° C. The duration of the annealing step is 10 seconds to 3 minutes.

[0161] The annealing step involves diffusion or has the effect of diffusing metal atoms from each of the upper outer metal layers 9, 91, 92, 93 into the semiconductor layer 21. Preferably, the annealing time and temperature are selected such that metal atoms diffuse from each of the metal layers 9, 91, 92, 93 into the semiconductor layers 21, 22.

[0162] The annealing step has the effect of forming ohmic contacts between the upper outer metal layer 9 , 91 , 92 , 93 and the drain 3 , source 4 and especially the lateral gate 5 .

[0163] In prior art TEGFETs, diffusion of metal atoms from the upper outer metal layer 50 forming the upper or lower outer metal gate 50 is prohibited in order to avoid short circuits and / or to avoid a drop in the breakdown voltage and / or to limit leakage currents. For this purpose, it is necessary to deposit the upper outer metal layer 50 forming the upper or lower outer metal gate after performing an annealing step in order to form an ohmic contact between the upper outer metal layer 9, 92 of the drain 3 and the upper outer metal layer 9, 93 of the source 4. As a result, the method for manufacturing the TEGFET 1 according to the invention involves fewer steps, which saves time and energy.

[0164] Figures 10, 11 and 12 show the performance and characteristics of two different geometries of the channel 6 of the TEGFET 1 according to the invention as shown in Figure 9. In the first geometry shown in Figure 9a), known as TEGFETa)1, the channel 6 has a length of 730 μm between the source 4 and the drain 3 and a thickness of 10 μm between the sides 7, 71 and 7, 72 of the channel 6. In the second geometry shown in Figure 9b), known as TEGFETb)1, the channel 6 has a length of 30 μm between the source 4 and the drain 3 and a thickness of 10 μm between the sides 7, 71 and 7, 72 of the channel 6. The width and / or length of the channel 6 is only limited by the manufacturing method and equipment used to manufacture the TEGFET 1. If the manufacturing method allows, the length and / or width of the channel 6 may be several millimeters.

[0165] FIG. 10a) shows the variation of the drain-source current, indicated as IDS, as a function of the drain-source voltage, indicated as VDS, for various gate-source voltages, indicated as VGS, at a temperature of 300 K, for a TEGFET b)1. A potential difference is applied between one of the two lateral gates 5 and the source 4. In particular, one of the lateral gates 5 is grounded and the other is polarized. It should be noted that a saturated IDS is still observed even when VGS is equal to 0. When VGS is equal to 0, the lateral gate 5 is at the same potential as the source 4, which is grounded according to the embodiment. Furthermore, in the case of a negative polarization of the lateral gate 5, i.e. a VGS less than 0, the IDS decreases and in the case of a positive VGS, the IDS increases. This configuration provides the conventional characteristics of a TEGFET.

[0166] FIG. 10b) shows the variation of the potential in the channel 6 along the horizontal axis 10 at the source 4 end of the channel 6, denoted VYS, as a function of VDS, for TEGFET b)1, at a temperature of 300 K. FIG. 10c) shows the variation of the potential in the channel 6 along the horizontal axis 10 at the drain 3 end of the channel 6, denoted VYD, as a function of VDS, for TEGFET b)1, at a temperature of 300 K. The carrier density of the two-dimensional electron gas in this case is 2.4×10 at 300 K. 11 .cm -2 , 1.1×10 at 1.5K 11 .cm -2 It is.

[0167] Note that when VGS is equal to zero, neither VYS nor VYD are zero, indicating that even in this case, charge may build up along each side 7, 71 and 7, 72 of the channel 6. However, when the lateral gate 5 is maintained at the same floating potential, VYS and VYD do not tend towards zero, demonstrating that the lateral gate 5 strongly modifies the potential along the lateral axis 10 and the length L of the channel 6, even when VGS is equal to zero.

[0168] Note also that these results confirm the direct and consequential effect of VGS on the potential in channel 6 along the horizontal axis 10 and along the axis along the length L of channel 6.

[0169] Figure 11 shows the 4×10 10 .cm -2 Figure 1 shows the variation of the drain-source current, denoted IDS, as a function of the drain-source voltage, denoted VDS, for various gate-source voltages, denoted VGS, at a temperature of 300 K for a TEGFETb)2 with a δ-doped layer containing beryllium atoms acting as acceptors with a density of 1000 K. The δ-doped layer is located at a distance of 2 nm from the GaAS / GaAlAs interface. The carrier density of the two-dimensional electron gas in this case is 2.7.10 at 300 K. 11 .cm -2 , 1.25.10 at 1.5K 11 .cm -2 This demonstrates that the geometry of the TEGFET 1 does not affect the characteristics of the TEGFET 1 according to the invention, especially the IDS vs. VDS. The saturation current IDS and the stability IDS remain unchanged regardless of the geometry of the TEGFET 1.

[0170] Figure 12 shows an 8 x 10 10 .cm -2 The variation of the drain-source current, denoted IDS, as a function of the drain-source voltage, denoted VDS, for various gate-source voltages, denoted VGS, at a temperature of 1.5 K for a TEGFETb)2 with a δ-doped layer containing beryllium atoms acting as acceptors with a density of 6×10. The δ-doped layer is located at a distance of 2.5 nm from the GaAS / GaAlAs interface. The inset in Fig. 12 shows the results for a temperature of 1.5 K and a carrier density of the two-dimensional electron gas of 6×10. 10 .cm -2 , and a temperature of 300 K and a two-dimensional electron gas carrier density of 1.6 × 10 11 .cm -24 shows the change in drain-source current, denoted as IDS, upon successive changes in voltage VGS from -0.5 volts to +0.5 volts and then from +0.5 volts to -0.5 volts, i.e., without any interruption in the voltage changes.

[0171] It should also be noted that at 1.5K, the quality of the change in IDS as a function of VDS is maintained compared to 300K shown in Figures 10 and 11. This is due to the 8×10 10 .cm -2 Even at such a low carrier density, TEGFET 1 exhibits low noise and is therefore suitable for low temperature applications.

[0172] Naturally, the invention is not limited to the examples described here, and many adjustments can be made to these examples without going beyond the scope of the invention.

[0173] Further, the various features, forms, variations, and embodiments of the invention can be combined with each other in various combinations, unless they are mutually incompatible or exclusive.

Claims

1. A two-dimensional electron gas field effect transistor (1), called a TEGFET, comprising a drain (3), a source (4) and at least one channel (6) contained in a heterostructure formed by the stacking of at least two layers (21, 22) of semiconductors, said at least one channel connecting said source and said drain along a maximum dimension called the length (L) of said at least one channel, said TEGFET comprising: at least two lateral gates (5) arranged on either side of said at least one channel, each lateral gate (5) arranged opposite one side surface (7, 71, 72) of said at least one channel, said side surface of said at least one channel having a smaller dimension of said at least one channel, called the thickness (e) of said at least one channel, extending along the axis (8) of the stack of said at least two semiconductor layers and perpendicular to said length of said at least one channel, said at least one channel does not comprise a gate located below or above said at least one channel with respect to an axis perpendicular to a plane, called the channel plane, extending between said source and said drain, said channel plane being perpendicular to said thickness of said at least one channel; The TEGFET comprises: the width of said at least one channel, and / or the length of the portion of the at least one channel facing the at least two lateral gates, the conductivity of which is modulated and / or controlled, and / or a length of the at least two side gates, the dimension of the at least two side gates in a direction parallel to the length of the at least one channel; is 500 nanometers or more.

2. 2. The TEGFET of claim 1, wherein none of said at least two lateral gates (5) is in contact with, or has a common portion or interface with, said at least one channel (6).

3. 3. A TEGFET as claimed in claim 1 or 2, wherein the at least two lateral gates (5) are arranged to modulate and / or modify and / or change the potential in the at least one channel (6) along an axis (10) known as the transverse axis, which is contained in the channel plane and perpendicular to the axis joining the source and drain.

4. The TEGFET of any one of claims 1 to 3, comprising a dielectric (11) arranged between each of said at least two lateral gates (5) and said at least one channel (6).

5. The TEGFET according to claim 4, wherein the dielectric (11) is arranged in the form of a recess (11).

6. The TEGFET of claim 5, wherein the recess (11) contains a gas.

7. The TEGFET according to any one of claims 1 to 6, wherein the at least two lateral gates (5) are made of a semiconductor material.

8. A TEGFET according to claim 7, wherein the semiconductor material constituting the at least two lateral gates (5) comprises metal atoms diffused into the semiconductor material.

9. The TEGFET of any one of claims 1 to 8, wherein one of the lateral gates (5) is electrically connected to the source (4).

10. A method for modulating the conductivity of at least one channel (6) of a two-dimensional electron gas field effect transistor (1), also known as a TEGFET, comprising the steps of: - applying a potential difference between the source (4) and the drain (3) of the TEGFET; applying the same potential difference between at least one of the at least two lateral gates (5) of the TEGFET arranged on either side of the at least one channel of the TEGFET and the source of the TEGFET; and / or applying the same potential to one or each of the lateral gates and to the source of the TEGFET; and / or applying a potential difference between at least one of the lateral gates of the TEGFET and the source of the TEGFET; modulating and / or modifying and / or varying the electron density of the two-dimensional electron gas in the width of said at least one channel and / or modulating the current non-uniformity; Including, The at least one channel connects the source and the drain of the TEGFET along a maximum dimension of the at least one channel, called the length (L) of the at least one channel, the TEGFET having no gate located below or above the at least one channel with respect to an axis perpendicular to a plane, called the channel plane, in which the at least one channel extends between the source and the drain, the channel plane extending along an axis (8) of a stack of at least two semiconductor layers (21, 22) forming a heterostructure including the at least one channel and extending along the length of the at least one channel. a width of the channel and / or a length of a segment of the at least one channel whose conductivity is modulated and / or controlled facing the at least two lateral gates and / or a length of the at least one lateral gate is greater than or equal to 500 nm.

11. 11. The method according to claim 10, comprising modulating and / or modifying and / or changing the potential and / or conductivity in at least one channel (6) along a so-called transverse axis (10) lying in the channel plane and perpendicular to the axis joining the source and the drain by applying the same potential difference between at least one of the lateral gates (5) and the source (4) and / or applying the same potential difference between one or each of the lateral gates and the source and / or applying a potential difference between at least one or each of the lateral gates and the source.

12. 12. The method according to claim 10 or 11, comprising the step of non-uniformly modulating and / or modifying and / or varying the electrical potential in the at least one channel (6) and / or the conductivity of the two-dimensional electron gas along a width (l) of the at least one channel extending along an axis perpendicular to the length (L) of the at least one channel and perpendicular to the thickness (e) of the at least one channel by applying the same potential difference between at least one lateral gate (5) and the source (4) and / or applying the same potential difference between one or each of the lateral gates and the source and / or applying a potential difference between at least one or each of the lateral gates and the source.

13. A method for manufacturing a two-dimensional electron gas field effect transistor (1), also called a TEGFET, comprising the steps of: between a first metal layer (9, 92) intended to form an electrical contact and the drain (3) of said TEGFET, and between a second metal layer (9, 93) intended to form an electrical contact and the source (4) of said TEGFET, and between a third metal layer (9, 91) intended to form an electrical contact and at least two lateral gates (5) of said TEGFET; a single annealing step for simultaneously forming in a single step separate ohmic contacts of at least one TEGFET, said at least two lateral gates (5) being arranged on either side of at least one channel of said TEGFET, each lateral gate (5) being arranged facing one side (7, 71, 72) of said at least one channel, said side of said at least one channel comprising a smaller dimension of said at least one channel called a thickness (e) of said at least one channel extending along an axis (8) of the stack of said at least two semiconductor layers and perpendicular to a length of said at least one channel, and wherein the annealing time and temperature are selected such that metal atoms diffuse from each of said metal layers (9, 91, 92, 93) into said semiconductor layers (21, 22).

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