Clock-efficient random number generation system and method

Abstract

A system and method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system. The process includes loading a data loop (a looped array of stored values ​​with an index) with random data from a source of random data, and then repeating the following: reading a value from the data loop relative to the index, operating on the multi-bit value thereby outputting a induced random number, and moving the index relative to the looped array. The data loop may be a simple feedback loop that may be a shift register loaded by direct memory access (DMA). The operations may be guided by one or more data feeds and may be performed by one or more arithmetic logic units (ALUs) capable of performing XOR, Mask Generator, Data MUX, and / or MOD.

Description

[Technical field]

[0001] Background technology CROSS-REFERENCE TO RELATED APPLICATIONS This invention claims priority under the Patent Cooperation Treaty and the Paris Convention to U.S. Nonprovisional Patent Application No. 18 / 104,438, filed February 1, 2023, by Patrick D. Ross, which is incorporated herein by reference. This invention also claims priority under the Patent Cooperation Treaty and the Paris Convention to U.S. Provisional Patent Application No. 63 / 306,073, filed February 2, 2022, by Patrick D. Ross, which is incorporated herein by reference.

[0002] Technical Field The present invention relates to methods and systems for generating random numbers, and in particular to computer-generated random numbers.

[0003] Industrial Applicability The present invention is applicable in various ways and in various industries. The present invention may be used in the generation of random numbers for use in computing and communication systems. It may be utilized by system operators, system developers, programmers, and engineers and may be applied to computing networks, computing systems, telecommunication systems, etc. [Background technology]

[0004] 2. Description of Related Art Computing systems and operations are sometimes required to generate and / or utilize random or pseudorandom numbers (deterministic numbers that appear to be random but are not actually random) for various purposes, including but not limited to gaming, simulation, modeling, security, seeding, etc., and combinations thereof. Random and pseudorandom number streams are provided with various qualities of randomness, and some applications of their use require minimum standards of quality. NIST Special Publication 800-22 is an example of a body of standards for random and pseudorandom number generators, which includes methods for testing number streams for randomness, unpredictability, etc., including 15 different tests for various types of non-randomness. Various sources of random / pseudorandom number streams produce streams of particular quality, and high quality streams are often particularly difficult / expensive to generate and / or produce with a reliable / consistent quality.

[0005] Examples of physical sources of random number streams include noise in electronic circuits, the natural decay of radioactive nuclei, date / time vectors, mouse movements, delays between keyboard presses, and combinations thereof. Examples of sources of pseudorandom number streams include seeded PRNG functions (e.g., mean square method, Lehmer generator, Linear Congruential Generator (LCG), Linear Feedback Shift Register (LFSR), Nonlinear Feedback Shift Register, Inversive Congruential Generator (ICG)), cryptographic algorithms, cryptographic hashes, and combinations thereof (including some highly complex combinations).

[0006] In the related art, it is known to use computing systems to generate on-demand streams of random / pseudorandom numbers. A variety of hardware, software, and hybrid systems have been developed to address the need for random value streams. Several improvements have been made in this field. Examples of references relevant to the present invention are set forth below in their own words, and the supporting teachings of each reference are incorporated herein by reference: Chinese Patent Application No. 101515228, entitled TRUE RANDOM NUMBER GENERATOR, teaches a true random number generator, which includes a probabilistic source module and a post-processing module. The probabilistic source module is used to generate a digital signal with random characteristics and provide the digital signal to a post-processing module, which performs post-processing on the digital signal by using a loop code error correction method, thereby removing the bias of the data signal to obtain a random number sequence. The probabilistic source module can be composed of multiple sets of inverter oscillation rings, and the post-processing module is realized by a linear feedback shift register (LFSR). Since TRNG (True Random Number Generator) has a simple structure and only common digital logic devices are used, the true random number generator has good technical weak correlation and can be quickly implanted into the integrated circuit design flow after prototype verification is performed, thereby improving the efficiency of module design and reducing development risks.

[0007] U.S. Patent No. 6,954,770 issued to Carlson et al. discloses a random number generator comprising an oscillator having an output signal dependent on a random number source, a sampling device for sampling the output signal from the oscillator to obtain a sampled oscillator output, and a fixed frequency clocked linear feedback shift register (LFSR) communicatively coupled to the sampling device via a digital gate to receive the sampled oscillator output and provide a random number at an output of the LFSR. Additionally, the random number generator may comprise an optional mixing function communicatively coupled to the LFSR for reading the random number and inserting the random number into an algorithm to obtain a robust random number.

[0008] US Patent Publication No. 20050036607 by Wan et al. discloses a method of generating pseudorandom numbers performed by sampling an output sequence of a linear feedback shift register with a specified periodicity. In one embodiment, the generation of pseudorandom numbers using a linear feedback shift register is achieved by periodically switching between repeated outputs generated by multiple linear feedback shift registers. In one embodiment, the method of encrypting the pseudorandom numbers generated by the linear feedback shift register includes using a nonlinear operator. In one embodiment, the method of further encrypting the pseudorandom numbers is achieved by using a hash function whose initial value changes over time by a function operating on one or more variables. In one embodiment, an apparatus for generating pseudorandom numbers using a linear feedback shift register comprises digital hardware.

[0009] Known inventions suffer from several drawbacks, including being slow, inefficient, degrading or not maintaining a quality standard of randomness, having an exponentially increasing cost for additional random values ​​beyond the initial generation cycle, requiring many clock cycles to generate random values, generating deterministic values, and failing to generate actual random number streams.

[0010] What is needed is a method and / or system that solves one or more of the problems described herein and / or one or more problems that may come to the attention of those of skill in the art upon becoming familiar with this specification. Summary of the Invention [Problem to be solved by the invention]

[0011] Disclosure of the Invention The present invention has been developed in response to the current state of the art, and in particular in response to problems and needs in the art that have not yet been fully addressed by currently available methods and systems for generating random numbers. Accordingly, the present invention has been developed to provide a system and / or method for generating random numbers. [Means for solving the problem]

[0012] According to one non-limiting embodiment, there is a method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system. The method includes one or more of: loading a data loop with random data, which may be from a source of random data, the data loop including one or more of a looped array of stored values ​​and an index, reading a value, which may be multi-bit, from the data loop with respect to the position of the index within the looped array, performing a first data operation on the value, thereby deriving a derived random number from the multi-bit value, moving the index with respect to the looped array to a different position within the looped array, and / or repeating one or more of these steps, thereby generating the sequence of derived random numbers.

[0013] The data loop may be a shift register. The shift register may be a universal shift register. The different locations may be adjacent locations. The data operation may be a decoupling operation that may be selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD. The source of random data may be the output of one or more methods / processes described herein. Loading the data loop may be performed by direct memory access. The data operation may be a MOD operation performed with a multi-bit value as a numerator and a denominator having fewer bits than the multi-bit value. The denominator may be a value obtained directly or derived from the source of random data. The denominator may be larger than a desired range of the induced random numbers. The controller may include one or more of a programmable logic circuit, a script, and a driver.

[0014] There may be an automatic selection of a decoupling operation from a plurality of decoupling operations according to a controller. Concurrent with performing the first data operation, there may be a second data operation performed on the multi-bit value, thereby deriving a second induced random number from the multi-bit value. Furthermore, the second / secondary computing system may independently perform one or more of the steps described herein using substantially the same source of random data as the primary computing system, such that the data loop of the second computing system identically loads the data loop of the primary system, and using substantially the same data operations as the primary computing system, such that the resulting induced random numbers are the same as those derived by the primary system / method, thereby generating a second series of induced random numbers that are identical to the series of induced random numbers of the primary system.

[0015] The second computing system may be structurally different from the primary computing system in at least one of the following: data loop, read operator, shifter, controller type, and type of data loop loader.

[0016] In another non-limiting embodiment, there may be a computerized system for efficiently generating a stream of random numbers. The system may include a simple feedback loop-like array of random data, a data loop including one or more of an index and / or output port that reads a value from the simple feedback loop-like array that may be based on a relative position of the index with respect to the simple feedback loop-like array, a data operator having an input and one or more of an output that can provide access to an output value from the data operator, the data operator may be operatively coupled to the output port such that a value from the output port is provided to the data operator as an input value, the data operator, and / or one or more of an incrementer that may be operatively coupled to the data loop that shifts an index with respect to the simple feedback loop-like array.

[0017] The data loop may further include an input port. The value from the output port may be a multi-bit value. The data loop may be a universal shift register. The data loop may be a shift register. The data operator may be a decoupling operation that may be selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD.

[0018] There may also be a second data loop that may have an input port that may be operatively coupled to the output of the data operator such that the output value from the data operator is input to the second data loop.

[0019] There may also be a source of random data that may be operatively coupled to an input port of the data loop such that the looped array of random data is data supplied from the source of random data.

[0020] References to features, advantages, or similar language throughout this specification do not imply that all of the features and advantages that may be realized in the present invention should be in any single embodiment of the present invention, or are in any single embodiment of the present invention. Rather, language referring to features and advantages is understood to mean that the particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, descriptions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same embodiment.

[0021] Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in a particular embodiment that may not be present in all embodiments of the invention.

[0022] These features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

[0023] BRIEF DESCRIPTION OF THE DRAWINGS In order that the advantages of the present invention may be readily understood, a more detailed description of the invention, briefly described above, will now be made by reference to certain embodiments illustrated in the accompanying drawings. It should be noted that the drawings of the present invention are not to scale. The drawings are merely schematic and do not depict specific parameters of the invention. With the understanding that these drawings depict only typical embodiments of the invention and therefore should not be considered as limiting its scope, the present invention will be described and explained with additional specificity and detail using the accompanying drawings. [Brief description of the drawings]

[0024] [Figure 1]FIG. 1 illustrates a computerized system for efficiently generating a stream of random numbers, according to one embodiment of the present invention. [Diagram 2] FIG. 1 illustrates a primary hardware computerized system for efficiently generating a stream of random numbers, according to one embodiment of the present invention. [Diagram 3] FIG. 1 illustrates a hybrid hardware computerized system for efficiently generating a stream of random numbers, according to one embodiment of the present invention. [Figure 4] FIG. 1 illustrates a primary software computerized system for efficiently generating streams of random numbers, according to one embodiment of the present invention. [Diagram 5] 1 is a flow chart illustrating a method for efficiently generating random numbers in a computerized system, according to one embodiment of the present invention. [Figure 6] FIG. 2 is a sequence diagram illustrating a method for efficiently generating random numbers in a paired / parallel computerized system according to one embodiment of the present invention. [Figure 7] FIG. 1 illustrates an implementation of an XOR decoupling operation in a computerized system for efficiently generating random numbers, according to one embodiment of the present invention. [Figure 8] FIG. 1 illustrates an implementation of a Mask Generator or Data Mux decoupling operation in a computerized system for efficiently generating random numbers according to one embodiment of the present invention. [Figure 9] FIG. 1 illustrates an implementation of a MOD decoupling operation in a computerized system for efficiently generating random numbers, according to one embodiment of the present invention. [Figure 10] FIG. 2 is a clock diagram illustrating the synchronous operation of components of a computerized system for efficiently generating a stream of random numbers, according to one embodiment of the present invention. [Figure 11] FIG. 1 is a partial diagram of a computerized system including a data bus for efficiently generating a stream of random numbers, according to one embodiment of the present invention. [Figure 12]12 is a partial view of an output port of the computerized system of FIG. 11 according to one embodiment of the present invention. [Figure 13] FIG. 2 is a symbolic operational diagram of a data bus of a computerized system for generating random numbers, according to one embodiment of the present invention. [Figure 14] FIG. 1 is a schematic diagram of a highly configurable computerized system for efficiently generating streams of random numbers, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS For the purposes of promoting an understanding of the principles of the invention, reference will now be made to exemplary embodiments illustrated in the drawings and specific language will be used to describe them. It will be understood, however, that no limitation of the scope of the invention is intended thereby. Any alterations and further modifications of the features of the invention herein presented, and any further applications of the principles of the invention herein presented, which would occur to one of ordinary skill in the art having access to this disclosure, should be considered within the scope of the invention.

[0026] Throughout this specification, reference to an "embodiment," "example," or similar language means that the particular feature, structure, characteristic, or combination thereof described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, throughout this specification, appearances of the phrases "embodiment," "example," and similar language may, but do not necessarily, all refer to the same embodiment, different embodiments, or one or more figures. Furthermore, reference to an "embodiment," "example," or similar language in reference to two or more features, elements, etc. does not necessarily mean that the features are related, similar, the same, etc.

[0027] Each description of an embodiment or example should be considered independent of any other description of the embodiment, despite the use of similar or identical words characterizing each embodiment. Thus, if one embodiment is identified as "another embodiment", the identified embodiment is independent of any other embodiment characterized by the wording "another embodiment". Features, functions, etc. described in this specification are considered to be combinable with each other in whole or in part, as the claims and / or techniques may directly or indirectly, implicitly or explicitly indicate.

[0028] As used herein, "comprising," "including," "containing," "is," "are," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps. "Comprising" should be interpreted to include the more restrictive terms "consisting of" and "consisting essentially of."

[0029] 1 illustrates a computerized system 100 for efficiently generating a stream of random numbers, according to one embodiment of the present invention. Shown is a controller 110 operatively coupled to a data loop 120, a data operator 130, and a derived random number utilization system (DRNUS) 140. There is also a random number source 150 operatively coupled to the data loop 120, and a number of data feeds 160 coupled to the data operator 130. The illustrated data loop 120 also feeds into the data operator 130, which feeds into the derived random number utilization system 140. The DRNUS 140 may or may not be part of the illustrated system, depending on the particular implementation.

[0030] The illustrated controller 110 provides operational control for various parts of the illustrated system. The controller may include one or more scripts, programs, control circuits, processors, buses, memories, network adapters, power systems, etc., such that the controller can interface with and provide instruction and / or control signals to the data loop, data operators, and induced random number utilizing systems along with any analysis, processing, or configuration thereof. The controller may be a microcontroller, plug-in board, state machine, flash controller, etc., and / or combinations thereof. The controller is coupled to the data loop via at least an incrementer 125, which may be embodied within the controller, within the data loop, and / or between them. The controller sends an increment / decrement signal to the data loop, which, via the incrementer / decrementer 125 (incrementer and decrementer as used herein are synonymous), causes the data loop's index to move a position relative to the loop-like array of the data loop. The incrementer 125 may be as simple as a clock signal coupled to a shift register in a manner that causes the shift register to shift a value around the loop, thereby moving the value relative to other structures (e.g., index, input / output ports). The incrementer 125 may include logic circuitry that changes which lines are actively coupled to the loop so that the structure is coupled to the loop at a different location. It may include gated connections that are either open or closed according to a gate signal. Since there are many implementations that may be very expensive, slow, difficult, and / or require large amounts of power requirements compared to others, it is generally expected that the exact implementation of the incrementer will generally follow operational requirements and manufacturing constraints, and thus simple incrementer structures are generally preferred.

[0031] Thus, the controller can manage the relative positions of the indexes and changes thereto. The controller sends control signals to the data operators to manage the selection, changing, modifying, activating, deactivating, driving, etc. of active operators from the data operators' operator libraries. The controller receives requests from the induced random number utilising system for further induced random numbers and, in response to such requests, drives the activity of the data loops and data operators to generate induced random numbers to satisfy the requested requirements.

[0032] The following is a non-limiting prophetic example of a controller and its internal structure. Such a controller may include a bus through which it communicates with the system for which it requires induced random numbers. The controller receives such requests and utilizes internal drivers to interpret such requests, e.g., how many numbers are desired, when, what address / instance is specified for the resulting value, what format / size / range is sufficient to satisfy the request. The controller may then check an index age counter within the controller that counts the number of times to check if the index needs to move before generating further random numbers. If the age counter is zero, a control signal is sent to the incrementer to increment the index, thereby moving its position relative to the looped array, and then the age counter is reset to a number (which may be predefined according to a schema or may be a random number that can be derived from a random number source and / or the output of the computerized system itself). If not zero, the age counter is decremented. The controller may also check an operator age counter, and if the counter is non-zero it may be decremented, but if it is zero it is reset and a signal is sent to the data operator to select a new operator from the operator library, and the new operator may be selected according to a predefined or random scheme.

[0033] The controller can then signal the data loop and the data operator to jointly generate a specific number of random values ​​and output them to the induced random number utilizing system at a specific network address or otherwise make them available to the DRNUS. If additional random values ​​are required by the illustrated system in its operation, the random values ​​may be sequenced by the controller in addition to those requested by the DRNUS and a specific delivery address / location may be used. Alternatively, the computerized system may "double dip" by utilizing the random values ​​generated internally during the operation of one or more DRNUSs and delivering or otherwise making those values ​​available to the requesting DRNUS. As a non-limiting example, the illustrated data feed 160 may be a network address location and / or memory location where the output of the data operator sends the induced random values ​​and then used by the data operator in creating subsequent random values. Additionally, since the illustrated system utilizes a random number source 150, that random number source may be the output of the illustrated data operator and / or the output of a separate computerized system for efficiently generating random numbers as described herein.

[0034] The illustrated data loop 120 includes a simple feedback loop-like array of random data 122 with an index 124 associated with it at a particular position in the loop-like array. There are also input ports 126 and output ports 128 through which data may be imported into and exported from the loop-like array, each associated with an index position. It may be a shift register that may be fabricated using D-type flip-flops, generally one flip-flop per data bit. The data loop may be a shift register. Such a shift register may be a universal shift register, such as, but not limited to, TTL74LS194, 74LS195, or CMOS4035. Additionally, many integrated circuits include shift registers as components of the chip (e.g., CPU, GPU, serial port, System on a Chip (SoC)).

[0035] The illustrated simple feedback loop array of random data 122 is a hardware memory element that structures the array in a loop (i.e., the head and tail of the array are adjacent to each other). Furthermore, if the hardware includes the ability to shift data along the position of the loop, then a simple feedback relationship exists between the head and tail of the loop, so that data passing from the tail to the head or vice versa does so without changing its data value. This differs from a linear or nonlinear feedback shift register in that the data values ​​passing between the head and tail of the loop of such a register change according to a linear or nonlinear process. As non-limiting examples, a simple feedback loop-like arrangement of random data may be implemented as a circular shift register, a circular memory buffer, a series of sequential (either actually sequential or logically sequential) memory address locations on a hard drive, a solid state drive, a flash drive, RAM, SRAM, DRAM, Z-RAM, A-RAM, FERAM, CBRAM, PRAM, STT-RAM, SONOS, RRAM, racetrack memory, NRAM, 3D XPOINT, millipede memory, virtual memory associated with one or more of a variety of hardware memory sources, ROM, PROM, EPROM, EEPROM, etc., and combinations thereof.

[0036] The size of the data loop (i.e., the number of serial bits) is generally large enough to produce the desired output in a manner satisfactory for its intended use. This generally means that the data loop will be large compared to the expected rate of use (e.g., the larger the data loop, the less frequently it will need to be reloaded with more data from the random number source). Thus, the size of the data loop is selected to be large enough that the reload operation does not significantly impair the desired speed / efficiency of operation.

[0037] The illustrated index 124 points to a particular location within the looped array of random data. It may point to the boundary between the beginning and end of the looped array, or it may point to a different location. The index itself may be movable while the looped array remains fixed, the index may remain stationary while the looped array shifts the data along the array, or both may move relative to each other. Regardless of the actual movement / shift of the index and the looped array, it is possible to change their positional relationship relative to each other, thereby changing the effective "value" held by the looped array. Changing the positional relationship between the index and the looped array may also change the positional relationship between the input / output ports and the looped array and / or the index. The hardware representation of the index will vary depending on the particular hardware environment of the looped array. The index may be as simple as a record metatag, a gate, a line in, a uniquely identified memory cell, etc., or a combination thereof, or may be a more complex implementation such as, but not limited to, a separate record, a pointer implementation in a computerized program / script, a counter, etc., or a combination thereof.

[0038] As a non-limiting prophetic example, the following may be a string of binary values ​​held in a 16-bit looped array as defined by the relationship of an index to the looped array: Although a 16-bit example is provided to help explain the concept of a simple feedback looped array, it is believed that many practical implementations of the simple feedback looped arrays described herein will result in looped arrays of thousands to millions of bits or more.

[0039] 1001011110010010 This value is represented in decimal as 38802. If this value is shifted one bit to the right in a simple feedback loop array, the value changes to:

[0040] 0100101111001001 This value is represented in decimal as 19401. Subsequent one-bit shifted values, represented in decimal, are 42468, 21234, 10617, 38076, and 19038. The 16-bit looped array can be shifted 15 times to repeat the sequence. Thus, a single 16-bit value loaded into a simple feedback looped array may be used as if it were actually 16 different values.

[0041] The illustrated input port 126 and illustrated output port 128 allow write / read operations to / from the looped array so that values ​​stored therein can be changed to new values ​​and so that values ​​stored therein can be read from it. The ports may be single-bit write / read ports that allow a single bit to be changed / read. In such a case, the entire looped array may be rewritten / read by changing / reading one bit, then shifting the looped array to shift a new value into the port, then writing / reading that bit, then repeating until the entire looped array has been rewritten / read. The input port may be a multi-bit write port that allows writing to multiple bits at a time, which may further include the ability to write to all bits of the looped array. The structure of the input port varies depending on the hardware of the looped array. If the looped array is a shift register, the input port may simply include a line in with a gate to determine whether the input port writes or not. The shift register port (and other ports) can be a serial-in serial-out (SISO) port, a serial-in parallel-out (SIPO) port, or a parallel-in serial-out (PISO) port.

[0042] The illustrated random number source 150 provides true random and / or pseudo-random values ​​to the data loop. Such values ​​may be derived from physical sources such as atmospheric noise, thermal noise, radio noise, clock drift, avalanche noise in Zener diodes, optical perturbations, amplified spontaneous emission noise, external electromagnetic and / or quantum phenomena (e.g., radioactive decay, cosmic microwave background radiation), pseudo-random number generators (PRNGs) such as, but not limited to, linear congruential generators, middlesquare methods, Weyl sequences, Lehmer generators, lagged Fibonacci generators, linear feedback shift registers, Wichman-Hill generators, rule 30, inverted congruential generators, Park-Miller generators, ACORN generators, MIXMAX generators, and those based on carry add, carry subtract, carry multiply, maximally periodic round trip, KISS, Xorshift, WELL, JSF, ARS, Threefly, Philox, SplitMix, PCG, Xoroshiro128+, 64-bit MELG, Squares RNG, and Mersenne Twister algorithms. There is also the TRNG9803 hardware random number generator, which combines multiple methods together. Additionally, there are cryptographic algorithms for (expensively) generating very high quality streams of random values, including but not limited to stream ciphers, block ciphers, and cryptographic hash functions. Instead of relying on algorithms, there are also techniques that link computationally difficult problems together, which can generate high quality values, but at a large computational scale, including but not limited to the Blum-Micali algorithm, Blum Blum Shub, and Naor-Reingold pseudorandom functions.

[0043] The illustrated random number source 150 may include a memory storage device for holding random values ​​supplied to the system. It may also include hardware and / or software for implementing one or more algorithms and / or computational operations for generating random values ​​as required by the illustrated system. As a non-limiting example, the illustrated system may be utilized to generate random values ​​for itself and / or another computerized system described herein. Thus, the systems described herein may be daisy-chained to various implementations of themselves to generate multiple streams of random values.

[0044] The illustrated data operator 130 operates on the output of the data loop 120 and is operatively coupled to its output port 128. The data operator 130 inputs values ​​from the output port 128 and values ​​from a number of data feeds 160 at inputs 134. The inputs are operatively coupled to active operators 136 invoked from an illustrated operator library 137. The active operators 136 operate on the received values ​​and are operatively coupled to outputs 138 that provide resultant values.

[0045] The data operators that may be utilized are numerous and may include one or more arithmetic and / or bitwise operations. Non-limiting examples include adding 1, dividing by 2 (with truncation or rounding up), bitwise NOT, etc. These examples are examples of data operators that change the input value from the input value to some other value, which is sufficient to generate a new value. That new value may or may not preserve the randomness quality of the original value, which may or may not be important depending on the particular implementation required.

[0046] However, it is often important and / or valuable for a data operator to have certain qualities. One such quality is that the data operator decouples the resulting output from the input, meaning that the input value cannot be determined by knowing the operator and the output. As an example, if the operator is Add one or Divide by two, and the operator (including one of the operands) is known and the resulting value is known, then the input is also known, e.g., if the operator is x+1=y and y is known, then x is also known. In contrast, if the operator is Add or Divide, but the other operand comes from an unknown data feed, then the input cannot be determined by knowing the output and the operator (e.g., if x+z=y and y is known, it does not determine the value of the input x). This decoupling provides important value for many implementations. The following are non-limiting examples of decoupling operators, where the input operands are not specified along with the operator: arithmetic Add, Subtract, Divide, Mod, bitwise OR, XOR, ADD, Mask / MUX operations on two or more operands, etc., and combinations thereof.

[0047] Another data operator quality is the preservation of randomness quality from input to output. Different operators can preserve / maintain or degrade the quality of randomness of the input. In general, it is not possible to reliably improve the randomness quality of an input to an output with a data operator. As a non-limiting example, an operator that has a significant bias over time towards generating one of 1 or 0 will degrade the randomness quality, even if the input has no bias towards its value in the output (e.g., arithmetic Add one). This is because one of the tests for randomness is to check for a substantially equal number of 1s and 0s in the output. For many purposes, degrading the randomness quality is not appropriate.

[0048] XOR, Mod, and Mask / MUX are examples of data operators that preserve the randomness of the input stream. In particular, such operators are not recursive functions and therefore do not have any "memory" between sequential operations, so they have no bias toward any particular values ​​and no tendency toward generating patterns in the output stream.

[0049] Yet another quality of a Data operator is whether it consumes more "randomness" than it produces. XOR and Mask / MUX each require multiple streams of random values ​​to operate on, then produce a single stream of random values. Thus, they can be said to consume more values ​​than they produce. In contrast, the Mod operator can continue to generate random values ​​with a single static divisor, and thus consumes only a single stream of random values ​​to produce a single stream of random values. It is also possible to generate more bits of random values ​​than Mod consumes. Thus, Mod operators and the like have the quality of maintaining or multiplying the amount of random values ​​in a system, which can be beneficial for some applications.

[0050] The illustrated data feed 160 provides values ​​to the data operator 130 for use thereby in manipulating values ​​from the data loop 120. Multiple data feeds 160 are shown, with the exact number of different data feeds being implementation specific. In particular, various operators in the operator library may require multiple inputs of values ​​to perform their respectful value manipulations, and the data feeds allow for the supply of such values. It may include the output of a PRNG function, a pool of uncertain values, a real-time feed of random values ​​(e.g., atmospheric noise), the output of a system similar to those described herein, and the like, and combinations thereof. The exact configuration of the data feeds depends on the objectives and operational constraints provided by a particular implementation. As a non-limiting example where replication or pair generation of output values ​​from a data operator is desired, the data feeds generally need to be supplied in an exactly repeatable / replicable manner (e.g., PRNG) and not in a manner that is not exactly replicable (e.g., atmospheric noise).

[0051] The illustrated Driving Random Number Utilization System (DRNUS) 140 is operatively coupled to the data operator 130 such that the DRNUS can receive values ​​therefrom. The DRNUS 140 is also operatively coupled to the controller 110 such that it can request values ​​from the controller 110 and / or provide the controller 110 with requested characteristics (e.g., bit length of the value, quality of the value, seed value, and / or other metadata necessary to replicate a set of random values, such as, but not limited to, circumstances under which the DRNUS should receive a replicated set of random values ​​as a paired system). Non-limiting examples of the DRNUS 140 include programs / systems that utilize random values ​​(e.g., gaming engines, gaming devices, simulation systems, gaming systems, cryptographic systems, authenticators, key generators, compression engines, expansion circuits, hash circuits, noise generators, statistical sampling systems, etc., and combinations thereof). Thus, a computerized system for efficiently generating a stream of random numbers similar to the embodiments described herein may also be a DRNUS of another such system.

[0052] During operation, the data loop 120 is loaded with values ​​from a random source 150 via its input port 126. The directed random number utilization system DRNUS 140 requests a value from the controller 110, the request may include details regarding the requested value. The controller 110 may provide operating instructions to a set of data operators 130 and / or an incrementer 125 coupled to the index 124 of the data loop. Such instructions may include one or more of the set of the following instructions (or similar instructions), which may be executed directly by the recipient and / or indirectly by issuing further instructions to appropriate resources.

[0053] - Increment / decrement index 124 relative to loop 122 - Start / Stop / Change the output of values ​​from the Data Loop 120 through the output port 128 to the input of the Data Operator 130 - Start / Stop / Modify the output of values ​​from one or more data feeds 160 - Start / End / Change active operator 136 -changing the restrictions imposed on the operator library 137 (e.g., which operators or groups of operators are valid selections) -Toggle output of value from output 138 and / or output port 128 -changing the mode (e.g., word size, value type, e.g., binary, ternary, decimal) of the output 138 and / or output from the output port 128 - Load values ​​from the random number source 150 into the data loop 120 - Terminate / start / change connections between resources in the system (e.g., attach a new data feed to the input of a data operator, swap out a data loop attached to the input of a data operator, add a parallel operating data operator to the system fed by the same data loop, switch to a new DRNUS, terminate an existing DRNUS connection) The system, under the command of the controller 110, supplies values ​​from a data loop 120 to a data operator 130 where they are manipulated and then output to the DRNUS as required. Generally, the manipulations provided by the data operator decouple the output of the data operator from the output of the data loop, although this is not always the case.

[0054] As a non-limiting example, if an active operator performs a simple NOT operation, the output preserves the quality characteristics of the random values ​​of the data loop, but is not decoupled from it. In particular, the NOT operation flips bit values ​​from 1 to 0 and 0 to 1. This essentially creates a mirror image of it, so preserves the ratio of 1 and 0 values ​​in the stream (as their inverse), and in evaluating the random value stream, the inverse ratio is of the same quality as the non-inverse ratio, since quality is judged relative to the "distance" from a single ratio. However, the mirror image of the values ​​from the data loop provides a map of what those values ​​are. Specifically, by knowing the output of the data operator and that a NOT operator was used, it is possible to tell what the data loop values ​​are. That said, if decoupling is not needed, the NOT operator provides a very fast and efficient output value that is different from what was loaded into the data loop.

[0055] For purposes requiring decoupling, the following non-limiting operator types are useful: XOR, Mask Generator, Data MUX, and MOD. These operator types require the use of a data feed and can generate a decoupled output value from a value stored in the data loop. In particular, if the operator is known and the output is known, the value in the data loop is not revealed. Furthermore, the value from the data feed is not revealed. Thus, the security of the value in the data loop is preserved even if the architecture of the system is known. This is extremely valuable because it allows the value stored in the data loop to operate as if it were a one-time pad, which is generally understood to be provably unbreakable, but a PRNG, no matter how complex, is provably breakable.

[0056] According to one embodiment, there may be a computerized system for efficiently generating a stream of random numbers. The system may include a simple feedback loop-like array of random data, a data loop including one or more of an index and / or output port that reads a value from the simple feedback loop-like array that may be based on a relative position of the index with respect to the simple feedback loop-like array, a data operator having an input and one or more of an output that can provide access to an output value from the data operator, the data operator may be operatively coupled to the output port such that a value from the output port is provided as an input value to the data operator, the data operator, and / or one or more of an incrementer that may be operatively coupled to the data loop that shifts an index with respect to the simple feedback loop-like array.

[0057] The data loop may further include an input port. The value from the output port may be a multi-bit value. The data loop may be a universal shift register. The data loop may be a shift register. The data operator may be a decoupling operation that may be selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD.

[0058] There may also be a second data loop that may have an input port that may be operatively coupled to the output of the data operator such that the output values ​​from the data operator are input to the second data loop. There may also be a source of random data that may be operatively coupled to the input port of the data loop such that the looped array of random data is data provided from the source of random data.

[0059] 2 illustrates a primary hardware computerized system 200 for efficiently generating a stream of random numbers, according to one embodiment of the present invention. Shown is a controller 210 operatively coupled to a shift register 220, a data operator 230, and a derived random number utilizing system (DRNUS) 240. Also shown are a number of data feeds 260 coupled to the data operator 230. The illustrated shift register 220 also feeds into the data operator 230, which in turn feeds into the derived random number utilizing system 240. The DRNUS 240 may or may not be part of the illustrated system, depending on the particular implementation.

[0060] In contrast to FIG. 1, there is no random number source operatively coupled to the shift register 220. The illustrated shift register is loaded at the time of its manufacture and does not change. The shift register is therefore of sufficient size to be able to generate the desired output to the satisfaction of its intended use. This generally means that the shift register will be very large compared to the expected cycle of use. As a non-limiting example, if the device is expected to generate approximately 500,000 random value outputs over the life of the device, a 10,000+ bit shift register is far more than sufficient for the expected use and therefore does not need to provide any additional random values.

[0061] The illustrated shift register 220 is generally a cascade of flip-flops sharing the same clock. The output of each flip-flop is connected to the input of the next flip-flop in the chain / loop. Thus, the circuit shifts the bit array stored therein by one position (i.e., shifts right / left) at each transition of the clock input. This occurs when, on the clock signal, each flip-flop shifts its value to the input of the next flip-flop. Here, the shift register is a simple feedback shift register (a so-called circular shift register) in which the last bit in the array is shifted to the input of the first bit in the array without any modification or manipulation.

[0062] The shift register can have both parallel and serial inputs and outputs (e.g., SIPO and / or PISO configurations). The illustrated output port 228 may include multiple pins / wires to allow for the simultaneous output of multiple bits with each shift of the register, up to the total number of bits in the shift register. Also, the illustrated shift register's input port 226 may be disabled or removed after fabrication to prevent any further changes to the values ​​in the array. While typical shift registers used in various computing applications (e.g., delay circuits, hardware stack implementations, hardware solutions to the problem of too few pins / wires, changing inputs to / from parallel and serial as pulse extenders, and circular memories) are on the order of magnitude of 10, 100, 1000, or 10k bit arrays, it is contemplated that shift registers used in various embodiments of the present invention may be much larger, on the order of 100k, 1M, 10M, 100M, and / or 1B+.

[0063] Here, the illustrated controller and data operators are also hardware devices, and Figure 2 may represent a fully hardware system for efficiently generating a stream of random numbers. In such an example, the operator library 237 may include an array of operator circuits (e.g., XOR, MUX, MOD, Mask Generator) that are gated such that only one (or an otherwise limited amount) may be active at a time, each with similarly gated / limited access to the output. The data feed 260 may include hardware random number generators, including but not limited to a hardware PRNG generator and / or memory components (e.g., delay circuits, circular memory) having random values ​​stored therein.

[0064] 3 illustrates a hybrid hardware computerized system 300 for efficiently generating a stream of random numbers, according to one embodiment of the present invention. The illustrated system includes a controller operatively coupled to a shift register, a data operator, and a directed random number utilizing system (DRNUS). There is also a memory component 302 operatively coupled to an input port 326 of the shift register via direct memory access (DMA) 304. There are multiple data feeds coupled to the data operator. The illustrated shift register also feeds into the data operator, which feeds into the directed random number utilizing system. The DRNUS may or may not be part of the illustrated system, depending on the particular implementation.

[0065] The illustrated memory component is a device used to store information for use in a computer or related hardware device. It is typically a semiconductor memory device, often a metal-oxide semiconductor (MOS) memory where data is stored in memory cells on a silicon integrated circuit chip. It may be implemented as a RAM, DRAM, SRAM, cache memory, ROM, PROM, EPROM, EEPROM, tape drive memory storage, hard drive memory storage, floppy disk memory storage, CD / DVD / optical disk storage, volatile / non-volatile / semi-volatile memory, FERAM, CBRAM, PRAM, STT-RAM, SONOS, RRAM, racetrack memory, NRAM, 3D XPoint, virtual memory, and / or millipede memory, and / or combinations thereof. The illustrated memory 302 contains random values ​​and is operatively coupled to a shift register via a DMA 304.

[0066] The illustrated DMA 304 allows for memory access independent of the CPU. Thus, the illustrated system can operate to load new values ​​into the illustrated shift register on demand without having to wait or occupy CPU cycles. This is especially important when the DRNUS utilizes available CPU cycles and intrusion by the illustrated system into the CPU's resources would cause slowdowns or delays in the DRNUS. In DMA, the CPU typically initiates a transfer first, then performs other operations while the transfer is in progress, and finally receives an interrupt from a DMA controller (DMAC) when the operation is complete. Standard DMA, also known as third-party DMA, uses a DMA controller. The DMA controller generates memory addresses and can initiate memory read or write cycles. It contains several hardware registers that can be written to and read by the CPU. These include a memory address register, a byte count register, and one or more control registers.

[0067] Depending on what functions the DMA controller provides, these control registers may specify some combination of the source, destination, direction of the transfer (read from or write to an I / O device), the size of the transfer unit, and / or the number of words / bytes to transfer in one burst. To perform an input, output, or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of words to transfer and the memory address to use. The CPU then commands the peripheral device to begin the data transfer. The DMA controller then provides the address and read / write control lines to the system memory. Each time a byte of data is ready to be transferred between the peripheral device and memory, the DMA controller increments its internal address register until the entire block of data has been transferred.

[0068] 4 illustrates a primary software computerized system 400 for efficiently generating a stream of random numbers, according to one embodiment of the present invention. A controller is shown operatively coupled to a data loop 420 in memory, a data operator, and a directed random number system (DRNUS). There are also multiple data feeds coupled to the data operator. The illustrated data loop 420 in memory also feeds into the data operator, which feeds into the directed random number system. The DRNUS may or may not be part of the illustrated system, depending on the particular implementation.

[0069] The illustrated data loop in memory 420 includes one or more memory devices / structures such as those described herein, which may be managed through a memory controller, but are not limited to, a body of virtual memory and / or may further include one or more swap files, caches, databases, and / or may further include one or more federated databases. The data loop in memory 420 includes a logical arrangement of physical and / or virtual (with associated physical components) memory cells that relate to each other to form a looped array of memory associated with an index, such that the contents of the memory "cells" may be shifted in one direction or another, and / or such that the index may be shifted relative to the array of memory "cells" while the order of the contents of the memory "cells" remains unchanged. The logical arrangement may be managed / controlled by scripts, a system of pointers, data arrays / matrices, etc., and combinations thereof.

[0070] 5 is a flow chart illustrating a method for efficiently generating random numbers in a computerized system according to one embodiment of the present invention. The illustrated method for efficiently generating random numbers in a computerized system 500 includes loading 510 a data loop, then reading 520 a value from the data loop, where the current decoupling operation is "stale", selecting 530 a decoupling operation, and then performing 540 a decoupling operation on the read value thereby generating an output value, after which the index of the data loop moves 550 and the process loops back to reading 520 a value from the data loop. Advantageously, a single n-digit random value stored in the data loop may be utilized to efficiently generate a large number (≧n) of decoupled random values ​​therefrom.

[0071] The illustrated loading 510 of the data loop sets bit values ​​as stored values ​​in a looped array of data storage units (e.g., memory cells, bit registers, data latches, and flip-flops). The loading may be accomplished sequentially / sequentially and / or in parallel, or a combination thereof. The loading may be performed at the time of manufacturing the data loop. It may be performed in real time during operation of the associated device / system for generating random values. There may be one or more input lines that may be gated to allow a write operation to be performed on the data storage unit. The quality of the resulting randomness of the decoupling generally depends heavily on the quality of randomness of the values ​​in the data loop, and it is appropriate to be selective as to where / how to source the load values ​​for loading, i.e., that the source of random data from which the data loop is loaded has a quality of randomness equal to or greater than the desired quality of randomness intended for the output values.

[0072] Reading values ​​from the illustrated data loop 520 generally involves reading a multi-bit value from the data storage units of the data loop as a contiguous series of bits (with respect to the relative position of the index to the data storage units). The read may be performed as a bit-by-bit read and / or in parallel where multiple bits may be read simultaneously (e.g., via multiple parallel gated control lines operatively communicating with a particular data storage unit). Additionally, multiple multi-bit values ​​may be contemporaneously and / or simultaneously read from the same data loop, with the read structure allowing for contemporaneous and / or simultaneous reads from different portions of the same data loop (e.g., two different arrangements of gated red lines operatively coupled to two non-identical sets of data storage units of the data loop). The size of the reading value may be equal to the size of the data loop (e.g., the data loop includes 1 million sequentially arranged data storage units and the reading value is 1 million bits long) or the size of the reading value may be less than the size of the data loop (e.g., the data loop includes 1 million sequentially arranged data storage units and the reading value is 50,000 bits long). As a reading value, the value is held / stored by the system / device in a manner that makes it accessible to operations performed on it.

[0073] The illustrated selecting 530 decoupling operation includes conditionally determining (e.g., by operation of a script, random number selection, instructions by a third party device set during installation / manufacturing of the associated device / system, instructions from a controller) one or more decoupling operations and / or parameters (as well as associated physical structure / programming implementing such decoupling operations and / or parameters) to be utilized therewith in order to be "activated" so as to be able to operate on readings held / stored by the system / device. "Activating" the associated structure / programming may include activating one or more gate control input lines for a set of transistors, flip-flops, chips, chipsets, etc. that function to perform the selected decoupling operation, thereby allowing the readings to be input into the structure for processing. If the decoupling operation includes a software component, the activation may include invoking a function or software module that performs the selected decoupling operation.

[0074] Although selecting 530 the decoupling operation may occur every cycle of the illustrated method, it is expected that in general new decoupling operators and / or parameters will not be required very often. As a non-limiting example, if the loaded values ​​of length n are values ​​of reasonable quality of randomness, a device / system operating the illustrated method can continue to use the same decoupling operator without changing the decoupling operator or the parameters used therewith n times before risking repeating the pattern appearing in the output. Thus, it is expected that selecting 530 is generally unlikely to occur in most cycles of the illustrated method, especially if the data loop is large. Indeed, in some implementations (e.g., where the data loop is large compared to the size of the data loop and the actual utilization / life cycle of the system is small), selecting the decoupling operation may occur only once during the manufacture of the device / system and may never be changed thereafter.

[0075] The illustrated decoupling 540 of the reading value includes performing a selected decoupling operation on the reading value, thereby generating an output in the form of a new value decoupled from the reading value. Such decoupling is performed by a hardware and / or software implementation of the selected decoupling operation. As a non-limiting example, if the decoupling operation is an XOR operation, it may include a CMOS XOR gate (e.g., using pass transistor logic), a MOSFET XOR, an XNOR gate followed by a NOT gate, etc., or combinations thereof.

[0076] If multiple operations are selected, the decoupling may be performed multiple times, which may be done in parallel. Thus, a single reading may result in multiple or even multiple output values ​​decoupled from the reading. If the provision of decoupled random values ​​is desired at a rate that is an order of magnitude of the clock rate of the associated system, this feature of multiple parallel decoupling operations may be utilized to compensate for significant mismatches between the clock rate of the device / system generating the output values ​​and the device / system for which the output values ​​are desired.

[0077] Moving the index of the illustrated data loop 550 includes changing the location of the index with respect to the looped arrangement of the data storage units of the data loop. This may include shifting all stored values ​​in the data storage units in one direction by one or more positions. This may include deactivating an active index structure at one position around the data loop and activating an index structure associated with a different position around the data loop. This may include shifting the index value around the data loop (e.g., in the case of a paired set of data loops, the first is for a looped arrangement of stored values, and the second, which circumscribes the first or is otherwise structurally parallel to the first, serves to hold an index marker, which may be a single bit value (e.g., one and the rest all zeros) that shifts around the second loop, thereby identifying the current position of the index around the first loop). Once the reading 520 is performed relative to the index, moving the index changes the next read value to a new value that is significantly different (if the stored values ​​are sufficiently random) compared to the previous read value.

[0078] According to one non-limiting embodiment, there is a method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system. The method includes one or more of: loading a data loop with random data, which may be from a source of random data, the data loop including one or more of a looped array of stored values ​​and an index, reading a value, which may be multi-bit, from the data loop with respect to the position of the index within the looped array, performing a first data operation on the value, thereby deriving a derived random number from the multi-bit value, moving the index with respect to the looped array to a different position within the looped array, and / or repeating one or more of these steps, thereby generating the sequence of derived random numbers.

[0079] The data loop is a shift register, and the shift register may be a simple feedback shift register, where "simple feedback" means that the data is not manipulated as the shift register increments, but instead remains constant as the value shifts through the register, especially in the case of values ​​going from the "tail" back to the "head" of the register. It may be fabricated using D-type flip-flops, typically one flip-flop per data bit. The shift register may be a universal shift register, such as, but not limited to, TTL74LS194, 74LS195, or CMOS4035, and / or may be included as part of a larger integrated circuit (e.g., CPU, GPU, serial port, SoC). The different locations may be adjacent locations. The data operation may be a decoupling operation, which may be selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD. The source of the random data may be the output of one or more of the methods / processes described herein. Loading the data loop may be performed by direct memory access. The data operation may be a MOD operation performed on a multi-bit value as a numerator and a denominator having fewer bits than the multi-bit value. The denominator may be a value obtained directly from a source of random data or derived. The denominator may be larger than a desired range of the induced random numbers. The controller may include one or more of a programmable logic circuit, a script, and a driver.

[0080] There may be an automatic selection of a decoupling operation from a plurality of decoupling operations according to a controller. Concurrent with performing the first data operation, there may be a second data operation performed on the multi-bit value, thereby deriving a second induced random number from the multi-bit value. Furthermore, the second / secondary computing system may independently perform one or more of the steps described herein using substantially the same source of random data as the primary computing system, such that the data loop of the second computing system identically loads the data loop of the primary system, and using substantially the same data operations as the primary computing system, such that the resulting induced random numbers are the same as those derived by the primary system / method, thereby generating a second series of induced random numbers that are identical to the series of induced random numbers of the primary system.

[0081] The second computing system may be structurally different from the primary computing system in at least one of the following: data loop, read operator, shifter, controller type, and type of data loop loader. As a non-limiting example, the second computing system may use a shifter to shift stored values ​​in a looped array, while the first computing system activates and deactivates an index structure to thereby shift the index value. As another non-limiting example, the second computing system may utilize a universal shift register as its data loop, while the first computing system may utilize a virtual data loop formed using data stored on a hard drive. As yet another non-limiting example, the second computing system may utilize DMA, while the first computing system does not. As yet another non-limiting example, the second computing system may have a controller with a script stored in RAM, while the first computing system has a pure hardware controller that stores the script in ROM. Each of these examples illustrates a first and second computing system capable of generating the same set of random values ​​while having different specific structural implementations.

[0082] FIG. 6 is a sequence diagram illustrating a method for efficiently generating random numbers in paired / parallel computerized systems, according to one embodiment of the present invention. The illustrated computerized systems include controllers (Controller 1 and Controller 2) operatively coupled to respective decoupling operators (Decoupling Operator 1 and Decoupling Operator 2, respectively), each operatively coupled to a respective data loop (Data Loop 1 and Data Loop 2, respectively). In the illustrated example, the two computerized systems may be said to be paired systems (i.e., their structures are sufficiently identical to generate identical output streams when provided with identical input values ​​from the illustrated random number source). The two computerized systems may alternatively or additionally be said to be parallel systems (i.e., their structures include sufficient differences to generate different output streams when provided with identical input values ​​from the illustrated random number source). It is also possible for the two systems to be both paired and parallel, particularly when multiple decoupling operators are used simultaneously within the same system, with identical streams being generated between the two systems, and one or more other streams being generated that are not identical between the two systems. Thus, a single random number source may be efficiently utilized across multiple systems as desired to generate outputs in a paired / parallel manner.

[0083] In the illustrated example, values ​​from a random number source are loaded into each system's data loop at 610. A loop operation 620 is then performed within each system where the data loop is read at 630, the controller determines at 640 whether the decoupling operator and / or its parameters should be changed, and if such a change occurs, the decoupling operator operates on the read value at 650, the result of such operation is provided as an output, the data loop's index is shifted (e.g., incremented) at 660, and the loop is then repeated, thereby generating a stream of decoupled values.

[0084] FIG. 7 illustrates an implementation of an XOR decoupling operation in a computerized system for efficiently generating random numbers, according to an embodiment of the present invention. The illustrated XOR decoupling operation 700 is shown as an active operator selected from an operator library of data operators (see FIG. 1) and is thus functionally coupled to the inputs of the data operators. The XOR decoupling operation 700 receives a read value 710 as one of its inputs and a second input 720 from a data feed. There is an XOR operator 730, which may be a set of logic gates, a software XOR function, etc., or a combination thereof. It may include a CMOS XOR gate (e.g., using pass transistor logic), a MOSFET XOR, an XNOR gate followed by a NOT gate, etc., or a combination thereof. The XOR operator 730 may include multiple sets of logic gates, each capable of performing an XOR operation on a single bit, but which may together simultaneously perform an XOR operation on many or all of the bits of the read value 710 at the same time. The output of the XOR operator 740 is operatively combined with the output of the data operator so that it may be provided to one or more DRNUS (see FIG. 1) as desired.

[0085] FIG. 8 illustrates an implementation of a Mask Generator or Data Mux decoupling operation (Mask / MUX selector / operator) in a computerized system for efficiently generating random numbers according to an embodiment of the present invention. For clarity, the Mask operator / generator is a software implementation of a Data MUX. The illustrated Mask / MUX selector 800 is shown as an active operator selected from an operator library of Data Operators (see FIG. 1) and is thus functionally coupled to the inputs of the Data Operators. The Mask / MUX selector 800 receives a read value 810 as one of its inputs, and a second input 820 and a third input 830 from a data feed. There is a Mask / MUX operator 850, which may be a set of logic gates, a software Mask / MUX function, etc., or a combination thereof. It may include one or more multiplexers / data selectors.

[0086] The illustrated Mask / MUX operator is called a Selector because the bit value of the read value from the looped array acts as a "selector" that selects whether the resulting bit value is selected from the first input (Data0) from the data feed or the second input (Data1) from the data feed. If the bit value of the read value is 0, then whatever value in the corresponding Data0 becomes the output value and the bit value in Data1 is ignored and not used. If the bit value of the read value is 1, then whatever value in the corresponding Data1 becomes the output value and the bit value in Data0 is ignored and not used. It may be embodied in hardware as a switching gate (or an array of many switching gates) that switches the Data0 and Data1 input lines based on the 0 / 1 bit value of the read value.

[0087] The Mask / MUX operator 850 may include multiple sets of logic gates, each capable of performing a Mask / MUX operation on a single bit, but which together can perform a Mask / MUX operation on many or all of the bits of the read value 810 at the same time. The output 840 of the Mask / MUX operator 850 is operatively coupled to the output of the data operator so that it may be provided to one or more DRNUS (see FIG. 1 ) as desired.

[0088] FIG. 9 illustrates an implementation of a MOD decoupling operation in a computerized system for efficiently generating random numbers, according to one embodiment of the present invention. The illustrated MOD decoupling operation 900 is shown as an active operator selected from an operator library of data operators (see FIG. 1) and is thus functionally coupled to the inputs of the data operators. The MOD decoupling operation 900 receives a read value 910 as one of its inputs and a second input 920 from a data feed. There is a MOD operator 930, which may be a CPU, SoC, GPU, or other computational integrated circuit, a set of logic gates, a software MOD function, etc., or a combination thereof. If the MOD operator is unable to perform the mod operation in a single system clock cycle, the CPU may place one or more other components of the system on hold until the MOD operator completes its operation and generates an output.

[0089] The MOD operator 930 generally includes programming / circuitry that performs the following operations to output the modulo:

[0090] -Determine the molecule -Determine the denominator -Divide the numerator by the denominator and round down to determine the quotient - Multiply the denominator and the quotient, thereby determining the product -Subtract the product from the numerator, thereby determining the modulo Special techniques exist for generating modulos using other operations that may be used, provided their associated constraints (e.g., numerator or denominator of a particular type / size / relationship) are met within the context of the system. As a non-limiting example, the system may convert the numerator to the difference between a first number that is the rounded product of the numerator and a second number that must be subtracted from it, such that the difference is equal to the original numerator. The second number may then be similarly reduced via addition or subtraction. This may continue until no further reduction is possible. A specific example of such an operation is as follows:

[0091] 9322=9500-178=9500-190+12≡12(mod95) In contrast to the XOR and Mask / MUX operators, the MOD operation is not performed as a single bit-parallel operation across the width of the bits, instead there is generally a sequence of operations that are performed in a particular order. This means that in order to produce an output value at the system clock speed, the MOD operator must either operate on clock cycles faster than the system clock, or the CPU must hold the system clock to wait for the MOD operator to finish.

[0092] In the operation of the MOD operation, the entire value of the read value 910 is utilized as the numerator in a mathematical division operation with a second value 920 as the denominator. The output is the remainder of such a division, but the quotient is generally not used at all, and often not even determined. Thus, since the remainder is not divisible by the denominator in 900, it must have a bit length (D bits) equal to or less than the denominator, and thus the selection of the size of the denominator controls the output bit length and the range of possible values ​​of the output. Also, for the output to have a random number quality similar to the read value, the size of the numerator (Y bits) must be significantly larger than the size of the denominator (D bits), i.e. Y>>D. Thus, the values ​​drawn from the data feed are selected by the system to be values ​​that will generate an output word size as required by the associated DRNUS, and the read value is read to generate a value having a sufficient bit length to result in a high quality output. The output 940 of the MOD operator 930 is operatively coupled to the output of the data operator, so that it may be provided to one or more DRNUS (see FIG. 1) as desired.

[0093] 10 is a clock diagram illustrating the synchronous operation of components of a computerized system for efficiently generating a stream of random numbers, according to one embodiment of the present invention. n :arithmetic logic unit), one or more data feeds (DataFeed0~DataFeed n ), and a system clock that pulses a system clock signal that synchronizes the operation of the DRNUS receiving the random number stream. The illustrated operation can generate random values ​​in the random value stream of quality substantially equal to the quality of the values ​​used to fill the shift register (which can be of very high quality) at the clock speed, which can be very efficient and very fast compared to computerized systems that generate random values ​​of similar quality.

[0094] The illustrated system clock creates a computerized system's concept of the passage of time and provides a timing structure relative to which various components can operate synchronously. The system clock generates a clock signal and the various components functionally communicate with the clock signal so that they can perform operations in conjunction with a portion of the clock signal. The illustrated signal is a series of clock cycles (ticks) that alternate in a square wave between a first state (e.g., 0) and a second state (e.g., 1). The system clock includes a clock generator, which is generally an electronic oscillator that generates the clock signal. The clock generator is often a quartz piezoelectric oscillator, although alternative generators (e.g., tank circuits, and RC circuits) may be utilized. Although a system can have more than one clock and various components can operate according to different clocks (e.g., an internal clock vs. a system clock) or multiple versions of the same clock (e.g., using dividers and / or clock multipliers), the illustrated embodiment focuses on a single clock to which the illustrated components are connected.

[0095] The illustrated shift register may be any type of shift register described herein and / or may include any of the features, functions, structures, etc. described herein. The shift register may be loaded with random values ​​and may include structures that provide for the loading of further values ​​as needed. The illustrated shift register is configured to shift values ​​around the register relative to an index upon a change of the clock signal from a first state to a second state, and then output the value upon a change of the clock signal from the second state to the first state. Thus, on every cycle, a new set of random values ​​from the shift register or random values ​​are presented to the system.

[0096] The illustrated ALUs are functionally coupled to shift registers and any associated data feeds necessary for their operation. They are generally combinational digital circuits that perform arithmetic or bitwise operations on integer binary numbers, but can operate on other numbers and / or perform other operations as the system context requires. The inputs to the illustrated ALUs are loaded from the output of the shift registers and the output of the data feeds. The ALUs then output the result value from the operation (e.g., Mask, XOR, AND, Mod) that the particular ALU is configured to perform in opposition to the output timing of the shift register, i.e., at the change of the clock signal from a first state to a second state. Thus, when the shift register is outputting, the ALU is loading, and when the shift register is shifting, the ALU is outputting. The ALUs can be very simple, such as a Mask operation, where the output of the shift register determines which of two values ​​to output from two separate data feeds, which can be accomplished in a single internal clock cycle. The ALU may be more complex (e.g., Mod) and therefore may require its own internal clock running faster than the system clock shown in order to be able to output values ​​as shown.

[0097] The illustrated data feeds provide the ALU with the required output values ​​and therefore provide those values ​​when the associated ALU is ready to load. The data feeds may be shift registers, DMA, memory output / access, etc., and combinations thereof. The illustrated data feeds are shown to output values ​​once each clock cycle, but such rapid delivery of values ​​is not always necessary. As an example, if the ALU is performing a sequential Mod operation, the same denominator may be used many times (e.g., 100,000+) before a change is required. However, if the ALU is performing a Mask operation, new data feed values ​​from two different data feeds will be required every cycle. Thus, the outputs of the illustrated data feeds may be available every clock cycle, but are not necessarily loaded every time. The illustrated data feeds include a modify operation where the output value is changed to a new value. If a new value is required every time (e.g., Mask), the modify operation is performed on the other side of the output. If not required every cycle, the modify operation is performed on demand, which may be controlled by a controller.

[0098] The illustrated DRNUS loads the output of the ALU, thereby doing so in synchronization with the output timing of the associated ALU. The illustrated DRNUS receives new values ​​every clock cycle for all connected ALUs. This is useful because a single system may be able to generate multiple random values ​​every clock cycle, as illustrated, with multiple ALUs utilizing the same shift register. Thus, random value generation may occur at speeds that exceed the system clock. Furthermore, when shift registers and DMA are utilized, the illustrated system places minimal to zero burden on the computerized system's CPU resources, and thus random values ​​may be provided to applications or hardware devices (i.e., DRNUS) without causing significant slowdown of the computer system. This means that a system that has a high need for random values ​​can receive random values ​​of known quality essentially "for free."

[0099] In operation of the illustrated process, a system clock drives the timing of the operations of the illustrated components. When the illustrated clock signal rises, the shift register shifts and the ALU outputs an output value to the DRNUS where it is received. When the illustrated clock signal falls, the shift register (and data feed, if necessary) outputs a new value to the ALU, which loads the required value for further operation.

[0100] Advantageously, the illustrated system can generate a large number of random values ​​of known quality for use by one or more DRNUS at system clock speeds and without significant bottlenecks or burdens on the CPU. This is very different from known methods of generating random values ​​within computerized systems, where such known systems generate insufficient / limited quality / quantity of random values, cannot do so at clock speeds, and / or place significant burdens on the associated CPU or require a separate computing system with a separate CPU in order to operate.

[0101] FIG. 11 is a partial view of a computerized system including a data bus and FIG. 12 is a partial view of an output port of the computerized system of FIG. 11, for efficiently generating a stream of random numbers, according to one embodiment of the present invention. Shown are a controller, a data loop, and a number of data feeds (1-N), each functionally communicating with a data operator via a data bus 1100 (bus). The illustrated bus 1100 receives inputs via lines entering its left side and provides outputs therefrom exiting its right side. As shown in the figures herein, the lines attached to the left side of the bus are input lines and the lines attached to the right side are output lines (see FIGS. 13 and 14). Thus, the illustrated data flows across the bus from left to right. This illustrative convention used herein does not negate the understanding that multiplexed buses may be used in various embodiments of the present invention, with data flowing differently from the illustrated left to right.

[0102] The illustrated controller provides operational control over various portions of the illustrated system. It may include one or more of the features, structures, elements, components, etc. described herein. The illustrated controller communicates directly with an index of data loops via line 1102 and indirectly with a data operator via line 1104 that feeds into the bus. Although not shown, the controller may communicate directly and / or indirectly with each of the data loops and data feeds 1-N. Thus, the controller can issue commands to activate / deactivate / alter the operation of the connected modules (i.e., data loops, data feeds, and data operators).

[0103] The controller may issue commands to the operating units of the computerized system through such direct and / or indirect communication. Generally, direct lines allow for faster control that does not interrupt operations occurring in clock cycles. However, they require more circuitry, and generally more complex circuit designs. Furthermore, they are generally not "reconfigurable," so relying on direct lines may result in a hardware configuration that cannot be improved upon later. As shown in the illustrated computerized system, there may be a hybrid utilization of direct and indirect control lines.

[0104] The illustrated data loop includes a simple feedback loop-like array of random data with an index associated with a particular position in the loop-like array. There is also an output port that delivers a value from the loop-like array. Such a data loop may include one or more of the features, structures, elements, components, etc. described herein. The output port may include (e.g., in the case of a SIPO port) a set of parallel output lines, each of which may be individually switchable (e.g., bit masked) such that not all of the output bits are selectively provided to the bus. Even if the output is serial, the output lines may be selectively switched such that not all bits in the output series are provided to the bus.

[0105] The illustrated output line 1108 of the data loop output port 1110 includes a number of switchable lines 1200, 1201, 1202 through 1231, 1232. These lines are selectively switchable such that the output traveling on the lines may be selectively disabled. This switching may be controllable via commands from a controller and / or by operation of a script, function, etc. The switching may have to occur every clock cycle, or the switch may be reset after a given or predefined number of clock cycles, or may persist until the switching is changed. The topmost illustrated line 1200 represents bit position 0 of the parallel output of the data loop. The next lines 1201 and 1202 represent bit positions 1 and 2 of the parallel output of the data loop. The bottommost lines 1231 and 1232 represent bit positions N-1 and N of the parallel output of the data loop. If the parallel output of the data loop is a 32-bit output, then the bottommost lines 1231 and 1232 represent bit positions 31 and 32. As shown, each and every individual output line of the output of the data loop is switchable. As used herein, the term "bit masked" or "bit masking" when used in connection with parallel output lines refers to the ability to selectively switch parallel on-off output lines, whether or not accomplished by sending a command signal that uses bits to determine which bit values ​​are switched off (i.e., "masked") and on.

[0106] The illustrated data feeds provide values ​​to a data operator for use by it in manipulating values ​​from a data loop. Such data feeds may include one or more of the features, structures, elements, components, etc. described herein. The data feeds may be other data loops that may be similar to the illustrated data loop, may be pseudorandom number generators, may be data pools, outputs of data operators, combinations thereof, etc. The illustrated data feeds each include an output port 1106 that may be similar to and have a structure similar to that of the output port of the data loop. Thus. The output of the data feeds may be bit masked or otherwise partially provided to the bus instead of being provided as a complete set of bits.

[0107] The illustrated data operator operates on the output of the data loop and is operatively coupled to its output port via bus 1100. Such a data operator may include one or more of the features, structures, elements, components, etc. described herein. The data operator receives data from the bus via the data operator's input port and then operates on that data using active operators from the operator library. The controller may issue commands to the data operator (via line 1104 to bus 1100) from time to time to change which operators are active and thereby change the manipulation of data from the data loop. Also, the input port may be a parallel port and may be configured and / or communicate with the active operators to process different bit positions in different ways (e.g., bits 0-31 are values ​​that are manipulated and bits 32-63 are values ​​used by the active operators in their operations).

[0108] The illustrated bus 1100 is a communication system that transfers data between components of a computerized system. A bus may include one or more hardware components that transfer data, such as, but not limited to, wires, optical fibers, and registers. Additionally, the illustrated bus may include multiple bus systems, such as, but not limited to, a bus controller, a channel controller, memory, an I / O controller, a control bus, an address, bus, and / or a data bus. The illustrated bus receives parallel data input from active outputs of coupled modules and then provides parallel data outputs to connected modules (e.g., the illustrated data operators).

[0109] If the input data comes from multiple sources of random data simultaneously, the input data may be bit masked to allow for the aggregation of the random data across a single bus. As an example, if the Data Loop output port provides 32 parallel bits of random data that can be bit masked, and the Data Feed 1 output port provides 32 parallel bits of random data that can be bit masked, the bus may receive the aggregation of the random data from both sources simultaneously as a single 32-bit value that is passed to the Data Operator. As a non-limiting example, the first 16 bits of the 32-bit value from the Data Loop may be concatenated with the last 16 bits from the 32-bit value from Data Feed 1, thereby generating a single 32-bit value that includes the random bit values ​​from both sources. This may be accomplished by switching off the last 16 lines of the Data Loop output port and also switching off the first 16 lines of the Data Feed 1 output port.

[0110] 13 is a symbolic operational diagram of a data bus of a computerized system for generating random numbers, according to one embodiment of the present invention. A bus is shown having multiple output switching inputs (i.e., source A, source B, and source C), an N-bit wide bit register (shown as a 1-bit deep register), and a bus output. The illustrated bus allows for the aggregation of data from multiple sources, e.g., the aggregation of random data from sources of random data.

[0111] The 1-bit deep registers of the illustrated buses are shown for purposes of illustrating the data passed by the buses on a particular clock cycle, and are not intended to be limiting. It is understood that buses generally do not include registers of any width or depth, and thus many embodiments exist in which the buses have no registers. The illustrated registers include multiple bit positions: bit 0, bit 1, bit 2, bit 3 through bit N, bit N-1, and bit N-2. If the registers were 32 bits wide, then bit N would be bit 31, bit N-1 would be bit 30, and bit N-2 would be bit 29.

[0112] The letters (A, B, C) shown in the various bit positions represent sources of values ​​that will be in those bit positions at a particular time, and do not represent the actual values. As an example, in a binary computing system, the value of each bit position will be either 0 or 1. In the illustrated example, output switching source A has its own output bit positions for bit 0, bit 1, and bit N switched on, and bit positions for bit 2, bit 3, bit N-2, and bit N-1 switched off. Thus, only values ​​in the bit positions whose outputs are switched on can be passed to the bus. This may be represented by a masking value of (1100...001), where 1 corresponds to on and 0 corresponds to off.

[0113] Such a masking value may have been passed to source A by the controller, or control signals may have been sent to source A over time resulting in a masking effect consistent with the masking value. Similarly, source B's contribution to the aggregate value in the register may be represented by a masking value of (0001...100), and source C's contribution may be represented by a masking value of (0010...010). For clarity, the masking value is not the actual value in the register. As an example, the value in the register could be any value anyway, including but not limited to (1111...11) or (0000...000) or any variation therebetween, and the mask value simply represents which output lines of each source are switched on / off, thereby allowing / not allowing them to contribute to the aggregate value passed by the bus as an output, regardless of which modules are active and receiving such output.

[0114] FIG. 14 is a schematic diagram of a highly configurable computerized system for efficiently generating streams of random numbers, according to one embodiment of the present invention. The illustrated bus is connected via both inputs (input lines to its left) and outputs (output lines from its right) to each of the controller, DRNUS ports, data operators 1-N, data loops 1-N, and data feeds 1-N. Thus, depending on which modules are active (e.g., via control signals from the controller) and how the individual output lines of each module's parallel output lines are switched on / off, the system can manipulate data in a nearly infinite plethora of ways. The state of certain modules may be altered via control signals, and the structure of the data manipulation may be altered in real time.

[0115] As a non-limiting example, the illustrated computerized system may activate Data Feed 1 and Data Feed 2, with the first half of the output lines of Data Feed 1 switched off, the second half of the output lines of Data Feed 2 switched off, the inputs of Data Loop 1 activated, and all other modules inactive in the system. Such a configuration would concatenate the second half of each output of Data Feed 1 with the first half of the output of Data Feed 2 ("dropping" the remaining bits "onto the floor") and load those values ​​into Data Loop 1. Thus, if the values ​​from Data Feed 1 and Data Feed 2 are random values, Data Loop 1 is loaded with random values ​​that are aggregated from Data Feeds 1 and 2. Alternatively, the computerized system may activate the output lines of Data Feeds 1 and 2 in modes different from those described above to perform other forms of aggregation, including but not limited to other forms of concatenation, bit selection, and dynamic mixing of N data feeds.

[0116] Once enough clock cycles have elapsed to complete the loading of Data Loop 1, the illustrated controller deactivates Data Feeds 1 and 2 and the input to Data Loop 1, and activates the outputs of Data Loop 1 and Data Feeds 3 and 4 and the input to Data Operator 1 from which the MOD operator may be selected. The output lines of Data Loop 1 and Data Feed 3 may be switched on in a bit position configuration on the bus such that values ​​from them are aggregated into the numerator of the MOD operation, and the output line of Data Feed 4 is switched on to provide the denominator of the desired bit width. Data Feed 4 may then be deactivated so that it does not continue to provide new values, but instead holds the same value for many clock cycles, and Data Loop 1 and Data Feed 3 may continue to provide a new value every clock cycle, thereby aggregating the new value. The system may alternate this configuration with a configuration in which the output of Data Operator 1 and the inputs of both the DRNUS port and Data Loop 2 are activated with all other modules disabled. Thus, such a system supplies the values ​​required to generate new values ​​to a data operator 1, and the output of the data operator 1 is then supplied to each DRNUS (via the DRNUS port) and loaded into the data loop 2.

[0117] Such a system, initially loaded with only a pair of data feeds, can then load an unlimited number of data loops and provide an unlimited source of values ​​for any number of DRNUS. Moreover, identical systems will not produce the same values ​​unless configured in exactly the same way. Thus, such systems can be mass-produced and, further, can be configured in a manner that allows for repeatable generation of diverse values ​​between systems if they are configured in the same way. If the data feeds and / or data loops of two different computerized systems have the same values ​​and are configured in the same way, they can produce the same output value.

[0118] Furthermore, if the initialized data feed is of a particular quality of random values, the systems may be configured to load identical data loops (both across two identically configured systems) with unlimited random values ​​of the same quality, which may then be utilized to very efficiently generate many more unlimited values ​​of the same quality (and also identical to each other across two identically configured systems). However, a third party system with the exact same initialized data feed would not be able to replicate the same random value output stream without knowing the other system's configuration (including output masking and random value aggregation patterns).

[0119] Such computerized systems may thus be mass-produced in hardware and widely distributed with an initial data feed known to any and all parties. Moreover, these same systems are capable of generating streams of random values ​​that are unpredictable when the configuration details are unknown and highly reliably replicable (while still random) when the configuration details are known. Such computerized systems may be advantageously utilized in essentially any situation in which random values ​​are useful, and may be configured to generate such values ​​quickly and efficiently, without significant interruption to the clock cycles of the associated systems, and in sufficient quantity and quality to suit the situation of use.

[0120] The computerized system may include a process for resetting the aggregation mask and / or other configuration characteristics of the computerized system, which may include one or more of the following steps:

[0121] - The control component identifies that it is time to reset the aggregation mask. The control component uses the random value stream to dynamically select new properties for the aggregate mask (e.g., run-time duration of the mask, specific bit selection for the mask) or other features of the computerized system (e.g., values ​​of the MOD numerator and / or denominator, run-time duration of the MOD numerator / denominator values).

[0122] A control component controls the aggregation mask to match dynamically selected characteristics. It will be understood that the above-described embodiments are merely illustrative of the application of the principles of the present invention. The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is therefore indicated by the appended claims rather than the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0123] The following is a non-limiting, exemplary description of embodiments. 1. A method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system, comprising: a. loading a data loop with random data from a source of random data, the data loop comprising: i. a looped array of stored values; and ii. Index loading a data loop, b. reading a multi-bit value from a data loop with respect to an index position in a looped array; c. performing a first data operation on the multi-bit value to thereby derive an induced random number from the multi-bit value; d. moving the index with respect to the looped array to a different position within the looped array; Repeating eb~d, thereby generating a series of induced random numbers. A method comprising:

[0124] 2. The method of claim 1, wherein the data loop is a shift register. 3. The method of claim 2, wherein the shift register is a universal shift register.

[0125] 4. The method of any of statements 1-15, wherein the different locations are adjacent locations. 5. The method of any of statements 1-15, wherein the data operation is a decoupling operation selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD.

[0126] 6. The method of any of claims 1 to 15, wherein the source of the random data is the output of the method of claim 1.

[0127] 7. The method of any of statements 1-15, wherein loading the data loop is performed by direct memory access.

[0128] 8. The method of any of statements 1-15, further comprising performing a second data operation on the multi-bit value simultaneously with performing the first data operation, thereby deriving a second derived random number from the multi-bit value.

[0129] 9. A method according to any of statements 1-15, in which a second computing system independently performs the steps of statement 1 using a substantially identical source of random data such that the data loop of the second computing system identically loads the data loop of statement 1, and using substantially identical data operations such that the resulting induced random numbers are the same as those of statement 1, thereby generating a second series of induced random numbers that are identical to the series of induced random numbers of statement 1.

[0130] 10. The method of claim 9, wherein the second computing system is structurally different from the computing system of statement 1 in at least one type of data loop, read operator, shifter, controller type, and data loop loader.

[0131] 11. The method of any of statements 1-15, wherein the data operation is a MOD operation performed on a multi-bit value as a numerator and a denominator having fewer bits than the multi-bit value.

[0132] 12. The method of claim 11, wherein the denominator is a value obtained directly or derived from a source of random data.

[0133] 13. The method of claim 11, wherein the denominator is greater than a desired range of induced random numbers. 14. The method of any of statements 1-15, further comprising automatically selecting a decoupling operation from a plurality of decoupling operations according to a controller.

[0134] 15. The method of claim 14, wherein the controller comprises one or more of a programmable logic circuit, a script, and a driver.

[0135] 16. A computerized system for efficiently generating streams of random numbers, comprising: A data loop comprising: i. A simple feedback loop arrangement of random data; ii. Indexes, and iii. An output port that reads a value from the simple feedback loop array based on the relative position of the index to the simple feedback loop array. A data loop including: b. A data operator, i. Input, and ii. has an output that provides access to the output value from the data operator; a data operator operatively coupled to an output port such that values ​​from the output port are provided as input values ​​to the data operator; c. an incrementer operatively coupled to the data loop for shifting an index for a simple feedback loop-like array; A system comprising:

[0136] 17. The system of any of statements 16-23, wherein the data loop further includes an input port.

[0137] 18. The system of any of statements 16-23, wherein the value from the output port is a multi-bit value.

[0138] 19. The system of any of statements 16-23, wherein the data loop is a universal shift register.

[0139] 20. The system of any of statements 16-23, wherein the data loop is a shift register.

[0140] 21. The system of any of statements 16-23, wherein the data operator is a decoupling operation selected from the group consisting of XOR, Mask Generator, Data MUX, and MOD.

[0141] 22. The system of any of statements 16-23, further comprising a second data loop having an input port operatively coupled to the output of the data operator such that an output value from the data operator is input to the second data loop.

[0142] 23. The system of any of statements 16-23, further comprising a source of random data operatively coupled to the input port of the data loop such that the looped array of random data is supplied with data from the source of random data.

[0143] Thus, while the invention has been fully described above with specificity and detail in connection with what are presently considered to be the most practical and preferred embodiments of the invention, it will be apparent to those skilled in the art that numerous modifications, including but not limited to changes in size, material, shape, form, function, mode of operation, assembly, and use, may be made without departing from the principles and concepts of the invention as set forth in the claims. Moreover, it is contemplated that embodiments may be limited to consist of, or consist essentially of, one or more of the features, functions, structures, and methods described herein.

Claims

1. 1. A method for quickly and efficiently generating a sequence of random numbers from a source of random numbers in a computing system, comprising: a. loading a data loop with random data from a source of random data, said data loop comprising: i. a looped array of stored values; and ii. Index Including, b. reading a multi-bit value from said data loop for said index position in said looped array; c) performing a first data operation on the multi-bit value to thereby derive a derived random number from the multi-bit value; d. moving the index with respect to the looped array to a different position within the looped array; e. Repeating b through d, thereby generating a series of induced random numbers; A method comprising:

2. The method of claim 1 , wherein the data loop is a shift register.

3. The method of claim 2 , wherein the shift register is a universal shift register.

4. The method of claim 1 , wherein the different locations are adjacent locations.

5. The method of claim 1 , wherein the source of the random data is the output of the method of claim 1 .

6. The method of claim 1 , wherein the loading of the data loop is performed by direct memory access.

7. 2. The method of claim 1, further comprising performing a second data operation on the multi-bit value simultaneously with performing the first data operation, thereby deriving a second derived random number from the multi-bit value.

8. 2. The method of claim 1, wherein a second computing system independently performs the steps of claim 1 using a substantially identical source of random data such that the data loop of the second computing system loads identically to the data loop of claim 1, and the resulting induced random numbers are the same as the induced random numbers of claim 1, using substantially the same data operations to generate a second series of induced random numbers that are identical to the series of induced random numbers of claim 1.

9. 9. The method of claim 8, wherein the second computing system is structurally different from the computing system of claim 1 in at least one type of data loop, read operator, shifter, controller type, and data loop loader.

10. 2. The method of claim 1, wherein the data operation is a MOD operation performed on the multi-bit value as the numerator and a denominator having fewer bits than the multi-bit value.

11. The method of claim 1 , further comprising automatically selecting the decoupling operation from a plurality of decoupling operations according to a controller.

12. 1. A computerized system for efficiently generating streams of random numbers, comprising: a. A data loop comprising: i. A simple feedback loop sequence of random data; ii. Index; and an output port that reads a value from the simple feedback loop array based on the relative position of the index with respect to the simple feedback loop array; A data loop including: b. A data operator: i. Input, and ii. An output that provides access to the output value from said data operator a data operator having a data input port and operatively coupled to the data output port such that values ​​from the data output port are provided as input values ​​to the data operator; c. an incrementer operatively coupled to the data loop for shifting the index relative to the simple feedback loop array; A system comprising:

13. The system of claim 12 , wherein the value from the output port is a multi-bit value.

14. The system of claim 12 , wherein the data loop is a shift register.

15. 13. The system of claim 12, further comprising a second data loop having an input port operatively coupled to the output of the data operator such that an output value from the data operator is input to the second data loop.

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