Datapath circuits and methods
JP2025505783APending Publication Date: 2025-02-28INFINEON TECHNOLOGIES LLC
Patent Information
- Application Number
- JP2024548478
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-06
- Filing Date
- 2023-02-15
- Publication Date
- 2025-02-28
AI Technical Summary
Benefits of technology
【0010】 本発明およびその利点のより完全な理解のために、ここで、添付の図面と併せて以下の説明を参照する。
✦ Generated by Eureka AI based on patent content.
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Abstract
In one embodiment, a memory circuit includes a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store the read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits, and is configured to select one data input of the N data inputs of the data multiplexer to connect to a data output of the data multiplexer based on a select input of the data multiplexer. The data path is configured to cause propagation of data from the data output of the data multiplexer to the data input of the logic circuit.
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Citation Information
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