Semiconductor device and semiconductor device manufacturing method

Abstract

The embodiments of this application provide a semiconductor device and a method for manufacturing the semiconductor device, which includes a substrate, an epitaxial layer located on one side of the substrate, a doped region formed on a surface of the epitaxial layer remote from the substrate, the epitaxial layer including an active area and a termination area surrounding the active area, a passivation layer covering the termination area, the passivation layer having a window formed therein corresponding to the active area, and a metal layer covering the window and the inner edge of the passivation layer forming the window and forming a Schottky contact with the active area within the window. By using the solution of the embodiments of this application, the structure of the passivation layer is placed under the metal layer, so that the passivation layer does not need to wrap around the metal layer, thereby reducing the number of corners formed in the passivation layer. This can reduce the stress on the passivation layer during temperature change scenarios such as thermal cycling, making it less susceptible to cracks, thereby preventing device failure caused by moisture ingress through the cracks and improving device robustness in high temperature and humidity environments.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202210176403.6, entitled “Semiconductor Device and Semiconductor Device Manufacturing Method,” filed with the China State Intellectual Property Administration on February 24, 2022, which is hereby incorporated by reference in its entirety.

[0002] This application relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices. [Background technology]

[0003] Power electronics is an important technology for power conversion and control, of which power semiconductor devices are the core and foundation. Due to its excellent physical and chemical properties, silicon carbide (SiC) can be used to fabricate high-temperature and high-voltage power semiconductor devices to develop power electronics systems with higher power density and lower power consumption at low manufacturing costs.

[0004] A power semiconductor device includes an active region and a termination region. The termination region can be used to extend the high electric field in reverse bias to increase the breakdown voltage. In addition, a passivation layer needs to be disposed on the termination region for protection, in order to prevent moisture ingress and other undesirable factors arising under the action of high electric field from affecting the reliability of the device.

[0005] In existing semiconductor devices, the structure of the passivation layer has serious stress concentration problems and is therefore prone to cracking due to excessive stress exerted in temperature change scenarios such as thermal cycling (especially in extreme thermal cycling conditions). As a result, moisture intrusion paths are formed, which can cause the semiconductor device to fail, thereby affecting the reliability of the product. Summary of the Invention

[0006] The embodiments of the present application provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the stress on the passivation layer in temperature change scenarios, such as thermal cycling (especially in extreme thermal cycling conditions), such that cracks are less likely to occur, which can prevent device failure caused by moisture ingress through cracks, and thereby improve the robustness of the device in high temperature and high humidity environments.

[0007] Therefore, the embodiments of this application use the following technical solutions.

[0008] According to a first aspect, an embodiment of the present application provides a semiconductor device comprising: a substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer having a doped region formed on a surface of the epitaxial layer remote from the substrate, the epitaxial layer including an active region and a termination region surrounding the active region; a passivation layer covering the termination region, the passivation layer having a window formed therein corresponding to the active region; and a metal layer covering the window and an inner edge of the passivation layer forming the window, and forming a Schottky contact with the active region within the window.

[0009] In the semiconductor device of this embodiment of this application, the passivation layer is disposed between the metal layer and the epitaxial layer. In other words, the structure of the passivation layer is placed under the metal layer. Thus, the passivation layer does not need to wrap around the outer edge of the metal layer, thereby reducing the number of corners formed in the passivation layer. This can reduce the stress on the passivation layer in temperature change scenarios such as thermal cycling (especially in extreme thermal cycling conditions), resulting in less cracks, which prevents moisture intrusion through the cracks and improves the robustness of the semiconductor device in high temperature and high humidity environments.

[0010] In one possible implementation, the passivation layer includes a first passivation layer, a second passivation layer, and a third passivation layer that are stacked in order and arranged in contact with each other, the first passivation layer is located between the epitaxial layer and the second passivation layer, and the material of the second passivation layer is different from both the material of the first passivation layer and the material of the third passivation layer. In other words, in this implementation, the passivation layer can be arranged in a three-layer structure. The material of the second passivation layer is different from both the material of the first passivation layer and the material of the third passivation layer. Therefore, their thermal expansion coefficients are also different. In other words, the difference between the thermal expansion coefficients can be used to optimize the structure of the passivation layer, which further prevents the passivation layer from cracking, thereby better preventing moisture intrusion.

[0011] In one possible implementation, a first window corresponding to the active region is disposed in the first passivation layer, a second window corresponding to the active region is disposed in the second passivation layer, the second window is located outside the first window, and a third passivation layer includes a first portion located on a surface of the second passivation layer remote from the first passivation layer, a second portion covering the inner peripheral wall of the second window, and a third portion disposed in a stacked manner on the first passivation layer, and the third window corresponding to the active region is disposed on the third portion of the third passivation layer, and the first window and the third window correspond to each other and communicate with each other to form a window. Thus, the inner edge of the first passivation layer forming the first window and the inner edge of the third passivation layer forming the third window are stacked and in contact with each other and encapsulate the inner edge of the second passivation layer forming the second window.

[0012] In one possible implementation, the material of the first passivation layer and the material of the third passivation layer are the same and include silicon oxide, and / or the material of the second passivation layer includes silicon nitride. The CTE value of metal is relatively large, the CTE value of silicon nitride is relatively small, and the CTE value of silicon oxide is between them. Thus, the third passivation layer is made to completely envelop the inner edge of the second passivation layer close to the active area. On the one hand, this can relieve the deformation stress on the metal layer in a thermal cycle scenario, and on the other hand, it can protect the second passivation layer from crack generation.

[0013] In one possible implementation, the thickness of the third passivation layer is smaller than the thickness of the first passivation layer and the thickness of the second passivation layer. In other words, in this implementation, the second passivation layer has a certain thickness, and a corner is formed when the third passivation layer wraps around the inner edge of the second passivation layer near the active area. Therefore, by making the thickness of the third passivation layer smaller than the thickness of the first passivation layer and the thickness of the second passivation layer, the stress when deformation occurs at the corner due to temperature change can be reduced, and as a result, cracks are less likely to occur, thereby improving the reliability of the device.

[0014] In one possible implementation, the semiconductor device includes a protective layer covering the passivation layer and the outer edge of the metal layer. In other words, in this implementation, a protective layer can be disposed to better protect the semiconductor device. For example, the protective layer can be a PI adhesive layer, i.e., polyimide.

[0015] According to a second aspect, an embodiment of the present application provides a method of manufacturing a semiconductor device, the method comprising forming a doped region on a surface of an epitaxial layer remote from a substrate, the epitaxial layer being on one side of the substrate and including an active area and a termination area surrounding the active area, disposing a passivation layer on the termination area, the passivation layer having a window corresponding to the active area, and disposing a metal layer on the window and on an inner edge of the passivation layer forming the window, the metal layer forming a Schottky contact with the active area within the window.

[0016] In one possible implementation, the passivation layer includes a first passivation layer, a second passivation layer, and a third passivation layer, and disposing the passivation layer on the termination region includes forming a first dielectric layer and a second dielectric layer, in sequence, on the epitaxial layer, where a material of the first dielectric layer is different from a material of the second dielectric layer, etching a second window in a portion of the second dielectric layer corresponding to the active region to form a second passivation layer, forming a third dielectric layer over the second window and over the second passivation layer, and etching the third dielectric layer in the second window. a layer covers an inner peripheral wall of the second window and is stacked on the first dielectric layer to contact the first dielectric layer, the material of the second dielectric layer being different from the material of the third dielectric layer, and etching the first dielectric layer and the third dielectric layer at a position inside the second window corresponding to the active region, the etching including: etching a third window in the third dielectric layer to form a third passivation layer; and etching a first window in the first dielectric layer to form a first passivation layer, the first window and the third window corresponding to each other and communicating with each other to form a window.

[0017] In one possible implementation, the first window and the third window are formed using a single etching process.

[0018] In one possible implementation, the method further includes disposing a protective layer over the passivation layer and over an outer edge of the metal layer.

[0019] Other features and advantages of the present invention are described in detail in the following specific embodiment sections. [Brief description of the drawings]

[0020] The following briefly describes the accompanying drawings that are necessary to be used in describing the embodiments or the prior art. [Figure 1A] 1 is a schematic diagram of a top surface structure of a semiconductor device. [Figure 1B] 1B is a schematic diagram of a cross-sectional structure of the semiconductor device shown in FIG. 1A taken along line AA. [Diagram 2] FIG. 2 is a schematic diagram of a top surface structure of a semiconductor device in which a protective layer is partially removed according to an embodiment of the present application. [Diagram 3] 3 is a schematic diagram of a cross-sectional structure of the semiconductor device shown in FIG. 2 taken along line BB. [Figure 4] 1 is a flow chart of a semiconductor device manufacturing method according to one embodiment of the present application. [Diagram 5] 5 is a specific flowchart of step S402 of the method for manufacturing the semiconductor device shown in FIG. [Figure 6] 6 to 10 are specific flow charts of step S402 of the semiconductor device manufacturing method shown in FIG. [Figure 7] 6 to 10 are specific flow charts of step S402 of the semiconductor device manufacturing method shown in FIG. [Figure 8] 6 to 10 are specific flow charts of step S402 of the semiconductor device manufacturing method shown in FIG. [Figure 9] 6 to 10 are specific flow charts of step S402 of the semiconductor device manufacturing method shown in FIG. [Figure 10] 6 to 10 are specific flow charts of step S402 of the semiconductor device manufacturing method shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the technical solutions in the embodiments of this application will be described with reference to the accompanying drawings in the embodiments of this application.

[0022] In the description of this application, locations or positional relationships indicated by terms such as "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," and "outer" are based on locations or positional relationships shown in the accompanying drawings, and are intended only to facilitate and simplify the description of this application, instead of indicating or implying that the devices or components referenced are required to be provided or constructed and operated in a particular location, and therefore should not be understood as limitations on this application.

[0023] It should be noted that in the description of this application, unless otherwise expressly stated or limited, the terms "mount", "link" and "connect" should be understood in a broad sense, for example, a fixed connection, a detachable connection, a butt joint connection or an integral connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific case.

[0024] The acronyms and abbreviations and important terms used in the embodiments of this application are explained in detail below: SBD: Schottky barrier diode; MOSFET: metal-oxide-semiconductor field-effect transistor; PI: polyimide; TC: thermal cycle; CTE: coefficient of thermal expansion.

[0025] It should be noted that, unless contradiction occurs, the embodiments and features in the embodiments of this application can be combined with each other. Hereinafter, this application will be described in detail with reference to the accompanying drawings by using embodiments.

[0026] As the most widely applied SiC power device in industry, SiC SBDs have no minority carrier accumulation effect during the switching process. The reverse recovery current of SiC SBDs mainly depends on the junction capacitance of the depletion region, and the reverse recovery charge and reverse recovery loss are very small. Therefore, the switching speed of SiC SBDs is improved and the switching loss is reduced. This greatly improves the switching frequency in application circuits, thereby providing nearly ideal dynamic performance. SiC SBDs are widely applied in rectifiers, photovoltaic inverters, automotive electric drive systems, and other fields.

[0027] FIG. 1A is a schematic diagram of a top view structure of a semiconductor device. FIG. 1B is a schematic diagram of a cross-sectional structure of the semiconductor device shown in FIG. 1A along line AA. The semiconductor device may be an SBD. It may be understood that the semiconductor device may alternatively be other devices, such as a pin diode. As shown in FIG. 1A and FIG. 1B, the semiconductor device includes a substrate 10, an epitaxial layer 20, a passivation layer 30, a metal layer 40, and a PI adhesion layer 50. The substrate 10 may be Si or SiC. The passivation layer 40 may include silicon oxide or silicon nitride.

[0028] As shown in FIG. 1B, the epitaxial layer 20 includes an active region and a termination region. The passivation layer 30 includes a first passivation layer 301, a second passivation layer 302, and a third passivation layer 303. The first passivation layer 301 covers the termination region. The metal layer 40 covers the active region and the inner edge of the first passivation layer 301 close to the active region. The second passivation layer 302 and the third passivation layer 303 are stacked in order to cover the portion of the first passivation layer 301 on which the metal layer 40 is not disposed, and to cover the outer edge of the metal layer 40. In other words, the second passivation layer 302 and the third passivation layer 303 directly cover the metal layer 40. A PI adhesion layer 50 covers the second passivation layer 302 , the third passivation layer 303 and the outer edge of the metal layer 40 .

[0029] The inherent thermal properties of layers of materials in semiconductor devices are not consistent. In reliability testing procedures, such as thermal cycling, the CTEs of molding compounds, PI adhesives, and semiconductor materials (such as substrate Si or SiC) are not matched, resulting in shear stress. Over a certain number of cycles, the stress even exceeds the yield strength of the metal material, causing it to deform. Thus, materials with poor ductility, such as silicon oxide or silicon nitride, in the second passivation layer 302 and the third passivation layer 303 covering the metal layer 40 are prone to crack generation due to excessive stress at the bending positions that encase the metal layer 40. As a result, moisture ingress paths are formed, which can cause the semiconductor device to fail and affect product reliability.

[0030] In addition, compared with integrated circuit chips, the metal layer on the surface of power devices is thicker and larger in size, so the deformation is more serious.Compared with Si materials, SiC materials have a larger difference in CTE value with the passivation layer materials, so the problem of stress concentration is more serious.

[0031] In view of this, the embodiments of this application provide a semiconductor device and a semiconductor device manufacturing method, in which a passivation layer is disposed between a metal layer and an epitaxial layer. In other words, the structure of the passivation layer is placed under the metal layer. Thus, the passivation layer does not need to wrap around the outer edge of the metal layer, thereby reducing the number of corners formed in the passivation layer. This can reduce the stress on the passivation layer in temperature change scenarios such as thermal cycling (especially in extreme thermal cycling conditions), resulting in less cracks, thereby preventing moisture intrusion through the cracks and improving the robustness of the semiconductor device in high temperature and high humidity environments. In the embodiments of this application, the semiconductor device can be a SiC power device, such as a diode or a MOS transistor. In the following, a SiC SBD power device is used as an example for illustration.

[0032] FIG. 2 is a schematic diagram of a top structure of a semiconductor device with a protective layer partially removed according to an embodiment of this application. FIG. 3 is a schematic diagram of a cross-sectional structure of the semiconductor device shown in FIG. 2 along line BB. As shown in FIG. 3, the semiconductor device includes a substrate 1, an epitaxial layer 2, a passivation layer 3, and a metal layer 4. The epitaxial layer 2 is located on one side of the substrate 1. A doped region is formed on the surface of the epitaxial layer 2 farther from the substrate 1, and the epitaxial layer 2 includes an active region and a termination region surrounding the active region. For example, the substrate 1 has a first type of impurity, the epitaxial layer 2 has a first type of impurity, and the doped region of the epitaxial layer 2 has a second type of impurity. In addition, the material of the substrate 1 and the material of the epitaxial layer 2 are not limited and may be, for example, Si or SiC.

[0033] A passivation layer 3 covers the termination region, and a window W corresponding to the active region is formed in the passivation layer 3. A metal layer 4 covers the window W and the inner edge of the passivation layer 3 close to the active region, i.e., the inner edge forming the window W, and forms a Schottky contact with the active region within the window W. Specifically, the metal layer 4 is disposed in a stacked manner on the active region and covers the inner edge of the passivation layer 3 close to the active region. In other words, the metal layer 4 is bonded to the inner edge of the passivation layer 3 close to the active region, and the inner edge of the passivation layer 3 is located between the metal layer 4 and the epitaxial layer 2.

[0034] In addition, the semiconductor device may further include a protective layer 5 covering the passivation layer 3 and the outer edge of the metal layer 4. For example, the protective layer 5 may be a PI adhesive layer, i.e., polyimide. In FIG. 2, the protective layer 5 between the inner edge of the passivation layer 3 and the outer edge of the passivation layer 3 is removed to show the specific structure of the metal layer 4 and the passivation layer 3. As shown in FIG. 2, the passivation layer 3 and the PI adhesive layer 5 are in a ring-like structure arranged around the metal layer 4.

[0035] Referring again to FIG. 3, in order to better mitigate moisture intrusion, the passivation layer 3 may include a first passivation layer 31, a second passivation layer 32, and a third passivation layer 33, which are stacked in sequence and arranged in contact with each other. The first passivation layer 31 is located between the epitaxial layer 2 and the second passivation layer 32, and the material of the second passivation layer 32 is different from both the material of the first passivation layer 31 and the material of the third passivation layer 33. For example, the material of the first passivation layer 31 and the material of the third passivation layer 33 are the same and include silicon oxide. The material of the second passivation layer 32 includes silicon nitride. It can be understood that other materials may be selected instead for the first passivation layer 31, the second passivation layer 32, and the third passivation layer 33, if necessary.

[0036] A first window W1 corresponding to the active region is disposed in the first passivation layer 31, and a second window W2 corresponding to the active region is disposed in the second passivation layer 32, with the second window W2 located outside the first window W1. The third passivation layer 33 includes a first portion located on the surface of the second passivation layer 32 farther from the first passivation layer 31, a second portion covering the inner peripheral wall of the second window W2, and a third portion laminated and disposed on the first passivation layer 31. A third window W3 corresponding to the active region is disposed in the third portion of the third passivation layer 33, and the first window W1 and the third window W3 correspond to each other and communicate with each other to form a window W.

[0037] Thus, the inner edge of the first passivation layer 31 forming the first window W1 and the inner edge of the third passivation layer 33 forming the third window W3 can be stacked and in contact with each other and encapsulate the inner edge of the second passivation layer 32 forming the second window W2. In other words, the inner edge of the first passivation layer 31 and the inner edge of the third passivation layer 33 extend beyond the inner edge of the second passivation layer 32. The extended portions of the first passivation layer 31 and the third passivation layer 33 are stacked and in contact with each other so that the first passivation layer 31 and the third passivation layer 33 completely encapsulate the second passivation layer 32. The CTE value of metal is relatively large, the CTE value of silicon nitride is relatively small, and the CTE value of silicon oxide is between them. Thus, the third passivation layer 33 is made to completely encase the inner edge of the second passivation layer 32 close to the active area, which on the one hand can relieve the deformation stress on the metal layer 4 in a thermal cycling scenario, and on the other hand can protect the second passivation layer 32 so that it is less susceptible to cracking.

[0038] Further, the second window W2 can be etched using an etching process for forming the second passivation layer 32, and the first window W1 and the third window W3 can be etched simultaneously using another etching process for forming the first passivation layer 32 and the third passivation layer 33.

[0039] Also, for example, as shown in FIG. 3, the outer edges of the first passivation layer 31 away from the active region, the outer edges of the second passivation layer 32 away from the active region, and the outer edges of the third passivation layer 33 away from the active region can be arranged in alignment. In another example, the outer edge of the first passivation layer 31 away from the active region and the outer edge of the third passivation layer 33 away from the active region are stacked and in contact with each other, wrapping the outer edge of the second passivation layer 32 away from the active region. In other words, the structure of the outer edge of the passivation layer 3 may be the same as the structure of the inner edge of the passivation layer 3.

[0040] Also, the thicknesses of the first passivation layer 31, the second passivation layer 32, and the third passivation layer 33 can be selected as needed. For example, the value range of the thickness H1 of the first passivation layer 31 can be 0.5 μm ≤ H1 ≤ 1.5 μm, the value range of the thickness H2 of the second passivation layer 32 can be 0 μm < H2 ≤ 1 μm, and the value range of the thickness H3 of the third passivation layer 33 can be 0 μm < H3 ≤ 0.5 μm.

[0041] Considering that an excessive thickness of the third passivation layer 33 will aggravate bending deformation of the outer edge of the metal layer 4 located on the passivation layer 3, making the outer edge of the metal layer 4 prone to crack generation in a thermal cycle scenario, the third passivation layer 33 may be set to a relatively small thickness. For example, the thickness of the third passivation layer 33 may be smaller than the thickness of the first passivation layer 31 and the thickness of the second passivation layer 32. The second passivation layer 32 has a certain thickness, and a corner is formed when the third passivation layer 33 wraps around the inner edge of the second passivation layer 32 close to the active area. Therefore, by making the thickness of the third passivation layer 33 smaller than the thickness of the first passivation layer 31 and the thickness of the second passivation layer 32, the stress when deformation occurs at the corner position due to temperature change, for example, in a thermal cycle scenario, can be reduced, and as a result, cracks are less likely to occur, thereby improving the reliability of the device.

[0042] In the semiconductor device of this embodiment of this application, the phenomenon of stress concentration at the corners of the passivation layer is alleviated, so that cracks are less likely to occur. Specifically, the passivation layer is disposed between the metal layer and the epitaxial layer. In other words, the structure of the passivation layer is placed under the metal layer. Thus, the passivation layer does not need to wrap around the outer edge of the metal layer, thereby reducing the number of corners formed in the passivation layer. This can reduce the stress on the passivation layer in temperature change scenarios such as thermal cycling (especially in extreme thermal cycling conditions). In addition, the structure of the passivation layer is further optimized using the difference between the thermal expansion coefficients to prevent the passivation layer from cracking, thereby preventing moisture intrusion through the cracks and improving the robustness of the semiconductor device in high temperature and high humidity environments.

[0043] 4 is a flow chart of a semiconductor device manufacturing method according to an embodiment of this application. As shown in FIG. 4, the manufacturing method includes the following steps:

[0044] S401: Form a doped region on a surface of an epitaxial layer 2 remote from a substrate 1, the epitaxial layer 2 being located on one side of the substrate 1 and including an active region and a termination region surrounding the active region.

[0045] Specifically, first, the doping positions on the epitaxial layer 2 can be determined using a mask, and then ion implantation is performed at the doping positions. After the ion implantation, high temperature annealing is performed to form the doped regions.

[0046] S402: Dispose a passivation layer 3 on the termination area, where the passivation layer 3 has a window corresponding to the active area.

[0047] S403: Dispose a metal layer 4 on the window W and on the inner edge of the passivation layer 3 forming the window W, the metal layer 4 forming a Schottky contact with the active area in the window W.

[0048] S404: A protective layer 5 is disposed on the passivation layer 3 and on the outer edge of the metal layer 4.

[0049] In this embodiment of the application, the structure of the passivation layer of the semiconductor device is optimized so that the passivation layer does not encapsulate the metal layer, thus the passivation layer has a small number of corners, which can reduce the stress on the passivation layer under extreme thermal cycling conditions, thereby preventing the passivation layer from cracking, and improving the robustness of the device in high temperature and high humidity environments.

[0050] Figure 5 is a specific flowchart of step S402 of the semiconductor device manufacturing method shown in Figure 4. Figures 6 to 10 are specific flowcharts of step S402 of the semiconductor device manufacturing method shown in Figure 5. The passivation layer 3 may include a first passivation layer 31, a second passivation layer 32, and a third passivation layer 33. In this case, as shown in Figure 5, S402 may specifically include the following sub-steps:

[0051] S4021: A first dielectric layer 3a and a second dielectric layer 3b are formed in this order on the epitaxial layer 2, and the material of the first dielectric layer 3a is different from the material of the second dielectric layer 3b.

[0052] Before S4021 is performed, as shown in Figure 6, an epitaxial layer 2 is formed on one side of a substrate 1, and a doped region is formed on the surface of the epitaxial layer 2 away from the substrate 1. After S4021 is performed, as shown in Figure 7, a first dielectric layer 3a and a second dielectric layer 3b are formed in this order on the epitaxial layer 2.

[0053] Also, the first dielectric layer 3a and the second dielectric layer 3b may be sequentially formed on the epitaxial layer 2 through deposition. Specifically, the first dielectric layer 3a is first formed through deposition, and then the second dielectric layer 3b is formed through deposition.

[0054] S4022: Etch a second window W2 in the portion of the second dielectric layer 3b corresponding to the active area to form a second passivation layer 32, as shown in FIG.

[0055] S4023: As shown in FIG. 9, a third dielectric layer 3c is formed on the second window W2 and on the second passivation layer 32, and within the second window W2, the third dielectric layer 3c covers the inner wall of the second window W2 and is stacked on and in contact with the first dielectric layer 3a, and the material of the second dielectric layer 3b is different from the material of the third dielectric layer 3c.

[0056] In particular, the third dielectric layer 3c may be formed on the first dielectric layer 3a and the second passivation layer 32 through deposition.

[0057] S4024: As shown in FIG. 10, etching is performed on the first dielectric layer 3a and the third dielectric layer 3c at a position inside the second window W2 corresponding to the active region, the etching including etching a third window W3 in the third dielectric layer 3c to form a third passivation layer 33, and etching a first window W1 in the first dielectric layer 3a to form a first passivation layer 31, and the first window W1 and the third window W3 correspond to each other and communicate with each other to form a window W.

[0058] Thus, the inner edge of the first passivation layer 31 near the active area (i.e., the inner edge forming the first window W1) and the inner edge of the third passivation layer 33 near the active area (i.e., the inner edge forming the third window W3) are stacked and in contact, and the inner edge of the first passivation layer 31 near the active area and the inner edge of the third passivation layer 33 near the active area envelop the inner edge of the second passivation layer 32 near the active area.

[0059] The material of the first dielectric layer 3a and the material of the second dielectric layer 3b are different. Therefore, different etching processes can be used. Specifically, first, a second passivation layer 32 is formed on the second dielectric layer 3b using an etching process, the etching is stopped at the first dielectric layer 3a, and the second passivation layer 32 completely covers the termination area.

[0060] Also, the first dielectric layer 3a and the third dielectric layer 3c may use the same etching process. For example, the materials of the first dielectric layer 3a and the third dielectric layer 3c are the same. Therefore, after the second passivation layer 32 is formed on the second dielectric layer 3b through etching and the third dielectric layer 3c is formed through deposition, the first dielectric layer 3a and the third dielectric layer 3c can be formed by using the same etching process to form the first passivation layer 31 and the third passivation layer 33, respectively, and the etching is stopped at the epitaxial layer 2. In other words, the first window W1 and the third window W3 can be formed by using one etching process. The first window W1 is formed on the first passivation layer 31 through etching, and the third window W3 is formed on the third passivation layer 33 through etching. The first window W1 and the third window W3 correspond to each other and communicate with each other to form a window W. For example, the first window W1 and the third window W3 are aligned and the window W may correspond to an active region of the epitaxial layer 2.

[0061] In the surface passivation structure of existing semiconductor power devices, during reliability testing procedures such as thermal cycling, the structure of the passivation layer covering the metal wraps around the bent position of the metal, which forms a corner, and as a result, the material with poor ductility in the structure of the passivation layer is prone to crack generation due to excessive stress at the corner position, which leads to device failure.

[0062] By using the solution of this embodiment of this application, the passivation layer is placed under the metal layer, and therefore the passivation layer does not need to wrap around the outer edge of the metal layer, thereby reducing the number of corners formed in the passivation layer, which can reduce the stress on the passivation layer in temperature change scenarios such as thermal cycling (especially in extreme thermal cycling conditions), resulting in less cracks, thereby preventing device failure caused by moisture ingress through the cracks, and improving the robustness of the semiconductor device in high temperature and high humidity environments.

[0063] The passivation layer may include a first passivation layer, a second passivation layer, and a third passivation layer. The inner edge of the second passivation layer near the active area may be enveloped by the first passivation layer below and the third passivation layer above. Furthermore, the material of the second passivation layer is different from both the material of the first passivation layer and the material of the third passivation layer, and the thermal expansion coefficients are also different. Therefore, the structure of the passivation layer can be optimized by using the difference between the thermal expansion coefficients to prevent the passivation layer from cracking, which can further improve the robustness of the device in high temperature and high humidity environments.

[0064] It should be noted that the above embodiments are merely intended to describe the technical solutions of this application, and are not intended to limit this application. Although this application is described in detail with reference to the above embodiments, those skilled in the art should understand that, without departing from the scope of the technical solutions of the embodiments of this application, modifications can still be made to the technical solutions described in the above embodiments, or equivalent replacements can be made for some technical features thereof.

Claims

1. A substrate; an epitaxial layer on one side of the substrate, the epitaxial layer having a doped region formed in a surface of the epitaxial layer remote from the substrate, the epitaxial layer having an active region and a termination region surrounding the active region; a passivation layer covering the termination region, the passivation layer having a window formed therein corresponding to the active region; a metal layer covering the window and an inner edge of the passivation layer that defines the window and forming a Schottky contact with the active area within the window; A semiconductor device having

2. 2. The semiconductor device of claim 1, wherein the passivation layer comprises a first passivation layer, a second passivation layer, and a third passivation layer stacked in sequence and arranged in contact with one another, the first passivation layer being located between the epitaxial layer and the second passivation layer, and the material of the second passivation layer being different from both the material of the first passivation layer and the material of the third passivation layer.

3. 3. The semiconductor device of claim 2, wherein a first window corresponding to the active area is disposed in the first passivation layer, a second window corresponding to the active area is disposed in the second passivation layer, the second window being located outside the first window, the third passivation layer has a first portion located on a surface of the second passivation layer farther from the first passivation layer, a second portion covering an inner wall of the second window, and a third portion stacked and disposed on the first passivation layer, and a third window corresponding to the active area is disposed on the third portion of the third passivation layer, and the first window and the third window correspond to each other and communicate with each other to form the window.

4. the material of the first passivation layer and the material of the third passivation layer are the same and comprise silicon oxide; and / or the material of the second passivation layer comprises silicon nitride; The semiconductor device according to claim 2 or 3.

5. 5. The semiconductor device of claim 2, wherein a thickness of the third passivation layer is less than a thickness of the first passivation layer and a thickness of the second passivation layer.

6. The semiconductor device is a protective layer covering the passivation layer and an outer edge of the metal layer; 6. The semiconductor device according to claim 1 , further comprising:

7. forming a doped region in a surface of the epitaxial layer remote from a substrate, the epitaxial layer being located on one side of the substrate and having an active region and a termination region surrounding the active region; disposing a passivation layer over the termination region, the passivation layer having a window corresponding to the active region; disposing a metal layer over the window and on an inner edge of the passivation layer that defines the window, the metal layer forming a Schottky contact with the active region within the window; A method for manufacturing a semiconductor device comprising:

8. The passivation layer includes a first passivation layer, a second passivation layer, and a third passivation layer, and the disposing of the passivation layer over the termination region includes: forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer, the material of the first dielectric layer being different from the material of the second dielectric layer; etching a second window in a portion of the second dielectric layer corresponding to the active area to form the second passivation layer; forming a third dielectric layer on the second window and on the second passivation layer, in the second window, the third dielectric layer covering an inner peripheral wall of the second window and stacked on the first dielectric layer to contact the first dielectric layer, the material of the second dielectric layer being different from the material of the third dielectric layer; etching the first dielectric layer and the third dielectric layer at a position inside the second window corresponding to the active region, the etching including: etching a third window in the third dielectric layer to form the third passivation layer; and etching a first window in the first dielectric layer to form the first passivation layer, the first window and the third window corresponding to each other and communicating with each other to form the window; The semiconductor device manufacturing method of claim 7, comprising:

9. 9. The semiconductor device manufacturing method of claim 8, wherein the first window and the third window are formed using a single etching process.

10. disposing a protective layer over the passivation layer and over an outer edge of the metal layer; 10. The method of claim 7, further comprising:

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