Equalizer Circuit

Abstract

The present application discloses an equalizer circuit, which includes a current source module, an RC network, and a differential transistor pair, the current source module being electrically connected to the RC network, the RC network being electrically connected to the differential transistor pair, the equalizer circuit further including an adjustable active inductor module electrically connected to the first transistor and the second transistor in the differential transistor pair, respectively, and a control module electrically connected to the current source module, the RC network, and the adjustable active inductor module, respectively, for adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module to change the frequency of the dominant pole and the non-dominant pole of the equalizer circuit. The equalizer circuit can obtain compensation curves for different frequency peaking, and can well and harmoniously solve the channel compensation problem in different protocols and different rates, solving the problem that the gain boost of each frequency peaking cannot be adjusted within 0-15 dB in the related art due to the channel attenuation to be compensated by the equalizer being different in different protocols and different rates.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application filed with the China Patent Office on February 7, 2023, bearing application number 202310115480.5 and entitled "Equalizer Circuit," the entire contents of which are incorporated herein by reference.

[0002] [Technical field] The present application relates to the technical field of data transfer, and more particularly to equalizer circuits. [Background technology]

[0003] The equalizer (EQ), as an important component of the receiving side of the chip, is used to compensate for the signal attenuation in the channel. For different interface protocols and different rates, the channel attenuation that the EQ should compensate for is also different. To solve the difference in attenuation between long and short channels, the gain boost of the EQ is generally an adjustable mode, for example, adjustable within 0-15 dB with a step size of about 1 dB.

[0004] In the related art, compensation is performed for the maximum bandwidth in data transfer so that the frequency point of the maximum gain boost that the EQ can provide is at the maximum bandwidth. For example, in a re-driver chip (signal retiming chip), the module that compensates for channel attenuation is mainly an EQ. If this chip not only supports USB4.0 but also USB3.2, and the EQ circuit is designed according to the design at the USB4.0 rate with a frequency peaking of 10GHz and a maximum gain boost of 15dB, and is designed to be adjustable within 0 to 15dB taking into account long and short channels, at the position of the Nyquist frequency point (5GHz) of USB3.2, the gain boost will be much smaller than 15dB, and the application to re-attenuation of the USB3.2 channel will be limited. On the other hand, if the frequency peaking is designed to be 5 GHz and the maximum gain boost is also designed to be 15 dB, the gain boost at 10 GHz will be much larger than 15 dB, resulting in a significant waste of power consumption. It will also be difficult to ensure that the gain boost is adjustable within the range of 0 to 15 dB, and in particular, it will be difficult to cover the minimum gain boost.

[0005] In the related art, the channel attenuation to be compensated by the EQ differs for different protocols and different rates, and it is difficult to achieve adjustable gain boost for each frequency peaking within 0 to 15 dB. To address this problem, no effective solution has yet been proposed. Summary of the Invention [Problem to be solved by the invention]

[0006] The present application provides an equalizer circuit to solve the problem in the related art that the channel attenuation that the equalizer needs to compensate for is different for different protocols or different rates. [Means for solving the problem]

[0007] The present application provides an equalizer circuit including a current source module, an RC network, and a differential transistor pair, the current source module being electrically connected to the RC network, and the RC network being electrically connected to the differential transistor pair, the equalizer circuit further including a tunable active inductor module electrically connected to a first transistor and a second transistor in the differential transistor pair, respectively; and a control module electrically connected to the current source module, the RC network, and the tunable active inductor module, respectively, for changing frequencies of dominant poles and non-dominant poles of the equalizer circuit by adjusting performance parameters of the current source module, the RC network, and the tunable active inductor module.

[0008] Optionally, the adjustable active inductor module may include a first adjustable current source, a first adjustable resistor, a first adjustable capacitance, and a first transistor, the RC network being electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor, respectively, a first terminal of the first adjustable resistor being electrically connected to the RC network, and a second terminal of the first adjustable resistor being electrically connected to a gate of the first transistor and the first adjustable capacitance, respectively.

[0009] Optionally, the current source module may include a second current source and a third current source, the differential transistor pair may include a second transistor and a third transistor, the RC network may include a second adjustable resistor, a second adjustable capacitance module, and a third adjustable capacitance module, the second adjustable resistor is connected in parallel with the second adjustable capacitance module, the second current source may be electrically connected to a first parallel connection node of the second adjustable resistor and the second adjustable capacitance module, the third current source may be electrically connected to a second parallel connection node of the second adjustable resistor and the second adjustable capacitance module, the first parallel connection node may be electrically connected to a first terminal of the third adjustable capacitance module through the second transistor, and the second parallel connection node may be electrically connected to a second terminal of the third adjustable capacitance module through the third transistor.

[0010] Optionally, the control module may include a decoder that receives the coded signal and decodes the coded signal according to a truth table of the decoder to obtain a logical control signal, and a controller that is electrically connected to the decoder, the current source module, the RC network, and the tunable active inductor module, respectively, and adjusts performance parameters of the current source module, the RC network, and the tunable active inductor module based on the logical control signal.

[0011] Optionally, the decoder may receive the first coded signal, and decode the first coded signal according to a truth table of the first decoder to obtain a first logic control signal for instructing the controller to provide control information to increase the current values ​​of the second current source and the third current source, decrease the capacitance value of the first adjustable capacitance, and decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a first preset range, and the controller may adjust the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source based on the first logic control signal to reduce the frequencies of the dominant pole and the non-dominant pole of the equalizer circuit.

[0012] Optionally, the decoder may receive a second coded signal, and decode the second coded signal according to a truth table of the second decoder to obtain a second logic control signal for instructing the controller to receive control information for decreasing the current values ​​of the second current source and the third current source, increasing the capacitance value of the first adjustable capacitance, and increasing the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a second preset range, and the controller may adjust the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source based on the second logic control signal to increase the frequency of the dominant pole and the non-dominant pole of the equalizer circuit.

[0013] Optionally, the decoder may receive the second coded signal and the third coded signal, and decode the second coded signal according to a truth table of the second decoder to obtain a second logic control signal, and decode the third coded signal according to a truth table of the third decoder to obtain a third logic control signal for instructing the controller to provide control information to decrease the current values ​​of the second current source and the third current source, decrease the capacitance value of the first adjustable capacitance, and decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a second preset range, and the controller may adjust the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source in accordance with the order of the second logic control signal and the third logic control signal.

[0014] Optionally, the second adjustable capacitance module may include a plurality of first capacitance branches connected in parallel, each of the first capacitance branches including a first capacitance and a first switch connected in series, and the third adjustable capacitance module may include a plurality of second capacitance branches connected in parallel, each of the first capacitance branches including a second capacitance and a second switch connected in series.

[0015] Optionally, the controller may further control the on-off of the first switch and the second switch based on the logic control signal. Effect of the Invention

[0016] According to the present application, the equalizer circuit further includes an adjustable active inductor module and a control module, and the control module is electrically connected to the current source module, the RC network, and the adjustable active inductor module, respectively. Therefore, by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module, the frequencies of the dominant poles and the non-dominant poles of the equalizer circuit can be changed, so that compensation curves for different frequency peaking can be obtained, which can well reconcile and solve the channel compensation problem in different protocols and different rates, and can realize that the gain boost of multiple frequency peakings can be adjusted within 0-15dB, which solves the problem in the related art that the gain boost of each frequency peaking cannot be adjusted within 0-15dB due to the different channel attenuation to be compensated by the equalizer (EQ) in different protocols and different rates. [Brief description of the drawings]

[0017] The drawings constituting a part of this application are provided to facilitate a better understanding of the present application, and the schematic embodiments and description thereof are provided to illustrate the present application, but are not intended to unduly limit the present application.

[0018] [Figure 1] FIG. 2 is a schematic diagram of an equalizer circuit according to an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram of a dynamically adjustable active inductor in an equalizer circuit according to an embodiment of the present application. [Diagram 3]FIG. 2 is a schematic diagram of a zero-pole distribution of a dynamically tunable active inductor according to an embodiment of the present application. [Figure 4] FIG. 2 is a schematic diagram of a truth table for a decoder that adjusts the frequency peaking of an equalizer circuit to move towards higher frequencies, according to an embodiment of the present application. [Diagram 5] FIG. 2 is a schematic diagram of a relationship curve between frequency and gain boost for adjusting the frequency peaking of an equalizer circuit to move to higher frequencies, according to an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of a truth table of a decoder for adjusting the frequency peaking of an equalizer circuit to move it to lower frequencies, according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a relationship curve between frequency and gain boost for adjusting the frequency peaking of an equalizer circuit to move it to lower frequencies, according to an embodiment of the present application. [Figure 8] FIG. 13 is a schematic diagram of a truth table of another decoder that adjusts the frequency peaking of an equalizer circuit to move to lower frequencies, according to an embodiment of the present application. [Figure 9] FIG. 13 is a schematic diagram of another relationship curve between frequency and gain boost that adjusts the frequency peaking of the equalizer circuit to move to lower frequencies, according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In addition, the embodiments and constituent elements in the embodiments of the present application may be combined with each other as long as they are not inconsistent. Hereinafter, the present application will be described in detail based on the embodiments with reference to the drawings.

[0020] In order to allow those skilled in the art to better understand the present invention, the technical aspects of the present application will be described clearly and completely below with reference to the drawings according to the embodiments of the present application. Of course, the described embodiments are only some of the embodiments of the present application, and are not all of them. Any other embodiments that a person skilled in the art can obtain based on the embodiments of the present application without requiring creative labor should all be included in the scope of protection of the present application.

[0021] In addition, the terms "first", "second", and the like used in the specification, claims, and drawings are intended to distinguish between similar objects, and are not intended to describe a particular order or priority. It should be understood that the numerals used in this way can be interchanged where appropriate to allow the embodiments of the present invention described herein to be performed in an order other than that shown or described herein. In addition, the terms "comprise", "have" and any variations thereof are intended to cover what is included without being exclusive, for example, a process, method, system, product, or apparatus including a series of steps or units need not be limited to the steps or units explicitly shown, but may include steps or units not explicitly shown for these processes, methods, products, or apparatus, or other steps or units inherent thereto.

[0022] For the sake of convenience, some nouns and terms used in the embodiments of the present application will be explained below.

[0023] Equalizer: Abbreviated as EQ and called Equalizer in English.

[0024] Decoder: Abbreviated as Dec, and called Decoder in English.

[0025] Gain boost: In English it is called gain boost.

[0026] Frequency peaking: In English, this is called frequency peaking.

[0027] According to an embodiment of the present application, an equalizer circuit is provided. As shown in FIG. 1, the equalizer circuit includes a current source module 10, an RC network, and a differential transistor pair 20, where the current source module is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair, and the equalizer circuit includes: a tunable active inductor module 30 electrically connected to the first and second transistors of the differential transistor pair 20, respectively; and a control module 40 electrically connected to the current source module 10, the RC network, and the tunable active inductor module 30, respectively (connection relationships not shown in the figure), for changing the frequencies of the dominant poles and non-dominant poles of the equalizer circuit by adjusting performance parameters of the current source module 10, the RC network, and the tunable active inductor module 30.

[0028] According to this embodiment, the control module is electrically connected to the current source module, the RC network, and the adjustable active inductor module, respectively, so that the frequency of the dominant pole and the non-dominant pole of the equalizer circuit can be changed by adjusting the performance parameters of the current source module, the RC network, and the adjustable active inductor module, thereby obtaining compensation curves for different frequency peaking, which can well reconcile and solve the channel compensation problem in different protocols and different rates, and realize that the gain boost of multiple frequency peakings can be adjusted within 0 to 15 dB, solving the problem in the related art that the gain boost of each frequency peaking cannot be adjusted within 0 to 15 dB due to different channel attenuation to be compensated by the equalizer (EQ) in different protocols and different rates.

[0029] In some optional embodiments, in the equalizer circuit according to this embodiment, the adjustable active inductor module includes a first adjustable current source, a first adjustable resistor, a first adjustable capacitance, and a first transistor, the RC network is electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor, respectively, a first terminal of the first adjustable resistor is electrically connected to the RC network, and a second terminal of the first adjustable resistor is electrically connected to the gate of the first transistor and the first adjustable capacitance, respectively.

[0030] In the above alternative embodiment, the adjustable active inductor module contributes to a zero pole of an equalizer circuit, where the first adjustable current source is responsible for shunting the current of the first transistor and adjusting the transconductance of the first transistor.

[0031] Exemplarily, as shown in FIG. 1 and FIG. 2, the adjustable active inductor module 30 is composed of a first adjustable current source I1, a first adjustable resistor R1, a first adjustable capacitance C1, and a first transistor M1, and the zero pole contributed by the adjustable active inductor module is as shown in FIG. 3, specifically, R f is the resistance of the first adjustable resistor R1, and C f is the capacitance value of the first adjustable capacitance C1, and g md is the transconductance of the first transistor M1, and as can be seen intuitively from FIG. 3, high frequencies have a larger amplitude than low frequencies, so this corresponds to the zero point.

[0032] In some optional embodiments, in the equalizer circuit according to this embodiment, the current source module includes a second current source and a third current source, the differential transistor pair includes a second transistor and a third transistor, the RC network includes a second adjustable resistor, a second adjustable capacitance module, and a third adjustable capacitance module, the second adjustable resistor is connected in parallel with the second adjustable capacitance module, the second current source is electrically connected to a first parallel connection node between the second adjustable resistor and the second adjustable capacitance module, the third current source is electrically connected to a second parallel connection node between the second adjustable resistor and the second adjustable capacitance module, the first parallel connection node is electrically connected to a first terminal of the third adjustable capacitance module through the second transistor, and the second parallel connection node is electrically connected to a second terminal of the third adjustable capacitance module through the third transistor.

[0033] Exemplarily, as shown in FIG. 1, the current source module 10 includes a second current source I2 and a third current source I3 that supply the same quiescent current, the differential transistor pair 20 includes a second transistor M2 and a third transistor M3, and the RC network includes a second adjustable resistor R2, a second adjustable capacitance module C2, and a third adjustable capacitance module C3 connected in parallel.

[0034] Specifically, in order to solve the problem that the channel attenuation to be compensated by the equalizer (EQ) differs depending on the protocol or rate, and to realize that the gain boost of each frequency peaking can be adjusted within 0 to 15 dB, the dominant pole and non-dominant pole of the equalizer are made dynamically adjustable, thereby making it possible to adjust the frequency peaking.

[0035] Take the equalizer circuit shown in Figure 1 as an example, by adjusting its adjustable resistance, adjustable capacitance and adjustable resistance, the positions of zero point, dominant pole and non-dominant pole can be changed, thereby changing the frequency response of the equalizer and compensating for the attenuation of the signal in the channel. Specifically, the transfer function of the above equalizer circuit is expressed by the following Equation 1.

number

[0036] Based on the above transfer function, the zero point of the equalizer circuit is expressed by the following equation 2, the dominant pole is expressed by the following equation 3, and the non-dominant pole is expressed by the following equation 4.

number

number

number

[0037] In the equalizer circuit according to this embodiment, the control module may include a decoder and a controller, where the decoder receives the coded signal and decodes the coded signal according to the truth table of the decoder to obtain a logic control signal, and the controller is electrically connected to the decoder, the current source module, the RC network, and the tunable active inductor module respectively, and adjusts performance parameters of the current source module, the RC network, and the tunable active inductor module according to the logic control signal.

[0038] Specifically, the decoder configures the performance parameters of the current source module, the RC network, and the adjustable active inductor module. When designing high frequency peaking, the dominant pole ω p1 and non-dominant pole ω p2 When moving both to the high frequency side and designing low frequency peaking, ω p1 and ω p2 By moving both of the poles to the lower frequency side, the frequency of the two poles can be changed, which solves the compensation problem at different rates and different channels and also reduces the power consumption for data transmission at low rates.

[0039] Exemplarily, a first adjustable current source I1 has a current value I f and a second adjustable current source I2 and a third adjustable current source I3 have a current value I s and the first adjustable resistor R1 has a resistance value R f and the first adjustable capacitance C1 has a capacitance value C f and a second adjustable capacitance C2 has a capacitance value C s and a third adjustable capacitance C3 has a capacitance value C d Then the decoder will generate I s , C d , C s , R f , C f , I f By configuring the value of p1 and non-dominant pole ωp2 The control logic of the controller can be realized by a decoder.

[0040] Furthermore, the capacitance value C s and C d In order to realize the adjustment of the capacitance value C of the second adjustable capacitance module C2, the second adjustable capacitance module C2 may include a plurality of first capacitance branches connected in parallel, each of which includes a first capacitance and a first switch connected in series. The truth table of the decoder determines whether the first capacitance in the plurality of first capacitance branches is in an operating state, thereby determining that the corresponding capacitance is connected to the internal node of the equalizer circuit through the first switch, and the controller controls the on / off of the first switch based on the logic control signal to adjust the capacitance value C of the second adjustable capacitance module C2. s The third adjustable capacitance module C3 may also include a plurality of second capacitance branches connected in parallel, each of which includes a second capacitance and a second switch connected in series. The truth table of the decoder determines whether the second capacitances in the plurality of second capacitance branches are in an active state, thereby determining that the corresponding capacitances are connected to the internal nodes of the equalizer circuit through the second switches, so that the controller controls the on / off of the second switches based on the logic control signal to adjust the capacitance value C of the third adjustable capacitance module C3. d Here, whether the first capacitance and the second capacitance are in an operating state is represented by 0 and 1, respectively, in the truth table.

[0041] In some optional embodiments, to achieve high frequency peaking, the decoder receives the first coded signal and obtains a first logic control signal by decoding the first coded signal according to a truth table of the first decoder, where the first logic control signal is for instructing the controller to provide control information to increase the current values ​​of the second current source and the third current source, decrease the capacitance value of the first adjustable capacitance, and decrease the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a first preset range. The controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source based on the first logic control signal to reduce the frequencies of the dominant pole and the non-dominant pole of the equalizer circuit.

[0042] Exemplarily, the truth table of the first decoder is as shown in FIG. 4, and the first capacitance C s1 ~C s7 When each of them takes a value of 1 (represented as true), it indicates that the corresponding capacitance is connected to the internal node of the equalizer circuit through the first switch that is turned on, and the first capacitance C s1 ~C s7 When takes a value of 0 (represented as false), it indicates that the corresponding capacitance is not connected to the internal node of the equalizer circuit due to the first switch being turned off, and the second capacitance C d1 ~C d8 When is equal to 1, it indicates that the corresponding second capacitance is connected to the internal node of the equalizer circuit through the turned-on second switch, and the second capacitance C d1 ~C d8 When I is equal to 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit due to the second switch being turned off. s is the current value of the current source that supplies the current to the equalizer (EQ), and R s is used to adjust the DC gain of the circuit, the input of the decoder is A<5:0> and the output is B<16:0>. Here, the first capacitance C s1 ~C s7The boolean values ​​in the table are binary operators on A<3:0>, and the binaries on A<3:0> are the first capacitance C s1 ~C s7 It changes depending on the truth value in the table, and A<5:4> always keeps the input value 00.

[0043] Specifically, when designing high frequency peaking, as shown in Figure 4, I s Set to a large value x1, and C f Set y1 to a small value and R f By setting z1 to a small value, I s Increase the size of R f and C f Decrease each and I f can be set to a reasonable value X. The gain boost of the equalizer is s and C d This can be achieved by adjusting the gain boost, resulting in a set of 16 curve bands with adjustable gain boost, as shown in Figure 5. Here, the frequency peaking is 10 GHz, and the gain boost of the frequency peaking satisfies the adjustable range of 0 to 15 dB.

[0044] In some optional embodiments, to achieve low frequency peaking, the decoder receives the second coded signal and obtains a second logic control signal by decoding the second coded signal according to a truth table of the second decoder, where the second logic control signal is for instructing the controller to provide control information to decrease the current values ​​of the second current source and the third current source, increase the capacitance value of the first adjustable capacitance, and increase the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a second preset range. The controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source based on the second logic control signal to increase the frequency of the dominant pole and the non-dominant pole of the equalizer circuit.

[0045] Exemplarily, the truth table of the second decoder is as shown in FIG. 6, and the first capacitance C s1 ~C s7 When each of them takes a value of 1 (represented as true), it indicates that the corresponding capacitance is connected to the internal node of the equalizer circuit through the first switch that is turned on, and the first capacitance C s1 ~C s7 When takes a value of 0 (represented as false), it indicates that the corresponding capacitance is not connected to the internal node of the equalizer circuit due to the first switch being turned off, and the second capacitance C d1 ~C d8 When is equal to 1, it indicates that the corresponding second capacitance is connected to the internal node of the equalizer circuit through the turned-on second switch, and the second capacitance C d1 ~C d8 When I is equal to 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit due to the second switch being turned off. s is the current value of the current source that supplies the current to the equalizer (EQ), and R s is used to adjust the DC gain of the circuit, the input of the decoder is A<5:0> and the output is B<16:0>. Here, the first capacitance C s1 ~C s7 The boolean values ​​in the table are binary operators on A<3:0>, and the binaries on A<3:0> are the first capacitance C s1 ~C s7 The input value of A<5:4> always remains 01, depending on the truth value in the table.

[0046] Specifically, in order to move the frequency peaking to the lower frequency side, as shown in Figure 6, s First, by setting I s This reduces the current of the dominant pole ω p1 To the lower frequency side, f Set y2 to a large value and R f By setting z2 to a large value, R f and C f and the non-dominant pole ωp2 to the lower frequency side, and I f can be set to a reasonable value Y. Similarly, the gain boost of the equalizer can be set to C s and C d This can be achieved by adjusting the gain boost, resulting in a set of 16 curve bands with adjustable gain boost, as shown in Figure 7. Here, the frequency peaking is 5 GHz, and the gain boost of the frequency peaking satisfies the adjustable range of 0 to 15 dB.

[0047] C f and R f In this case, in order to realize low frequency peaking, since the increase in the frequency peaking ratio may lead to an overall increase in the relationship curve between the frequency and the gain boost, in another optional embodiment, the decoder receives the second coded signal and the third coded signal, and obtains a second logic control signal by decoding the second coded signal according to a truth table of the second decoder, and obtains a third logic control signal by decoding the third coded signal according to a truth table of the third decoder. Here, the third logic control signal is for instructing the controller to provide control information to reduce the current values ​​of the second current source and the third current source, reduce the capacitance value of the first adjustable capacitance, and reduce the resistance value of the first adjustable resistor, so that the current value of the first adjustable current source meets a second preset range. The controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistor, and the first adjustable current source in the order of the second coded signal and the third logic control signal.

[0048] Exemplarily, the truth table of the third decoder is as shown in FIG. 8, and the first capacitance C s1 ~C s7 When each of them takes a value of 1 (represented as true), it indicates that the corresponding capacitance is connected to the internal node of the equalizer circuit through the first switch that is turned on, and the first capacitance C s1 ~C s7When takes a value of 0 (represented as false), it indicates that the corresponding capacitance is not connected to the internal node of the equalizer circuit due to the first switch being turned off, and the second capacitance C d1 ~C d8 When is equal to 1, it indicates that the corresponding second capacitance is connected to the internal node of the equalizer circuit through the turned-on second switch, and the second capacitance C d1 ~C d8 When I is equal to 0, it indicates that the corresponding second capacitor is not connected to the internal node of the equalizer circuit due to the second switch being turned off. s is the current value of the current source that supplies the current to the equalizer (EQ), and R s is used to adjust the DC gain of the circuit, the input of the decoder is A<5:0> and the output is B<16:0>. Here, the first capacitance C s1 ~C s7 The boolean values ​​in the table are binary operators on A<3:0>, and the binaries on A<3:0> are the first capacitance C s1 ~C s7 The input value of A<5:4> always remains 10, depending on the truth value of the table.

[0049] Specifically, the above embodiment can include two steps. First, as shown in FIG. f Adjust Y to a reasonable value and I s By setting to a small value x2, I s At the same time, C f Set y2 to a large value and R f By setting z2 to a large value, R f and C f Then increase the s and C d to obtain a set of 16 curve band gain boost curves. Then, f Set y1 to a small value and R f By setting z1 to a small value, R f and C f Then, reduce each of them ands and C d to obtain another set of gain boost curves of 16 curve bands. Then, the two sets of curves are superimposed to select 16 desired gain boost curves, as shown in FIG. 9. Here, the frequency peaking is 5 GHz, and the gain boost of the frequency peaking is adjustable within 0-15 dB, and the control logic is realized by a decoder to realize that the gain boost of each frequency peaking is adjustable within 0-15 dB.

[0050] According to an embodiment of the present application, a method for adjusting the pole frequency of an equalizer circuit is further provided. The method for adjusting the pole frequency of an equalizer circuit according to the embodiment of the present application can be applied to the equalizer circuit according to the above-mentioned embodiment. Hereinafter, the method for adjusting the pole frequency of an equalizer circuit according to the embodiment of the present application will be described.

[0051] The method for adjusting the pole frequency according to this embodiment is as follows: a control module in the equalizer circuit receiving a control signal; The control module adjusts performance parameters of a current source module, an RC network, and a tunable active inductor module in the equalizer circuit based on the control signal, and the controller adjusts the performance parameters of the current source module, the RC network, and the tunable active inductor module based on the logical control signal to change the frequencies of dominant poles and non-dominant poles of the equalizer circuit.

[0052] According to this embodiment, the control module in the equalizer circuit is electrically connected to the current source module, the RC network, and the adjustable active inductor module respectively, so that it can adjust the performance parameters of the current source module, the RC network, and the adjustable active inductor module according to the received control signal to change the frequency of the dominant pole and the non-dominant pole of the equalizer circuit, and obtain the compensation curves for different frequency peaking, which can well reconcile and solve the channel compensation problem in different protocols and different rates, and realize that the gain boost of multiple frequency peakings can be adjusted within 0-15dB, which solves the problem in the related art that the gain boost of each frequency peaking cannot be adjusted within 0-15dB due to the different channel attenuation to be compensated by the equalizer (EQ) in different protocols and different rates.

[0053] In some optional embodiments, the control module in the equalizer circuit includes a decoder and a controller, and the controller is electrically connected to the decoder, the current source module, the RC network, and the tunable active inductor module, respectively. The step of receiving the control signal includes the step of the decoder receiving the coded signal and decoding the coded signal according to a truth table of the decoder to obtain a logic control signal.

[0054] In the above optional embodiment, the decoder can obtain a logic control signal by decoding the coded signal according to the decoder's truth table, so that upon receiving the logic control signal, the controller can adjust the performance parameters of the current source module, the RC network, and the tunable active inductor module based on the logic control signal.

[0055] Specifically, the decoder configures the performance parameters of the current source module, the RC network, and the adjustable active inductor module. When designing high frequency peaking, the dominant pole ω p1 and non-dominant pole ω p2 When moving both to the high frequency side and designing low frequency peaking, ω p1 and ω p2 By moving both of the poles to the lower frequency side, the frequency of the two poles can be changed, which solves the compensation problem at different rates and different channels and also reduces the power consumption for data transmission at low rates.

[0056] It is to be understood that the terms "comprise", "have" and any variations thereof are intended to cover inclusive, but not exclusive, such that a process, method, product or apparatus comprising a set of elements includes not only those elements but also other elements not expressly stated or inherent in the process, method, product or apparatus. Without further limitation, an element qualified by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, product or apparatus that includes the element.

[0057] The above is merely an embodiment of the present application, and is not intended to limit the present application. Those skilled in the art can make various modifications and variations to the present application. Any modifications, equivalent replacements, improvements, etc. within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. an equalizer circuit including a current source module, an RC network, and a differential transistor pair, the current source module being electrically connected to the RC network, the RC network being electrically connected to the differential transistor pair, a tunable active inductor module electrically connected to a first transistor and a second transistor in the differential transistor pair, respectively; and a control module electrically connected to the current source module, the RC network, and the tunable active inductor module, respectively, for changing frequencies of dominant poles and non-dominant poles of the equalizer circuit by adjusting performance parameters of the current source module, the RC network, and the tunable active inductor module.

2. the tunable active inductor module includes a first tunable current source, a first tunable resistor, a first tunable capacitance, and a first transistor; 2. The equalizer circuit of claim 1, wherein the RC network is electrically connected to the first adjustable current source, the first transistor, and the first adjustable resistor, respectively, a first terminal of the first adjustable resistor is electrically connected to the RC network, and a second terminal of the first adjustable resistor is electrically connected to the gate of the first transistor and the first adjustable capacitance, respectively.

3. the current source module includes a second current source and a third current source, the differential transistor pair includes a second transistor and a third transistor, the RC network includes a second adjustable resistor, a second adjustable capacitance module, and a third adjustable capacitance module; 3. The equalizer circuit of claim 2, wherein the second adjustable resistor is connected in parallel with the second adjustable capacitance module, the second current source is electrically connected to a first parallel connection node of the second adjustable resistor and the second adjustable capacitance module, the third current source is electrically connected to a second parallel connection node of the second adjustable resistor and the second adjustable capacitance module, the first parallel connection node is electrically connected to a first terminal of the third adjustable capacitance module through the second transistor, and the second parallel connection node is electrically connected to a second terminal of the third adjustable capacitance module through the third transistor.

4. The control module includes: a decoder for receiving an encoded signal and decoding the encoded signal according to a decoder truth table to obtain a logic control signal; 4. The equalizer circuit of claim 3, further comprising: a controller electrically connected to the decoder, the current source module, the RC network, and the adjustable active inductor module, respectively, and configured to adjust performance parameters of the current source module, the RC network, and the adjustable active inductor module based on the logic control signal.

5. the decoder receives a first coded signal, and decodes the first coded signal according to a truth table of the first decoder to obtain a first logic control signal for instructing the controller with control information to increase current values ​​of the second current source and the third current source, decrease a capacitance value of the first adjustable capacitance, and decrease a resistance value of the first adjustable resistor, so that a current value of the first adjustable current source satisfies a first preset range; 5. The equalizer circuit of claim 4, wherein the controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistance, and the first adjustable current source based on the first logic control signal to reduce frequencies of dominant poles and non-dominant poles of the equalizer circuit.

6. the decoder receives a second coded signal, and decodes the second coded signal according to a truth table of the second decoder to obtain a second logic control signal for instructing the controller to receive control information for decreasing current values ​​of the second current source and the third current source, increasing a capacitance value of the first adjustable capacitance, and increasing a resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies a second preset range; 5. The equalizer circuit of claim 4, wherein the controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistance, and the first adjustable current source based on the second logic control signal to increase frequencies of dominant poles and non-dominant poles of the equalizer circuit.

7. the decoder receives the second coded signal and the third coded signal, and decodes the second coded signal according to a truth table of the second decoder to obtain the second logic control signal, and decodes the third coded signal according to a truth table of a third decoder to obtain a third logic control signal for instructing the controller to provide control information for decreasing current values ​​of the second current source and the third current source, decreasing a capacitance value of the first adjustable capacitance, and decreasing a resistance value of the first adjustable resistor, so that the current value of the first adjustable current source satisfies the second preset range; 7. The equalizer circuit of claim 6, wherein the controller adjusts the second current source, the third current source, the first adjustable capacitance, the first adjustable resistance, and the first adjustable current source according to an order of the second logic control signal and the third logic control signal.

8. the second adjustable capacitance module includes a plurality of first capacitance branches connected in parallel, each of the first capacitance branches including a first capacitance and a first switch connected in series; 5. The equalizer circuit of claim 4, wherein the third adjustable capacitance module includes a plurality of second capacitance branches connected in parallel, each of the first capacitance branches including a second capacitance and a second switch connected in series.

9. 9. The equalizer circuit according to claim 8, wherein the controller further controls on / off of the first switch and the second switch based on the logic control signal.

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