Signal detector device and method

Abstract

Device comprising: a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and second reference signals, the plurality of output signals indicative of the amplitude and phase of the input signal; one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity, and a controller (508) coupled to the quadrature demodulator, the controller (508) being configured to determine the amplitude and phase of the input signal according to the plurality of output signals, the one or more inverting circuits being configured to be coupled to the controller (508), the controller (508) further being configured to set the inverting circuits to the first programmable output polarity while determining first values ​​of the plurality of output signals, set the inverting circuits to the second programmable output polarity while determining second values ​​of the plurality of output signals, and determine one or more error values ​​from the first and second values ​​of the plurality of output signals, the controller (508) further being configured toto determine the error values ​​by subtracting the first values ​​of the plurality of output signals from the second values ​​of the plurality of output signals, wherein determining comprises subtracting the second values ​​of the plurality of output signals from respective ones of the first values ​​of the plurality of output signals to produce the one or more error values.

Description

Technical field

[0001] The present invention relates generally to signal analysis and, in particular embodiments, to a signal detector apparatus and a signal detector method. background

[0002] Communications, biomedical, and radar systems often measure the amplitude and phase of an analog signal. For example, wireless transmitters and receivers that incorporate beamforming arrays can measure the amplitude and phase of received signals in each RF device in the beamforming chain. Wireless devices such as base stations and access points, handheld devices such as phones and tablets, and personal computers may all need to measure the amplitude and phase of received signals. Such measurements typically require high accuracy and are often performed in a small device or package.

[0003] Accurate measurements of a signal's amplitude and phase can be performed using vector network analyzers (VNAs). Such measurement systems can provide greater accuracy but often require the use of analog-to-digital converters (ADCs), more powerful intermediate frequency (IF) sampling, and additional memory and digital signal processors (DSPs). Furthermore, VNAs can increase the cost and size of systems due to the use of specialized RF boards and connectors, as well as the presence of an operator to perform the measurements.

[0004] Integrated analog systems that perform amplitude and phase detection have increased in popularity as technology has improved and the trend toward integration has continued. Analog systems have the potential to reduce device area by having fewer components. However, the accuracy of analog systems can traditionally be improved by increasing the size of components in the system, which can increase the system's power consumption. Increasing component size or power consumption can increase accuracy, but can also increase chip area, reduce efficiency, or be hampered by other technology limitations. Furthermore, improving a device may sometimes be insufficient to achieve the desired performance.

[0005] DE 692 26 318 T2 discloses an FSK demodulator with direct conversion. WO 2013 / 011 973 A1 discloses a method for compensating I / Q mismatches and an RF transceiver. JP H11-340 860 A discloses multiband mobile radio devices. Brief description

[0006] An object of the present application is to provide an improved signal detector device and a corresponding improved method.

[0007] The problem is solved by the features of the appended claims.

[0008] According to a preferred embodiment of the present invention, an apparatus includes: a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and second reference signals, the plurality of output signals indicative of the amplitude and phase of the input signal; one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator,when the inverting circuits are set to the second programmable output polarity, and a controller coupled to the quadrature demodulator, the controller configured to determine the amplitude and phase of the input signal according to the plurality of output signals, the one or more inverting circuits configured to be coupled to the controller, the controller further configured to set the inverting circuits to the first programmable output polarity while determining first values ​​of the plurality of output signals, the inverting circuits to the second programmable output polarity while determining second values ​​of the plurality of output signals, and determine one or more error values ​​from the first and second values ​​of the plurality of output signals, the controller further configured toto determine the error values ​​by subtracting the first values ​​of the plurality of output signals from the second values ​​of the plurality of output signals, wherein determining comprises subtracting the second values ​​of the plurality of output signals from respective ones of the first values ​​of the plurality of output signals to produce the one or more error values. Short description of the drawings

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which: Fig. Show 1-3 signal detectors; Fig. 4 shows an inverter; Fig. 5 shows a receiver; Fig. 6 shows results measured in one embodiment; Fig. 7 is a block diagram of a wireless device and Fig. 8 is a flowchart of a device calibration procedure. Detailed description of illustrative embodiments

[0010] The making and using of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein may be applied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using various embodiments and should not be construed in a limiting sense.

[0011] According to various embodiments, a quadrature demodulator includes programmable buffers for inverting the input or reference signals of the quadrature demodulator. The outputs of the quadrature demodulator are measured once, the input or reference signals are inverted, and the outputs are measured again. By inverting the input or reference signals, the output of the quadrature demodulator is inverted, but the effects of errors on the output are not corrected. A DC offset or quadrature error of the demodulator can be calculated using the values ​​of the normal and inverted outputs, and these calculated error values ​​can be used to correct the effect of the errors during normal operation of the demodulator.

[0012] Fig. Figure 1 shows a signal detector 100. The signal detector 100 is a quadrature demodulator that determines the amplitude and phase of an input signal IN. The signal detector 100 includes a quadrature generator 102 and mixers 104, 106. During operation, the signal detector 100 receives a reference signal LO at an input terminal and provides output signals I and Q at output terminals.

[0013] The quadrature generator 102 is clocked by the reference signal LO and has two outputs. The quadrature generator 102 drives the mixers 104, 106 with reference signals that have a 90-degree phase shift between them. In some embodiments, the quadrature generator 102 is implemented using a 2:1 current mode logic (CML) divider that provides the reference signals at half the frequency of the reference signal LO. In some embodiments, the quadrature generator 102 may be, for example, a polyphase filter, a 3 dB quadrature hybrid coupler, a bipolar or MOS-based divider, a phase shifter, or the like.

[0014] Mixer 104 multiplies the reference signal provided by quadrature generator 102 by the input signal IN and produces the output signal I. Mixer 106 multiplies the reference signal provided by quadrature generator 102 by the input signal IN and produces the output signal Q. In some embodiments, mixers 104, 106 are implemented using double-balanced Gilbert cells. In some embodiments, mixers 104, 106 may be, for example, bipolar or MOS-based Gilbert mixers, passive mixers, voltage-mode mixers, current-mode mixers, or the like.

[0015] If the input signal IN and the reference signals produced by the quadrature generator 102 have the same frequency, the output signals I and Q are direct current (DC) signals and contain information about the amplitude and phase of the input signal IN. In particular, the output signal I is calculated according to I=GmixAINcos(ϕLO−ϕIN), and Q=GminAINsin(ϕLO−ϕIN) determined, where G mix the gain of the mixers 104, 106 is, A IN the amplitude of the input signal IN is, Ø IN is the phase of the input signal IN and Ø LO is the phase of the reference signal LO. The output signals I and Q can be sampled with an ADC and the amplitude and phase of the input signal IN can be determined by solving for A IN and Ø IN according to GmixAIN=l2+Q2, and ϕLO−ϕIN=tan−1(Ql).

[0016] Although equation (4) describes the variation of Ø LO -O IN with reference to a start value and not the absolute value of the phase Ø IN , it is understood that in some contexts the relative phase may provide sufficient information to perform device verification, calibration, and the like.

[0017] Non-ideal operation of basic circuit elements in signal detector 100 can affect the accuracy of the amplitude and phase measurements. For example, the output signals I and Q may have additional DC offset, and the quadrature generator 102 may experience quadrature errors, e.g., the quadrature generator 102 may not produce signals with a phase shift of exactly 90 degrees. Such errors can corrupt the amplitude and phase information in the output signals I and Q. By increasing the size of the circuit elements in signal detector 100, the accuracy of the output signals I and Q can be increased, but the size and power consumption of the signal detector 100 may also be increased.

[0018] Fig. Figure 2 shows a signal detector 200 according to an embodiment of the present invention. The signal detector 200 is similar to the signal detector 100, except that the signal detector 200 includes inverters 202, 204 between the quadrature generator 102 and the mixers 104, 106. The inverters 202, 204 are programmable buffers that invert the reference signals produced by the quadrature generator 102, for example, shift their phase by 180 degrees when the swap signals s I and s Q are active. Although inverters 202, 204 may not produce a phase shift of exactly 180, inversion errors of inverters 202, 204 may be significantly smaller than expected errors in signal detector 200 (discussed above).

[0019] By inverting the reference signals LO, the output signals I and Q are inverted. However, the errors discussed above (e.g., DC offset, quadrature inaccuracies) are not inverted when the output signals I and Q are inverted. Therefore, errors in the signal detector 200 can be determined by measuring the output signals I and Q once with the inverters disabled and again with the inverters enabled, and then performing post-processing calculations on the acquired data to calculate the errors. Determining errors through the post-processing calculations allows the signal detector 200 to more accurately measure the amplitude and phase of the input signal IN without significantly increasing device area or affecting power efficiency.Although post-processing may increase measurement time, measurement time is typically not a critical parameter since measurements can only be performed during a calibration sequence and not during regular operation.

[0020] The DC offset of the signal detector 200 can be adjusted by varying the phase Ø LO or Ø IN and measuring the output signals I and Q for different values ​​of the phase difference Ø LO -O IN (where Ø LO -O IN∈ [0,360]), inverting the reference signals LO, and re-measuring the output signals I and Q while varying the phase. The normal and inverted values ​​of the output signals I and Q are averaged to yield a DC offset for each measured phase difference. In some embodiments, the DC offset can be selected for a particular phase difference. In some embodiments, the DC offsets for each phase difference are averaged to yield an average total DC offset for the signal detector. The average total DC offset may then be the only selected offset. After an offset is selected, it is subtracted from the output signals I and Q when determining the amplitude and phase of the input signal IN during normal operation.

[0021] The quadrature error of the signal detector 200 can be determined by taking the same measurements used to determine the DC offset. The zero-crossing points of the normal and inverted values ​​of the output signals I and Q are determined. Some interpolation may be required to determine the zero-crossing points. The values ​​at the zero-crossing points can then be subtracted to determine the quadrature error. The quadrature error can be accounted for when the phase difference Ø LO -O IN is determined.

[0022] Fig. 3 shows a signal detector 300 according to an embodiment of the present invention. Signal detector 300 is similar to signal detector 200, except that signal detector 300 includes an inverter 302 that inverts the input signal IN instead of the reference signals LO. By inverting the input signal IN, the output signals I and Q are also inverted without inverting the errors of signal detector 300 (e.g., DC offset, quadrature inaccuracies). Inverter 302 is similar to inverters 202, 204. Signal detector 300 requires fewer inverters than signal detector 200.

[0023] Fig. Figure 4 shows an inverter 400. Inverter 400 may be a detailed view of inverters 202, 204, 302. Inverter 400 is an inverting / non-inverting buffer that includes transistors Q1-Q6. Transistors Q1-Q2 are configured as a differential pair, and transistors Q3-Q6 are connected to bias inputs VB1 and V B2 biased to perform signal inversion. When the bias input V B1 is driven, the current generated by transistors Q1 and Q2 flows through transistors Q3 and Q6, while transistors Q4 and Q5 remain off. In contrast, when the bias input V B2 is driven, the current generated by transistors Q1 and Q2 passes through transistors Q4 and Q5, while transistors Q3 and Q6 remain off. In some embodiments, the bias inputs V B1 and V B2 controlled by a CML inverter. The transistor O t and the resistance R t act as a current source with V B3 as preload.

[0024] Although the foregoing devices have been described with reference to specific circuit elements, it should be understood that other mixers, inverters, dividers, and the like could be used. For example, in some embodiments, the circuit elements could be MOS devices. Furthermore, the elements could be implemented in other circuit topologies without changing the operating principle. For example, in some embodiments, the inverters could be implemented in the quadrature generator 102 or in the topologies of the mixers 104, 106. Furthermore, although the errors were discussed with reference to DC offset and quadrature error, it should be understood that other types of errors could also be determined according to various embodiments.

[0025] Fig. Figure 5 shows a receiver 500 with integrated error detection according to an embodiment of the present invention. The integrated error detection is used for calibrating and / or testing devices. The receiver 500 may be part of a system requiring efficient phased beamforming arrays, such as radar and communications systems, such as 5G. The receiver 500 includes an RF device 502, a signal detector 504, a reference signal generator 506, and a controller 508.

[0026] The RF device 502 is a device that produces a signal to be characterized by the system. The output of the RF device 502 is the input signal IN. In some embodiments, the RF device 502 is a single RF channel. In some embodiments, the RF device 502 is one of multiple devices, such as an RF chain in a beamforming array. As shown in Fig. 5, the RF device 502 may be powered by an external source or by the reference signal generator 506.

[0027] Signal detector 504 evaluates the response of the input signal IN from RF device 502. Signal detector 504 may be implemented using embodiments such as signal detector 200, 300. The output signals I and Q produced by signal detector 504 contain information about the amplitude and phase of the input signal IN. In some embodiments, signal detector 504 may be part of RF device 502.

[0028] The reference signal generator 506 provides the reference signal LO to the signal detector 504. In some embodiments, the reference signal LO may be produced by the same source that powers the RF device 502; for example, the reference signal LO and the input signal IN of the signal detector 504 may be obtained from the same source. In some embodiments, the reference signal generator 506 provides the reference signal LO independently of the RF device 502.

[0029] The controller 508 is coupled to the signal detector 504 and the reference signal generator 506. The controller 508 may be a microcontroller, a microprocessor, a DSP, a digital logic device, or the like, and controls the phase shift introduced by the RF device 502. In some embodiments, the controller 508 may also control the reference signal LO produced by the reference signal generator 506. The controller 508 is configured to perform a sweep of all values ​​of the phase difference Ø LO -O INand measure the output signals I and Q of the signal detector 504 for each phase difference. The controller 508 then inverts either the input signal IN or the reference signals LO by controlling the signal detector 504 and again performs a phase sweep to measure the output signals I and Q. The controller 508 determines the error values ​​in the signal detector 504 according to the embodiment techniques discussed above using the normal and inverted values ​​of I and Q. The calculated errors are used by the controller 508 to more accurately calculate the amplitude and phase of the input signal IN. In some embodiments, the controller 508 provides a calibration signal to the signal detector 504 to compensate for the values ​​of the errors (e.g., DC offset and quadrature error).

[0030] Fig. Figure 6 shows results measured with one embodiment. As shown, the compensated phase measurements have a lower standard deviation of error compared to uncompensated measurements. Due to quantization effects of ADCs in the controller, the calculated error values ​​themselves may contain some errors. In some embodiments, the controller takes these quantization effects into account when determining the error values. Although Fig. 6 compensated phase measurements, similarly improved results can be achieved for compensated amplitude measurements.

[0031] Fig. 7 is a block diagram of a wireless device 700 according to an embodiment of the present invention. The wireless device 700 includes an RF device 702, a logic core 704, and a memory 706. The RF device 702 produces an input signal and measures the amplitude and phase of the input signal. In some embodiments, the RF device 702 includes both an RF receiver and a signal detector. The logic core 704 is coupled to the RF device 702 and includes an analog or digital device, such as a microcontroller. The RF device 702 produces DC outputs indicative of the amplitude and phase of the input signal, and the logic core 704 measures the DC outputs. According to some embodiments, the logic core 704 determines error values ​​in the RF device 702 by inverting the DC outputs and comparing the inverted DC outputs with the non-inverted DC outputs.Logic core 704 determines coefficients indicative of the errors in RF device 702 and stores the coefficients in memory 706, which may include, for example, random access memory (RAM), flash memory, or the like. After the coefficients are determined and stored, they can be reused to correct subsequent determinations of the amplitude and phase of the input signal.

[0032] Fig. 8 is a flowchart of a device calibration method 800. The device calibration method 800 may indicate operations occurring in devices in the receiver 500, such as the controller 508.

[0033] The controller receives first I and Q values ​​from a signal detector (step 802). The signal detector may be, for example, signal detector 504. The first I and Q values ​​may be single values ​​or ranges of values ​​obtained by sweeping the phase difference Ø LO-O IN be determined.

[0034] The controller inverts the input signal IN or the reference signals LO for the signal detector (step 804). The signals can be inverted by programming a device, such as inverter 400, in the path of the input signal IN or the reference signals LO. The inverter can be controlled by the controller with a logic-level line.

[0035] The controller receives second I and Q values ​​from the signal detector (step 806). The second I and Q values ​​may be received in a similar manner to the first I and Q values.

[0036] The controller determines the errors in the signal detector (step 808). The errors are determined using the first and second I and Q values. Determining the errors may include calculating the DC offset and quadrature error of the signal detector using techniques discussed above.

[0037] The controller calculates the amplitude and phase of the input signal IN using the errors in the signal detector and the I and Q values ​​from the signal detector (step 810). For example, the controller may determine the amplitude and phase using the I and Q values ​​and then correct the values ​​in a post-processing step.

[0038] According to a preferred embodiment of the present invention, an apparatus includes: a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and second reference signals, the plurality of output signals indicative of the amplitude and phase of the input signal;and one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity;

[0039] In some embodiments, the quadrature demodulator includes a quadrature generator, wherein the quadrature generator includes the one or more inverting circuits. In some embodiments, the quadrature demodulator includes a plurality of mixers, wherein the plurality of mixers includes the one or more inverting circuits. In some embodiments, the one or more inverting circuits are programmable inverters, wherein the programmable inverters are coupled to the quadrature demodulator. In some embodiments, the one or more inverting circuits invert the input signal when the inverting circuits are set to the second programmable output polarity.In some embodiments, the one or more inverting circuits invert the first and second reference signals when the inverting circuits are set to the second programmable output polarity. In some implementations, the apparatus further includes a controller coupled to the quadrature demodulator, the controller configured to determine the amplitude and phase of the input signal according to the plurality of output signals.In some embodiments, the one or more inverting circuits are configured to be coupled to the controller, the controller further configured to set the inverting circuits to the first programmable output polarity while determining first values ​​of the plurality of output signals, set the inverting circuits to the second programmable output polarity while determining second values ​​of the plurality of output signals, and determine one or more error values ​​from the first and second values ​​of the plurality of output signals. In some embodiments, the controller is further configured to determine the error values ​​by subtracting the first values ​​of the plurality of output signals from the second values ​​of the plurality of output signals. In some embodiments, the error values ​​indicate a DC offset of the quadrature demodulator.In some embodiments, the error values ​​indicate a quadrature error of the quadrature demodulator.

[0040] According to a preferred embodiment of the present invention, a method includes: measuring, by a controller, first values ​​of a plurality of output signals from a radio frequency (RF) signal detector, the first values ​​of the plurality of output signals indicative of the amplitude and phase of an input signal of the RF signal detector according to a plurality of reference signals; inverting, by the controller, one of the input signal or the plurality of reference signals; measuring, by the controller, second values ​​of the plurality of output signals from the RF signal detector, and determining, by the controller, one or more error values ​​of the RF signal detector according to the first values ​​of the plurality of output signals and the second values ​​of the plurality of output signals.

[0041] In some embodiments, inverting includes inverting the input signal. In some embodiments, inverting includes inverting the plurality of reference signals. In some embodiments, determining includes subtracting the second values ​​of the plurality of output signals from respective ones of the first values ​​of the plurality of output signals to produce the one or more error values. In some embodiments, determining further includes averaging the one or more error values ​​to produce a final error value.In some embodiments, the method further includes: storing, by the controller, coefficients indicative of the one or more error values ​​of the RF signal detector; determining, by the controller, the amplitude and phase of the input signal according to the plurality of output signals; and correcting, by the controller, the amplitude and phase of the input signal according to the coefficients. In some embodiments, the one or more error values ​​include a DC offset of the RF signal detector and a quadrature error of the RF signal detector. In some embodiments, the first and second values ​​of the plurality of output signals are determined at different relative phases of the input signal and the plurality of reference signals.

[0042] According to a preferred embodiment of the present invention, a system includes: a radio frequency (RF) device including one or more inverters, the RF device being configured to receive an input signal and a reference signal and produce a first output signal and a second output signal according to the amplitude and phase of the input signal, the RF device being configured to invert the first output signal and the second output signal according to programmed values ​​of the one or more inverters;a processor coupled to the RF device, the processor configured to measure the first output signal and the second output signal, invert the first output signal and the second output signal with the one or more inverters, measure the inverted first output signal and the inverted second output signal, and determine error values ​​of the RF device according to the first output signal, the second output signal, the inverted first output signal, and the inverted second output signal; and a memory coupled to the processor, the memory configured to store coefficients indicative of the error values ​​of the RF device.

[0043] In some embodiments, the one or more inverters are configured to invert the input signal. In some embodiments, the one or more inverters are configured to invert the reference signal. In some embodiments, the processor is further configured to determine the amplitude and phase of the input signal according to the first output signal and the second output signal and to correct the determined amplitude and phase according to the coefficients.

[0044] An advantage of an embodiment of the present invention includes the ability to be implemented in an RF device for performing both functional testing and time-of-flight calibration of the RF device. Such features may also be useful in downstream RF and communications devices, such as beamforming arrays.

[0045] Although this invention has been described with reference to illustrative embodiments, this description should not be construed in a limiting sense. Upon reference to the description, various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art. It is therefore intended that the appended claims include all such modifications or embodiments.

Claims

[1] Device comprising: a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and second reference signals, the plurality of output signals indicative of the amplitude and phase of the input signal; one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity, and a controller (508) coupled to the quadrature demodulator, the controller (508) being configured to determine the amplitude and phase of the input signal according to the plurality of output signals, the one or more inverting circuits being configured to be coupled to the controller (508), the controller (508) further being configured to set the inverting circuits to the first programmable output polarity while determining first values of the plurality of output signals, set the inverting circuits to the second programmable output polarity while determining second values of the plurality of output signals, and determine one or more error values from the first and second values of the plurality of output signals, the controller (508) being further configured toto determine the error values by subtracting the first values of the plurality of output signals from the second values of the plurality of output signals, wherein determining comprises subtracting the second values of the plurality of output signals from respective ones of the first values of the plurality of output signals to produce the one or more error values. [2] The apparatus of claim 1, wherein the quadrature demodulator comprises a quadrature generator, the quadrature generator including the one or more inverting circuits. [3] The apparatus of claim 1 or 2, wherein the quadrature demodulator comprises a plurality of mixers (104, 106), the plurality of mixers (104, 106) including the one or more inverting circuits. [4] The apparatus of any one of claims 1 to 3, wherein the one or more inverting circuits are programmable inverters (202, 204), the programmable inverters (202, 204) being coupled to the quadrature demodulator. [5] The apparatus of any one of claims 1 to 4, wherein the one or more inverting circuits invert the input signal when the inverting circuits are set to the second programmable output polarity. [6] The apparatus of any one of claims 1 to 5, wherein the one or more inverting circuits invert the first and second reference signals when the inverting circuits are set to the second programmable output polarity. [7] The apparatus of any one of claim 1, wherein the error values indicate a DC offset of the quadrature demodulator. [8] Apparatus according to any one of claims 1 or 7, wherein the error values indicate a quadrature error of the quadrature demodulator. [9] Procedure comprising: Measuring first values of a plurality of output signals from a radio frequency (RF) signal detector (504) by a controller (508), wherein the first values of the plurality of output signals indicate the amplitude and phase of an input signal of the RF signal detector (504) according to a plurality of reference signals; Inverting one of the input signals or the plurality of reference signals by the controller (508); Measuring second values of the plurality of output signals from the RF signal detector (504) by the controller (508); Determining one or more error values of the RF signal detector (504) by the controller (508) according to the first values of the plurality of output signals and the second values of the plurality of output signals, wherein the determining comprises subtracting the second values of the plurality of output signals from respective ones of the first values of the plurality of output signals to produce the one or more error values, Storing coefficients indicative of the one or more error values of the RF signal detector (504) by the controller (508); determining the amplitude and phase of the input signal by the controller (508) according to the plurality of output signals; and Correcting the amplitude and phase of the input signal by the controller (508) according to the coefficients. [10] The method of claim 9, wherein inverting comprises inverting the input signal. [11] The method of claim 9, wherein inverting comprises inverting the plurality of reference signals. [12] The method of claim 9, wherein determining further comprises averaging the one or more error values to produce a final error value. [13] The method of claim 9, wherein the one or more error values include a DC offset of the RF signal detector (504) and a quadrature error of the RF signal detector (504). [14] The method of any one of claims 9 to 13, wherein the first and second values of the plurality of output signals are determined at different relative phases of the input signal and the plurality of reference signals. [15] System comprising: a radio frequency (RF) device (502) comprising one or more inverters (202, 204), the RF device (502) being configured to receive an input signal and a reference signal and to produce a first output signal and a second output signal according to the amplitude and phase of the input signal, the RF device (502) being configured to invert the first output signal and the second output signal according to programmed values of the one or more inverters (202, 204); a processor coupled to the RF device (502), the processor configured to measure the first output signal and the second output signal, invert the first output signal and the second output signal with the one or more inverters (202, 204), measure the inverted first output signal and the inverted second output signal, and determine error values of the RF device (502) according to the first output signal, the second output signal, the inverted first output signal, and the inverted second output signal, the processor further configured to determine the amplitude and phase of the input signal according to the first output signal and the second output signal and to correct the determined amplitude and phase according to the coefficients; and a memory (706) coupled to the processor, the memory (706) configured to store coefficients indicative of the error values of the RF device (502). [16] The system of claim 15, wherein the one or more inverters (202, 204) are configured to invert the input signal. [17] The system of claim 15 or 16, wherein the one or more inverters (202, 204) are configured to invert the reference signal.

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