Back contact solar cell, preparation method and battery assembly

Abstract

A back contact solar cell, a preparation method and a battery assembly, which belong to the technical field of crystalline silicon solar cells. The back contact solar cell comprises: a semiconductor substrate, the back surface of which includes first polarity regions and second polarity regions alternately arranged in a first direction; a first functional layer, which is disposed in the first polarity regions; a second functional layer, which is disposed in the second polarity regions; a laser protection layer, which is disposed on the side of the second functional layer away from the semiconductor substrate and exposes electrode contact regions of the second functional layer, wherein the material of the laser protection layer includes laser absorption material; first electrode structures, which are disposed on the side of the first functional layer away from the semiconductor substrate; and second electrode structures, which are disposed on the side of the second functional layer away from the semiconductor substrate and located in the electrode contact regions.

Description

Back contact solar cell, preparation method and battery assembly

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number: 202410274595.3 and application date of March 11, 2024, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of crystalline silicon solar cells, and more specifically, to a back-contact solar cell, a preparation method, and a cell assembly. Background Art

[0004] As PERC (Passivated Emitter and Rear Cell) battery technology matures and continues to tap its potential, it is gradually approaching the theoretical limit of its conversion efficiency. The industry has begun to seek next-generation technologies. The mainstream technologies currently being promoted include TOPCon (Tunnel Oxide Passivated Contact) batteries, HJT (Heterojunction) batteries, and IBC (Interdigitated back contact) batteries.

[0005] Unlike traditional double-sided electrode contact cells, the most significant feature of back-contact (BC) cells is that the metal electrode is located on the back surface of the cell, leaving the front surface unobstructed by the metal electrode. This improves light utilization, resulting in higher short-circuit current and conversion efficiency. Among various BC technologies, HBC (Hybrid Back Contact) technology has the highest photoelectric conversion efficiency. By adopting hybrid technology, passivation contact technology is applied to the back of the cell to form an HBC cell.

[0006] Currently, laser film opening technology is widely used to shorten the HBC cell process and increase production capacity for large-scale mass production. However, laser damage is deep, easily damaging the cell membrane. Furthermore, the amorphous silicon-based heterojunction in HBC cells is a low-temperature process (<200°C). The grown film is sensitive to the thermal effects of the laser and experiences severe thermal degradation, which can lead to a decrease in the cell's open-circuit voltage and photoelectric conversion efficiency.

[0007] Summary of the Invention

[0008] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a back-contact solar cell, a preparation method, and a cell assembly that protect the functional layers in the cell from excess laser damage during laser debonding, prevents thermal degradation of the heterojunction, and improves the cell's open-circuit voltage and photoelectric conversion efficiency.

[0009] In a first aspect, the present application provides a back-contact solar cell, comprising:

[0010] A semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, wherein the backlight surface includes first polarity regions and second polarity regions alternately arranged along a first direction;

[0011] A first functional layer is provided in the first polarity region, the first functional layer comprising a first passivation layer and a first doped semiconductor layer stacked in a direction away from the semiconductor substrate;

[0012] a second functional layer disposed in the second polarity region, the second functional layer comprising a second passivation layer and a second doped semiconductor layer stacked in a direction away from the semiconductor substrate, the doping type of the first doped semiconductor layer and the doping type of the second doped semiconductor layer being opposite;

[0013] a laser shielding layer, disposed on a side of the second functional layer away from the semiconductor substrate and exposing the electrode contact region of the second functional layer, wherein the material of the laser shielding layer includes a laser absorbing material;

[0014] A first electrode structure is provided on a side of the first functional layer away from the semiconductor substrate;

[0015] The second electrode structure is arranged on a side of the second functional layer away from the semiconductor substrate and is located in the electrode contact area.

[0016] According to the back-contact solar cell of the present application, the passivation contact technology is combined with the back side of the semiconductor substrate to form a hybrid back-contact cell. A laser protection layer is provided on the outside of the functional layer, so that during the laser film opening process, excess laser light can be absorbed to protect the film layer between the laser protection layer and the semiconductor substrate. Thermal attenuation of the heterojunction can also be avoided, thereby improving the open circuit voltage and photoelectric conversion efficiency of the cell.

[0017] According to one embodiment of the present application, the laser protection layer includes:

[0018] an insulating dielectric layer, disposed on a side of the second functional layer away from the semiconductor substrate and exposing an electrode contact region of the second functional layer;

[0019] The laser absorption layer is arranged on the side of the insulating medium layer away from the semiconductor substrate. The material of the laser absorption layer includes laser absorption material.

[0020] According to one embodiment of the present application, the material of the insulating dielectric layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the insulating dielectric layer is in the range of 10 nm to 100 nm.

[0021] According to one embodiment of the present application, the material of the laser absorption layer includes at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon and polycrystalline silicon, and the thickness of the laser absorption layer is in the range of 5 nm to 100 nm.

[0022] According to one embodiment of the present application, the second functional layer at least partially extends to the first polarity region, and a first orthographic projection of the first functional layer on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second functional layer on the semiconductor substrate;

[0023] The overlapping parts of the first functional layer and the second functional layer are in direct contact.

[0024] According to one embodiment of the present application, in a first direction, the first electrode structure and the second electrode structure both extend to both sides, an opening is provided between adjacent first electrode structures and second electrode structures, and the third orthographic projection of the opening on the semiconductor substrate is located within the orthographic projection of the laser protection layer on the semiconductor substrate.

[0025] According to one embodiment of the present application, the light-receiving surface is a suede surface, and the surfaces of the first polarity region and the second polarity region are polished surfaces.

[0026] According to one embodiment of the present application, a first distance between the surface of the first polarity region and the light receiving surface is greater than a second distance between the surface of the second polarity region and the light receiving surface, and the difference between the first distance and the second distance is 0.05 μm-5 μm.

[0027] According to one embodiment of the present application, the semiconductor substrate further includes a substrate doping layer, the substrate doping layer is located in the first polarity region and contacts the first passivation layer, and the doping type of the substrate doping layer is the same as the doping type of the first doped semiconductor layer;

[0028] The thickness of the substrate doping layer ranges from 5 nm to 200 nm.

[0029] According to one embodiment of the present application, the electrode structure includes a conductive layer and an electrode, wherein the conductive layer is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer away from the doped semiconductor layer;

[0030] Among them, the material of the conductive layer includes at least one of zinc oxide, indium oxide and tin oxide, and the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum elements. The thickness of the conductive layer ranges from 10nm to 120nm.

[0031] According to one embodiment of the present application, the first passivation layer includes a tunneling oxide, the thickness of the first passivation layer is in the range of 0.5nm-2.5nm, the first doped semiconductor layer includes doped polycrystalline silicon, the thickness of the first doped semiconductor layer is in the range of 10nm-250nm, the second passivation layer includes intrinsic amorphous silicon, the thickness of the second passivation layer is in the range of 1nm-15nm, the second doped semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second doped semiconductor layer is in the range of 1nm-60nm.

[0032] According to one embodiment of the present application, the back-contact solar cell also includes a third functional layer and an anti-reflection layer located on the light-receiving surface of the semiconductor substrate and stacked in a direction away from the semiconductor substrate, the third functional layer includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, a stack of silicon oxide and doped polycrystalline silicon, silicon nitride, silicon oxynitride and aluminum oxide, and the anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a transparent conductive oxide and magnesium fluoride.

[0033] In a second aspect, the present application provides a method for preparing a back-contact solar cell, comprising:

[0034] Providing a semiconductor substrate, the semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, the backlight surface including first polarity regions and second polarity regions alternately arranged along a first direction;

[0035] forming a first functional layer in the first polarity region, wherein the first functional layer comprises a first passivation layer and a first doped semiconductor layer stacked in a direction away from the semiconductor substrate;

[0036] forming a second functional layer in the second polarity region, the second functional layer comprising a second passivation layer and a second doped semiconductor layer stacked in a direction away from the semiconductor substrate, the doping type of the first doped semiconductor layer and the doping type of the second doped semiconductor layer being opposite;

[0037] forming a laser shielding layer on a side of the second functional layer away from the semiconductor substrate, wherein the material of the laser shielding layer includes a laser absorbing material;

[0038] Removing the film layer on the side away from the semiconductor substrate corresponding to the electrode contact region of the first functional layer and the second functional layer to expose the electrode contact region;

[0039] Electrode structures are formed in the electrode contact regions of the first functional layer and the second functional layer, respectively.

[0040] According to the preparation method of the present application, the passivation contact technology is combined with the back side of the semiconductor substrate to form a hybrid back contact battery. At the same time, a laser protection layer is formed on the outside of the functional layer, so that during the laser film opening process, excess laser light can be absorbed to protect the film layer between the laser protection layer and the semiconductor substrate. It can also avoid thermal attenuation of the heterojunction and improve the open circuit voltage and photoelectric conversion efficiency of the battery.

[0041] According to one embodiment of the present application, forming a laser shielding layer on a side of the second functional layer away from the semiconductor substrate includes:

[0042] forming an insulating dielectric layer on a side of the second functional layer away from the semiconductor substrate;

[0043] A laser absorption layer is formed on a side of the insulating dielectric layer away from the semiconductor substrate. The material of the laser absorption layer includes a laser absorption material.

[0044] According to one embodiment of the present application, forming a second functional layer to cover the first functional layer, and removing the film layer on the side away from the semiconductor substrate corresponding to the electrode contact region of the first functional layer, includes:

[0045] removing the laser absorption layer in the portion of the first functional layer corresponding to the electrode contact region by laser ablation, removing the insulating dielectric layer in the portion of the first functional layer corresponding to the electrode contact region by wet etching, and removing the second functional layer in the portion of the first functional layer corresponding to the electrode contact region by laser ablation; or

[0046] Laser ablation is used to remove the laser absorption layer, the insulating dielectric layer and the second functional layer in the portion corresponding to the electrode contact region of the first functional layer.

[0047] According to one embodiment of the present application, a first orthographic projection of a first functional layer on a semiconductor substrate and a second orthographic projection of a second functional layer on the semiconductor substrate at least partially overlap, and electrode structures are formed in electrode contact regions of the first functional layer and the second functional layer, respectively, including:

[0048] forming a conductive layer on a side of the first functional layer and the second functional layer away from the semiconductor substrate;

[0049] forming an opening in the orthographic projection of the laser shielding layer on the semiconductor substrate by laser ablation, wherein the opening at least separates the conductive layer and at most exposes the first functional layer;

[0050] Electrodes are formed on the sides of the conductive layer contacting the electrode contact regions of the first functional layer and the second functional layer, respectively, away from the semiconductor substrate.

[0051] According to one embodiment of the present application, removing the film layer on the side away from the semiconductor substrate corresponding to the electrode contact region of the second functional layer includes:

[0052] removing the laser absorption layer of the second functional layer corresponding to the electrode contact region by laser ablation;

[0053] The insulating dielectric layer at a portion corresponding to the electrode contact region of the second functional layer is removed by wet etching.

[0054] According to one embodiment of the present application, after providing the semiconductor substrate, the method further includes:

[0055] The surface of the semiconductor substrate is processed so that the light-receiving surface forms a velvet surface, and the surfaces of the first polarity region and the second polarity region form polished surfaces.

[0056] According to one embodiment of the present application, processing the surface of a semiconductor substrate includes:

[0057] Texturing the light-receiving surface and the backlight surface of the semiconductor substrate;

[0058] forming a first mask on the light-receiving surface of the semiconductor substrate;

[0059] Polishing the backlight surface of the semiconductor substrate;

[0060] The first mask is removed.

[0061] According to one embodiment of the present application, before processing the surface of the semiconductor substrate, the method further includes:

[0062] A gettering process is performed on the semiconductor substrate.

[0063] According to one embodiment of the present application, a gettering process is performed on a semiconductor substrate, including:

[0064] removing a damaged layer of the semiconductor substrate by wet etching;

[0065] Gettering of semiconductor substrates by high-temperature phosphorus diffusion;

[0066] The gettering layer of the semiconductor substrate formed in the gettering process is removed by wet etching.

[0067] According to one embodiment of the present application, forming a first functional layer in a first polarity region includes:

[0068] forming a substrate doping layer, a first functional layer, and a second mask in sequence on the backlight surface of the semiconductor substrate;

[0069] removing the substrate doping layer and the first functional layer corresponding to the second polarity region of the semiconductor substrate;

[0070] The second mask is removed.

[0071] In a third aspect, the present application provides a battery assembly comprising the aforementioned back-contact solar cell, or comprising a back-contact solar cell prepared according to the aforementioned preparation method.

[0072] The battery assembly according to the present application has a higher open circuit voltage and photoelectric conversion efficiency.

[0073] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0075] FIG1 is a schematic cross-sectional view of a back-contact solar cell according to an embodiment of the present application;

[0076] FIG2 is a schematic flow chart of a method for preparing a back-contact solar cell according to an embodiment of the present application;

[0077] FIG3 is a schematic diagram of a cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0078] FIG4 is a second schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0079] FIG5 is a third schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0080] FIG6 is a fourth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0081] FIG7 is a fifth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0082] FIG8 is a sixth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0083] FIG9 is a seventh schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0084] FIG10 is an eighth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application;

[0085] FIG11 is a ninth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present application.

[0086] Reference numerals:

[0087] Semiconductor substrate 1, first functional layer 2, first passivation layer 2-1, first doped semiconductor layer 2-2, substrate doping layer 3, second functional layer 4, second passivation layer 4-1, second doped semiconductor layer 4-2, insulating dielectric layer 5, laser absorption layer 6, third functional layer 7, anti-reflection layer 8, conductive layer 9, first conductive layer 9-1, second conductive layer 9-2, first electrode 10, second electrode 11, first polarity region A, second polarity region B, first mask M1, second mask M2, first surface S1, second surface S2, third surface S3, first opening G1, second opening G2, third opening G3, fourth opening G4. DETAILED DESCRIPTION

[0088] Embodiments of the present application are described in detail below, with examples of the embodiments illustrated in the accompanying drawings. In the accompanying drawings, the sizes of layers, regions, and components, as well as their relative sizes, may be exaggerated for clarity. Throughout, the same or similar reference numerals represent the same or similar components or components having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and intended only to explain the present application, and are not to be construed as limiting the present application.

[0089] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0090] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0091] In related technologies, the HBC cell structure generally has a polished TOPCon area on the back, a suede morphology on the back heterojunction area and the front, and a transparent conductive oxide outer layer on the back. This structure has a relatively simple process flow. In addition, in order to shorten the process flow and increase the capacity of large-scale mass production, laser film opening technology has also been widely used. By analyzing the process flow in related technologies, the following problems are found:

[0092] 1) The depth of laser damage is deep, and mask protection is required to produce patterns during patterning. Conventional masks are difficult to protect the film layer below. The heterojunction based on amorphous silicon is a low-temperature process (<200°C). The grown film layer is sensitive to the thermal effect of the laser and has severe thermal attenuation, which will lead to a decrease in the open circuit voltage and photoelectric conversion efficiency of the battery.

[0093] 2) The outermost layer on the back of the HBC battery is a transparent conductive oxide, which has poor resistance to moisture and heat, affecting the reliability of the battery and components.

[0094] 3) The interface defects and carrier recombination on the velvet surface are more serious than those on the polished surface, resulting in the passivation of the rear heterojunction region not being optimal, thus affecting the battery efficiency.

[0095] 4) After laser patterning, wet etching is required. The first functional layer in the mask-protected area is not etched, while the first functional layer in the mask-removed area is etched to expose the substrate, and then the second functional layer is formed. At the junction of the two areas, because the mask is not easily etched, while the mask-protected first functional layer is easily etched, the edge of the mask will protrude and hang in the air, affecting the formation and passivation effect of the second functional layer, resulting in low open circuit voltage and low conversion efficiency of the battery.

[0096] This application proposes a back-contact solar cell, preparation method, and cell module to address the aforementioned issues. By adding a protective layer to the HBC cell, laser damage to the film layer below the absorption layer can be reduced, thereby improving cell efficiency. The protective layer also improves the cell's resistance to moisture and heat, and enhances the reliability of the cell and module products. The HBC cell utilizes a fully polished back surface, which reduces interface defects and carrier recombination in the back heterojunction region, thereby increasing the cell's open-circuit voltage and photoelectric conversion efficiency. Furthermore, by removing the insulating layer between the two polar layers, the mask can be prevented from protruding into the air, thereby improving the cell's open-circuit voltage and conversion efficiency.

[0097] 1 , which shows a cross-sectional structure of a back-contact solar cell, an embodiment of the present application provides a back-contact solar cell.

[0098] In this embodiment, a back-contact solar cell includes a semiconductor substrate 1, a first functional layer 2, a second functional layer 4, a laser shielding layer, a first electrode structure, and a second electrode structure. The semiconductor substrate 1 has a light-receiving surface and a backlight surface relative to each other, and the backlight surface includes a first polarity region A and a second polarity region B alternately arranged along a first direction D1; the first functional layer 2 is arranged in the first polarity region A, and the first functional layer 2 includes a first passivation layer 2-1 and a first doped semiconductor layer 2-2 stacked in a direction away from the semiconductor substrate 1; the second functional layer 4 is arranged in the second polarity region B, and the second functional layer 4 includes a second passivation layer 4-1 and a second doped semiconductor layer 4-2 stacked in a direction away from the semiconductor substrate 1, and the doping type of the first doped semiconductor layer 2-2 is opposite to the doping type of the second doped semiconductor layer 4-2; the laser shielding layer is arranged on the side of the second functional layer 4 away from the semiconductor substrate 1, and exposes the electrode contact area of ​​the second functional layer 4, and the material of the laser shielding layer includes a laser absorption material; the first electrode structure is arranged on the side of the first functional layer 2 away from the semiconductor substrate 1; the second electrode structure is arranged on the side of the second functional layer 4 away from the semiconductor substrate 1, and is located in the electrode contact area.

[0099] In some embodiments, the semiconductor substrate 1 may include single crystal silicon, germanium, gallium arsenide, etc. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0100] As shown in Figure 1, the first polarity region A and the second polarity region B are arranged adjacent to each other in a first direction D1. A first opening G1 is formed on the light-receiving surface of the semiconductor substrate 1. This first opening G1 is used to form the second polarity region B. The surface of the first polarity region A is denoted as the first surface S1, the surface of the second polarity region B is denoted as the second surface S2, and the light-receiving surface of the semiconductor substrate 1 is denoted as the third surface S3.

[0101] In the manufacturing process, the second passivation layer 4-1 and the second doped semiconductor layer 4-2 are usually formed by a film forming process. Therefore, the preliminarily formed second functional layer 4 covers the first functional layer 2, and then the second functional layer 4 is patterned. Among them, in order to save the process, the second functional layer 4 is patterned by laser ablation. In this embodiment, before the second functional layer 4 is patterned, a laser protection layer is also formed on the side of the second functional layer 4 away from the semiconductor substrate 1. Therefore, when the second functional layer 4 is laser ablated, the laser protection layer portion corresponding to the portion of the second functional layer 4 that needs to be removed is first removed, and the remaining laser protection layer covers the portion of the second functional layer 4 except the electrode contact area, and then the second functional layer 4 is laser ablated, which can avoid damaging the portion of the second functional layer 4 that does not need to be removed.

[0102] It is understood that by providing a laser shielding layer on the outside of the functional layer, it is possible to absorb excess laser light during the laser film opening process, protecting the film layer between the laser shielding layer and the semiconductor substrate 1, and preventing thermal decay of the heterojunction, thereby improving the open circuit voltage and photoelectric conversion efficiency of the battery. In addition, since the laser shielding layer covering the portion of the second functional layer 4 other than the electrode contact area is retained, this portion of the laser shielding layer can also act as a water vapor barrier, improving the moisture and heat resistance of the back-contact solar cell.

[0103] In some embodiments, the laser protection layer includes an insulating dielectric layer 5 and a laser absorption layer 6. The insulating dielectric layer 5 is arranged on the side of the second functional layer 4 away from the semiconductor substrate 1, and exposes the electrode contact area of ​​the second functional layer 4; the laser absorption layer 6 is arranged on the side of the insulating dielectric layer 5 away from the semiconductor substrate 1, and the material of the laser absorption layer 6 includes laser absorption material.

[0104] The laser shielding layer forms a second opening G2 on the side of the second functional layer 4 away from the semiconductor substrate 1. The second opening G2 exposes a region of the second functional layer 4 as an electrode contact region. The second electrode structure contacts the electrode contact region to collect carriers in the second functional layer 4.

[0105] In this embodiment, the laser protection layer adopts a double-layer structure. The insulating dielectric layer 5 separates the laser absorption layer 6 from the second functional layer 4 to further protect the second functional layer 4.

[0106] It should be noted that the insulating dielectric layer 5 has better moisture and heat resistance than the conductive layer 9. Therefore, the insulating dielectric layer 5 can also isolate water vapor, improve the moisture and heat resistance of the back contact solar cell, and increase reliability.

[0107] In some embodiments, the material of the insulating dielectric layer 5 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the insulating dielectric layer 5 ranges from 10 nm to 100 nm. For example, the thickness of the insulating dielectric layer 5 can be 10 nm, 50 nm, or 100 nm.

[0108] In some embodiments, the material of the laser absorption layer 6 includes at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon, and polycrystalline silicon, and the thickness of the laser absorption layer 6 ranges from 5 nm to 100 nm. For example, the thickness of the laser absorption layer 6 can be 5 nm, 50 nm, or 100 nm.

[0109] In some embodiments, the first surface S1 and the second surface S2 are polished surface structures. For example, the first surface S1 and the second surface S2 may be polished surface morphologies that have been polished. The polishing process may be performed using a conventional alkaline polishing solution.

[0110] Since the backlight surface of the semiconductor substrate 1 is made into a polished surface, the interface area between the backlight surface of the semiconductor substrate 1 and the polar structure is reduced, thereby reducing the interface defects and carrier recombination in the heterojunction region of the backlight surface, and improving the open circuit voltage and photoelectric conversion efficiency of the back contact solar cell.

[0111] The third surface S3 has a suede structure, for example, a pyramid suede morphology and / or a corrosion pit suede morphology.

[0112] In some embodiments, a first distance between the surface of the first polarity region A and the light receiving surface is greater than a second distance between the surface of the second polarity region B and the light receiving surface. This facilitates complete removal of the original film layer of the first polarity region A when forming the first opening G1.

[0113] The difference between the first distance and the second distance is 0.05 μm-5 μm. For example, the difference between the first distance and the second distance can be 0.05 μm, 1 μm, or 5 μm.

[0114] In some embodiments, the semiconductor substrate 1 further includes a substrate doping layer 3. The substrate doping layer 3 is located in the first polarity region A and is formed on a side close to the first passivation layer 2-1. The doping type of the substrate doping layer 3 is the same as the doping type of the first doped semiconductor layer 2-2.

[0115] The surface of the substrate doping layer 3 near the first passivation layer 2-1 is a polished surface. The substrate doping layer 3 is formed by doping a portion of the semiconductor substrate 1. For example, the portion of the semiconductor substrate 1 within the first polarity region A is doped with particles such as boron to form a P-type substrate doping layer 3; alternatively, the portion of the semiconductor substrate 1 within the first polarity region A is doped with particles such as arsenic and phosphorus to form an N-type substrate doping layer 3.

[0116] In some embodiments, the thickness of the substrate doping layer 3 ranges from 5 nm to 200 nm. For example, the thickness of the substrate doping layer 3 can be 5 nm, 50 nm, 100 nm, or 200 nm.

[0117] In some embodiments, the material of the first passivation layer 2-1 may include a tunneling oxide, and the thickness of the first passivation layer 2-1 may range from 0.5 nm to 2.5 nm. For example, the thickness of the first passivation layer 2-1 may be 0.5 nm, 1.5 nm, or 2.5 nm. This provides a good passivation effect on the first surface S1 while ensuring the majority tunneling effect.

[0118] The surface of the first passivation layer 2-1 close to the semiconductor substrate 1 is also polished, thereby reducing the interface area between the first passivation layer 2-1 and the semiconductor substrate 1, thereby reducing the recombination probability of carriers at the interface between the first passivation layer 2-1 and the semiconductor substrate 1.

[0119] In some embodiments, the material of the first doped semiconductor layer 2-2 may include doped polysilicon, and the thickness of the first doped semiconductor layer 2-2 may range from 10 nm to 250 nm. For example, the thickness of the first doped semiconductor layer 2-2 may be 10 nm, 50 nm, 150 nm, or 250 nm. This provides a good field passivation effect while reducing the thickness of the film layer and reducing parasitic absorption.

[0120] The doping type of the first doped semiconductor layer 2-2 is the same as or opposite to the doping type of the semiconductor substrate 1. For example, if the semiconductor substrate 1 is N-type doping, the first doped semiconductor layer 2-2 can be N-type doped or P-type doped.

[0121] In some embodiments, the second passivation layer 4-1 includes intrinsic amorphous silicon, and the thickness of the second passivation layer 4-1 ranges from 1 nm to 15 nm. For example, the thickness of the second passivation layer 4-1 can be 1 nm, 10 nm, or 15 nm, thereby achieving a good passivation effect on the second surface S2.

[0122] The second passivation layer 4-1 is also polished on the side close to the semiconductor substrate 1. This reduces the interface area between the second passivation layer 4-1 and the semiconductor substrate 1, thereby reducing the recombination probability of carriers at the interface between the second passivation layer 4-1 and the semiconductor substrate 1.

[0123] In some embodiments, the second doped semiconductor layer 4-2 includes doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second doped semiconductor layer 4-2 ranges from 1 nm to 60 nm. For example, the thickness of the second doped semiconductor layer 4-2 can be 1 nm, 30 nm, or 60 nm. This provides a good field passivation effect while reducing the thickness of the film layer and reducing parasitic absorption.

[0124] The doping type of the second doped semiconductor layer 4-2 is opposite to the doping type of the first doped semiconductor layer 2-2. For example, if the first doped semiconductor layer 2-2 is N-type doped, the second doped semiconductor layer 4-2 may be P-type doped.

[0125] In some embodiments, the second functional layer 4 at least partially extends to the first polarity region A, the first orthographic projection of the first functional layer 2 on the semiconductor substrate 1 at least partially overlaps with the second orthographic projection of the second functional layer 4 on the semiconductor substrate 1, and the overlapping parts of the first functional layer 2 and the second functional layer 4 are in direct contact.

[0126] In the first direction D1, the second passivation layer 4-1 and the second doped semiconductor layer 4-2 extend toward the first polarity regions A on both sides, and respectively overlap with the first passivation layer 2-1 and the first doped semiconductor layer 2-2 located in the first polarity regions A on both sides. The orthographic projection of the overlapping portion on the semiconductor substrate 1 is located within the first polarity region A. Therefore, in the first direction D1, both sides of the first polarity region A have overlapping portions.

[0127] In the overlapping region, a first passivation layer 2-1, a first doped semiconductor layer 2-2, a second passivation layer 4-1, and a second doped semiconductor layer 4-2 are sequentially stacked in a direction away from the semiconductor substrate 1. During the fabrication of the second functional layer 4, no mask is applied to the side of the first functional layer 2 in the overlapping region away from the semiconductor substrate 1. This avoids the problem of an overhanging mask, facilitates the fabrication of the second functional layer 4, and improves the passivation quality at the interface between the first and second functional layers 2 and 4.

[0128] In some embodiments, the electrode structure includes a conductive layer 9 and an electrode. The conductive layer 9 is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer 9 away from the doped semiconductor layer.

[0129] The first electrode structure may have a P polarity and the second electrode structure may have an N polarity. Alternatively, the first electrode structure may have an N polarity and the second electrode structure may have a P polarity. The polarity of the electrode structure depends on the doping type of the functional layer it contacts.

[0130] The first electrode structure includes a first conductive layer 9-1 and a first electrode 10. A third opening G3 is formed on a side of the first doped semiconductor layer 2-2 away from the first passivation layer 2-1. The first conductive layer 9-1 covers the third opening G3 and extends along the first direction D1 to both sides of the third opening G3. The first electrode 10 is located on a side of the first conductive layer 9-1 away from the first doped semiconductor layer 2-2.

[0131] A portion of the second functional layer 4 may be located between the portion of the first conductive layer 9-1 extending out of the third opening G3 and the first functional layer 2. That is, the second passivation layer 4-1 and the second doped semiconductor layer 4-2, the insulating dielectric layer 5, and the laser absorption layer 6 may be located between the first conductive layer 9-1 and the first doped semiconductor layer 2-2, or the second passivation layer 4-1 and the second doped semiconductor layer 4-2 may be located between the first conductive layer 9-1 and the first doped semiconductor layer 2-2.

[0132] The second electrode structure includes a second conductive layer 9-2 and a second electrode 11. The second conductive layer 9-2 is formed on a side of the second doped semiconductor layer 4-2 away from the second passivation layer 4-1 and covers the second polarity region B. The second electrode 11 is located on a side of the second conductive layer 9-2 away from the second doped semiconductor layer 4-2.

[0133] In the first direction D1, both sides of the second conductive layer 9-2 can at least partially extend to the first polarity region A, and the orthographic projection of the second conductive layer 9-2 on the semiconductor substrate 1 at least partially overlaps with the second orthographic projection of the second functional layer 4 on the semiconductor substrate 1. The second conductive layer 9-2 and the first doped semiconductor layer 2-2 are separated by a second passivation layer 4-1 and a second doped semiconductor layer 4-2, an insulating dielectric layer 5, and a laser absorption layer 6, or separated by a second passivation layer 4-1 and a second doped semiconductor layer 4-2.

[0134] In some embodiments, the first conductive layer 9-1 and the second conductive layer 9-2 include a transparent conductive oxide. For example, the material of the first conductive layer 9-1 and the second conductive layer 9-2 includes at least one of zinc oxide, indium oxide, and tin oxide. The material of the first electrode 10 and the second electrode 11 can be a metal material, such as silver or copper.

[0135] In some embodiments, the first conductive layer 9 - 1 and the second conductive layer 9 - 2 may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum.

[0136] In some embodiments, the first conductive layer 9 - 1 and the second conductive layer 9 - 2 have the same thickness, ranging from 10 nm to 120 nm. For example, the thickness of the conductive layer 9 can be 10 nm, 50 nm, or 120 nm.

[0137] In some embodiments, a fourth opening G4 is provided between adjacent first and second electrode structures, and a third orthographic projection of the fourth opening G4 on the semiconductor substrate 1 is located within the orthographic projection of the laser shielding layer on the semiconductor substrate 1. The first and second electrode structures are isolated by the fourth opening G4 to prevent short circuits.

[0138] The fourth opening G4 is located between each second opening G2 and the third opening G3. The orthographic projection of the fourth opening G4 on each of G2 and G3 on the semiconductor substrate 1 can be located at the first polarity region A, the second polarity region B, or the intersection of the first polarity region A and the second polarity region B. The fourth opening G4 at least separates the first conductive layer 9-1 and the second conductive layer 9-2 and exposes at most the first functional layer 2. As shown in Figure 1, the fourth opening G4 separates the first conductive layer 9-1 and the second conductive layer 9-2, and cuts off the second passivation layer 4-1 and the second doped semiconductor layer 4-2, exposing the insulating dielectric layer 5 or the first doped semiconductor layer 2-2.

[0139] In some embodiments, the back-contact solar cell further includes a third functional layer 7 and an anti-reflection layer 8 located on the light-receiving surface of the semiconductor substrate 1. The third functional layer 7 contacts the light-receiving surface of the semiconductor substrate 1, and the anti-reflection layer 8 is located on a side of the third functional layer 7 away from the semiconductor substrate 1 and contacts the third functional layer 7. The light-receiving surface of the semiconductor substrate 1 is a velvet surface, and the surface of the third functional layer 7 on the side close to the semiconductor substrate 1 is also a velvet surface.

[0140] The third functional layer 7 includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The anti-reflection layer 8 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a transparent conductive oxide.

[0141] Referring to Figure 2, which shows a process for preparing a back-contact solar cell, an embodiment of the present application further provides a method for preparing a back-contact solar cell.

[0142] In this embodiment, the method for preparing a back-contact solar cell includes step 10 , step 20 , step 30 , step 40 , step 50 and step 60 .

[0143] Step 10: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a light-receiving surface and a backlight surface opposite to each other, wherein the backlight surface includes first polarity regions A and second polarity regions B alternately arranged along a first direction;

[0144] Step 20: forming a first functional layer 2 in the first polarity region A, wherein the first functional layer 2 includes a first passivation layer 2-1 and a first doped semiconductor layer 2-2 stacked in a direction away from the semiconductor substrate 1;

[0145] Step 30: forming a second functional layer 4 in the second polarity region B, wherein the second functional layer 4 includes a second passivation layer 4-1 and a second doped semiconductor layer 4-2 stacked in a direction away from the semiconductor substrate 1, wherein the doping type of the first doped semiconductor layer 2-2 is opposite to the doping type of the second doped semiconductor layer 4-2;

[0146] Step 40: forming a laser shielding layer on a side of the second functional layer 4 away from the semiconductor substrate 1, wherein the material of the laser shielding layer includes a laser absorbing material;

[0147] Step 50: removing the film layers on the side away from the semiconductor substrate 1 corresponding to the electrode contact regions of the first functional layer 2 and the second functional layer 4 to expose the electrode contact regions;

[0148] Step 60 : forming electrode structures in the electrode contact regions of the first functional layer 2 and the second functional layer 4 , respectively.

[0149] In this embodiment, the structure of the back-contact solar cell prepared according to the preparation method can refer to the aforementioned embodiment. By forming a laser shielding layer on the outside of the second functional layer 4, it can absorb excess laser light during the laser film opening process, protecting the second functional layer 4 between the laser shielding layer and the semiconductor substrate 1, and preventing thermal decay of the heterojunction, thereby improving the open circuit voltage and photoelectric conversion efficiency of the cell.

[0150] 3-11 , which illustrate a cell cross-sectional structure at each stage in a preparation process, specifically illustrate an implementation of the method for preparing a back-contact solar cell provided in the present application.

[0151] As shown in FIG3 , in some embodiments, step 10 may be followed by: processing the surface of the semiconductor substrate 1 so that the light-receiving surface forms a velvet surface, and the surfaces of the first polarity region A and the second polarity region B form polished surfaces.

[0152] In this embodiment, the light-receiving and backlight-receiving surfaces of the semiconductor substrate 1 are first processed to impart a textured surface to the light-receiving surface, such as a pyramidal texture and / or a pitted texture, and to impart a polished surface to the backlight surface, such as a polished, light-receiving surface. Subsequently, various film layers are formed on the semiconductor substrate 1 to form a hybrid back-contact solar cell. This reduces interface defects and carrier recombination in the heterojunction region on the backlight side, resulting in a solar cell with a higher open-circuit voltage and photoelectric conversion efficiency. Furthermore, the fabrication process is simplified, facilitating large-scale mass production.

[0153] The semiconductor substrate 1 may include materials such as single crystal silicon, germanium, or gallium arsenide, etc. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0154] As an example, the specific process of processing the surface of the semiconductor substrate 1 can be: first, the light-receiving surface and the backlight surface of the semiconductor substrate 1 are textured; then, a first mask M1 is formed on the light-receiving surface of the semiconductor substrate 1; then, the backlight surface of the semiconductor substrate 1 is polished; and finally, the first mask M1 is removed.

[0155] The semiconductor substrate 1 is immersed in a texturing solution to achieve double-sided texturing on both the light-receiving and backlight-receiving surfaces. A mask M1 is then formed on the light-receiving surface to protect the textured morphology of the light-receiving surface during subsequent polishing. The material of the mask M1 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0156] Semiconductor substrate 1, with mask M1 prepared, is immersed in an alkaline polishing solution to polish the backlight side of semiconductor substrate 1 to form a polished surface. After polishing, a certain thickness of mask M1 remains on the backlight side of semiconductor substrate 1 to ensure a textured surface on the light-receiving side of semiconductor substrate 1. This remaining thickness can range from 10 nm to 100 nm, such as 10 nm, 50 nm, or 100 nm.

[0157] In some embodiments, the step of removing the mask M1 may be performed during the subsequent step of preparing the first functional layer 2 , that is, after polishing the backlight surface of the semiconductor substrate 1 , the first mask M1 is retained and step 20 is performed.

[0158] In some embodiments, before processing the surface of the semiconductor substrate 1, the step of performing a gettering treatment on the semiconductor substrate 1 may be further included. By performing the gettering treatment on the semiconductor substrate 1, the content of impurity elements in the semiconductor substrate 1 can be reduced, thereby reducing carrier recombination.

[0159] As an example, the process of performing a gettering treatment on the semiconductor substrate 1 may include: first, removing a damaged layer of the semiconductor substrate 1 by wet etching; then, performing a gettering treatment on the semiconductor substrate 1 by high-temperature phosphorus diffusion; and finally, removing a gettering layer formed during the gettering treatment on the semiconductor substrate 1 by wet etching. This can effectively reduce the content of impurity elements within the semiconductor substrate 1.

[0160] In some embodiments, the specific process of forming the first functional layer 2 in the first polarity region A may include: forming a substrate doping layer 3, a first functional layer 2 and a second mask M2 in sequence on the backlight surface of the semiconductor substrate 1; removing the substrate doping layer 3 and the first functional layer 2 corresponding to the second polarity region B of the semiconductor substrate 1; and removing the second mask M2.

[0161] 4 , a first passivation layer 2-1 and a first doped semiconductor layer 2-2 are prepared by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The material of the first passivation layer 2-1 may include a tunneling oxide, and its thickness ranges from 0.5 nm to 2.5 nm. For example, 0.5 nm, 1.5 nm, or 2.5 nm. The material of the first doped semiconductor layer 2-2 may include doped polysilicon, and its thickness ranges from 10 nm to 250 nm. For example, 10 nm, 50 nm, 150 nm, or 250 nm. The doping method of the first doped semiconductor layer 2-2 is to prepare in-situ doped amorphous / polycrystalline silicon and then perform high temperature annealing and crystallization, or to prepare an intrinsic amorphous / polycrystalline silicon layer and then perform high temperature diffusion for doping and crystallization.

[0162] In this embodiment, while forming the first functional layer 2, the dopant elements in the first doped semiconductor layer 2-2 enter the backlit surface of the semiconductor substrate 1 through the first passivation layer 2-1 to form a substrate doping layer 3. The doping type of the substrate doping layer 3 is the same as that of the first doped semiconductor layer 2-2. The thickness of the substrate doping layer 3 ranges from 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0163] After the first functional layer 2 is formed, a second mask M2 is prepared on a side of the first functional layer 2 away from the semiconductor substrate 1. The material of the second mask M2 includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0164] As shown in FIG5 , a first opening G1 is formed in the substrate doping layer 3, the first functional layer 2, and the second mask M2 on the side of the semiconductor substrate 1 that is away from the semiconductor substrate 1 and corresponds to the second polarity region B. The first opening G1 exposes the second surface S2. The distance between the first surface S1 and the third surface S3 is greater than the distance between the second surface S2 and the third surface S3. By removing a certain thickness of the semiconductor substrate 1, it is ensured that no substrate doping layer 3 remains.

[0165] As an example, a portion of the second mask M2 can be removed first by laser etching, ink printing, or other methods. Then, wet chemical etching can be used to remove the first doped semiconductor layer 2-2, the first passivation layer 2-1, and the substrate doping layer 3 in the area without the second mask M2. The wet chemical etching also includes the simultaneous removal of the first functional layer 2 deposited on the front side or plated around the front edge, exposing the first mask M1.

[0166] In some embodiments, the wet chemical etching solution used in the wet chemical etching process includes an alkaline polishing solution, so that the second surface S2 can be polished to form a polished surface while removing the substrate doping layer 3 to reduce surface defects.

[0167] 6 , the first mask M1 is removed to expose the third surface S3 , and the second mask M2 is simultaneously removed to expose the first doped semiconductor layer 2 - 2 . The first mask M1 and the second mask M2 can be removed by wet chemical etching, and the chemical solution may include hydrofluoric acid.

[0168] As shown in Figure 7, a second functional layer 4 is formed on the backlight side of the semiconductor substrate 1, and the second functional layer 4 covers the first functional layer 2. A second passivation layer 4-1 and a second doped semiconductor layer 4-2 are prepared on the backlight side of the semiconductor substrate 1 by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The second passivation layer 4-1 includes intrinsic amorphous silicon, and its thickness ranges from 1nm to 15nm. For example, 1nm, 10nm or 15nm. The second doped semiconductor layer 4-2 includes doped amorphous silicon and / or microcrystalline silicon, and its thickness ranges from 1nm to 60nm, such as 1nm, 30nm or 60nm. The doping type of the second doped semiconductor layer 4-2 is opposite to the doping type of the first doped semiconductor layer 2-2.

[0169] In some embodiments, after forming the second functional layer 4 on the backlight surface of the semiconductor substrate 1, the following steps may be performed: forming a third functional layer 7 and an anti-reflection layer 8 in sequence on the light-receiving surface of the semiconductor substrate 1. The third functional layer 7 and the anti-reflection layer 8 may also be formed using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The third functional layer 7 includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The anti-reflection layer 8 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a transparent conductive oxide.

[0170] In some embodiments, the process of forming a laser protection layer on the side of the second functional layer 4 away from the semiconductor substrate 1 may include: forming an insulating dielectric layer 5 on the side of the second functional layer 4 away from the semiconductor substrate 1; forming a laser absorption layer 6 on the side of the insulating dielectric layer 5 away from the semiconductor substrate 1, and the material of the laser absorption layer 6 includes a laser absorption material.

[0171] The laser shielding layer adopts a double-layer structure. The insulating dielectric layer 5 separates the laser absorption layer 6 from the second functional layer 4, further protecting the second functional layer 4. It should be noted that the insulating dielectric layer 5 has better moisture and heat resistance than the conductive layer 9. Therefore, the insulating dielectric layer 5 can also isolate water vapor, improving the moisture and heat resistance of the back-contact solar cell and enhancing its reliability.

[0172] As shown in FIG. 8 , a second opening G2 and a third opening G3 are formed to expose the electrode contact regions of the first functional layer 2 and the second functional layer 4 .

[0173] As an example, the specific process of removing the film layer on the side away from the semiconductor substrate 1 corresponding to the electrode contact area of ​​the second functional layer 4 may include: using laser ablation to remove the laser absorption layer 6 in the portion corresponding to the electrode contact area of ​​the second functional layer 4; and using wet etching to remove the insulating dielectric layer 5 in the portion corresponding to the electrode contact area of ​​the second functional layer 4.

[0174] In this embodiment, the insulating dielectric layer 5 is removed by wet etching, which can reduce the damage of the laser to the second functional layer 4 compared with directly removing the laser absorption layer 6 and the insulating dielectric layer 5 by laser ablation.

[0175] As an example, the specific process for removing the film layer on the side of the first functional layer 2, corresponding to the electrode contact region and away from the semiconductor substrate 1, may include: using laser ablation to remove the laser absorption layer 6 in the portion of the first functional layer 2 corresponding to the electrode contact region; using wet etching to remove the insulating dielectric layer 5 in the portion of the first functional layer 2 corresponding to the electrode contact region; and using laser ablation to remove the second functional layer 4 in the portion of the first functional layer 2 corresponding to the electrode contact region. Removing the insulating dielectric layer 5 by wet etching can reduce laser damage to the second functional layer 4.

[0176] In another example, laser ablation is used to remove the laser absorption layer 6, the insulating dielectric layer 5, the second doped semiconductor layer 4-2 and the second passivation layer 4-1 corresponding to the electrode contact area of ​​the first functional layer 2, exposing the first doped semiconductor layer 2-2 to form a third opening G3.

[0177] In step 50, after wet etching, the remaining thickness of the anti-reflection layer 8 after thinning is 20 nm to 120 nm. For example, the remaining thickness of the anti-reflection layer 8 can be 20 nm, 70 nm, or 120 nm.

[0178] After step 50, the second orthographic projection of the remaining second functional layer 4 on the semiconductor substrate 1 at least partially overlaps with the first orthographic projection of the first functional layer 2 on the semiconductor substrate 1. In the overlapping region, the first passivation layer 2-1, the first doped semiconductor layer 2-2, the second passivation layer 4-1, and the second doped semiconductor layer 4-2 are sequentially stacked in a direction away from the semiconductor substrate 1.

[0179] In some embodiments, the specific process of step 60 may include: forming a conductive layer 9 on the side of the first functional layer 2 and the second functional layer 4 away from the semiconductor substrate 1; forming a fourth opening G4 in the overlapping area of ​​the first orthographic projection and the second orthographic projection by laser ablation, and the fourth opening G4 at least isolates the conductive layer 9 and at most exposes the first functional layer 2; and forming electrodes on the side away from the semiconductor substrate 1 of the contact portion of the conductive layer 9 and the electrode contact area of ​​the first functional layer 2 and the second functional layer 4.

[0180] As shown in FIG9 , a conductive layer 9 is formed on the side of the first functional layer 2 and the second functional layer 4 away from the semiconductor substrate 1. The conductive layer 9 can be prepared by physical vapor deposition (PVD) and chemical vapor deposition (CVD), and can be selected from reactive plasma deposition (RPD), magnetron sputtering, pulsed laser deposition (PLD), vacuum evaporation, atomic layer deposition (ALD), etc. The material of the conductive layer 9 includes at least one of zinc oxide, indium oxide, and tin oxide, which can be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum. The thickness of the conductive layer 9 ranges from 10 nm to 150 nm, such as 10 nm, 50 nm, or 150 nm.

[0181] As shown in Figure 10, the fourth opening G4 is formed by etching the overlapping area of ​​the first functional layer 2 and the second functional layer 4 using laser etching, ink printing, and / or wet chemical methods. The fourth opening G4 is located between each second opening G2 and the third opening G3. The fourth opening G4 at least completely cuts off the conductive layer 9 to expose the laser absorption layer 6, and at most exposes the first doped semiconductor layer 2-2. The fourth opening G4 divides the conductive layer 9 into two parts: the first conductive layer 9-1 covering the third opening G3, and the second conductive layer 9-2 covering the second opening G2.

[0182] In some embodiments, the fourth opening G4 exposes the insulating dielectric layer 5 .

[0183] As shown in FIG11 , a first electrode 10 and a second electrode 11 are prepared by screen printing, inkjet printing, or electroplating. The first electrode 10 is located on a side of the first conductive layer 9-1 away from the semiconductor substrate 1. The second electrode 11 is located on a side of the second conductive layer 9-2 away from the semiconductor substrate 1.

[0184] One embodiment of the present application further provides a battery assembly. The battery assembly includes the aforementioned back-contact solar cell, or includes a back-contact solar cell prepared according to the aforementioned preparation method. The specific structure and principle of the back-contact solar cell, as well as the specific steps of the preparation method, can be referred to in the aforementioned embodiments and will not be described in detail in this embodiment. The battery assembly has a high open-circuit voltage and photoelectric conversion efficiency.

[0185] In this document, the terms "comprises", "includes" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0186] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A back contact solar cell, wherein: include: A semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, wherein the backlight surface includes first polarity regions and second polarity regions alternately arranged along a first direction; a first functional layer, disposed in the first polarity region, the first functional layer comprising a first passivation layer and a first doped semiconductor layer stacked in a direction away from the semiconductor substrate; a second functional layer disposed in the second polarity region, the second functional layer comprising a second passivation layer and a second doped semiconductor layer stacked in a direction away from the semiconductor substrate, the doping type of the first doped semiconductor layer being opposite to the doping type of the second doped semiconductor layer; a laser shielding layer, disposed on a side of the second functional layer away from the semiconductor substrate and exposing an electrode contact region of the second functional layer, wherein the material of the laser shielding layer comprises a laser absorbing material; a first electrode structure, disposed on a side of the first functional layer away from the semiconductor substrate; The second electrode structure is arranged on a side of the second functional layer away from the semiconductor substrate and is located in the electrode contact area.

2. The back contact solar cell according to claim 1, wherein: The laser protection layer comprises: an insulating dielectric layer, disposed on a side of the second functional layer away from the semiconductor substrate and exposing an electrode contact region of the second functional layer; The laser absorption layer is arranged on a side of the insulating dielectric layer away from the semiconductor substrate, and the material of the laser absorption layer includes a laser absorption material.

3. The back contact solar cell according to claim 2, wherein: The material of the insulating dielectric layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the insulating dielectric layer is in the range of 10 nm to 100 nm.

4. The back contact solar cell according to claim 2, wherein: The material of the laser absorption layer includes at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon and polycrystalline silicon, and the thickness of the laser absorption layer ranges from 5 nm to 100 nm.

5. The back-contact solar cell according to any one of claims 1 to 4, wherein The second functional layer at least partially extends to the first polarity region, and a first orthographic projection of the first functional layer on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second functional layer on the semiconductor substrate; The overlapping parts of the first functional layer and the second functional layer are in direct contact.

6. The back-contact solar cell according to any one of claims 1 to 5, wherein: In the first direction, the first electrode structure and the second electrode structure both extend to both sides, an opening is provided between adjacent first electrode structures and second electrode structures, and the third orthographic projection of the opening on the semiconductor substrate is located within the orthographic projection of the laser protection layer on the semiconductor substrate.

7. The back-contact solar cell according to any one of claims 1 to 6, wherein: The light-receiving surface is a suede surface, and the surfaces of the first polarity region and the second polarity region are polished surfaces.

8. The back contact solar cell according to claim 7, wherein: A first distance between the surface of the first polarity region and the light receiving surface is greater than a second distance between the surface of the second polarity region and the light receiving surface, and a difference between the first distance and the second distance is 0.05 μm-5 μm.

9. The back-contact solar cell according to any one of claims 1 to 8, wherein The semiconductor substrate further includes a substrate doping layer, the substrate doping layer is located in the first polarity region and contacts the first passivation layer, and the doping type of the substrate doping layer is the same as the doping type of the first doped semiconductor layer; Wherein, the thickness of the substrate doping layer ranges from 5nm to 200nm.

10. The back-contact solar cell according to any one of claims 1 to 9, wherein The electrode structure includes a conductive layer and an electrode, wherein the conductive layer is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer away from the doped semiconductor layer; The material of the conductive layer includes at least one of zinc oxide, indium oxide and tin oxide, the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum, and the thickness of the conductive layer is in the range of 10nm-120nm.

11. The back-contact solar cell according to any one of claims 1 to 10, wherein: The first passivation layer includes tunneling oxide, and the thickness of the first passivation layer ranges from 0.5nm to 2.5nm. The first doped semiconductor layer includes doped polycrystalline silicon, and the thickness of the first doped semiconductor layer ranges from 10nm to 250nm. The second passivation layer includes intrinsic amorphous silicon, and the thickness of the second passivation layer ranges from 1nm to 15nm. The second doped semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second doped semiconductor layer ranges from 1nm to 60nm.

12. The back-contact solar cell according to any one of claims 1 to 11, wherein: The back-contact solar cell also includes a third functional layer and an anti-reflection layer located on the light-receiving surface of the semiconductor substrate and stacked in a direction away from the semiconductor substrate. The third functional layer includes at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, silicon oxide, a stack of silicon oxide and doped polycrystalline silicon, silicon nitride, silicon oxynitride and aluminum oxide. The anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a transparent conductive oxide and magnesium fluoride.

13. A method for preparing a back-contact solar cell, wherein: include: Providing a semiconductor substrate, the semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, the backlight surface including first polarity regions and second polarity regions alternately arranged along a first direction; forming a first functional layer in the first polarity region, wherein the first functional layer includes a first passivation layer and a first doped semiconductor layer stacked in a direction away from the semiconductor substrate; forming a second functional layer in the second polarity region, the second functional layer comprising a second passivation layer and a second doped semiconductor layer stacked in a direction away from the semiconductor substrate, wherein the doping type of the first doped semiconductor layer is opposite to the doping type of the second doped semiconductor layer; forming a laser shielding layer on a side of the second functional layer away from the semiconductor substrate, wherein the material of the laser shielding layer includes a laser absorbing material; removing the film layers on the side away from the semiconductor substrate corresponding to the electrode contact regions of the first functional layer and the second functional layer to expose the electrode contact regions; Electrode structures are formed in the electrode contact regions of the first functional layer and the second functional layer respectively.

14. The preparation method according to claim 13, wherein The forming of a laser shielding layer on a side of the second functional layer away from the semiconductor substrate comprises: forming an insulating dielectric layer on a side of the second functional layer away from the semiconductor substrate; A laser absorption layer is formed on a side of the insulating dielectric layer away from the semiconductor substrate, and the material of the laser absorption layer includes a laser absorption material.

15. The preparation method according to claim 14, wherein The second functional layer is formed to cover the first functional layer, and the film layer on the side away from the semiconductor substrate corresponding to the electrode contact region of the first functional layer is removed, comprising: removing the laser absorption layer in the portion of the first functional layer corresponding to the electrode contact region by laser ablation, removing the insulating dielectric layer in the portion of the first functional layer corresponding to the electrode contact region by wet etching, and removing the second functional layer in the portion of the first functional layer corresponding to the electrode contact region by laser ablation; or Laser ablation is used to remove the laser absorption layer, the insulating dielectric layer and the second functional layer in the portion corresponding to the electrode contact region of the first functional layer.

16. The preparation method according to claim 15, wherein A first orthographic projection of the first functional layer on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second functional layer on the semiconductor substrate, and forming electrode structures in the electrode contact regions of the first functional layer and the second functional layer respectively includes: forming a conductive layer on a side of the first functional layer and the second functional layer away from the semiconductor substrate; forming an opening in the orthographic projection of the laser shielding layer on the semiconductor substrate by laser ablation, wherein the opening at least blocks the conductive layer and exposes at most the first functional layer; Electrodes are formed on the sides of the conductive layer contacting the electrode contact regions of the first functional layer and the second functional layer, respectively, away from the semiconductor substrate.

17. The preparation method according to claim 14, wherein Removing the film layer on the side away from the semiconductor substrate corresponding to the electrode contact region of the second functional layer, comprising: removing the laser absorption layer of the second functional layer corresponding to the electrode contact region by laser ablation; The insulating dielectric layer at a portion corresponding to the electrode contact region of the second functional layer is removed by wet etching.

18. The preparation method according to any one of claims 13 to 17, wherein After providing the semiconductor substrate, the method further includes: The surface of the semiconductor substrate is processed to form a velvet surface on the light receiving surface, and the surface of the first polarity region and The surface of the second polarity region forms a polished surface.

19. The preparation method according to claim 18, wherein The processing of the surface of the semiconductor substrate comprises: Texturing the light-receiving surface and the backlight surface of the semiconductor substrate; forming a first mask on the light-receiving surface of the semiconductor substrate; polishing the backlight surface of the semiconductor substrate; The first mask is removed.

20. The preparation method according to claim 18, wherein Before processing the surface of the semiconductor substrate, the method further comprises: A gettering process is performed on the semiconductor substrate.

21. The preparation method according to claim 20, wherein The step of performing gettering on the semiconductor substrate comprises: removing the damaged layer of the semiconductor substrate by wet etching; Performing a gettering process on the semiconductor substrate by high-temperature phosphorus diffusion; The gettering layer of the semiconductor substrate formed in the gettering process is removed by wet etching.

22. The preparation method according to any one of claims 13 to 21, wherein The forming of the first functional layer in the first polarity region includes: forming a substrate doping layer, a first functional layer, and a second mask in sequence on the backlight surface of the semiconductor substrate; removing the substrate doping layer and the first functional layer from portions corresponding to the second polarity region of the semiconductor substrate; The second mask is removed.

23. A battery assembly, wherein: A back-contact solar cell comprising the back-contact solar cell according to any one of claims 1-12, or a back-contact solar cell prepared by the preparation method according to any one of claims 13-22.

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