Method for manufacturing a substrate wafer for building III-V devices thereon and substrate wafer for building III-V devices thereon - Patents.com

Abstract

1. A method for manufacturing a substrate wafer for building III-V devices thereon, the method comprising: providing a silicon single crystal wafer; forming a gettering region below a top surface of the silicon single crystal wafer; and forming a nitrogen-rich passivation layer representing a top portion of the substrate wafer.

Description

[Technical field]

[0001] The present invention provides a method for manufacturing a substrate wafer for constructing III-V devices thereon, and a substrate wafer for constructing III-V devices thereon. [Background technology]

[0002] Conventional technology / issues III-V devices such as high-electron-mobility transistors (HEMTs) are known to have superior performance in high power and high frequency applications. A vast amount of patent and non-patent literature is available that covers this topic.

[0003] For example, U.S. Patent Application Publication No. 20160240646 discloses the structure and fabrication of several HEMT devices that can be constructed on a substrate wafer.

[0004] According to US Patent Publication No. 20140117502, a gettering region may be provided in a semiconductor substrate wafer.

[0005] Many approaches have been pursued to mitigate leakage currents in device structures, and the provision of a passivation layer is one tool to address this problem.

[0006] For example, WO2015123534 discloses a buried implant layer in the buffer region of a III-V device to suppress leakage current normal to the substrate. Summary of the Invention [Problem to be solved by the invention]

[0007] The present inventors have discovered that there is a need for improved substrate wafers, particularly to prevent dangling bonds from increasing the density of defect states and charge densities that disrupt the proper functioning of III-V devices. [Means for solving the problem]

[0008] explanation The present invention relates to a method for manufacturing a substrate wafer for constructing III-V devices thereon, the method comprising the steps of: Providing a silicon single crystal wafer; forming a gettering region below an upper surface of a silicon single crystal wafer; forming a nitrogen-rich passivation layer representing an upper portion of the substrate wafer; The present invention relates to a method comprising the steps of: [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates a cross-sectional view of a substrate wafer according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The dangling bonds are saturated or neutralized by providing at least one nitrogen-rich region to form a nitrogen-rich passivation layer. The nitrogen-rich passivation layer does not form a separate silicon nitride layer deposited on the silicon single crystal wafer and lacks the negative side effects of a separate layer. In addition, impurities are trapped by a gettering region provided below the top surface of the silicon single crystal wafer.

[0011] The nitrogen-rich passivation layer may be formed by diffusing nitrogen or implanting nitrogen ions into the upper region of the silicon single crystal wafer. In order to diffuse nitrogen into the upper region of the silicon single crystal wafer, the silicon single crystal wafer may be subjected to an annealing step in a nitrogen-containing gas atmosphere. The annealing step may be carried out as a flash lamp anneal. The nitrogen-containing atmosphere may contain nitrogen or ammonia (NH3) or a mixture thereof. The annealing temperature may be in the range of 300° C. to 1350° C. Alternatively, nitrogen ions may be implanted into the region below the upper surface of the silicon single crystal wafer and, optionally, a subsequent heat treatment may be performed. The temperature of the subsequent heat treatment may be in the range of 300° C. to 1350° C. A further alternative comprises introducing nitrogen radicals generated in a plasma to the surface of the silicon single crystal wafer. The concentration of nitrogen additionally present at the surface of the silicon single crystal wafer is greater than 1.0×10 11 atoms / cm 2 However, it is preferable that the amount is less than the amount that forms a stoichiometric silicon nitride layer on the surface of the silicon single crystal wafer. Thereby, the density of silicon atoms having dangling bonds on the surface is preferably less than 1×10 11 atoms / cm 2 less than 1×10 10 atoms / cm 2 less than 1×10 9 atoms / cm 2 It drops to less than

[0012] Additionally or alternatively, the nitrogen-rich passivation layer may be formed by depositing an AlN (aluminum nitride) nucleation layer in contact with the upper surface of the silicon single crystal wafer and temporarily adding additional nitrogen during deposition. As a result, the nitrogen concentration in the AlN nucleation layer is higher in the upper and lower regions of the AlN nucleation layer than in the region between the upper and lower regions. For this purpose, the partial pressure of the nitrogen-containing precursor gas may be temporarily increased during deposition of the AlN nucleation layer. The deposition of the AlN nucleation layer may be performed as MOCVD (metal organic chemical vapor deposition), molecular ion-beam epitaxy (MBE). As precursor compounds, trimethylaluminum and ammonia can be used for MOCVD. Hydrogen or nitrogen are suitable carrier gases. The growth temperature of the AlN layer is preferably 700°C to 1250°C for MOCVD and 400°C to 900°C for MBE. The AlN nucleation layer preferably has a thickness of 10 nm or more and preferably 500 nm or less, more preferably 200 nm or less. The nitrogen-rich passivation layer in the upper region of the AlN nucleation layer is 10 nm or less, most preferably 5 nm or less.

[0013] To enrich the AlN nucleation layer with nitrogen, additional nitrogen precursor gas is applied during deposition of the lower and upper regions of the AlN nucleation layer. The partial pressure of the nitrogen-containing precursor gas may be temporarily increased during deposition of the AlN nucleation layer. The concentration of nitrogen present in the lower and upper regions of the AlN nucleation layer is at least 1% higher than the Al concentration in the region between the upper and lower regions and up to 50% higher than that Al concentration.

[0014] Additionally, a gettering region is formed below the top surface of the silicon single crystal wafer. The gettering region may be formed before the nitrogen-rich passivation layer is formed. The gettering region may be formed by implanting hydrogen ions into the silicon single crystal wafer and annealing the silicon single crystal wafer to form a buried void layer. The gettering region may be formed after the nitrogen-rich passivation layer is formed by implanting hydrogen ions into the substrate wafer from its backside and annealing the substrate wafer.

[0015] Alternatively, the gettering region may be formed as an end-of-range defect (EOR) by implanting nitrogen ions into the silicon single crystal wafer when the nitrogen ions are implanted into an upper region of the silicon single crystal wafer to form a nitrogen-rich passivation layer.

[0016] The present invention further provides a substrate wafer for constructing III-V devices, comprising: A silicon single crystal wafer; a gettering region below a top surface of the silicon single crystal wafer; Nitrogen-enriched passivation layer and The present invention relates to a substrate wafer comprising:

[0017] The nitrogen-enriched passivation layer may be part of the AlN nucleation layer in contact with the top surface of the silicon single crystal wafer, or may form the top portion of the silicon single crystal wafer.

[0018] Preferably, the concentration of nitrogen in the AlN nucleation layer is higher in the upper and lower regions of the AlN nucleation layer compared to the region between the upper and lower regions of the AlN nucleation layer.

[0019] The gettering region may consist of a buried void or a layer of end-of-range damage.

[0020] The silicon single crystal wafer may be a wafer cut from a silicon single crystal grown according to the CZ method by pulling a seed crystal from a melt contained in a crucible, or according to the FZ method. The silicon single crystal wafer has a diameter of at least 150 mm, preferably at least 200 mm, and most preferably 300 mm. The lattice orientation of the silicon single crystal wafer may preferably be (100) or (111) or (110).

[0021] The description of the invention continues with reference to the drawings. 1 comprises a silicon monocrystalline wafer 1, a gettering region 2, and an AlN nucleation layer forming a nitrogen-rich passivation layer and consisting of a lower region 3, an upper region 5 and an intermediate region 4. The nitrogen concentration is higher in the upper region 5 and the lower region 3 compared to the nitrogen concentration in the intermediate region 4. [Explanation of symbols]

[0022] List of reference numbers used 1. Silicon single crystal wafer 2. Gettering Region 3 Lower area 4 Intermediate area 5 Upper area 6 Substrate Wafer

Claims

1. 1. A method for manufacturing a substrate wafer for building III-V devices thereon, comprising the steps of: Providing a silicon single crystal wafer; forming a gettering region below an upper surface of the silicon single crystal wafer; forming a nitrogen-rich passivation layer constituting an upper portion of the substrate wafer; A method comprising:

2. 2. The method of claim 1, wherein the nitrogen-rich passivation layer is formed by diffusing nitrogen or implanting nitrogen ions into an upper region of the silicon single crystal wafer.

3. 3. The method of claim 2, wherein the nitrogen-rich passivation layer is formed by subjecting the silicon single crystal wafer to a heat treatment in an atmosphere containing a nitriding gas.

4. 3. The method of claim 2, wherein the gettering region is formed as end-of-range damage when the nitrogen ions are implanted into the top region of the silicon single crystal wafer.

5. 2. The method of claim 1 , wherein the gettering region is formed by implanting hydrogen ions into the silicon single crystal wafer and annealing the silicon single crystal wafer to form a buried void layer below the top surface of the silicon single crystal wafer.

6. 2. The method of claim 1 , wherein the nitrogen-enriched passivation layer is formed by depositing an AlN nucleation layer in contact with the top surface of the silicon single crystal wafer, and wherein a nitrogen concentration in the AlN nucleation layer is higher in upper and lower regions of the AlN nucleation layer compared to an intermediate region between the upper and lower regions.

7. The method of claim 5 comprising temporarily increasing the partial pressure of a nitrogen-containing precursor gas during said deposition of said AlN nucleation layer.

8. 1. A substrate wafer for constructing III-V devices, comprising: A silicon single crystal wafer; a gettering region below a top surface of the silicon single crystal wafer; Nitrogen-enriched passivation layer and A substrate wafer comprising:

9. The substrate wafer of claim 8 , wherein the nitrogen-rich passivation layer forms a top portion of the substrate wafer.

10. The substrate wafer of claim 8 , wherein the nitrogen-enriched passivation layer is part of an AlN nucleation layer in contact with a top surface of the silicon single crystal wafer.

11. The substrate wafer of claim 10 , wherein a concentration of nitrogen in the AlN nucleation layer is higher in upper and lower regions of the AlN nucleation layer compared to a region between the upper and lower regions.

12. The substrate wafer of any of claims 8 to 11, wherein the gettering region comprises a buried gap layer.

13. The substrate wafer of any of claims 8 to 11, wherein the gettering region comprises end-of-range damage.

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