Polycrystalline semiconductor etching

Abstract

1. A method of processing a substrate comprising: performing a cyclical plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising: etching a patterning layer comprising a polycrystalline semiconductor material by exposing the substrate to a first plasma to form or extend a recess, the substrate comprising an oxide layer, the patterning layer being formed on the oxide layer; exposing the substrate to a second plasma comprising dihydrogen; and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

Description

[Technical field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-provisional Patent Application No. 17 / 690,715, filed March 9, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to methods of processing substrates, and in particular embodiments to etching polycrystalline semiconductors. [Background technology]

[0003] Generally, semiconductor devices, such as integrated circuits (ICs), are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials over a substrate to form a network of monolithically integrated electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias). Many of the processing steps used to form the constituent structures of semiconductor devices are performed using plasma processes. Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor industry has repeatedly reduced the minimum feature size of semiconductor devices to a few nanometers to increase the integration density of components. In response, the semiconductor industry is increasingly demanding plasma processing technologies to provide processes for patterning features with accuracy, precision, and profile control, often at atomic-scale dimensions. These requirements are particularly demanding for three-dimensional (3D) structures, such as fin field effect transistors (FinFETs), in which a gate electrode wraps around three sides of closely spaced, narrow, long, fin-shaped semiconductor features formed by etching trenches in a semiconductor substrate. Meeting this challenge with the uniformity and repeatability required for high-volume IC production will require further innovation in plasma processing technologies. [Means for solving the problem]

[0005] According to one embodiment of the present invention, a method of processing a substrate includes performing a cyclical plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material by exposing the substrate to a first plasma to form or extend a recess, the substrate including an oxide layer, the patterning layer being formed on the oxide layer; exposing the substrate to a second plasma including dihydrogen; and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

[0006] According to one embodiment of the present invention, a method of processing a substrate includes performing a cyclical plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first period of time, the substrate including an oxide layer, the polysilicon layer being formed on the oxide layer, the first plasma including hydrogen bromide and dichlorine, and exposing the substrate to a second plasma including dihydrogen for a second period of time.

[0007] According to one embodiment of the present invention, a method of fabricating a fin field effect transistor includes forming a fin feature on an oxide layer, the oxide layer being formed on a substrate, the fin feature including a fin hard mask and a fin below the fin hard mask, the fin including silicon; depositing a dummy gate material including polysilicon; depositing a gate hard mask layer on the dummy gate material; depositing a photoresist on the hard mask layer; performing a photolithography process to pattern the photoresist; etching the gate hard mask layer to transfer a pattern from the photoresist to the hard mask layer; and performing a cyclical plasma etch process using the gate hard mask layer as an etch mask, the cyclical plasma etch process exposing the fin hard mask, the cyclical plasma etch process including a plurality of cycles, each of the plurality of cycles including etching the dummy gate material to form a recess by exposing the substrate to a first plasma including a halogen; and exposing the substrate to a second plasma including hydrogen. [Brief description of the drawings]

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1A] 1A-1D depict cross-sectional views of an exemplary substrate at various stages during an exemplary cyclical plasma process according to various embodiments, showing an incoming substrate including polysilicon, a hardmask layer, and a patterned photoresist layer. [Figure 1B] 1A-1D depict cross-sectional views of an exemplary substrate at various stages during an exemplary cyclic plasma process, according to various embodiments, showing the substrate after a hard mask opening step. [Figure 1C]1A-1C illustrate cross-sectional views of an exemplary substrate at various stages during an exemplary cyclic plasma process, according to various embodiments, showing the substrate after a first main etch with a first plasma of the cyclic plasma process. [Figure 1D] 1A-1C show cross-sectional views of an exemplary substrate at various stages during an exemplary cyclic plasma process, according to various embodiments, showing the substrate after a first hydrogen treatment of the cyclic plasma process with a second plasma. [Figure 1E] 1A-1D depict cross-sectional views of an exemplary substrate at various stages during an exemplary cyclical plasma process, according to various embodiments, and depict the substrate after cycling through steps of the cyclical plasma process. [Figure 1F] 1A-1D depict cross-sectional views of an exemplary substrate at various stages during an exemplary cyclic plasma process, according to various embodiments, showing the substrate after surface treatment to form a protective surface layer. [Figure 1G] 1A-1D show cross-sectional views of an exemplary substrate at various stages during an exemplary cyclic plasma process, according to various embodiments, showing the substrate after a soft landing etch with a third plasma. [Figure 2A] 1A-1D illustrate perspective views of an exemplary substrate at various stages during an exemplary cyclic plasma process for fabricating three-dimensional (3D) semiconductor devices, according to various embodiments, showing an incoming substrate including an oxide layer, a fin feature, a polysilicon layer, a hardmask layer, and a patterned photoresist layer. [Figure 2B] 1A-1D depict perspective views of an exemplary substrate at various stages during an exemplary cyclic plasma process for fabricating three-dimensional (3D) semiconductor devices, according to various embodiments, showing the substrate after a hard mask opening step. [Figure 2C] 1A-1C show perspective views of an exemplary substrate at various stages during an exemplary cyclical plasma process for fabricating three-dimensional (3D) semiconductor devices according to various embodiments, with the substrate shown after cycling through steps of the cyclical plasma process. [Figure 2D]1A-1D show perspective views of an exemplary substrate at various stages during an exemplary cyclic plasma process for fabricating three-dimensional (3D) semiconductor devices according to various embodiments, showing the substrate after surface treatment to form a protective surface layer. [Figure 2E] 1A-1D depict perspective views of an exemplary substrate at various stages during an exemplary cyclic plasma process for fabricating a three-dimensional (3D) semiconductor device according to various embodiments, showing the substrate after a soft landing etch to form a dummy gate feature that encases a fin feature. [Figure 3A] 1 shows a process flow chart of a method of cyclical plasma processing according to various embodiments, illustrating the process flow of several embodiments. [Figure 3B] 1 shows a process flow chart of a method of cyclical plasma processing according to various embodiments, illustrating the process flow of an alternative embodiment. [Figure 3C] 1 shows a process flow diagram of a method of cyclical plasma processing according to various embodiments, and illustrates a process flow for yet another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present application relates to a method for processing a substrate, and more particularly, to a method for a cyclical plasma process that allows etch profile control in features with high aspect ratios (HAR). In semiconductor device fabrication, poor etch profile control in HAR features can result in critical dimension (CD) variations across the HAR features and poor line edge roughness (LER). This problem can be particularly challenging during plasma etching of polysilicon used in front-end (FEOL) fabrication of advanced logic nodes. Different silicon crystal orientations and grain boundaries in polysilicon tend to lead to lateral etch rate variations, which can cause degradation of sidewall profiles with surface roughness. Thus, plasma etching techniques for polysilicon in HAR features with better etch profile control may be desirable. An embodiment of the present application discloses a method for a cyclical plasma process that includes a main plasma etch step and a hydrogen plasma treatment step for sidewall smoothing. The cyclical plasma process can further include a soft landing etch performed after the final main plasma etch step.

[0011] The methods described in the present disclosure may advantageously reduce LER of HAR features formed in layers including polysilicon. The methods may be particularly useful for fabricating polysilicon gates or dummy gates in 3D semiconductor devices such as fin field effect transistors (FinFETs). Furthermore, the methods herein may improve critical dimension (CD) control of HAR features by providing uniform, controlled lateral etch rates on the sidewalls. In various embodiments, the cyclic plasma process may enable features with aspect ratios (ratio of feature height to feature width) of 10:1 or greater.

[0012] In the following, steps of a cyclic plasma process including a main plasma etch step and a hydrogen plasma treatment step for sidewall smoothing are first described with reference to Figures 1A-1G according to various embodiments. Then, with reference to Figures 2A-2E, several embodiments of a cyclic plasma process applied to gate etching during the fabrication of a fin field effect transistor (FinFET) are described. Exemplary process flow diagrams are shown in Figures 3A-3C. All figures in this disclosure are drawn for illustrative purposes only and are not to scale, including aspect ratios of features.

[0013] FIG. 1A shows a cross-sectional view of an incoming substrate 100 that includes a polysilicon layer 120 .

[0014] In FIG. 1A, substrate 100 comprises a semiconductor substrate in various embodiments. In one or more embodiments, substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, substrate 100 may comprise a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, or other compound semiconductors. In other embodiments, substrate 100 comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well as layers of silicon on silicon or SOI substrates. Substrate 100 may undergo multiple processing steps, for example according to conventional processes, to fabricate semiconductor structures. Thus, various device regions may be formed in substrate 100. At this stage, for example, substrate 100 may include isolation regions, such as shallow trench isolation (STI) regions, and other regions formed therein.

[0015] Substrate 100 may further include an insulating layer 110. In various embodiments, insulating layer 110 may include an oxide, such as silicon oxide. In certain embodiments, insulating layer 110 may be formed by thermal oxidation. In one or more embodiments, insulating layer 110 is a layer that is fabricated as an insulating region, such as a buried oxide (BOX) layer, of a semiconductor device. In one embodiment, insulating layer 110 may have a thickness of about 10 nm to about 1 μm.

[0016] A polysilicon layer 120 is formed on the insulating layer 110. The polysilicon layer 120 shown in FIG. 1A is a layer that is patterned by the method of the embodiments to form high aspect ratio (HAR) features. For example, the aspect ratio (width to height) of the HAR features can be 1:5 or more, such as 1:10 or more in some embodiments. In various embodiments, the polysilicon layer 120 is patterned to form gates or dummy gates for semiconductor devices. The polysilicon used in the polysilicon layer 120 can include doped polysilicon to have desired material properties, including electrical properties. The polysilicon layer 120 can be deposited on the insulating layer 110 using a suitable deposition technique, such as vapor deposition methods including chemical vapor deposition (CVD), physical vapor deposition (PVD), and other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes. In one or more embodiments, the polysilicon layer 120 can have a thickness of about 50 nm to about 500 nm. Because polysilicon is a polycrystalline form of silicon, it contains numerous crystallites 125 and grain boundaries between the individual crystallites, as shown in FIG. 1A.

[0017] Still referring to FIG. 1A, a hard mask layer 130 may be formed on the polysilicon layer 120. In one embodiment, the hard mask layer 130 may include silicon oxide. In various embodiments, the hard mask layer 130 may include silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). In alternative embodiments, the hard mask layer 130 may include titanium nitride. In one or more embodiments, the hard mask layer 130 may include other suitable organic materials, such as a spin-on carbon hard mask (SOH) material. Additionally, the hard mask layer 130 may be a stacked hard mask including, for example, two or more layers using two different materials. In some such embodiments, a first hard mask of the hard mask layer 130 may include a metal-based layer, such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds, and a second hard mask material of the hard mask layer 130 may include a dielectric layer, such as silicon oxide, silicon nitride, SiCN, SiOC, silicon oxynitride, or silicon carbide. The hardmask layer 130 can be deposited using a suitable deposition technique, such as vapor deposition techniques including chemical vapor deposition (CVD), physical vapor deposition (PVD), and other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes including wet processes. The hardmask layer 130 can have a thickness of about 5 nm to about 50 nm in various embodiments. In one or more embodiments, an additional layer, such as a silicon-containing antireflective coating film (SiARC) or other ARC film, can be formed over the hardmask layer 130.

[0018] A patterned photoresist layer 140 may be formed on the hard mask layer 130. In various embodiments, the patterned photoresist layer 140 provides a pattern for forming the respective features in the polysilicon layer 120. In the illustrated example, the patterned photoresist layer 140 serves as a first etch mask when forming the respective features in the hard mask layer 130 (FIG. 1B), and then the features formed in the hard mask layer 130 may serve as a second etch mask during a cyclic plasma process for etching the polysilicon such that the features of the patterned photoresist layer 140 are transferred to the polysilicon layer 120, as described below. In certain embodiments, the patterned photoresist layer 140 may include a 248 nm resist, a 193 nm resist, a 157 nm resist, an EUV (extreme ultraviolet) resist, or an electron beam (EB) sensitive resist. In various embodiments, the photoresist may be deposited on the hard mask layer 130 using a dry or wet process, such as a spin coating technique. The deposited photoresist may then be patterned using an appropriate lithography process to form a patterned photoresist layer 140. In one embodiment, the patterned photoresist layer 140 has a thickness between 20 nm and 100 nm. Features patterned using the patterned photoresist layer 140 may have a desired critical dimension (CD), i.e., width, for the layer being patterned. In some embodiments, the CD may be between 10 nm and 100 nm. In one or more embodiments, the CD may be between 10 nm and 40 nm.

[0019] FIG. 1B illustrates a cross-sectional view of a semiconductor structure-in-process after a hardmask opening step, according to one embodiment.

[0020] The hard mask opening step may be performed using a plasma etching process, such as a reactive ion etching (RIE) process, to form recesses 150 in the hard mask layer 130. Portions of the hard mask layer 130 that are not masked by the patterned photoresist layer 140 may be removed, thereby transferring the pattern defined by the patterned photoresist layer 140 to the hard mask layer 130. As shown in FIG. 1B, after the hard mask opening step, at least a portion of the polysilicon layer 120 may be exposed at the bottom of the recesses 150. In one or more embodiments, the substrate 100 may include additional layers above and / or below the hard mask layer 130, which may also be removed during the hard mask opening step. In certain embodiments, after the hard mask opening step, remaining portions of the patterned photoresist layer 140 may be removed before performing a subsequent step. In one or more embodiments, as shown in FIGS. 1B-1G, portions of the patterned photoresist layer 140 may remain during the next step, while in other embodiments, they may be removed at any stage.

[0021] FIG. 1C illustrates a cross-sectional view of the semiconductor structure-in-process after a first main etch with a first plasma of a cyclic plasma process.

[0022] A cyclical plasma process may be applied to etch the polysilicon with controlled etch profile and sidewalls. A cycle of the cyclical plasma process according to various embodiments may begin with a main etch by exposing the substrate 100 to a first plasma. The main etch may be anisotropic to extend the recess 150 into the polysilicon layer 120. The cyclical etch process may be performed in a suitable plasma processing chamber equipped with one or more plasma sources such as inductively coupled plasma (ICP), capacitively coupled plasma (CCP), microwave plasma (MW), etc. In various embodiments, the main etch may be a reactive ion etching (RIE) process and may use a first etch gas that includes, for example, a halogen gas. In a particular embodiment, the first etch gas may be hydrogen bromide (HBr) and dichlorine (Cl2). The first etch gas may also include dioxygen (O2) and / or a noble gas (e.g., He, Ne, Ar, Kr, etc.). The first etch gas can be selected so that the first plasma for etching polysilicon has high selectivity and a high polysilicon etch rate. The selectivity can be relative to the mask material of the hard mask layer 130, such as silicon oxide, silicon nitride, or SiON. Similarly, the plasma conditions for the main etch can be determined to obtain the desired selectivity and etch rate.

[0023] In certain embodiments, the main etch may be performed with a total gas flow rate of 50 sccm to 1000 sccm, a pressure of 5 mTorr to 300 Torr, a temperature of -10°C to 150°C, and an operating frequency of 100 kHz to 10 GHz. In one or more embodiments, the flow rate of HBr is maintained in the range of about 0 sccm to 500 sccm, and the flow rate of Cl2 is about 0 sccm to 100 sccm. In one embodiment, the total flow rate of the additional gases may range from about 50 sccm to 500 sccm. In various embodiments, the main etch may be performed for a process time of 5 seconds to 120 seconds, such as 10 seconds to 30 seconds in one embodiment.

[0024] The main etch may be an anisotropic etch with mostly vertical directionality to extend the recess 150 vertically, but some lateral etching may occur on the sidewalls of the recess 150. The effect of lateral etching may be important especially in CD control of narrow recesses and HAR features where the majority of the surface of the patterning layer is its sidewall. Lateral etching may lead to CD loss and line edge roughness (LER), which may significantly impede device performance and yield. These challenges of undesirable lateral etching may be further exacerbated in etching polysilicon. As shown in FIG. 1C, due to the various orientations of the crystallites 125 of the polysilicon layer 120, the sidewalls of the recess 150 contain different crystal grains and different crystal planes are exposed at the surface. Because the etch rate of silicon depends on the type of crystal plane, the lateral etch rate during the main etch may vary from the top to the bottom of the sidewall. As a result, the surface of the sidewall may not be smooth and may have poor LER. The inventors of the present disclosure have determined that implementing a subsequent exposure to a second plasma containing hydrogen (e.g., H), hereinafter referred to as a hydrogen treatment, in a cyclic plasma process can alleviate this challenge by smoothing the sidewall surface, as further described below.

[0025] At this stage after the first main etch process, the depth of the recess 150 may be less than the total thickness of the three layers (i.e., polysilicon layer 120, hard mask layer 130, and patterned photoresist layer 140). In other words, the recess 150 does not reach the bottom of the polysilicon layer 120. The recess 150 is extended stepwise by repeating the main etch of the cyclic plasma process to form high aspect ratio (HAR) features of the polysilicon layer 120. As will be further explained with reference to Figures 1D-1F, the stepwise removal of polysilicon by the cyclic plasma process advantageously allows sidewall smoothing to be performed multiple times between steps of the cyclic plasma process.

[0026] FIG. 1D illustrates a cross-sectional view of a semiconductor structure-in-progress after a first hydrogen treatment of a cyclic plasma process using a second plasma.

[0027] In various embodiments, the hydrogen treatment may be performed by exposing the substrate to a second plasma containing hydrogen. In certain embodiments, the second plasma contains molecular hydrogen, i.e., dihydrogen (H2). The hydrogen treatment smoothes the sidewall surface, as shown in FIG. 1D. Without wishing to be limited by any theory, the H-containing radical species in the second plasma may induce amorphization of a portion of the polysilicon on the surface and etching of silicon atoms, which may lead to the smoothing. This is shown in FIG. 1D as a surface-modified silicon layer 160 formed on the surface of the recess 150. In one or more embodiments, after the hydrogen treatment, the CD variation, e.g., 3 sigma (standard deviation from the mean of CD measured at different gate heights or depths of the recess 150 formed), may be reduced by 20% or more from the value before the hydrogen treatment. In one embodiment, the CD standard deviation after the hydrogen treatment may be below 1.0 nm. In certain embodiments, the surface roughness may be measured using the root mean square (RMS) of the height variation, the mean of the roughness (R a ) and other indices such as valley-to-peak height (h). Because the sidewalls are covered with amorphous silicon and there are no longer different crystal planes exposed at the surface, in addition to the smoothing effect, hydrogen treatment can also advantageously improve the etch uniformity of the next cycle in the cyclic plasma process.

[0028] In certain embodiments, the hydrogen treatment may further include flowing a mixture of optional inert gases (e.g., He, Ne, Ar, Kr, etc.) into the plasma treatment chamber. In certain embodiments, the exposure to the second plasma may be performed at a total gas flow rate of 50 sccm to 500 sccm, a pressure of 5 mTorr to 300 Torr, a temperature of -10°C to 200°C, and an operating frequency of 100 kHz to 10 GHz. In various embodiments, the exposure to the second plasma may be performed for a process time of 2 seconds to 50 seconds, such as 5 seconds to 10 seconds in one embodiment. Some process parameters such as flow rate, pressure, etc. may be selected to provide sufficient modification of the sidewall surface while keeping the process time as short as possible for better process efficiency. Furthermore, the process parameters for the hydrogen plasma step may be optimized with respect to the previous step (e.g., FIG. 1C) of the cyclic plasma process. In certain embodiments, inductively coupled plasma (ICP), microwave plasma (MW), or capacitively coupled plasma (CCP) may be used for the second plasma containing hydrogen. In one example, process conditions of a chamber pressure of 30-80 mTorr, a source pressure of 250-1000 W, and a H2 flow rate of 100-200 sccm may be used in an ICP plasma chamber.

[0029] In various embodiments, the steps of the main etch and hydrogen treatment may be repeated in a cyclic plasma process to reach a desired depth for the recess 150. For example, a second main etch may be performed after the first hydrogen treatment (e.g., FIG. 1D) to vertically extend the recess 150. The sidewall surfaces may be smoothed and amorphized by the first hydrogen treatment, and the second main etch may proceed with better etch profile control compared to the first main etch. The process conditions of the second main etch may be the same as the first main etch in some embodiments, but may be different in other embodiments. After the second main etch, a second hydrogen treatment may be performed to replenish the surface-modified silicon layer 160 to treat and smooth the sidewalls and bottom of the newly exposed recess 150. The process conditions of the second hydrogen treatment may be the same as the first hydrogen treatment in some embodiments, but may be different in other embodiments. In one or more embodiments, during the repeated cycle of the main etch and hydrogen treatment, one or more steps of the main etch or hydrogen treatment may be skipped or replaced with a different intervening process step according to the process recipe.

[0030] FIG. 1E shows the substrate 100 after cycling through the steps of the cyclical plasma process.

[0031] In FIG. 1E, after the cycle of steps, the recess 150 extends vertically in the polysilicon layer 120. The surface modified silicon layer 160 may also extend after the final hydrogen treatment. By performing multiple cycles of the cyclical etching process according to various embodiments, the recess 150 may extend stepwise and conformally from the top to the bottom of the recess without significant variation in critical dimension (CD). In various embodiments, any number of cycles may be performed until a desired level of etching is achieved. In certain embodiments, the cycle may end with the main etch and the final hydrogen treatment may be skipped. Whether a final hydrogen treatment is required may depend on the final etch profile, which is mostly determined by the polycrystalline state of the surface modified silicon layer 160 at the film depth. In one or more embodiments, after the final main etch and the final hydrogen treatment, the bottom of the recess 150 may still be above the insulating layer 110 as shown in FIG. 1E, and subsequent steps including a soft landing etch may further extend the recess 150 as described below.

[0032] FIG. 1F illustrates a cross-sectional view of the in-process semiconductor structure after surface treatment to form a protective surface layer 170.

[0033] After the cycle of the main etch and hydrogen treatment, a surface treatment may be performed to form a protective surface layer 170. The protective surface layer 170 is for providing sidewall protection during a subsequent soft landing etch. In certain embodiments, the surface treatment includes exposing the substrate to a reactive gas that induces a surface reaction with silicon atoms on the sidewall. For example, a reactive gas that includes oxygen (e.g., O2, CO, or CO2) and a thin layer that includes an oxide (e.g., silicon oxide) may be formed as the protective surface layer 170. In alternative embodiments, the reactive gas may include nitrogen (e.g., N2, NH3, etc.) and the protective surface layer 170 may include a nitride (e.g., silicon nitride). In one or more embodiments, the surface treatment is a plasma process. The surface treatment may also include depositing new material for the protective surface layer 170 on top of the silicon. In some embodiments, various deposition techniques can be used, such as gas phase deposition techniques including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD) and other processes. In one example, process conditions are used in an ICP plasma chamber with a chamber pressure of 80-120 mTorr, a source power of 100-300 W and a bias power of 0-50 W, and an O2 flow rate of 100-200 sccm with an Ar flow rate of 200-500 sccm.

[0034] FIG. 1G illustrates a cross-sectional view of the in-process semiconductor structure after a soft landing etch with a third plasma.

[0035] In various embodiments, the cyclic plasma process may further include another etching process having different process conditions than the main etch, referred to in this disclosure as a soft landing etch. The purpose of the soft landing etch is to remove more polysilicon to create the target high aspect ratio (HAR) features in the polysilicon layer 120 while preventing any damage to other components or features on the substrate 100. For example, the soft landing etch may have a higher etch selectivity (e.g., polysilicon to oxide selectivity) than the main etch so that the insulating layer 110 and other possible features (e.g., fin features as shown below in Figures 2A-2E) are not affected. As shown in Figure 1G, in various embodiments, the soft landing etch may further extend the recess 150 and expose the insulating layer 110. The soft landing etch may be a reactive ion etching (RIE) process and may use a second etching gas that includes, for example, a halogen gas. In a particular embodiment, the second etching gas may be hydrogen bromide (HBr) and dichlorine (Cl2). The second etching gas may also include dioxygen (O2) and / or a noble gas (e.g., He, Ne, Ar, Kr, etc.). In some embodiments, the composition of the second etching gas for the soft landing etch may be the same as the first etching gas for the main etch, but may be different in other embodiments. The second etching gas may be selected such that the third plasma that etches the polysilicon during the soft landing etch has a higher selectivity than the first plasma during the main etch. The selectivity may be to the mask material of the hard mask layer 130, the insulating layer 110, the fin structure, or other features. Similarly, the plasma conditions for the soft landing etch may be determined to obtain a desired selectivity. For this reason, in one embodiment, the etch rate of the soft landing etch may be less than the etch rate of the main etch. Thus, the process time of the soft landing etch may be longer than the process time of the main etch.Thus, the formation of protective surface layer 170 described above with reference to Figure 1F can be particularly useful for sidewall protection during the soft landing etch. In various embodiments, the amount of polysilicon etched by the soft landing etch is less than the amount of polysilicon etched by the main etch cycle.

[0036] In certain embodiments, the soft landing etch may be performed at a total gas flow rate of 100 sccm to 1000 sccm, a pressure of 10 mTorr to 800 Torr, a temperature of -10°C to 200°C, and an operating frequency of 100 kHz to 10 GHz. In one or more embodiments, the flow rate of HBr is maintained in the range of about 100 sccm to 500 sccm, and the flow rate of Cl2 is about 0 sccm to 300 sccm. In one embodiment, the total flow rate of the additive gas may be in the range of about 0 sccm to 200 sccm. In various embodiments, the main etch may be performed for a process time of 2 seconds to 120 seconds, such as 10 seconds to 50 seconds in one embodiment. To achieve high selectivity in the soft landing step, the process may be performed at conditions with higher chamber pressure, lower bias power, and higher additive flow rates (e.g., O2, CO2, or N2) to obtain more surface deposition compared to the main etch process conditions.

[0037] 2A-2E show perspective views of an exemplary substrate at various stages during an exemplary cyclical plasma process for fabricating three-dimensional (3D) semiconductor devices according to various embodiments. The cyclical plasma process according to various embodiments of the present disclosure may be applicable to and particularly useful in the fabrication of 3D semiconductor devices. Although FIGS. 2A-2E show an example with respect to a fin field effect transistor (FinFET), other 3D semiconductor devices may be fabricated utilizing the method of etching polysilicon described in the present disclosure. The details of the process may be the same as those already described above and may not be repeated.

[0038] In FIG. 2A, the substrate 100 includes the same features as described above in FIG. 1A, including the insulating layer 110, the polysilicon layer 120, the hard mask layer 130, and the patterned photoresist layer 140. Additionally, the substrate 100 in FIG. 2A includes a fin feature including a fin 200 including a semiconductor material and a fin hard mask 210 formed on the fin 200. Note that while two fins 200 are shown in FIG. 2A for illustrative purposes, the number of fins is not limited. In various embodiments, the fin 200 may form a transistor channel of a FinFET device upon completion of fabrication. In one or more embodiments, the fin 200 may have a height of about 20 nm to about 100 nm and a width of about 5 nm to about 30 nm. Although FIGS. 2A-2E show fabrication of an SOI FinFET, the cyclic plasma process is applicable to fabrication of a bulk FinFET in which the fin 200 is directly tethered and connected to the substrate 100.

[0039] In certain embodiments, fin 200 comprises silicon, silicon germanium, or other semiconductor material. An n-type field effect transistor or a p-type field effect transistor may be formed with different types of materials used for fin 200 in some embodiments. For example, an n-type FET may be fabricated using a material for fin 200 that has high electron mobility, while a p-type FET may be fabricated using a material for fin 200 that has high hole mobility. In one or more embodiments, fin 200 may be selected to be a material selected from the III-V groups of the periodic table.

[0040] The fin features may be formed by conventional methods, for example, by depositing a layer of material for the fin 200, depositing a fin hard mask 210, patterning the fin hard mask to define a pattern for the fin 200, and etching the material for the fin 200 using the patterned fin hard mask as an etch mask. In some embodiments, the deposition of the layer of material for the fin 200 may be formed by a deposition process, for example, by an epitaxial chemical vapor deposition (CVD) method.

[0041] In one embodiment, the fin hard mask 210 may include silicon oxide. In various embodiments, the fin hard mask 210 may include silicon nitride, silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). The fin hard mask 210 may be deposited using a suitable deposition technique, such as chemical vapor deposition (CVD), vapor deposition methods including physical vapor deposition (PVD) and other plasma processes such as plasma enhanced CVD (PECVD), sputtering, and other processes. The fin hard mask 210 may then be patterned, for example, by lithography and etching processes. In certain embodiments, the fin hard mask 210 may be removed prior to forming the polysilicon layer 120.

[0042] The fin feature may then be embedded in the polysilicon layer 120 after depositing the polysilicon layer 120. In one embodiment, the polysilicon layer 120 may be used to form a dummy gate. The deposition of the polysilicon layer 120 and the subsequent steps of depositing the hard mask layer 130 and forming the patterned photoresist may be performed as previously described with reference to FIG. 1A.

[0043] FIG. 2B shows a perspective view of the in-process semiconductor structure after a hardmask opening step.

[0044] The hard mask opening step may be performed using a plasma etching process, such as a reactive ion etching (RIE) process, as described above with reference to Figure 1B. Thus, the pattern of the patterned photoresist layer 140 may be transferred to the hard mask layer 130. As shown in Figure 2B, remaining portions of the patterned photoresist layer 140 may be removed after the hard mask opening step, such as by ashing.

[0045] FIG. 2C shows a perspective view of a semiconductor structure in fabrication after cycling through the steps of the cyclical plasma process.

[0046] As in the previous embodiment, a cycle of main etch and hydrogen treatment may be performed to etch the polysilicon layer 120 using the patterned hard mask layer 130 as an etch mask. For illustrative purposes, only one line feature is illustrated, but in various embodiments, high aspect ratio (HAR) features including multiple lines and recesses are envisioned. As shown in FIG. 2C, the cycle of the cyclical plasma process may end with a final hydrogen treatment, so that a surface-modified silicon layer 160 may cover the surface of the polysilicon layer exposed by the main etch. In other embodiments, the final hydrogen treatment may be skipped and the sidewalls of the polysilicon layer 120 may be exposed. In various embodiments, the cycle is stopped when the top surface of the fin feature (e.g., the top surface of the fin hard mask 210 in FIG. 2C) is first exposed, so that further removal of polysilicon in the polysilicon layer 120 may be performed separately by a more selective etch, such as a soft landing etch as described below.

[0047] FIG. 2D shows a perspective view of the in-process semiconductor structure after surface treatment to form a protective surface layer 170.

[0048] Prior to the soft landing etch as shown in Figure 2E, a surface treatment may be performed to form a protective surface layer 170 as described above with reference to Figure 1F. The protective surface layer 170 may cover or replace the surface of the surface-modified silicon layer 160 and any exposed portions of the polysilicon layer 120.

[0049] FIG. 2E illustrates a perspective view of the in-process semiconductor structure after a soft landing etch to form a dummy gate feature that encapsulates the fin feature.

[0050] A soft landing etch may then be performed to further etch the polysilicon with a selectivity higher than that of the main etch. The process conditions of the soft landing etch for the polysilicon may be selected to minimize or eliminate damage to the insulating layer 110 and other components such as the fin 200 and the fin hard mask 210. After the soft landing etch, subsequent process steps may follow to fabricate a semiconductor device such as a FinFET. In one embodiment, such steps may include, but are not limited to, gate spacer formation, gate implant, fin recess and source / drain formation, channel release, and middle-end (MOL) / back-end (BEOL) processes.

[0051] 3A-3C show process flow charts of methods for cyclical plasma processing according to various embodiments. The process flow can follow the above-mentioned figures and will not be described again.

[0052] In FIG. 3A, the process flow 30 starts with a cyclic plasma process 310 that includes etching a patterned layer including polysilicon by exposing the substrate to a first plasma as a main etch to form a recess (block 320, FIG. 1C). Next, in a loop of the cyclic plasma process 310, the substrate can be exposed to a second plasma including dihydrogen (H2) as a hydrogen treatment (block 330, FIG. 1D). The main etch and hydrogen treatment can be repeated any number of times to extend the recess (e.g., FIG. 1E). The substrate can then be exposed to a third plasma for a soft landing etch to further extend the recess (block 340, FIG. 1G). In certain embodiments, an optional surface treatment to form a protective surface layer can be performed before the soft landing etch (block 340) (block 335, FIG. 1F). In certain embodiments, a subsequent fabrication process step (e.g., gate spacer formation) to fabricate a semiconductor device can be performed (block 350).

[0053] In FIG. 3B, another process flow 32 starts with a cyclic plasma process 312 that includes etching the polysilicon layer to form a recess by exposing the substrate to a first plasma containing hydrogen bromide (HBr) and dichlorine (Cl2) for a first period of time as a main etch (block 322, FIG. 1C). The substrate can then be exposed to a second plasma containing dihydrogen (H2) for a second period of time as a hydrogen treatment (block 332, FIG. 1D). The main etch and hydrogen treatment can be repeated any number of times to extend the recess (e.g., FIG. 1E). In certain embodiments, a surface treatment to form a protective surface layer can be performed (block 335, FIG. 1F), followed by a soft landing etch in which the substrate can be exposed to a third plasma containing hydrogen bromide (HBr) and dichlorine (Cl2) for a third period of time (block 342, FIG. 1G).

[0054] In FIG. 3C, yet another process flow 34 begins with forming a fin feature including a fin hard mask and a silicon fin on an oxide layer (block 301). Next, a dummy gate material including polysilicon may be deposited (block 302), followed by depositing a gate hard mask layer on the dummy gate material (block 303). Photoresist is then deposited on the gate hard mask layer (block 304) and patterned by performing a photolithography process (block 305, FIG. 2A). The gate hard mask layer may then be etched to transfer a pattern from the photoresist to the hard mask layer (block 306, FIG. 2B). A cyclic plasma process (block 314) may follow to etch the dummy gate material using the patterned gate hard mask layer as an etch mask. The cyclic plasma process may begin with a main etch by exposing the substrate to a first plasma including a halogen to form or extend a recess in the dummy gate material (block 324). Next, the substrate may be exposed to a second plasma containing hydrogen (block 334) as a hydrogen treatment. The main etch and hydrogen treatment may be repeated any number of times to extend the recess. In one or more embodiments, the cyclical plasma process may be continued until the top surface of the fin hard mask is exposed at the bottom of the recess (e.g., FIG. 2C). In certain embodiments, the process flow 34 continues for a surface treatment to form a protective surface layer (block 335, FIG. 2D), followed by a soft landing etch, where the substrate may be exposed to a third plasma containing a halogen (block 344, FIG. 1G). In one or more embodiments, the soft landing etch may extend the recess to expose the oxide layer.

[0055]

[0023] Example embodiments are summarized here. Other embodiments can be seen throughout the specification and claims appended hereto.

[0056] Example 1. A method of processing a substrate comprising performing a cyclical plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising: etching a patterning layer comprising polycrystalline semiconductor material by exposing the substrate to a first plasma to form or extend a recess, the substrate comprising an oxide layer, the patterning layer being formed on the oxide layer; exposing the substrate to a second plasma comprising dihydrogen; and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

[0057] Example 2. The method of Example 1, further comprising forming a patterned hard mask layer on the patterning layer by a lithography process and etching before performing the cyclic plasma etching process, wherein the cyclic plasma etching process is performed using the hard mask layer as an etching mask.

[0058] Example 3. The method of Example 1 or 2, further comprising, after performing the cyclic plasma etching process and prior to extending the recess by exposing the substrate to a third plasma, performing a surface treatment to form a protective surface layer on the surface of the recess, the protective surface layer protecting the sidewalls of the recess during extending the recess by exposing the substrate to the third plasma.

[0059] Example 4. The method of any one of Examples 1-3, wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprising oxygen, and the protective surface layer comprises an oxide.

[0060] Example 5. The method of any one of Examples 1-4, wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprises nitrogen, and the protective surface layer comprises a nitride.

[0061] Example 6. The method of any one of Examples 1-5, wherein the first plasma comprises a halogen.

[0062] Example 7. The method of any one of Examples 1-6, wherein the first plasma comprises hydrogen bromide and dichlorine.

[0063] Example 8. The method of any one of Examples 1-7, wherein exposing the substrate to the second plasma causes the polycrystalline semiconductor material to become amorphized at the surfaces of the recesses.

[0064] Example 9. The method of any one of Examples 1-8, wherein exposing the substrate to the second plasma smoothes the surface of the sidewall of the recess.

[0065] Example 10. The method of any one of Examples 1-9, wherein the third plasma comprises a halogen.

[0066] Example 11. The method of any one of Examples 1-10, wherein the third plasma comprises hydrogen bromide and dichlorine.

[0067] Example 12. The method of any one of Examples 1-11, wherein an etch rate of the polycrystalline semiconductor material during exposure of the substrate to the third plasma is slower than an etch rate of the polycrystalline semiconductor material during exposure of the substrate to the first plasma.

[0068] Example 13. The method of any one of Examples 1-12, wherein the recess extended by exposing the substrate to the third plasma has a height-to-width ratio of about 5-10.

[0069] Example 14. A method of processing a substrate comprising performing a cyclical plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising: etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first period of time, the substrate comprising an oxide layer, the polysilicon layer being formed on the oxide layer, the first plasma comprising hydrogen bromide and dichlorine, and exposing the substrate to a second plasma comprising dihydrogen for a second period of time.

[0070] Example 15. The method of example 14, wherein the first period of time is between 5 seconds and 120 seconds, and the second period of time is between 2 seconds and 50 seconds.

[0071] Example 16. The method of example 14 or 15, wherein exposing the substrate to the second plasma amorphizes the polysilicon layer at the surfaces of the features and reduces the standard deviation of the critical dimensions of the features at different depths by 20% or more.

[0072] Example 17. The method of any one of Examples 14-16, further comprising, after performing the cyclic plasma etching process, performing a surface treatment to form a protective surface layer on the surface of the recess, and further extending the recess in the layer by an etching process including exposing the substrate to a third plasma for a third period of time, the third plasma including hydrogen bromide and dichlorine, the protective surface layer protecting the sidewalls of the recess from the third plasma.

[0073] Example 18. The method of any one of Examples 14-17, wherein the third period of time is longer than the first period of time.

[0074] Example 19. A method of fabricating a fin field effect transistor comprising: forming a fin feature on an oxide layer, the oxide layer being formed on a substrate, the fin feature comprising a fin hardmask and a fin below the fin hardmask, the fin comprising silicon; depositing a dummy gate material comprising polysilicon; depositing a gate hardmask layer on the dummy gate material; depositing a photoresist on the hardmask layer; performing a photolithography process to pattern the photoresist; etching the gate hardmask layer to transfer a pattern from the photoresist to the hardmask layer; and performing a cyclical plasma etch process using the gate hardmask layer as an etch mask, the cyclical plasma etch process exposing the fin hardmask, the cyclical plasma etch process comprising a plurality of cycles, each of the plurality of cycles comprising: etching the dummy gate material to form a recess by exposing the substrate to a first plasma comprising a halogen; and exposing the substrate to a second plasma comprising hydrogen.

[0075] Example 20. The method of example 19, further comprising, after performing the cyclical plasma etch process, extending the recess by exposing the substrate to a third plasma comprising a halogen, wherein performing the cyclical plasma etch process exposes a top surface of the fin hard mask, and wherein extending the recess by exposing the substrate to the third plasma exposes the oxide layer.

[0076] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to the above description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method of processing a substrate, the method comprising: Implementing a cyclical plasma etching process comprising a plurality of cycles, Each of the plurality of cycles comprises: etching a patterning layer comprising polycrystalline semiconductor material by exposing the substrate to a first plasma to form or extend a recess, the patterning layer comprising polycrystalline semiconductor material, the substrate comprising an oxide layer, the patterning layer being formed on the oxide layer; exposing the substrate to a second plasma, the second plasma comprising dihydrogen, wherein exposing the substrate to the second plasma amorphizes the polycrystalline semiconductor material at the surface of the recess; and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma; A method comprising:

2. 10. The method of claim 1, further comprising forming a patterned hard mask layer on the patterned layer by a lithography process and etching before performing the cyclical plasma etching process, wherein the cyclical plasma etching process is performed using the patterned hard mask layer as an etching mask.

3. 2. The method of claim 1, further comprising, after performing the cyclical plasma etching process and before extending the recess by exposing the substrate to the third plasma, performing a surface treatment to form a protective surface layer on the surface of the recess, wherein the protective surface layer protects sidewalls of the recess during extension of the recess by exposing the substrate to the third plasma.

4. The method of claim 3 , wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprising oxygen, and the protective surface layer comprises an oxide.

5. The method of claim 3 , wherein the surface treatment comprises exposing the substrate to a reactive gas, the reactive gas comprising nitrogen, and the protective surface layer comprises a nitride.

6. The method of claim 1 , wherein the first plasma comprises a halogen.

7. The method of claim 6 , wherein the first plasma comprises hydrogen bromide and dichlorine.

8. The method of claim 1 , wherein exposing the substrate to the second plasma smoothes a surface of a sidewall of the recess.

9. The method of claim 1 , wherein the third plasma comprises a halogen.

10. The method of claim 1 , wherein the third plasma comprises hydrogen bromide and dichlorine.

11. 10. The method of claim 1, wherein an etch rate of the polycrystalline semiconductor material during exposure of the substrate to the third plasma is slower than an etch rate of the polycrystalline semiconductor material during exposure of the substrate to the first plasma.

12. The method of claim 1 , wherein the recess extended by exposing the substrate to the third plasma has a height-to-width ratio of about 5-10.

13. The method described in claim 1, wherein the second plasma is a hydrogen plasma generated from dihydrogen.

14. 1. A method of processing a substrate, the method comprising: Implementing a cyclical plasma etching process comprising a plurality of cycles, Each of the plurality of cycles comprises: etching a polysilicon layer to form a recess by exposing the substrate to a first plasma for a first time period, the substrate including an oxide layer, the polysilicon layer being formed on the oxide layer, and the first plasma including hydrogen bromide and dichlorine; exposing the substrate to a second plasma for a second period of time, the second plasma comprising dihydrogen, and exposing the substrate to the second plasma smooths a surface of a sidewall of the recess; A method comprising, including performing,

15. 15. The method of claim 14, wherein the first period of time is between 5 seconds and 120 seconds, and the second period of time is between 2 seconds and 50 seconds.

16. 15. The method of claim 14, wherein exposing the substrate to the second plasma amorphizes the polysilicon layer at the surfaces of the recesses and reduces a standard deviation of critical dimensions of the recesses at different depths by 20% or more.

17. After performing the cyclic plasma etching process, performing a surface treatment to form a protective surface layer on the surface of the recess; 15. The method of claim 14, further comprising: further extending the recess in the polysilicon layer by an etching process comprising exposing the substrate to a third plasma for a third period of time, the third plasma comprising hydrogen bromide and dichlorine, and wherein the protective surface layer protects sidewalls of the recess from the third plasma.

18. 18. The method of claim 17, wherein the third period of time is longer than the first period of time.

19. 1. A method of fabricating a fin field effect transistor, the method comprising: forming a fin feature on an oxide layer, the oxide layer being formed over a substrate, the fin feature including a fin hard mask and a fin below the fin hard mask, the fin including silicon; depositing a dummy gate material comprising polysilicon; depositing a gate hard mask layer over the dummy gate material; depositing a photoresist over the gate hard mask layer; performing a photolithography process to pattern the photoresist; Etching the gate hard mask layer to transfer a pattern from the photoresist to the gate hard mask layer; performing a cyclical plasma etching process using the gate hard mask layer as an etch mask, the cyclical plasma etching process exposing the fin hard mask and including a plurality of cycles; Each of the plurality of cycles comprises: etching the dummy gate material to form a recess by exposing the substrate to a first plasma, the first plasma including a halogen; exposing the substrate to a second plasma, the second plasma including hydrogen, and exposing the substrate to the second plasma smoothes a surface of a sidewall of the recess; and A method comprising:

20. 20. The method of claim 19, further comprising extending the recess by exposing the substrate to a third plasma after performing the cyclical plasma etching process, the third plasma comprising a halogen, wherein performing the cyclical plasma etching process exposes a top surface of the fin hard mask, and wherein extending the recess by exposing the substrate to the third plasma exposes the oxide layer.

21. The method described in claim 19, wherein exposing the substrate to the second plasma causes the dummy gate material to become amorphous at the surface of the recess.

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