Method for forming a semiconductor device having memory cells, high voltage devices, and logic devices in a substrate using dummy areas - Patents.com

Abstract

A method of forming devices in a semiconductor substrate having a first, second, third, and dummy area includes recessing a top surface of the substrate in the first, second, and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulating layer over the substrate, forming a first trench in the substrate through the first insulating layer in the third area and the second portion of the dummy area, forming a second trench in the substrate through the first insulating layer, the first conductive layer in the first and second areas and the first portion of the dummy area, and filling the first and second trenches with an insulating material. Memory cells are then formed in the first area, HV devices are formed in the second area, and logic devices are formed in the third area.

Description

[Technical field]

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 310,020, filed February 14, 2022, and U.S. Patent Application No. 17 / 745,639, filed May 16, 2022.

[0002] FIELD OF THEINVENTION The present invention relates to semiconductor devices having embedded non-volatile memory cells. [Background technology]

[0003] Non-volatile memory semiconductor devices formed in silicon semiconductor substrates are well known. For example, U.S. Patent Nos. 6,747,310, 7,868,375, and 7,927,994 disclose memory cells having four gates (floating gate, control gate, select gate, and erase gate) formed in a semiconductor substrate, which are incorporated herein by reference for all purposes. The source and drain regions are formed as diffusion embedded regions in the substrate and define a channel region therebetween in the substrate. The floating gate is disposed above a first portion of the channel region and controls the conductivity of the first portion, the select gate is disposed above a second portion of the channel region and controls the conductivity of the second portion, the control gate is disposed above the floating gate, and the erase gate is disposed above the source region and laterally adjacent to the floating gate.

[0004] It is also known to form low-voltage and high-voltage logic devices in the same substrate as non-volatile memory cells. See, for example, U.S. Patent No. 9,276,005, which is incorporated herein by reference for all purposes. New gate materials, such as high-K dielectric and metal gates, are also used to improve performance. However, processing steps in forming memory cells may adversely affect simultaneously fabricated logic devices, and vice versa.

[0005] What is needed is an improved method for fabricating devices that include memory cells, low voltage logic devices, and high voltage devices on the same substrate. Summary of the Invention

[0006] The problems and needs noted above are addressed by a method of forming a semiconductor device, the method comprising: providing a substrate of a semiconductor material including a first area, a second area, a third area, and a dummy area, the dummy area having a first and a second portion; recessing an upper surface of the substrate in a first area, an upper surface of the substrate in a second area, and an upper surface of the substrate in a dummy area, the recessing being relative to an upper surface of the substrate in a third area; forming a first conductive layer disposed above an upper surface in the first area, the second area, the third area, and the dummy area and insulated from the upper surface in the first area, the second area, the third area, and the dummy area; removing the first conductive layer from the third area and from a second portion of the dummy area; forming a first insulating layer in the first area, the second area, the third area, and the dummy area; forming a first trench in the substrate through the first insulating layer within the third area and a second portion of the dummy area; forming a second trench in the substrate through the first insulating layer and the first conductive layer in the first area, the second area, and a first portion of the dummy area after the step of forming the first trench; filling the first and second trenches with an insulating material; removing the first insulating layer from the first area, the second area, the third area and the dummy area after filling the first and second trenches; forming a second insulating layer in the first area, the second area, and the third area; forming a second conductive layer on the second insulating layer in the first area, the second area, and the third area; performing one or more etches to selectively remove portions of the first and second conductive layers in a first area, completely remove the first and second conductive layers from a second area, and completely remove the second conductive layer from a third area, the one or more etches resulting in a pair of stack structures in the first area, each of the stack structures including a control gate of the second conductive layer disposed above a floating gate of the first conductive layer and insulated from the floating gate of the first conductive layer; forming first source regions in a substrate in a first area, each of the first source regions being disposed between one of the pairs of stack structures; forming a third conductive layer disposed above an upper surface of the substrate in the first area, the second area, and the third area and insulated from the upper surface of the substrate in the first area, the second area, and the third area; forming a first protective insulating layer above the third conductive layer in the second area; After the step of forming the first protective insulating layer, forming a fourth conductive layer disposed above the first protective insulating layer in the second area and above the third conductive layer in the first and third areas, the third and fourth conductive layers forming a composite conductive layer in the first area; performing chemical mechanical polishing or etch-back to remove the third and fourth conductive layers from the third area and to remove the fourth conductive layer from the second area; performing an etch to recess an upper surface of the composite conductive layer below a top of the stack structure in the first area to leave a plurality of erase gates of the composite conductive layer each disposed above and insulated from one of the first source regions in the first area; forming a second protective insulating layer over the composite conductive layer in the first area; removing the second conductive layer and the second insulating layer from a third area; forming a block of dummy conductive material disposed above and insulated from the top surface of the substrate in the third area after removing the second conductive layer and the second insulating layer from the third area; after the step of forming the block of dummy conductive material in the third area, etching portions of the first and second protective insulating layers, portions of the composite conductive layer in the first area, and portions of the third conductive layer in the second area to form a plurality of select gates of the composite conductive layer in the first area, each disposed adjacent to one of the stack structures, and a plurality of HV gates of the third conductive layer in the second area, each disposed above and insulated from a top surface of the substrate; forming first drain regions in the substrate in a first area, each first drain region adjacent one of the select gates; forming second source regions in the substrate in a second area, each second source region adjacent one of the HV gates; forming second drain regions in the substrate in a second area, each second drain region adjacent one of the HV gates; forming third source regions in the substrate in a third area, each third source region adjacent one of the blocks of dummy conductive material; forming third drain regions in the substrate in a third area, each third drain region adjacent one of the blocks of dummy conductive material; and replacing each of the blocks of dummy conductive material in the third area with a block of metallic material.

[0007] Other objects and features of the present disclosure will become apparent from a review of the specification, claims, and accompanying drawings.

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[0013] [Brief description of the drawings]

[0014] [Figure 1A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 1B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 1C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 1D] 1A-1C are cross-sectional views of dummy areas illustrating steps in forming a logic device. [Figure 2A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 2B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 2C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 2D] 1A-1C are cross-sectional views of dummy areas illustrating steps in forming a logic device. [Figure 3A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 3B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 3C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 3D] 1A-1C are cross-sectional views of dummy areas illustrating steps in forming a logic device. [Figure 4A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 4B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 4C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 4D] 1A-1C are cross-sectional views of dummy areas illustrating steps in forming a logic device. [Figure 5A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 5B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 5C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 5D] 1A-1C are cross-sectional views of dummy areas illustrating steps in forming a logic device. [Figure 6A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 6B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 6C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 7A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 7B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 7C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 8A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 8B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 8C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 9A]1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 9B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 9C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 10A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 10B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 10C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 11A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 11B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 11C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 12A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 12B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 12C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 13A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 13B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 13C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 14A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 14B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 14C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 15A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 15B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 15C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 16A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 16B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 16C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 17A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 17B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 17C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 18A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 18B] 1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 18C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 19A] 1A-1D are cross-sectional views of a memory cell area illustrating steps in forming a memory cell. [Figure 19B]1A-1D are cross-sectional views of HV areas illustrating steps in forming an HV device. [Figure 19C] 1A-1C are cross-sectional views of logic areas illustrating steps in forming a logic device. [Figure 20] FIG. 2 is a cross-sectional view of a memory cell area showing a completed memory cell. [Figure 21] FIG. 13 is a cross-sectional view of the HV area showing the completed HV device. [Figure 22] 1 is a cross-sectional view of a logic area showing a completed logic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present disclosure relates to a process for forming a semiconductor device by simultaneously forming memory cells, low voltage logic devices, and high voltage logic devices in the same semiconductor substrate. For purposes of this disclosure, a low voltage logic device is one that has an operating voltage lower than that of a high voltage logic device. The process described below includes forming memory cells in one or more memory cell areas 2 (also referred to as first area or MC area 2) of substrate 10, high voltage logic devices in one or more high voltage logic device areas 4 (also referred to as second area or HV area 4) of substrate 10, and low voltage logic devices in one or more low voltage logic device areas 6 (also referred to as third area or logic area 6) of substrate 10. The process also includes forming dummy structures in one or more dummy areas 8 (also referred to as fourth or dummy area 8) of substrate 10. The process is described with respect to simultaneously forming pairs of memory cells in MC area 2, high voltage logic devices in HV area 4, and low voltage logic devices in logic area 6. However, multiple such devices in each area may be formed simultaneously. Substrate 10 is a substrate of semiconductor material (eg, silicon).

[0016] 1A-19A for MC area 2, 1B-19B for HV area 4, 1C-19C for logic area 6, and 1D-5D for dummy area 8, cross-sectional views of steps in a process for fabricating a semiconductor device are shown. The process begins by recessing a top surface 10a of a silicon substrate 10 into the MC areas 2, HV areas 4, and dummy areas 8 by a recession amount R relative to the logic areas 6. The step of recessing the substrate top surface 10a may be performed by forming a silicon dioxide (also referred to herein as "oxide") layer on the substrate top surface 10a and forming a silicon nitride (also referred to herein as "nitride") layer on the oxide layer. A photolithography masking operation is performed to cover the logic area 6 and to leave the photoresist uncovered in the MC, HV and dummy areas 2 / 4 / 8 (i.e., form photoresist over all four areas, selectively expose portions of the photoresist, and selectively remove portions of the photoresist, leaving exposed portions of the underlying structure (in this case, the nitride layer in the MC, HV and dummy areas 2 / 4 / 8) while leaving other portions of the underlying structure covered by the photoresist (in this case, the nitride layer in the logic area 6). A nitride and oxide etch is performed to remove these layers from the MC, HV and dummy areas 2 / 4 / 8, leaving the top surface 10a in these areas exposed. After photoresist removal, a thermal oxidation is then performed to form an oxide layer on the exposed portions of the top surface 10a in the MC, HV and dummy areas 2 / 4 / 8, while the top surface 10a in the logic area 6 is unaffected (protected by the nitride and oxide layers). This thermal oxidation process consumes some of the silicon of the substrate 10 in the MC, HV and dummy areas 2 / 4 / 8, effectively lowering (recessing) the top surface 10a in these three areas by a recess amount R. Nitride and oxide etches are then used to remove all of the oxide and nitride layers, resulting in the structure shown in Figures 1A, 1B, 1C and 1D. The top surface 10a in the MC, HV and dummy areas 2 / 4 / 8 is recessed by a recess amount R (e.g., about 300A) relative to the top surface 10a in the logic area 6. The dummy area 8 is disposed between the logic area 6 on the one hand and the MC and HV areas 2 / 4 on the other hand.The dummy area 8 may be of any suitable shape, including but not limited to, the shape of a ring that partially or completely surrounds the logic area 6 .

[0017] Next, an oxide layer 12 is formed (e.g., by deposition or thermal growth) on the top surface 10a. A conductive layer 14 (i.e., a first conductive layer), such as a polysilicon layer, is then formed on the oxide layer 12. The conductive layer 14 can alternatively be amorphous silicon, either in-situ doped or undoped. If polysilicon or amorphous silicon is used for the conductive layer 14, an implant and anneal is performed. A photolithographic masking operation is then performed to cover the MC area 2 and the HV area 4, and the first portion 8a of the dummy area 8 with photoresist 17, but leave the logic area 6 and the second portion 8b of the dummy area 8 exposed (i.e., the photoresist 17 is removed from the logic area 6 and the second portion 8b of the dummy area 8 as part of the masking operation). One or more etches are used to remove the exposed portions of the conductive layer 14 and the oxide layer 12 in the logic area 6, and the second portion 8b of the dummy area 8. The resulting structures are shown in Figures 2A, 2B, 2C, and 2D.

[0018] After removing the photoresist 17, an oxide layer 18 is formed on the conductive layer 14 in the first portion 8a of the MC, HV areas 2 / 4 and dummy areas 8, and on the top surface 10a of the substrate 10 in the second portion 8b of the logic area 6 and dummy areas 8. A nitride layer 20 (also referred to herein as a first insulating layer) is formed on the oxide layer 18. The resulting structure is shown in Figures 3A, 3B, 3C and 3D. A photolithographic masking operation is then performed to completely cover the nitride layer 20 with photoresist 21a in the first portion 8a of the MC areas 2, HV areas 4 and dummy areas 8, and selectively cover the nitride layer 20 with photoresist 21a in the second portion 8b of the logic area 6 and dummy areas 8 (i.e., leaving selective portions of the nitride layer 20 exposed in the second portion 8b of the logic area 6 and dummy areas 8). One or more etches are performed to form trenches in the silicon substrate 10 through the exposed portions of the nitride layer 20, the oxide layer 18, leaving trenches 10b (also referred to herein as first trenches) formed in the substrate 10 in the logic area 6 and in the second portion 8b of the dummy area 8 where the first conductive layer 14 is absent, but no such trenches are formed in the MC and HV areas 2 / 4, as shown in Figures 4A, 4B, 4C, and 4D. After the photoresist 21a is removed, a photolithographic masking operation is then performed to completely cover the nitride layer 20 in the logic area 6 and the second portion 8b of the dummy area 8 with the photoresist 21b, and selectively cover the nitride layer 20 in the MC area 2, the HV area 4, and the first portion 8a of the dummy area with the photoresist 21b (i.e., leaving selective portions of the nitride layer 20 exposed in the MC area 2, the HV area 4, and the first portion 8a of the dummy area 8).One or more etches are performed to form trenches in silicon substrate 10 through exposed portions of nitride layer 20, oxide layer 18, polysilicon layer 14, and oxide layer 12, as shown in Figures 5A, 5B, 5C, and 5D, leaving trenches 10c (also referred to herein as second trenches) formed in substrate 10 and first portion 8a of dummy area 8 in MC and HV area 2 / 4, but not in logic area 6 (trench 10c in MC area 2 is parallel to the view in Figure 5A and therefore is not shown in Figure 5A).

[0019] After the photoresist 21b is removed, the first and second trenches 10b and 10c are then filled with oxide 22 by oxide deposition and chemical mechanical polish (CMP) stopping on the nitride layer 20, as shown in Figures 6A, 6B, and 6C. The second trench 10c filled with oxide 22 extends parallel to the active areas in the MC area 2, but the second trench 10c filled with oxide 22 in the MC area 2 is not shown in Figure 6A because Figure 6A is a cross-sectional view of one of the active areas. The oxide 22 is an insulating material that may also be referred to as STI (shallow trench isolation) oxide 22. The STI oxide 22 may include a liner oxide formed by thermal oxidation before oxide deposition.

[0020] A nitride etch is then used to remove the nitride layer 20 from the MC / HV / Logic / Dummy areas 2 / 4 / 6 / 8. A series of implants can be performed to create the desired wells in the substrate 10 in each of the MC / HV / Logic areas 2 / 4 / 6 (with photoresist protecting one or more of the other areas during each implant), followed by an oxide etchback to recess the STI oxide 22 below the top of the nitride layer 20. An insulating layer 24 (also referred to herein as a second insulating layer) is then formed over the structure. The insulating layer 24 can be an ONO insulating layer, which is a composite layer having oxide / nitride / oxide sublayers (formed by oxide, nitride, oxide deposition, and anneal). However, the insulating layer 24 can instead be formed of a composite of other dielectric layers, or a single dielectric material with no sublayers. A conductive layer 26 (i.e., a second conductive layer), such as a polysilicon layer, is then formed in the structure, in one example by deposition. Conductive layer 26 may alternatively be amorphous silicon, either in-situ doped or undoped. If polysilicon or undoped amorphous silicon is used for conductive layer 26, implantation and annealing are performed. A hard mask layer 28 is then formed on conductive layer 26. Hard mask layer 28 may be a nitride layer, a SiCN layer, or a composite that may include an oxide layer, a nitride layer, or a SiCN layer. The resulting structure is shown in Figures 7A, 7B, and 7C.

[0021] A photolithographic masking operation is used to form photoresist 30 on the structure, where the photoresist 30 is removed from the HV areas 4 and selectively removed from the MC areas 2 to expose the hardmask layer 28 in the HV areas 4 and to expose portions of the hardmask layer 28 in the MC areas 2. A series of etches is used to remove the exposed portions of the hardmask layer 28, the conductive layer 26, and the insulating layer 24, leaving a pair of spaced apart stack structures S1 and S2 of the hardmask layer 28, the conductive layer 26, and the insulating layer 24 in the MC areas 2, completely removing these layers from the HV areas 4. The resulting structure is shown in Figures 8A, 8B, and 8C.

[0022] After the photoresist 30 is removed, oxide deposition or thermal oxidation followed by oxide etching is used to form oxide spacers 32 along the sides of the stack structures S1 and S2 in the MC area 2. Nitride deposition and etching is used to form nitride spacers 34 along the sides of the oxide spacers 32. Oxide and nitride etching can be combined. Depending on the material of the conductive layer 14, an etch such as polysilicon etching or silicon etching is performed to remove the exposed parts of the conductive layer 14, so that each spaced apart stack structure S1 / S2 includes a block of remaining conductive material 14a from the conductive layer 14 in the MC area 2, and the conductive layer 14 is completely removed from the HV area 4. By oxide deposition and oxide anisotropic etching, oxide spacers 36 are formed along the exposed ends of the blocks of conductive material 14a on the sides of the stack structures S1 / S2, as shown in Figures 9A, 9B, and 9C.

[0023] A photolithographic masking operation is used to cover the MC and logic areas 2 / 6 with photoresist, but leave the HV area 4 exposed. An oxide etch is used to remove the oxide layer 12 from the HV area 4. After removal of the photoresist, an insulating layer 38 is then formed on the substrate top surface 10a in the HV area 4, and the structures in the MC area 2 and logic area 6 by thermal growth, deposition, or both. The insulating layer 38 can be an oxide, an oxynitride, or both, and serves as the gate oxide of the HV devices. However, it should be noted that the removal of the oxide layer 12 and replacement with the insulating layer 38 is optional, and the oxide layer 12 can instead be used as part or the entire gate oxide of the HV devices in the HV area 4. After removal of the photoresist, a photoresist 40 is formed on the structures and removed from the area between the pairs of stack structures S1 and S2 in the MC area 2 (referred to herein as the inner stack area). A fill process is performed to form source region 42 (referred to herein as first source region) in the substrate between the pair of stack structures S1 and S2, i.e., in the inner stack area. An oxide etch is then used to remove insulating layer 38, oxide spacer 36, and oxide layer 12 in the inner stack area. The resulting structure is shown in Figures 10A, 10B, and 10C.

[0024] After removal of the photoresist 40, a tunnel oxide 44 is formed in the structure. The tunnel oxide 44 can be an oxide, an oxynitride, or both formed by deposition, thermal growth, or both. Due to the catalytic effect of the higher dopant level in the source region 42, the tunnel oxide 44 can have a thicker portion 44a in the source region 42. Using a photolithographic masking operation, the inner stack areas in the HV and logic areas 4 / 6 and the MC area 2 are covered with photoresist. The areas of the stack structures S1 and S2 opposite the inner stack areas (referred to herein as the outer stack areas) remain exposed. Filling can be performed at this point for the portions of the substrate 10 in the outer stack areas (i.e., those substrate portions that will be under the select gates that will be formed later). An oxide etch is used to remove the exposed portions of the oxide layer 12 in the outer stack areas. After removal of the photoresist, an insulating layer 46 is formed in the structure. The insulating layer 46 can be an oxide, an oxynitride, or both formed by deposition, thermal growth, or both, or any other suitable dielectric material. The formation of insulating layer 46 thickens or becomes part of tunnel oxide 44 and insulating layer 38. The resulting structure is shown in Figures 11A, 11B, and 11C.

[0025] A conductive layer 48, such as a polysilicon layer (referred to herein as the third conductive layer), is formed on the structure in the MC, HV, and logic areas 2 / 4 / 6. The conductive layer 48 can be in-situ doped or undoped, and can alternatively be amorphous silicon. If undoped polysilicon or amorphous silicon is used for the conductive layer 48, doping and annealing can be performed. A protective insulating layer 54 (referred to herein as the first protective insulating layer) is formed over the structure. The protective insulating layer 54 can be oxide, nitride, SiCN, or a combination thereof. Using a photolithographic masking operation, the HV area 4 is covered with photoresist, leaving the MC and logic areas 2 / 6 exposed. Using an insulating layer etch, the protective insulating layer 54 is removed from the MC and logic areas 2 / 6. After the insulating layer etch and photoresist removal, a conductive layer 50 (referred to herein as a fourth conductive layer), such as a polysilicon layer, is then formed on the structure above the protective insulating layer 54 in the HV area 4 and above the conductive layer 48 in the MC and logic areas 2 / 6, and the conductive layer 50 is formed directly on the conductive layer 48 to collectively form a composite conductive layer 52 from both layers 48 / 50. The conductive layer 50 can alternatively be amorphous silicon, either in-situ doped or undoped. A chemical mechanical polishing (CMP) or etchback is performed to planarize the top surface of the structure, which completely removes the composite conductive layer 52 from the logic area 6, removes the conductive layer 50 from the HV area 4, removes the insulating layer 38 from the logic area 6, and planarizes the top surface of the composite conductive layer 52 in the MC area 2. The hard mask layer 28 in the logic area 6 can be used as a stop layer for the CMP or etchback, as shown in Figures 12A, 12B, and 12C.

[0026] A further etch-back process is used to recess the top surface of composite conductive layer 52 below the tops of stack structures S1 and S2 to a target height. At this point in the process, most of the memory cell formation is completed. A protective insulating layer 55 (herein referred to as the second protective insulating layer) is formed over the structure, followed by planarizing the top surface of the structure by chemical mechanical polishing (CMP) or etch-back. Protective insulating layer 55 can be oxide, nitride, SiCN, or a combination thereof. A photolithographic masking operation is used to cover the MC and HV areas 2 / 4 with photoresist while leaving logic area 6 exposed. One or more etches are used to remove protective insulating layer 55, hard mask 28, conductive layer 26, and insulating layer 24 in logic area 6, as shown in Figures 13A, 13B, and 13C (after photoresist removal). Protective insulating layers 54 and 55 protect the MC and HV areas 2 / 4 from this etch sequence.

[0027] The implantation may be performed to form doped P and N wells in the substrate 10 in the logic area 6. A dielectric layer 56 is formed on the exposed substrate top surface 10a in the logic area 6 (which may function as a gate dielectric for the logic devices). The dielectric layer 56 may be silicon oxide, silicon oxynitride, a high-K dielectric layer, or a composite thereof. A high-K insulating material is an insulating material that has a dielectric constant K greater than that of silicon dioxide. Examples of high-K insulating materials include HfO2, ZrO2, TiO2, Ta2O5, and combinations thereof. A dummy conductive layer 58, such as a polysilicon layer, is then formed above the structure. An insulating layer 59, such as nitride (also referred to herein as logic insulating layer 59), and a hard mask layer 60 are then formed on the dummy conductive layer 58. Using a photolithographic masking operation, selected portions of the logic area 6 are covered with photoresist, leaving the insulating layer 59 and hard mask layer 60 exposed throughout the MC and HV areas 2 / 4, as well as portions of the logic area 6. Then, etching is used to remove the exposed areas of the insulating layer 59 and the hard mask layer 60 in the MC area, the HV area, and the logic areas 2 / 4 / 6. After removing the photoresist, etching is used to remove the exposed parts of the dummy conductive layer 58 and the dielectric layer 56 (i.e., all parts not protected by the remaining parts of the hard mask layer 60 in the logic area 6), leaving the logic stack structures LS1 and LS2 in the logic area 6 including blocks of dummy conductive material 58 disposed in the remaining dielectric layer 56. Dielectric spacers 62 (e.g., nitride) are formed on the sides of the logic stack structures LS1 / LS2 by deposition and etching. An embedding can be performed on the substrate 10 in the logic area 6. The resulting structure is shown in Figures 14A, 14B, and 14C.

[0028] Using a photolithographic masking operation, the logic area 6, a portion of the HV area 4, and a portion of the MC area 2 are covered with photoresist 64 (i.e., covering the inner stack area, the stack structures S1 and S2, and those portions of the outer stack area directly adjacent to the stack structures S1 and S2). Using an etch, the exposed portions of the protective insulating layers 54 and 55, the composite conductive layer 52, and the conductive layer 48 in the MC and HV areas 2 / 4 are removed, as shown in Figures 15A, 15B, and 15C. After removing the photoresist 64, additional selective filling and etching can be performed (i.e., by additional photolithographic masking operations and filling) in different exposed portions of the substrate 10. For example, the logic area 6 can be covered by photoresist, while the MC and HV areas 2 / 4 are left exposed, and the portions of the substrate 10 covered by the insulating layers 38 and 46 are subjected to filling. Using a photolithographic masking operation, the logic area 6 can be covered, while the MC and HV areas 2 / 4 are left exposed. Etching is then used to thin the exposed portions of insulating layers 38 and 46 (and also thin the protective insulating layers 54 and 55) so that subsequent processing can provide better buried penetration into HV area 4. The resulting structure is shown in Figures 16A, 16B, and 16C (after photoresist removal).

[0029] A semi-nonconformal layer 70 is formed on the structure. The semi-nonconformal layer 70 retains some of the conformality of the underlying topography, but is thinner on top of the underlying topography compared to where the vertical and horizontal surfaces meet. To achieve such a varying thickness, a flowable material may be used to form the layer 70. A non-limiting exemplary material for the semi-nonconformal layer 70 is a BARC material (bottom anti-reflective coating), which is commonly used to reduce reflectivity at the resist interface during photolithography. BARC materials are flowable and wettable, and are easily etched and removed with minimal process damage due to their high selectivity to oxides. Other materials that can be used for the semi-nonconformal layer 70 include photoresist or spin-on glass (SOG). An etch (e.g., anisotropic) is used to remove the upper portion of the semi-nonconformal layer 70 from the protective insulating layers 54 and 55 on the stack structures S1 / S2 and on the remaining portions of the composite conductive layer 52 and conductive layer 48, and the hard mask layer 60 of the logic stack structures LS1 / LS2, exposing them, while the semi-nonconformal layer 70 remains covering the insulating layers 38 and 46 (i.e., this portion of the semi-nonconformal layer 70 serves as a hard mask for the next etching operation). An etch is used to remove the hard mask layer 60 of the logic stack structures LS1 / LS2. The resulting structure is shown in Figures 17A, 17B, and 17C.

[0030] After removal of the semi-nonconformal layer 70, oxide and nitride deposition, followed by spacer etching, is used to form oxide spacers 66 and nitride spacers (not shown) on the sides of the stack structures S1 / S2 in the MC area 2, the sides of the stack structures LS1 / LS2 in the logic area 6, and the sides of the structures in the HV area 4. Implantation is performed to form a drain region 74 (referred to herein as a first drain region 74) in the substrate adjacent to the oxide spacer 66 in the MC area 2, to form source and drain regions 76 / 78 (referred to herein as a second source region 76 and a second drain region 78) adjacent to the oxide spacer 66 in the HV area 4, and to form source and drain regions 80 / 82 (referred to herein as a third source region 80 and a third drain region 82) adjacent to the oxide spacer 66 and the dummy conductive material 58 in the logic area 6. The implantation of any given region can be performed by forming a photoresist to prevent implantation of other regions that should not be implanted. For example, drain region 74 in MC area 2, source / drain regions 76 / 78 in HV area 4, and source / drain regions 80 / 82 in logic area 6 of the same doping type can be formed simultaneously by forming photoresist in the areas of opposite source / drain doping type and then performing a single implant in MC, HV, and logic areas 2 / 4 / 6. A deposition, masking operation, and an etch can form a blocking layer 84 to prevent any silicidation in a subsequent operation. The remaining portions of protective insulating layers 54 and 56 in MC and HV areas 2 / 4 that are not protected by blocking layer 84 are also removed during this etch, exposing composite conductive layer 52 and conductive layer 48 to subsequent silicidation. Metal deposition and annealing are then performed to form silicide 86 on the top surfaces of the exposed portions of composite conductive layer 52 and conductive layer 48, source region 76 / 80, and drain region 74 / 78 / 82. Blocking layer 84 prevents silicide formation anywhere such formation is undesirable.Optionally, blocking layer 84 may be maintained over selected portions of source / drain regions 74 / 76 / 78 / 80 / 82 and any portion of conductive layer 48 to prevent silicide formation in those selected regions. An etch such as a nitride etch is then used to remove oxide spacers 66 and nitride spacers of insulating layer 59 in logic area 6 (exposing blocks of dummy conductive layer 58) and hardmask layer 28 in MC area 2. The resulting structure is shown in Figures 18A, 18B, and 18C.

[0031] An insulating layer 88 (e.g., nitride) is formed over the structure. A relatively thick layer of insulating material 90 (also referred to herein as an inter-layer dielectric (ILD) insulating material layer) is then formed on the insulating layer 88. CMP is performed to planarize and recess the ILD insulating material layer 90 to expose the dummy conductive layer 58 in the logic area 6. A photolithographic masking operation is used to cover the MC and HV areas 2 / 4 with photoresist, leaving the logic area 6 exposed. An etch, such as a polysilicon etch, is then used to remove the blocks of dummy conductive layer 58 in the logic area 6. A layer of metallic material, such as, but not limited to, Al, Ti, TiAlN, TaSiN, TaN, TiN, or other suitable metallic material, or a composite thereof, is formed over the structure. CMP is then performed to remove the layer of metallic material, leaving blocks of metallic material 94 disposed on the dielectric layer 56 in the logic area 6. The final structure is shown in Figures 19A, 19B, and 19C.

[0032] FIG. 20 shows the final memory cell structure in MC area 2, which includes a pair of memory cells, each sharing a source region 42 spaced from two drain regions 74, and having a channel region 96 in silicon 10 extending between the drain region 74 and the source region 42. Each memory cell includes a floating gate 14a (i.e., a block of remaining conductive material from the conductive layer 14) disposed above and insulated from a first portion of the channel region 96 to control the conductivity of the first portion of the channel region 96, a select gate 52a (i.e., which may also be referred to as a word line gate and is a block of remaining conductive material from the composite conductive layer 52) disposed above and insulated from a second portion of the channel region 96 to control the conductivity of the second portion of the channel region 96, a control gate 26a (i.e., a block of remaining conductive material from the conductive layer 26) disposed above and insulated from the floating gate 14a, and an erase gate 52b (i.e., a block of remaining conductive material from the composite conductive layer 52) disposed above and insulated from a source region 42 (shared by a pair of memory cells). The memory cell pairs extend in a column direction (i.e., in the bit line direction), and columns of memory cells are formed with STI oxide 22 between adjacent columns. Rows of control gates 26a are formed as continuous control gate lines that interconnect the control gates 26a across the rows of memory cells. Rows of select gates 52a are formed as continuous select gate lines (also referred to herein as word gate lines) that interconnect the select gates 52a across the rows of memory cells. Rows of erase gates 52b are formed as continuous erase gate lines that interconnect the erase gates across the rows of memory cell pairs.

[0033] The final HV devices are shown in Figure 21. Each HV device includes spaced apart source and drain regions 76 and 78 with a channel region 98 of silicon substrate 10 extending therebetween. An HV gate 48c (i.e., a block of remaining conductive material from conductive layer 48) is disposed above and insulated from channel region 98 (i.e., source and drain regions 76 and 78 are adjacent to HV gate 48c) to control the conductivity of channel region 98.

[0034] The final logic device is shown in Figure 22. Each logic device includes spaced apart source and drain regions 80 and 82 with a channel region 100 of the silicon substrate 10 extending therebetween. A block of metal material 94 is disposed above and insulated from the channel region 100 (by a dielectric layer 56) as a metal gate 94 to control the conductivity of the channel region 100 (i.e., the source and drain regions 80 and 82 are adjacent to the metal gate 94).

[0035] The above method of forming memory cells, HV devices, and logic devices on the same substrate has many advantages. Because the formation of the memory cells and HV devices is completed before the metal gate 94 is formed in the logic area 6, the metal gate 94 in the logic area 6 is not adversely affected by the formation of the memory cells and HV devices. The process operations for forming the gates in the MC and HV areas 2 / 4 are separate and independent from (and can be customized to) the process operations for the formation of the gates in the logic area 6. The MC and HV areas 2 / 4 are covered by protective insulating layers 54 and 55 after the majority of the formation of the memory cells and HV devices is completed and before processing in the logic area 6 (i.e., before the removal of layers in the remaining logic area 6 from the formation of the memory cells and HV devices, and before the deposition and removal of layers used in the formation of the logic devices, including but not limited to the removal of dummy polysilicon). The top surface 10a of the substrate 10 is recessed in the MC and HV areas 2 / 4 compared to the logic area 6 to accommodate the taller structures in the MC / HV areas 2 / 4 (i.e., the tops of the lower height logic devices in the logic area 6 are approximately flush with the tops of the higher height memory cells and HV devices in the MC / HV areas 2 / 4, and CMP across all three areas can be used for processing - e.g., the tops of the select gates 52a and HV gates 48c are substantially flush with the dummy conductive layer 58 during CMP of the ILD 90). Layer 88 protects the suicided conductive layer 48 and the suicided composite conductive layer 52 from the CMP used in forming the metal gate 94, and the conductive layer 26 serves as a stop layer for this CMP. Silicide 86 increases the conductivity of drain region 74, and source / drain regions 76 / 78, source / drain regions 80 / 82, select gate 52a, erase gate 52b, and HV gate 48c. Semi-nonconformal layer 70 protects the oxide and silicon in the source / drain regions of MC and HV areas 2 while hardmask layer 60 is removed from logic area 6.The memory cell select gate 52a, the memory cell erase gate 52b, and the HV gate 48c can be formed using a single conductive material deposition (i.e., a single polysilicon layer formed by a single polysilicon deposition can be used to form all three types of gates). Furthermore, the same polysilicon etch can be used to define one edge of each select gate 52a and both edges of each HV gate 48c. The thicknesses of the various layers 46, 12, 38, and 56 (used as gate oxides) are independent of each other and can therefore be set independently for each gate operation. For example, the insulating layer 46 under the select gate 52a can be thinner than the oxide layer 12 under the floating gate 14a.

[0036] The formation of STI isolation 22 in various areas is improved by removing polysilicon layer 14 and oxide layer 12 in parts of logic area 6 and dummy area 8 before the formation of oxide layer 18 and nitride layer 20, and then forming STI trench 10b in logic area 6 separately from the formation of STI trench 10c in MC and HV areas 2 / 4. This creates an STI trench in logic area 6 without having to etch through polysilicon layer 14 and oxide layer 12 (i.e., oxide layer 12 can be difficult to punch through during trench etch). Thus, by forming trench 10b and trench 10c separately through different layers and using different trench etches, it is easier to obtain the desired dimensions of trench 10b and trench 10c, resulting in a better STI profile in all three areas. It also allows the layers present in the MC and HV areas 2 / 4 and the layers present in the logic area 6 to be set for their respective trench etches without having to be compromised if a common trench etch is used for all three areas. There is a transition between the nitride layer 20 formed over three layers (12, 14, 18) in the MC and HV areas 2 / 4 and the nitride layer 20 formed over a single layer (18) in the logic area 6, where a transition area is provided that is protected by photoresist during both the STI etch in the MC and HV areas 2 / 4 (to form trench 10c) and the STI etch in the logic area 6 (to form trench 10b) by providing a dummy area 8 where trench 10b is formed in one portion and trench 10c is formed in another portion. The dummy area 8 as a transition area prevents a transition area silicon double etch that could occur if the trench formed in the first STI etch is exposed during the second STI etch. Finally, using a single oxide deposition to fill both types of trenches 10b and 10c reduces complexity.

[0037] The CMP used to planarize the composite conductive layer 52 in the MC area 2, followed by an etch to recess the composite conductive layer 52 below the tops of the stack structures S1 and S2 (see FIGS. 12A-12C and related discussion) provides reliable control of the height of the composite conductive layer 52 in the MC area 2 (e.g., using an auto process control (APC) to measure the thickness of the composite conductive layer 52 prior to the etching process and then derive the etching time based on the etch rate of the etch) and allows height differentiation between the composite conductive layer 52 in the MC area 2 and the conductive layer 48 in the HV area 4, thus avoiding additional masking operations. Finally, the protective insulating layers 54 and 55 in the MC and HV areas 2 / 4, as well as the hard mask layer 60 in the logic area 6, are etched after the formation of the semi-conformal layer 70, thereby avoiding the need for an extra masking operation before forming the silicide 86.

[0038] It will be understood that the present disclosure is not limited to the embodiments described above and illustrated herein, but encompasses any and all modifications within the scope of the appended claims. For example, reference to the present disclosure herein is not intended to limit the scope of the claims or the terms of the claims, but instead merely refers to one or more features that may be covered by one or more of the claims. The material, process, and numerical examples described above are merely examples and should not be considered as limiting the scope of the claims. Furthermore, as will be apparent from the claims and the specification, the operations of all methods need not be performed in the exact order illustrated or claimed, but rather, any order is possible for proper formation of the memory cell areas and logic areas of the present invention, unless otherwise specified in the claims. Finally, a single layer of material can be formed as multiple layers of such or similar materials, and vice versa.

[0039] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate materials, elements, or spaces disposed therebetween) and "indirectly" (with intermediate materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intermediate materials, elements, or spaces disposed therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate without any intermediate materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A method of forming a semiconductor device, the method comprising: providing a substrate of semiconductor material including a first area, a second area, a third area, and a dummy area, the dummy area having a first and a second portion; recessing an upper surface of the substrate in the first area, an upper surface of the substrate in the second area, and an upper surface of the substrate in the dummy area, the recessing being relative to an upper surface of the substrate in the third area; forming a first conductive layer disposed above the top surface in the first area, the second area, the third area, and the dummy area and insulated from the top surface in the first area, the second area, the third area, and the dummy area; removing the first conductive layer from the third area and from the second portion of the dummy area; forming a first insulating layer in the first area, the second area, the third area, and the dummy area; forming a first trench in the substrate through the first insulating layer within the third area and the second portion of the dummy area; forming a second trench in the substrate through the first insulating layer and the first conductive layer in the first area, the second area, and the first portion of the dummy area after the forming step of the first trench; filling the first and second trenches with an insulating material; removing the first insulating layer from the first area, the second area, the third area, and the dummy area after the filling of the first and second trenches; forming a second insulating layer in the first area, the second area, and the third area; forming a second conductive layer on the second insulating layer within the first area, the second area, and the third area; performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, completely remove the first and second conductive layers from the second area, and completely remove the second conductive layer from the third area, the one or more etches resulting in a pair of stack structures in the first area, each of the stack structures including a control gate of the second conductive layer disposed above and insulated from a floating gate of the first conductive layer; forming first source regions in the substrate in the first area, each of the first source regions being disposed between one of the pairs of stack structures; forming a third conductive layer disposed over the top surface of the substrate in the first area, the second area, and the third area and insulated from the top surface of the substrate in the first area, the second area, and the third area; forming a first protective insulating layer over the third conductive layer in the second area; forming, after the forming step of the first protective insulating layer, a fourth conductive layer disposed above the first protective insulating layer in the second area and above the third conductive layer in the first and third areas, the third and fourth conductive layers forming a composite conductive layer in the first area; performing a chemical mechanical polishing or etch-back to remove the third and fourth conductive layers from the third area and to remove the fourth conductive layer from the second area; performing an etch to recess an upper surface of the composite conductive layer beneath a top of the stack structure in the first area to leave a plurality of erase gates of the composite conductive layer each disposed above and insulated from one of the first source regions in the first area; forming a second protective insulating layer over the composite conductive layer in the first area; removing the second conductive layer and the second insulating layer from the third area; forming a block of dummy conductive material disposed above and insulated from the top surface of the substrate in the third area after the removing step of the second conductive layer and the second insulating layer from the third area; after the forming step of the blocks of dummy conductive material in the third area, etching portions of the first and second protective insulating layers, portions of the composite conductive layer in the first area, and portions of the third conductive layer in the second area to form a plurality of select gates of the composite conductive layer in the first area, each disposed adjacent one of the stack structures, and a plurality of HV gates of the third conductive layer in the second area, each disposed above and insulated from the top surface of the substrate; forming first drain regions in the substrate in the first area, each first drain region adjacent one of the select gates; forming second source regions in the substrate in the second area, each second source region adjacent one of the HV gates; forming second drain regions in the substrate in the second area, each second drain region adjacent one of the HV gates; forming third source regions in the substrate in the third area, each third source region adjacent one of the blocks of dummy conductive material; forming third drain regions in the substrate in the third area, each third drain region adjacent one of the blocks of dummy conductive material; and replacing each of the blocks of dummy conductive material in the third area with a block of metallic material.

2. The method of claim 1 , wherein each of the blocks of metallic material is insulated from the top surface of the substrate in the third area by a layer of high-K insulating material.

3. 2. The method of claim 1 , wherein prior to the replacing step, each of the blocks of dummy conductive material is insulated from the top surface of the substrate in the third area by a layer of high-K insulating material, and the replacing step further comprises forming each of the blocks of metal material in the layer of high-K insulating material.

4. 2. The method of claim 1, wherein each of the first, second, third and fourth conductive layers is formed of polysilicon or amorphous silicon.

5. 2. The method of claim 1, further comprising forming a silicide on said first, second and third drain regions and said second and third source regions.

6. 2. The method of claim 1, further comprising forming a silicide on the select gate, the erase gate, and the HV gate prior to the replacing step.

7. 2. The method of claim 1, wherein the second insulating layer is an insulating layer having a first oxide, a nitride, and a second oxide sublayer.

8. 2. The method of claim 1, wherein the forming of the blocks of dummy conductive material comprises forming a logic insulation layer on the blocks of dummy conductive material and forming a hard mask layer on the logic insulation layer.

9. Prior to the replacing step, forming a layer of flowable material in the first, second, and third areas; removing a portion of the layer of flowable material to expose the hard mask layer; removing the hard mask layer; The method of claim 8 , further comprising the step of: removing the layer of flowable material.

10. 10. The method of claim 9, further comprising forming a silicide on the select gate, the erase gate, and the HV gate, wherein the logic insulation layer prevents the formation of silicide on the blocks of dummy conductive material.

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