Barrier layer for word line contact in 3D NAND memory and its fabrication method

Abstract

The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a step structure and a divider wall in the alternating dielectric stack. The step structure and the divider wall extend in a second direction parallel to the substrate, and the divider wall is adjacent to the step structure. The method also includes forming, in sequence, a first barrier layer on the step structure and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the divider wall. The GLS opening penetrates the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to International Patent Application No. PCT / CN2021 / 140362, filed December 22, 2021, which is incorporated by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates generally to the field of semiconductor technology, and more specifically to structures and fabrication methods for forming a barrier layer to provide an etch stop for wordline contacts in 3D NAND flash memory. [Background technology]

[0003] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0004] In 3D NAND flash memory, many layers of memory cells can be stacked vertically, which can greatly increase the storage density per unit area. The vertically stacked memory cells are addressed through word lines and bit lines, with each word line controlling a memory cell on one layer. To make electrical connections to the vertically stacked word lines, a staircase structure can be used to form a contact structure for each word line.

[0005] To further increase the storage density of 3D NAND flash memory, the number of vertically stacked word lines is significantly increased. Thus, the contact structures for the word lines have a wide range of depths, the shortest for the top word line and the longest for the bottom word line. To simultaneously form the contact structures for the word lines, an etch stop layer (e.g., silicon nitride) is disposed on the staircase structure, thereby avoiding overetching on the top word lines. However, the etch stop layer may be lost in various processes before fabricating the contact structure. In addition, the etch stop layer may introduce other problems. For example, a thick etch stop layer may cause seams in tungsten refill during word line formation. Thus, there is a need to provide an improved method for forming 3D NAND flash memory. Summary of the Invention [Problem to be solved by the invention]

[0006] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Improved structure and fabrication method embodiments for forming a barrier layer to provide an etch stop for wordline contacts in three-dimensional (3D) memory devices are described in this disclosure. [Means for solving the problem]

[0007] One aspect of the disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a step structure and a divider wall in the alternating dielectric stack. The step structure and the divider wall extend in a second direction parallel to the substrate, and the divider wall is adjacent to the step structure. The method also includes forming, in sequence, a first barrier layer on the step structure and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the divider wall. The GLS opening penetrates the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0008] In some embodiments, forming the first barrier layer on the staircase structure further comprises disposing the first barrier layer to cover at least sidewalls of the staircase steps of the staircase structure.

[0009] In some embodiments, forming a second barrier layer on the staircase structure includes disposing a dielectric material on the staircase structure and the dividing wall, and removing a first portion of the dielectric material disposed on the dividing wall.

[0010] In some embodiments, the method further includes removing a second portion of the dielectric material disposed in a second region of the staircase structure adjacent to the dividing wall to form a second barrier layer in the first region of the staircase structure, the first region and the second region extending in a second direction, and the first region being at a center of the staircase structure.

[0011] In some embodiments, the method also includes disposing a blocking mask to expose the dividing wall and a second region of the stair-like structure adjacent to the dividing wall.

[0012] In some embodiments, the method further includes disposing a GLS filler inside the GLS opening to form a GLS, the GLS filler including an insulating material.

[0013] In some embodiments, the method further includes removing a second dielectric layer from between the first dielectric layers through the GLS opening to form a lateral tunnel, and disposing a first conductive material in the lateral tunnel to form a film stack including alternating conductive layers and the first dielectric layer.

[0014] In some embodiments, removing the second dielectric layer includes etching the second dielectric layer selectively with respect to the first dielectric layer and the first barrier layer.

[0015] In some embodiments, the method further includes disposing an insulating layer on the second barrier layer overlying the stepped structure.

[0016] In some embodiments, the method further includes forming a contact structure in contact with one of the conductive layers in the film stack, the contact structure including penetrating the insulating layer in a first direction to expose a portion of the one of the conductive layers, and disposing a second conductive material in the contact opening to contact the exposed portion of the one of the conductive layers.

[0017] In some embodiments, forming the contact opening includes etching the insulating layer selectively with respect to the second barrier layer and etching the second barrier layer and the first barrier layer to expose a portion of one of the conductive layers in the contact opening.

[0018] Another aspect of the present disclosure provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having alternating conductive layers and first dielectric layers on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes a step-like structure disposed in the film stack and extending in a second direction parallel to the substrate, and a dividing wall extending in the second direction and disposed adjacent to the step-like structure. The three-dimensional memory device further includes a gate line slit (GLS) disposed in the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction. The 3D memory device also includes a first barrier layer disposed on the step-like structure, and a second barrier layer disposed on the first barrier layer in a first region of the step-like structure, the second barrier layer being different from the first barrier layer and being far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0019] In some embodiments, the first barrier layer covers at least the sidewalls of the stair steps of the stair structure.

[0020] In some embodiments, the 3D memory device further comprises an insulating layer disposed on the second barrier layer so as to cover a top surface and sidewalls of the second barrier layer.

[0021] In some embodiments, the 3D memory device also includes a contact structure that penetrates the insulating layer, the second barrier layer, and the first barrier layer in a first direction, the contact structure contacting one of the conductive layers of the film stack.

[0022] In some embodiments, the first region is at the center of the stepped structure and extends in the second direction.

[0023] In some embodiments, the stepped structure further comprises a second region, the second region of the stepped structure extending in a second direction and positioned between the dividing wall and the first region.

[0024] In some embodiments, the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

[0025] In some embodiments, the first barrier layer comprises a thickness in the range of 10 nm to 100 nm.

[0026] In some embodiments, the second barrier layer comprises a thickness in the range of 50 nm to 500 nm.

[0027] In some embodiments, the GLS includes insulating material and is configured to divide a storage unit into sub-storage units that independently perform read or program operations.

[0028] Yet another aspect of the present disclosure provides a memory storage system comprising a three-dimensional memory device and a memory controller, the three-dimensional memory device including the features described above, the memory controller configured to control the operation of the three-dimensional memory device and connected to the three-dimensional memory device.

[0029] Yet another aspect of the present disclosure provides a 3D memory die including a three-dimensional memory device and peripheral circuitry. The 3D memory device includes the features described above. The peripheral circuitry is coupled to the 3D memory device and configured to support operation of the 3D memory device.

[0030] Other aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure.

[0031] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. [Brief description of the drawings]

[0032] [Figure 1] 1 is a schematic top-down view illustrating an example three-dimensional (3D) memory device according to some embodiments of the present disclosure. [Diagram 2] 1 is a schematic top-down view illustrating regions of a 3D memory device according to some embodiments of the present disclosure. [Diagram 3] 1 is a perspective view illustrating a portion of an example 3D memory array structure according to some embodiments of the present disclosure. [Figure 4-1] FIG. 1 illustrates a process flow for manufacturing a 3D memory device according to some embodiments of the present disclosure. [Figure 4-2] FIG. 1 illustrates a process flow for manufacturing a 3D memory device according to some embodiments of the present disclosure. [Diagram 5] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 6] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 7]1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 8] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 9] 1A-1C are perspective views illustrating an example structure of a 3D memory device at a particular process step according to some embodiments of the present disclosure. [Figure 10] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 11] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 12] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 13A] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 13B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 13C] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 13D] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 14A] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 14B]1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 14C] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 15A] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 15B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 16A] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 16B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 16C] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 17A] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 17B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 17C] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 18A] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 18B]1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 19A] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 19B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 20A] 1A-1D are top-down views illustrating an example structure of a 3D memory device at a particular process step in accordance with some embodiments of the present disclosure. [Figure 20B] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 20C] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 20D] 1A-1D are cross-sectional views illustrating an example structure of a 3D memory device at certain process steps according to some embodiments of the present disclosure. [Figure 21A] 1 is a cross-sectional view illustrating another example structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 21B] 1 is a cross-sectional view illustrating another example structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 21C] 1 is a cross-sectional view illustrating another example structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 22] FIG. 1 illustrates a storage system having one or more memory chips in accordance with some embodiments of the present disclosure. [Figure 23A] FIG. 1 illustrates a storage system having one or more memory chips in accordance with some embodiments of the present disclosure. [Figure 23B]FIG. 1 illustrates a storage system having one or more memory chips in accordance with some embodiments of the present disclosure. [Figure 24] 1 is a schematic diagram illustrating a three-dimensional (3D) memory die according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The features and advantages of the present invention will become more apparent from the detailed description set forth below when read in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) of the corresponding reference number.

[0034] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0035] While specific configurations and arrangements have been described, it will be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0036] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like, indicate that the embodiment being described may comprise a particular feature, structure, or characteristic, but that all embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in the context of one embodiment, it will be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in the context of other embodiments, whether or not explicitly described.

[0037] Although "first," "second," or similar terms may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Generally, terms can be understood, at least in part, from their usage in context. For example, the phrase "one or (or) more" as used herein can be used in a singular sense to describe a feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, articles such as "a," "an," or "the" in the English text can again be understood as conveying the use of the singular or conveying the use of the plural, depending at least in part on the context. In addition, the phrase "based on" can be understood as not necessarily intended to convey an exclusive series of elements, but instead can permit the presence of additional elements not necessarily explicitly described, again depending at least in part on the context.

[0039] It should be readily understood that the meanings of "on," "above," and "over" in the English original text of this disclosure should be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with an intermediate feature or layer in between. Furthermore, "above" or "over" in the English original text can also include the meaning of being "on" something or "on" something without an intermediate feature or layer in between (i.e., directly on something).

[0040] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein for ease of description in describing the relationship of one element or feature to another, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or at a process stage in addition to the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0041] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are applied. The substrate comprises a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and thus the semiconductor devices are formed on the top side of the substrate unless otherwise noted. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material applied onto the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0042] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, with the bottom of the layer being relatively close to the substrate and the top side being relatively far from the substrate. A layer may extend across an underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be disposed between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces. A layer may extend along a horizontal, vertical, and / or tapered surface. A substrate may be a layer and may include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer may also include multiple layers. For example, the interconnect layers may include one or more conductor layers and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0043] In this disclosure, for ease of explanation, "tier" is used to refer to elements that are substantially the same height along the vertical direction. For example, a wordline and an underlying gate dielectric layer may be referred to as a "tier," a wordline and an underlying insulating layer may be collectively referred to as a "tier," a wordline of substantially the same height may be referred to as a "tier of a wordline," or the like, and so forth.

[0044] As used herein, the phrase "nominal / nominal" refers to a desired or target value of a characteristic or parameter for a component or process step that is set during the design phase of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0045] In this disclosure, the term "horizontal / horizontally / lateral / outer / laterally" means nominally parallel to the outer surface of the substrate, and the phrase "vertical / vertically" means nominally perpendicular to the outer surface of the substrate. Similarly, the terms "parallel" or "vertical" also mean nominally parallel or perpendicular.

[0046] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND strings) on a laterally oriented substrate such that the memory strings extend vertically with respect to the substrate.

[0047] FIG. 1 illustrates a schematic top-down view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100, such as a 3D NAND flash memory, can be a memory chip (package), a memory die, or any portion of a memory die, and can include one or more memory planes 101, each of which can include a memory block 103. The same concurrent operations can be performed in each memory plane 101. The memory blocks 103, which can have a size in megabytes (MB), are of a minimum size for performing an erase operation. As shown in FIG. 1, the exemplary 3D memory device 100 includes four memory planes 101, each of which includes six memory blocks 103. Each memory block 103 can include memory cells, which can be addressed through interconnects such as bit lines and word lines. The bit lines and word lines can be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. 1, the directions in which the bit lines and word lines extend are labeled "BL" and "WL" and are also referred to as the WL direction and the BL direction. In this disclosure, the memory blocks 103 are also referred to as "memory arrays" or "arrays." The memory array is the core region within a memory device that performs the storage function.

[0048] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the memory plane 101. The peripheral region 105 includes many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0049] Please note that the arrangement of memory planes 101 in the 3D memory device 100 and the arrangement of memory blocks 103 in each memory plane 101 illustrated in FIG. 1 are used as examples only and are not intended to limit the scope of the present disclosure.

[0050] Referring to FIG. 2, an enlarged top-down view of a region 108 of the memory block 103 in FIG. 1 is illustrated according to some embodiments of the present disclosure. The region 108 of the 3D memory device 100 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212 each including a stacked memory cell. The stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, slit structures (also referred to as gate line slits) 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 may divide the memory block into a number of memory fingers 218. At least some of the slit structures 216 may function as a common source contact (e.g., to an array common source) of the array of memory strings 212 in the channel structure region 211. A top select gate cut 220 may be disposed, for example, in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two parts, thereby dividing the memory finger into two memory slices 224, and memory cells in the memory slices 224 that share the same word line form a programmable (read / write) memory page. While erase operations of 3D NAND memory may be performed at the memory block level, read and write operations may be performed at the memory page level. The memory page may have a size in kilobytes (KB). In some embodiments, the region 108 also includes dummy memory strings 222 for process variation control during manufacturing and / or for additional mechanical support.

[0051] 3 illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure. The memory array structure 300 comprises a substrate 330, an insulating film 331 overlying the substrate 330, a tier of bottom select gates (BSG) 332 overlying the insulating film 331, and a tier of control gates 333, also referred to as "word lines (WL)", stacked over the BSG 332 to form a film stack 335 of alternating conductors and dielectric layers. The dielectric layers adjacent to the tiers of control gates are not shown in FIG. 3 for clarity.

[0052] The control gates of each tier are separated by slit structures 216-1 and 216-2 that penetrate the film stack 335. The memory array structure 300 also includes a tier of top select gates (TSGs) 334 formed over the stack of control gates 333. The stack of TSGs 334, control gates 333, and BSGs 332 is also referred to as a "gate electrode." The memory array structure 300 further includes memory strings 212 and doped source line regions 344 in a portion of the substrate 330 between adjacent BSGs 332. Each memory string 212 includes a channel hole 336 that penetrates the insulating film 331 and the film stack 335 of alternating conductors and dielectric layers. The memory strings 212 also include a memory film 337 disposed on a sidewall of the channel hole 336, a channel layer 338 disposed on a sidewall of the memory film 337, and a core filler 339 surrounded by the channel layer 338. At the intersections of the control gates 333 (e.g., 333-1, 333-2, 333-3) and the memory strings 212, memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed. A portion of a channel layer 338 is responsive to each control gate, also referred to as the channel 338 of the memory cell. The memory array structure 300 further includes a bit line (BL) 341 connected to the memory strings 212, the BL 341 being positioned above the TSG 334. The memory array structure 300 also includes a metal interconnect line 343 connected together with the gate electrodes through the contact structure 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to each tier of the gate electrodes.

[0053] In FIG. 3, for illustrative purposes, three tiers of control gates 333-1, 333-2, and 333-3 are illustrated along with one tier of TSG 334 and one tier of BSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 300 may also include other structures, such as TSG cuts, common source contacts (i.e., array common source), and dummy memory strings. These structures are not shown in FIG. 3 for simplicity.

[0054] To further increase the storage density of 3D NAND memory, the number of vertically stacked word lines 333 has been constantly increased. Thus, the contact structures 214 for the word lines 333 have a wide range of depths, the shortest for the top word line and the longest for the bottom word line. To simultaneously form the contact structures 214 for all the word lines 333, an etch stop layer is disposed on the stepped structure, which can avoid over-etching on the top word lines. However, the etch stop layer may be lost in various processes before fabricating the contact structure. For example, as shown in FIG. 21A, the etch stop layer for forming the contact structure 214 (also referred to as the second barrier layer 1166 in the detailed description below) and the sacrificial layer used for forming the word lines 333 (also referred to as the second dielectric layer 454 in the detailed description below) are usually made of the same material, for example, silicon nitride. During the replacement process to form the word line 333, the etch stop layer 1166 may be removed simultaneously with the sacrificial layer 454 through the gate line slit (GLS) opening 1582. As shown in FIG. 21B, lateral tunnels 1684 and 2184 may be formed. An additional conductive layer 2186 may be formed simultaneously as a conductive layer 1786 that may function as the word line 333. As such, a parasitic leakage path may occur due to the additional conductive layer 2186. In addition, the thick etch stop layer 1166 may cause a seam in the additional conductive layer 2186, which may weaken the mechanical strength of the 3D memory structure. Thus, there is a need to provide an improved method for forming a 3D NAND memory.

[0055] 4 illustrates a method 400 for forming a three-dimensional (3D) memory device according to some embodiments of the present disclosure. It should be understood that the process steps shown in method 400 are not exhaustive and that other steps may be performed before, after, or between any of the illustrated steps as well. In some embodiments, some steps of method 400 are omitted or may include other steps not described here for simplicity. In some embodiments, the steps of method 400 may be performed in a different order and / or may be varied.

[0056] Figures 5-12, 13A-13D, 14A-14C, 15A-15B, 16A-16C, 17A-17C, 18A-18B, 19A-19B, and 20A-20D illustrate example structures of a 3D memory device at specific process steps according to method 400.

[0057] 4, in process step S405, an alternating dielectric stack can be disposed on a substrate plate, the alternating dielectric stack including a first dielectric layer and a second dielectric layer alternately stacked on a substrate. A cross-sectional view of an exemplary 3D memory structure 500 according to process step S405 is shown in FIG.

[0058] As shown in FIG. 5, the 3D memory structure 500 includes an alternating dielectric stack 450 disposed on a substrate 330 .

[0059] The substrate 330 can provide a platform for forming subsequent structures. In some embodiments, the substrate 330 can be any suitable semiconductor substrate having any suitable semiconductor material, such as a single crystal, polycrystalline, or monocrystalline semiconductor. For example, the substrate 330 can include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 330 can include a handle wafer, e.g., a layer of semiconductor material formed on a glass, plastic, or another semiconductor substrate.

[0060] The front surface 330f of the substrate 330 is also referred to herein as the "major surface" or "top surface" of the substrate. Layers of materials may be disposed on the front surface 330f of the substrate 330. The "top" or "upper" layer is the layer furthest or further away from the front surface 330f of the substrate. The "bottom" or "lower" layer is the layer closest or closer to the front surface 330f of the substrate.

[0061] The alternating dielectric stack 450 includes pairs of dielectric layers alternately stacked along a vertical direction (i.e., z-direction or first direction) perpendicular to the front surface 330f of the substrate 330, with each dielectric layer pair including a first dielectric layer 452 (also referred to as a "dielectric layer") and a second dielectric layer 454 (also referred to as a "sacrificial layer") that is different from the first dielectric layer 452. The alternating dielectric stack 450 extends in a lateral direction (e.g., WL direction or second direction) parallel to the front surface 330f of the substrate 330.

[0062] In the alternating dielectric stack 450, the first dielectric layers 452 and the second dielectric layers 454 alternate in a vertical direction perpendicular to the substrate 330. In other words, each second dielectric layer 454 is sandwiched between two first dielectric layers 452, and each first dielectric layer 452 may be sandwiched between two second dielectric layers 454 (except for the bottom and top layers).

[0063] Forming the alternating dielectric stack 450 can include disposing the first dielectric layers 452 to each have the same thickness or to each have different thicknesses. An exemplary thickness of the first dielectric layers 452 can be in the range of 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layers 454 can each have the same thickness or to each have different thicknesses. An exemplary thickness of the second dielectric layers 454 can be in the range of 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs in FIG. 5 is for illustrative purposes only, and any suitable number of layers can be included in the alternating dielectric stack 450.

[0064] In some embodiments, the first dielectric layer 452 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide loaded with F-, C-, N-, and / or H-. The first dielectric layer 452 can also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide films. In some embodiments, the first dielectric layer 452 can be any combination of the above materials.

[0065] Formation of the first dielectric layer 452 on the substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high density plasma CVD (HDP-CVD), sputtering, evaporation, thermal oxidation, nitridation, other suitable deposition methods, and / or combinations thereof.

[0066] In some embodiments, the second dielectric layer 454 is different from the first dielectric layer 452 and includes any suitable material that can be selectively removed with respect to the first dielectric layer 452. For example, the second dielectric layer 454 can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any combination thereof. In some embodiments, the second dielectric layer 454 also includes an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The second dielectric layer 454 can be disposed using a technique similar to the first dielectric layer 452, such as CVD, PVD, ALD, sputtering, evaporation, thermal oxidation or nitridation, or any combination thereof.

[0067] In some embodiments, the first dielectric layer 452 may be silicon oxide and the second dielectric layer 454 may be silicon nitride.

[0068] In some embodiments, the alternating dielectric stack 450 can include layers in addition to the first dielectric layer 452 and the second dielectric layer 454 and can be made of different materials and / or different thicknesses.

[0069] 4, a first stepped structure may be formed in the alternating dielectric stack in process step S410. A cross-sectional view of an exemplary 3D memory structure 600 in accordance with process step S410 is shown in FIG.

[0070] As shown in FIG. 6, the 3D memory structure 600 includes a first staircase structure 656 in which a first staircase step 658 is formed in the alternating dielectric stack 450. The first staircase step 658, or "staircase layer", refers to a layer stack having the same lateral dimension in a surface parallel to the substrate surface 330f. Each of the first staircase steps terminates at a lateral dimension "a" shown in FIG. 6 that is shorter than the first staircase step below it. In some embodiments, the first staircase structure 656 has the first staircase step 658 facing the WL direction, and each of the first staircase steps 658 includes a lateral dimension "a" along the WL direction. In this example, the first staircase structure 656 extends in the WL direction (or second direction) parallel to the substrate.

[0071] In some embodiments, each of the first staircase steps 658 includes one pair of the first dielectric layer 452 and the second dielectric layer 454. In some embodiments, each of the first staircase steps 658 can include two or more pairs of the first dielectric layer 452 and the second dielectric layer 454. As shown in FIG. 6, each of the first staircase steps 658 includes one pair of the first dielectric layer 452 and the second dielectric layer 454, with the first dielectric layer 452 overlying the second dielectric layer 454. Each of the first staircase steps 658 exposes a portion of the first dielectric layer 452.

[0072] The first stair-like structure 656 may be formed by applying a repetitive etch-trim process on the alternating dielectric stack 450. The etch-trim process includes an etching process and a trimming process. In the etching process, a part of the first stair-like step 658 whose surface is exposed may be removed. The remaining part of the first stair-like step 658 is either covered by the upper level of the stair-like step or covered by the patterning mask and is not etched. The etching depth is the thickness of the first stair-like step 658. In some embodiments, the thickness of the first stair-like step 658 is the thickness of one pair of the first dielectric layer 452 and the second dielectric layer 454. The etching process for the first dielectric layer 452 may have high selectivity over the second dielectric layer 454 and / or vice versa. Thus, the underlying dielectric layer pair may function as an etch stop layer. By switching the etching process for each layer, the first stair-like step 658 may be etched during one etching cycle. And, as a result, one of the first stair-like steps 658 may be formed during each etch trim cycle.

[0073] In some embodiments, the first staircase step 658 may be etched using an anisotropic etch such as a reactive ion etch (RIE) or other dry etching process. In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, the silicon oxide etch may include RIE using a fluorine-based gas, such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6, and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch approach may be used. In some embodiments, the second dielectric layer 454 is silicon nitride. In this example, the silicon nitride etch may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof. The method and etchant for removing the monolayer stack should not be limited by the embodiments of the present disclosure.

[0074] The trimming process includes subjecting the patterning mask to a suitable etching process (e.g., isotropic dry etching or wet etching) so that the patterning mask can be pulled back laterally. The lateral pullback dimension determines the lateral dimension "a" of each step of the first staircase structure 656. After trimming the patterning mask, a portion of the top first staircase step 658 is exposed, and another portion of the top first staircase step 658 remains covered by the patterning mask. The next cycle of the etch trim process resumes with the etching process. In some embodiments, the patterning mask trimming process can include a dry etch, such as RIE using O2, Ar, N2, or the like.

[0075] 4, in process step S415, a second staircase structure may be formed by removing exposed portions of the first dielectric layer 452. Cross-sectional, top-down, and perspective views of an exemplary 3D memory structure 700 according to process step S415 are shown in FIGS.

[0076] As shown in FIG. 7, the 3D memory structure 700 includes a second staircase structure 760 (also referred to as a staircase structure) in which a second staircase step 762 (also referred to as a staircase step) is formed in the alternating dielectric stack 450. The second staircase structure 760 may be formed by removing exposed portions of the first dielectric layer 452 in the 3D memory structure 600 (FIG. 6). Similar to the first staircase structure 656, the second staircase step 762 also faces in the WL direction, and the second staircase step 762 has a lateral dimension "a" in the WL direction. In this example, the second staircase structure 760 extends in the WL direction (or second direction) parallel to the substrate.

[0077] The first dielectric layer 452 may be etched using an anisotropic etch, such as a reactive ion etch (RIE) or other dry etching process. In some embodiments, the first dielectric layer 452 is silicon oxide. In this example, the silicon oxide etch may include RIE using a fluorine-based gas, such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6, and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch approach may be used. The etching process for the first dielectric layer 452 may have high selectivity over the second dielectric layer 454. Thus, the second dielectric layer 454 may function as an etch stop layer.

[0078] In some embodiments, each of the second staircase steps 762 also includes one pair of the first dielectric layer 452 and the second dielectric layer 454, with the second dielectric layer 454 overlying the first dielectric layer 452. Each of the second staircase steps 762 exposes a portion of the second dielectric layer 454. In some embodiments, each of the second staircase steps 762 can also include two or more pairs of the first dielectric layer 452 and the second dielectric layer 454.

[0079] FIG. 7 illustrates a cross-sectional view along line CC' in FIG. 8. As shown in FIG. 8 and FIG. 9, the stepped region 210 extends along the WL direction and can include one or more of the second stepped structures 760 extending along the WL direction. Each of the second stepped structures 760 includes a second stepped step 762 that steps up or down along the WL direction in the lateral dimension "a". As an example, FIG. 8 illustrates two second stepped structures 760, and FIG. 9 illustrates more dielectric layer pairs of the first dielectric layer 452 and the second dielectric layer 454. It should be noted that the number of stepped structures and the number of dielectric layer pairs in the 3D memory structure 700 are not limited to the examples in the present specification.

[0080] As shown in Figures 8 and 9, the 3D memory structure 700 also includes a number of split regions 863 separating the second staircase structures 760. A portion of the alternating dielectric stack 450 in the split regions 863 is not etched during the repeated etch trim process to form the first staircase structure 656, forming a split wall 865 (in Figure 6). The split regions 863 are disposed adjacent to the second staircase structure 760. As such, the split wall 865 formed in the alternating dielectric stack 450 is positioned adjacent to the second staircase structure 760 and extends in the WL direction, similar to the second staircase structure 760.

[0081] 4, in process step S420, a first barrier layer can be disposed on the second stepped structure and the dividing wall of the alternating dielectric stack. A cross-sectional view of an exemplary 3D memory structure 1000 according to process step S420 is shown in FIG.

[0082] As shown in FIG. 10, the 3D memory structure 1000 includes a first barrier layer 1064 disposed on the 3D memory structure 700 (in FIGS. 7-9). The first barrier layer 1064 covers the second staircase structure 760 and the dividing wall 865 of the alternating dielectric stack 450 (as shown in FIGS. 8-9) on both the outer surface and the vertical sidewalls. The first barrier layer 1064 on the outer surface and the vertical sidewalls can have the same thickness or different thicknesses. In some embodiments, the first barrier layer 1064 is conformal, and the thickness of the first barrier layer 1064 on the outer surface and the vertical sidewalls is approximately the same. The first barrier layer 1064 can have a thickness in the range of 10 nm to 100 nm. The portion of the first barrier layer 1064 formed on the outer surface of the staircase structure can function as an etch stop layer for an etching process in the z-direction (first direction) perpendicular to the substrate 330. The portion of the first barrier layer 1064 formed on the sidewalls of the stepped structure 760 can, for example, function as an etch stop layer for an etching process in a WL direction (or a second direction) parallel to the front surface 330f of the substrate 330.

[0083] In some embodiments, the first barrier layer 1064 may be any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The first barrier layer 1064 may be disposed by any suitable thin film deposition technique, such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, evaporation, etc. In some embodiments, the first barrier layer 1064 may be silicon oxide.

[0084] 4, in process step S425, a second barrier layer, different from the first barrier layer, can be disposed on the first barrier layer over the second stepped structure and the dividing wall of the alternating dielectric stack. A cross-sectional view of an exemplary 3D memory structure 1100 according to process step S425 is shown in FIG.

[0085] As shown in FIG. 11, the 3D memory structure 1100 includes a second barrier layer 1166 disposed on the 3D memory structure 1000 on the first barrier layer 1064. The second barrier layer 1166 covers the first barrier layer 1064 on the outer surface. In some embodiments, the second barrier layer 1166 also covers the first barrier layer 1064 on the vertical sidewalls. The second barrier layer 1166 on the outer surface and the vertical sidewalls can have the same thickness or different thicknesses. In some embodiments, the second barrier layer 1166 is non-conformal, and the thickness of the second barrier layer 1166 on the vertical sidewalls is thinner than that on the outer surface. As described below, the second barrier layer 1166 can be used as an etch stop layer for forming a contact structure on the staircase steps. Therefore, a second barrier layer 1166 with a larger thickness on the outer surface of the staircase steps is preferred. In some embodiments, the second barrier layer 1166 and the first barrier layer 1064 can cover the outer surface and vertical sidewalls of the second stepped structure 760 and the dividing walls 865 of the alternating dielectric stack 450 (shown in Figures 8-9).

[0086] In some embodiments, the second barrier layer 1166 can include any suitable dielectric material different from the first barrier layer 1064. The second barrier layer 1166 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The second barrier layer 1166 can be disposed by any suitable thin film deposition technique, such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, evaporation, etc. In some embodiments, the second barrier layer 1166 can be silicon nitride, the first barrier layer 1064 can be silicon oxide, the first dielectric layer 452 can be silicon oxide, and the second dielectric layer 454 can be silicon nitride. In this example, the first barrier layer 1064 and the first dielectric layer 452 may be used as an etch stop layer when removing the second dielectric layer 454. When the first barrier layer 1064 is positioned between the second dielectric layer 454 and the second barrier layer 1166 on the outer surface and vertical sidewalls, the first barrier layer 1064 may protect the second barrier layer 1166 from being etched when removing the second dielectric layer 454.

[0087] 4, in process step S430, a block mask can be disposed to cover a first area in the center of the second staircase structure. A top-down view of an exemplary 3D memory structure 1200 according to process step S430 is shown in FIG.

[0088] As shown in FIG. 12, the 3D memory structure 1200 includes a block mask 1270 disposed on the 3D memory structure 1100 (in FIG. 11). The block mask 1270 is configured to expose a portion of the alternating dielectric stack 450 adjacent to the second staircase structure 760. For example, the block mask 1270 exposes the dividing wall 865 of the dividing region 863 disposed adjacent to the second staircase structure 760. In some embodiments, the block mask 1270 also exposes a portion of the second staircase structure 760 adjacent to the dividing region 863 and the dividing wall 865. In other words, the block mask 1270 covers a first region 1272 in the center of the second staircase structure 760. The first region 1272 extends in the WL direction. The second staircase structure 760 may include a first region 1272 covered by the block mask 1270 and a second region 1274 exposed by the block mask 1270. In some embodiments, the second region 1274 does not include the second barrier layer 1166. The second region 1274 also extends in the WL direction and is positioned between the dividing wall 865 and the first region 1272. The exposed portion of the second staircase structure 760 in the second region 1274 and the exposed dividing wall 865 are collectively referred to as an exposed structure 1276. The block mask may be used in a subsequent process to remove a portion of the second barrier layer 1166 disposed on the exposed structure 1276.

[0089] The block mask 1270 may include any suitable photoresist. In some embodiments, the block mask 1270 may also include a hard mask, such as silicon oxide, silicon nitride, TEOS, amorphous or polycrystalline silicon, spin-on glass, or any combination thereof. In some embodiments, the block mask 1270 may also include a carbon-based polymer material, a silicon-containing anti-reflective coating (SiARC), or the like. The block mask 1270 may be formed through lithography, and a pattern may be transferred from a reticle to the block mask 1270. In some embodiments, forming the block mask 1270 may also include dry etching (e.g., reactive ion etching), wet etching, or a combination thereof.

[0090] Note that the second barrier layer 1166 and the first barrier layer 1064 are omitted from the top-down view of FIG. 12 for clarity.

[0091] 4, in process step S435, the second barrier layer may be removed from structures exposed by the block mask. A top-down view and various cross-sectional views of an exemplary 3D memory structure 1300 in accordance with process step S435 are shown in FIGS. 13A-13D.

[0092] FIG. 13B illustrates a cross-sectional view along line BB′ of FIG. 13A in the second region 1274 of the second staircase structure 760. FIG. 13C illustrates a cross-sectional view along line CC′ of FIG. 13A in the first region 1272 of the second staircase structure 760. As previously described, the block mask 1270 covers the first region 1272 of the second staircase structure 760. The block mask exposes an exposed structure 1276, including the second region 1274 of the second staircase structure 760 and the dividing wall 865 of the dividing region 863. Thus, the second barrier layer 1166 can be removed from the exposed structure 1276, for example, in the second region 1274 of the second staircase structure 760. Similarly, the second barrier layer 1166 can also be removed from the dividing wall 865 of the dividing region 863. That is, a first portion of the second barrier layer 1166 (or dielectric material) may be removed from the dividing wall 865. And a second portion of the second barrier layer 1166 may be removed from the second region 1274 of the second staircase structure 760. As such, the second barrier layer 1166 may be formed in the first region of the staircase structure.

[0093] In some embodiments, the second barrier layer 1166 may be selectively removed with respect to the first barrier layer 1064. For example, the second barrier layer 1166 may be etched at a rate significantly faster than the etch rate of the first barrier layer 1064. The second barrier layer 1166 may be removed by using any suitable etching process, for example, a dry etch, a wet etch, or a combination thereof. In some embodiments, the second barrier layer 1166 may be etched by RIE.

[0094] FIG. 13D illustrates a cross-sectional view along line AA′ in FIG. 13A across the exposed structure 1276 and the first region 1272 of the second stair-like structure 760. Due to the topology between the dividing wall 865 and the second stair-like step 762, in some embodiments, the second barrier layer 1166 and the first barrier layer 1064 can cover the sidewalls of the dividing wall 865. See also FIG. 9. In some embodiments, in process step S435, the second barrier layer 1166 on the sidewalls of the dividing wall 865 can also be removed, stopping on the first barrier layer 1064 underneath. In this example, the removal of the second barrier layer 1166 from the sidewalls of the dividing wall 865 can be performed by an isotropic etching process (e.g., isotropic RIE, wet etching, etc.), and the second barrier layer 1166 can be etched laterally in addition to etching vertically.

[0095] As the storage capacity of the 3D NAND memory increases, the number of first dielectric layers 452 and second dielectric layers 454 also increases. As a result, the topology between the dividing wall 865 and the second stair-like structure 760 also increases. By using the block mask 1270, the second barrier layer 1166 is etched isotropically (i.e., vertically and laterally), which can significantly reduce the etching time and the risk of overetching on the outer surface.

[0096] After removing the second barrier layer 1166 from the exposed structure 1276, the block mask 1270 (in FIG. 12) may be stripped away. As shown in FIGs. 13A-13D, after completing process step S435, the second barrier layer 1166 covers the first region 1272 of the second stepped structure 760, and the second barrier layer 1166 may be removed from other regions.

[0097] 4, in process step S440, an insulating layer can be disposed on the second stair-like structure and the dividing wall of the alternating dielectric stack. Cross-sectional views of an exemplary 3D memory structure 1400 along lines AA', BB', and CC' (see FIG. 13A) according to process step S440 are shown in FIGS. 14A-14C, respectively.

[0098] 14A-14C, the 3D memory structure 1400 includes an insulating layer 1480 disposed on the second barrier layer 1166 and the first barrier layer 1064 above the second staircase structure 760 and the dividing wall 865 of the alternating dielectric stack 450. The insulating layer 1480 covers at least the top surface (the surface away from the substrate 330) and the sidewalls of the second barrier layer 1166. The insulating layer 1480 can protect the second barrier layer 1166 from being etched in a subsequent process when the second dielectric layer 454 is removed.

[0099] The insulating layer 1480 may include any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on glass, a low-k dielectric material such as carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), etc. The insulating layer 1480 may be disposed by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the insulating layer 1480 may have a planar top surface over the second staircase structure 760 and the dividing wall 865 of the alternating dielectric stack 450. The insulating layer 1480 may be planarized using CMP.

[0100] 4, in process step S445, gate line slit (GLS) openings can be formed in the dividing walls, the GLS openings vertically penetrating the alternating dielectric stacks. Top-down and cross-sectional views of an exemplary 3D memory structure 1500 in accordance with process step S445 are shown in FIGS. 15A-B.

[0101] 15A , the 3D memory structure 1500 comprises a GLS opening 1582 extending laterally along the WL direction parallel to the second stepped structure 760. In some embodiments, the GLS opening 1582 may be formed in the dividing wall 865 of the alternating dielectric stack 450.

[0102] 15B illustrates a cross-sectional view along line AA′ in FIG. 15A. The GLS openings 1582 penetrate the insulating layer 1480 and the dividing walls 865 of the alternating dielectric stack 450 in the z-direction perpendicular to the substrate 330. In some embodiments, the GLS openings 1582 penetrate further into the substrate 330. The GLS openings 1582 may be formed by lithography and etching processes. The etching process may include any suitable dry etching, wet etching, or a combination thereof.

[0103] As previously described, the second barrier layer 1166 may be removed from the exposed structure 1276 in process step S435. Thus, the GLS opening 1582 is far (or distant) from the second barrier layer 1166 in the BL direction (also referred to as the WL direction or the third direction, which is parallel to the substrate 330 and perpendicular to the second direction), and the second barrier layer 1166 is disposed in the first region 1272 on the second stair-like step 762. As a result, the second barrier layer 1166 may be covered by the insulating layer 1480 from the top and sides, and is not exposed by the GLS opening 1582.

[0104] 4, in process step S450, the second dielectric layer (including the dividing wall and the second stepped structure) in the alternating dielectric stack can be removed through the GLS opening. Cross-sectional views of the exemplary 3D memory structure 1600 along lines AA', BB', and CC' (see FIG. 15A) according to process step S450 are shown in FIGS. 16A-16C, respectively.

[0105] 16A-16C, the 3D memory structure 1600 includes a lateral tunnel, where the second dielectric layer 454 of the alternating dielectric stack 450 can be selectively removed with respect to the first dielectric layer 452 and the first barrier layer 1064. The lateral tunnel 1684 can extend laterally between adjacent first dielectric layers 452. Note that the term "lateral / side / outer" as used herein refers to a plane parallel to the top surface 330f of the substrate 330.

[0106] As previously described, the second dielectric layer 454 (see FIG. 15B ) in the alternating dielectric stack 450, also referred to as a sacrificial layer, can be selectively removed from between the first dielectric layers 452. In other words, the etching process of the second dielectric layer 454 can be stopped on the first dielectric layer 452. The second dielectric layer 454 can be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in the dry / wet etching can move vertically and laterally from the GLS opening 1582. For example, the plasma and / or chemicals can move along the WL direction and / or BL direction from the GLS opening 1582 toward the second staircase structure 760 (see also FIG. 15A ). In some embodiments, the second dielectric layer 454 can be silicon nitride and the first dielectric layer 452 can be silicon oxide. In this example, the second dielectric layer 454 may be removed by RIE using one or more etchants such as CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer 454 may be removed using a wet etch such as phosphoric acid.

[0107] When the etching process used to remove the second dielectric layer 454 (e.g., silicon nitride) is selective to the first barrier layer 1064 (e.g., silicon oxide), the first barrier layer 1064 disposed on the second staircase structure 760 can also function as an etch stop layer in addition to the first dielectric layer 452 (e.g., silicon oxide). For example, when the second barrier layer 1166 and the second dielectric layer 454 can both be removed in process step S450 (i.e., both include silicon nitride), the first barrier layer 1064 covering the top surface (i.e., outer surface) and vertical surface (i.e., sidewall) of the second staircase step 762 can protect the second barrier layer 1166 from being etched from the lateral tunnel 1684 below it (see FIG. 16C). The portion of the first barrier layer 1064 formed on the outer surface of the staircase structure can function as an etch stop layer for the etching process in the z-direction perpendicular to the substrate 330. The portions of the first barrier layer 1064 formed on the vertical sidewalls of the staircase structure 760 may act as an etch stop layer for etching processes in the WL and BL directions parallel to the front surface 330 f of the substrate 330 .

[0108] As previously described, by using the block mask 1270 in process steps S430 and S435, the second barrier layer 1166 can be removed from the exposed structures 1276, thereby moving away or away from the GLS opening 1582. The second barrier layer 1166 can be covered and protected by the insulating layer 1480 near the dividing wall 865. Thus, the etching chemistry traveling through the GLS opening 1582 does not attack the second barrier layer 1166 (see FIG. 16A ) and does not form extra lateral tunnels above the first barrier layer 1064.

[0109] 4, in process step S455, a first conductive material can be disposed inside the lateral tunnel through the GLS opening to form a conductive layer between the first dielectric layers. Cross-sectional views of an example 3D memory structure 1700 along lines AA', BB', and CC' (see FIG. 15A) according to process step S455 are shown in FIGS. 17A-17C, respectively.

[0110] 17A-17C, the 3D memory structure 1700 includes a conductive layer 1786 disposed inside the lateral tunnel 1684 (in FIGS. 16A-16C) through the GLS opening 1582. The conductive layer 1786 can be disposed between adjacent first dielectric layers 452, and the conductive layer 1786 and the first dielectric layer 452 can form a film stack 335 in which the conductive layers and dielectric layers are alternated (as in FIG. 3).

[0111] In some embodiments, the conductive layer 1786 may be formed by filling the lateral tunnel with a first conductive material. The first conductive material of the conductive layer 1786 may include a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the first conductive material of the conductive layer 1786 may also include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any other suitable material, and / or combination thereof. In some embodiments, the polycrystalline material may be incorporated with any suitable type of dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the first conductive material may also be an amorphous semiconductor, such as amorphous silicon. In some embodiments, the first conductive material may be disposed using a suitable deposition method, such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the conductive layer 1786 (or the first conductive material) comprises tungsten (W) deposited by CVD.

[0112] In some embodiments, a gate dielectric layer 1785 may be disposed inside the lateral tunnel 1684 (in FIGS. 16A-16C ) before disposing the conductive layer 1786. In some embodiments, the gate dielectric layer 1785 surrounds the conductive layer 1786. For example, in the z-direction, the gate dielectric layer 1785 is disposed between the first dielectric layer 452 and the conductive layer 1786. In the WL or BL direction, the gate dielectric layer 1785 is disposed between the conductive layer 1786 and the first barrier layer 1064. The gate dielectric layer 1785 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 1785 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer 1785 may be disposed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD.

[0113] In some embodiments, an etching and cleaning process can be used to remove excess first conductor material on the sidewalls of the GLS opening 1582. As such, each conductor layer 1786 of the film stack 335 can be electrically isolated from one another. In some embodiments, excess first conductor material above the insulating layer 1480 can also be removed, for example, by CMP.

[0114] After completing process step S455, the second dielectric layer 454 may be replaced with a conductive layer 1786 and the alternating conductor stack 450 becomes a film stack 335 of alternating conductive and dielectric layers. Thus, the second staircase structure 760 becomes a third staircase structure 1760 and the second staircase step 762 becomes a third staircase step 1762.

[0115] However, if the block mask 1270 is not used and the second barrier layer 1166 is not removed near the GLS opening 1582 (see FIGS. 21A - 21C), if the second barrier layer 1166 and the second dielectric layer 454 are made of the same material, for example silicon nitride, the second barrier layer 1166 can be removed together with the second dielectric layer 454 in process step S450. An additional tunnel 2184 can be formed under the insulating layer 1480. In process step S455, an additional conductor layer 2186 can also be formed under the insulating layer 1480. The additional conductor layer 2186 can cause a circuit shot and / or increase leakage. Furthermore, in order to completely fill the additional tunnel 2184, the thickness "t" of the additional conductor layer 2186 needs to be at least the thickness of the second barrier layer 1166. However, if the width of the GLS opening 1582 is not wide enough, for example, if it has a width w < t, the GLS opening 1582 can be filled and pitch - off can occur before the additional tunnel 2184 can be completely filled. The resulting seam of the additional conductor layer 2186 can cause structural problems (such as a decrease in mechanical strength, attracting defects and chemicals, etc.), thereby reducing the product yield. Therefore, removing the second barrier layer 1166 by using the block mask 1270 can improve the manufacturing process for 3D NAND flash memory.

[0116] Referring to FIG. 4, it can be seen that in process step S460, a GLS filler can be disposed inside the GLS opening to form GLS. Top - down views and cross - sectional views of an exemplary 3D memory structure 1800 according to process step S460 are shown in FIGS. 18A - 18B.

[0117] 18A and 18B (along line AA′), the 3D memory structure 1800 includes a gate line slit (GLS) 216 (similar to the slit structure 216 of FIGS. 2-3) between adjacent third staircase structures 1760. The GLS 216 may be formed in the dividing wall 865 of the dividing region 863. The GLS 216 extends laterally along the WL direction.

[0118] The GLS 216 penetrates the insulating layer 1480, the first barrier layer 1064, and the film stack 335, which has alternating conductive and dielectric layers in the z-direction. In some embodiments, the GLS 216 can penetrate further into the substrate 330.

[0119] The GLS 216 includes a GLS filler 1888 disposed within the GLS opening 1582 (in FIG. 17A ). The GLS filler 1888 can include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus doped silicon oxide, carbon doped oxide (CDO or SiOC or SiOC:H), fluorine doped oxide (SiOF), or any combination thereof. The GLS filler 1888 can be deposited by using, for example, ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable film deposition technique.

[0120] In some embodiments, the GLS fill 1888 outside the GLS opening 1582 may be removed by etching (e.g., RIE) or CMP. As such, the GLS 216 may be flush with the insulating layer 1480.

[0121] 2 and 3, the GLS 216 can divide a storage unit (e.g., memory block 103) into sub-storage units (e.g., memory fingers 218), which can independently perform read and / or program operations. As such, read and program speeds can be improved for 3D NAND memory.

[0122] 4, in process step S465, a contact opening can be formed to expose a portion of one of the conductive layers of the third stepped structure. Top-down and cross-sectional views of an exemplary 3D memory structure 1900 according to process step S465 are shown in FIGS. 19A-B.

[0123] 19A, the 3D memory structure 1900 includes contact openings 1990 in the first region 1272 of the third staircase structure 1760. As shown in the cross-sectional view along line CC′ in FIG. 19B, the contact openings 1990 penetrate the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z-direction and expose a portion of the conductive layer 1786. In some embodiments, each contact opening 1990 exposes a portion of one of the conductive layers 1786 of the third staircase structure 1760.

[0124] In some embodiments, forming the contact opening 1990 includes etching the insulating layer 1480 selectively with respect to the second barrier layer 1166, which can act as an etch stop. The second barrier layer 1166 and the first barrier layer 1064 can then be etched to expose a portion of the conductive layer 1786 inside the contact opening 1990.

[0125] In some embodiments, photoresist or polymeric material may be used as a mask layer for etching the contact openings 1990. Due to the topology of the staircase structure, the depth of the contact openings 1990 depends on the arrangement of the staircase steps. The contact openings 1990 for the lower staircase steps may be much deeper than the contact openings 1990 for the upper staircase steps. Thus, the contact openings 1990 for the third staircase step 1762 closer to the substrate 330 require a longer etching time than the contact openings 1990 away from the substrate 330. A selective etching process may be used such that the etching rate of the insulating layer 1480 is much higher than the second barrier layer 1166. In other words, in the etching process for the contact openings 1990, the second barrier layer 1166 may act as an etch stop layer to protect the underlying structure until all the contact openings 1990 are formed on the second barrier layer 1166 for the third staircase structure 1760. The second barrier layer 1166 and the portion of the first barrier layer 1064 inside the contact opening 1990 may then be removed.

[0126] In some embodiments, when a gate dielectric layer is disposed prior to disposing the conductive layer 1786, the etch also includes removing the gate dielectric layer inside the contact opening 1990.

[0127] The etching process for the contact opening 1990 may include dry etching, wet etching, and / or combinations thereof. When the insulating layer 1480 is silicon oxide and the second barrier layer 1166 is silicon nitride, anisotropic RIE may be used with chemical etchants such as CF4, CHF3, C2F6, C3F6, and / or any combinations thereof when etching silicon oxide, and RIE may be used with chemical etchants such as O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof when etching silicon nitride. The etching processes and chemistries listed here are examples only and should not be limited.

[0128] The second barrier layer 1166 can function as an etch stop during the etching process for the contact opening 1990, so that the second barrier layer 1166 can have a thickness sufficient to protect the underlying structure. For example, the second barrier layer 1166 can have a thickness in the range of 10 nm to 500 nm, more specifically, 50 nm to 500 nm. By using a block mask 1270, as previously described with respect to FIGS. 16A-16C, 17A-17C, and 21A-21B, the second barrier layer 1166 can be pulled back from the GLS opening 1582. The second barrier layer 1166 can be surrounded by the insulating layer 1480 and the first barrier layer 1064 upon removal of the second dielectric layer 454 and formation of the lateral tunnel 1684. Thereby, the additional tunnel 2184 and the additional conductive layer 2186 can be avoided. Thus, the thickness of the second barrier layer 1166 can be optimized for the etching process of the contact opening 1990 without limitations from the additional tunnel 2184 and / or the additional conductive layer 2186. That is, the thickness of the second barrier layer 1166 can be increased to provide a sufficient etch stop function in forming the contact opening 1990 on the third staircase structure 1760.

[0129] 4, in process step S470, a second conductive material can be disposed inside the contact opening to form a contact structure to the third stepped structure. A top-down view of an exemplary 3D memory structure 2000 according to process step S470 is shown in FIG. 20A. FIGS. 20B-20D show cross-sectional views of the 3D memory structure 2000 along lines CC', AA', and BB' in FIG. 20A.

[0130] As shown in FIGS. 20A and 20B, the 3D memory structure 2000 comprises a contact structure 214 in the first region 1272 of the third stepped structure 1760. The contact structure 214 (similar to that shown in FIGS. 2-3) includes a second conductive material 1992 disposed inside a contact opening 1990 (in FIGS. 19A-19B). The contact structure 214 penetrates the insulating layer 1480, the second barrier layer 1166, and the first barrier layer 1064 in the z-direction. The contact structure 214 can contact one of the conductive layers 1786 of the film stack 335 through the third stepped structure 1760. In some embodiments, when the gate dielectric layer 1785 is disposed before disposing the conductive layer 1786, the contact structure 214 also penetrates the gate dielectric layer 1785.

[0131] In some embodiments, the second conductive material 1992 inside the contact opening 1990 can be in direct contact with the conductive layer 1072. The second conductive material 1992 can include any suitable conductive material, for example, a metal or metal compound, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The metal or metal compound can be disposed by using a suitable deposition method, such as CVD, PVD, ALD, sputtering, evaporation, and the like. The second conductive material 1992 can be WSi x , CoSi x , NiSi x , or AlSi xand the like. The metal silicide material may be formed by disposing a metal layer directly on the polysilicon layer inside the contact opening 1990 and then going through a thermal annealing process to subsequently remove the unreacted metal. In some embodiments, the second conductive material 1992 comprises a combination of TiN / W / TiN deposited by CVD.

[0132] Formation of the contact structures 214 may also include a planarization process, such as CMP, to remove excess second conductor material 1992 over the insulating layer 1480. As shown in FIG. 20B, the contact structures 214 may be coplanar with the insulating layer 1480.

[0133] The present disclosure also provides a 3D memory device manufactured using the methods described above.

[0134] 20A-20D, the 3D memory structure 2000 includes a film stack 335 having alternating conductive and dielectric layers. The film stack 335 includes a conductive layer 1786 and a first dielectric layer 452 arranged on a substrate 330 in an alternating z-direction perpendicular to the substrate 330. In some embodiments, the first dielectric layer 452 includes silicon oxide and the conductive layer includes tungsten.

[0135] The third staircase structure 1760 (also referred to as a staircase structure) may be disposed in the film stack 335 in the staircase region 210. The third staircase structure 1760 extends in the WL direction and includes third staircase steps 1762 (also referred to as staircase steps) that run up and down along the WL direction (i.e., facing the WL direction). The third staircase steps 1762, or "staircase layers", refer to layer stacks that have the same lateral dimensions in a surface parallel to the substrate surface 330f. Each of the third staircase steps terminates at a shorter length than the third staircase step below it.

[0136] The film stack 335 may include a dividing wall 865 in the dividing region 863. The dividing wall 865 extends parallel to the third stair-like structure 1760 in the WL direction. The dividing wall 865 is adjacent to the third stair-like structure 1760.

[0137] The 3D memory structure 2000 also includes a first barrier layer 1064 and a second barrier layer 1166. The first barrier layer 1064 may be disposed on the third staircase structure 1760 and cover the top surface and sidewall of the third staircase step 1762. The second barrier layer 1166, which is different from the first barrier layer 1064, may be disposed on the first barrier layer 1064 in a first region 1272 of the third staircase structure 1760, the first region 1272 being disposed at the center of the third staircase structure 1760. The first region 1272 extends along the WL direction. In other words, the second barrier layer 1166 may be disposed at the center of the third staircase structure 1760 and cover the central portion of the third staircase step 1762. The second barrier layer 1166 may be removed from the second region 1274 of the third staircase structure 1760. The second region 1274, which extends along the WL direction, is adjacent to the dividing wall 865. In some embodiments, the second region 1274 is disposed on each side of the first region 1272. In some embodiments, the first barrier layer includes silicon oxide and the second barrier layer includes silicon nitride. In some embodiments, the first barrier layer 1064 has a thickness in the range of 10 nm to 100 nm and the second barrier layer 1166 has a thickness in the range of 50 nm to 500 nm.

[0138] The 3D memory structure 2000 also includes a GLS 216 that penetrates vertically through the film stack 335 in the z-direction. In some embodiments, the GLS 216 penetrates further into the substrate 330. The GLS 216 extends parallel to the WL direction and parallel to the third staircase structure 1760. The GLS 216 extends parallel to the first region 1272 and the second region 1274 of the third staircase structure 1760. In some embodiments, the second barrier layer 1166 is remote from the GLS 216 in the BL direction. The GLS 216 can include a GLS filler 1888, which can include any suitable insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc.

[0139] The 3D memory structure 2000 also includes an insulating layer 1480 disposed on the first barrier layer 1064 and the second barrier layer 1166 above the third staircase structure 1760 and the dividing wall 865 of the film stack 335. In some embodiments, the GLS 216 may be coplanar with the insulating layer 1480. The GLS 216 is configured to divide the memory block into sub-storage units (e.g., memory fingers).

[0140] The 3D memory structure 2000 also includes a contact structure 214 formed on the third staircase step 1762 of the third staircase structure 1760, which can provide an electrical connection to a conductive layer 1786 of the film stack 335 of alternating conductive and dielectric layers. In some embodiments, the contact structure 214 can be disposed in the first region 1272 of the staircase structure. The contact structure 214 penetrates vertically through the insulating layer, the second dielectric layer, and the first dielectric layer to contact a portion of one of the conductive layers 1786 of the film stack 335.

[0141] In some embodiments, the conductive layer 1786 can be electrically connected to a bottom select gate 332 (of FIG. 3), a control gate or word line 333, or a top select gate 334 of a 3D memory device. In some embodiments, the 3D memory device can include memory strings 212 (see FIGS. 2-3) that run vertically through the film stack 335 in the z-direction, and the intersections between the control gates 333 and the memory strings 212 can form memory cells 340 as shown in FIGS. 2-3.

[0142] FIG. 22 illustrates a block diagram of an exemplary system S1 having a storage system 10 according to some embodiments of the present disclosure. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system 10 (also referred to as a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereinafter simply "memory chip") may be a NAND chip (i.e., "flash", "NAND flash" or "NAND"). Storage system 10 may communicate with host computer 15 through a memory controller 20, which may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 may be managed by memory controller 20 via a memory channel 30.

[0143] In some embodiments, the host computer 15 may comprise a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host computer 15 sends data to be stored in the NAND storage system or storage system 10, or retrieves data by reading storage system 10.

[0144] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chips 25. To perform these tasks, the controller executes firmware 21, which may be executed by one or more processors 22 (e.g., microcontroller units, CPUs) within the controller 20. For example, the controller 20 executes firmware 21 to map logical addresses (i.e., addresses utilized by the host that are associated with host data) to physical addresses (i.e., actual locations where data is stored) within the memory chips 25. The controller 20 also executes firmware 21 to manage defective memory blocks within the memory chips 25, which may remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The controller 20 can also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.), which may be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can also perform error recovery through an error correction code (ECC) engine 29. ECC can be used to detect and correct raw bit errors that occur within each memory chip 25 .

[0145] The memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 according to a chip enable signal.

[0146] In some embodiments, each memory chip 25 of FIG. 22 can include one or more memory dies 2201, where each memory die 2201 can include a 3D NAND memory 100 as shown in FIGS. 1-3. In some embodiments, each of the one or more memory dies 2201 can include a 3D memory device 2000 as shown in FIGS. 20A-20D, which can be manufactured using the method 400 of FIG. 4. In some embodiments, the memory controller 20 can be configured to control the operation of a three dimensional memory device (e.g., a 3D NAND memory 100), where the controller is in communication with the three dimensional memory device.

[0147] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices and included in the same package, such as, for example, a universal flash storage (UFS) package or an eMMC package. That is, the storage system 10 can be implemented and packaged in different types of end electronic products. In one example, as shown in FIG. 23A, the memory controller 20 and a single memory chip 25 can be integrated into a memory card 26. The memory card 26 can include a PC card (PCMCIA, PC Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, and the like. The memory card 26 can further include a memory card connector 24 that couples the memory card 26 with a host (e.g., the host computer 15 of FIG. 22). In another example, as shown in FIG. 23B, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may further include an SSD connector 28 that couples the SSD 27 to a host (eg, the host computer 15 of FIG. 22).

[0148] FIG. 24 illustrates a schematic diagram of a memory die 2201 according to some embodiments of the present disclosure. In one example, the memory die 2201 may include the 3D memory device 100 in FIG. 1 having the 3D memory array structure 300 shown in FIG. 3. In this example, the memory die 2201 may further include the 3D memory structure 2000 shown in FIGS. 20A-20D. In some embodiments, the memory die 2201 includes one or more memory blocks 103 (e.g., 103-1, 103-2). Each memory block 103 includes a memory string 212. Each memory string 212 includes memory cells 340. The memory cells 340 that share the same word line form a memory page 432. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end, which is controlled by a bottom select gate (BSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the bottom select transistor 332-T may be connected to an array common source (ACS) 430. The ACS 430 may be shared by the memory strings 212 within an entire memory block, and is also referred to as a common source line.

[0149] The memory die 2201 may also include peripheral circuits 2402, which include numerous digital, analog, and / or mixed-signal circuits that support the functionality of the memory blocks 103, such as page buffers / sense amplifiers 50, row decoders / word line drivers 40, column decoders / bit line drivers 52, control circuits 70, voltage generators 65, and input / output buffers 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to one skilled in the art.

[0150] The memory blocks 103 may be coupled to the row decoder / word line driver 40 via word lines ("WL") 333, bottom select gates ("BSG") 332 and top select gates ("TSG") 334. The memory blocks 103 may be coupled to the page buffer / sense amplifier 50 via bit lines ("BL") 341. The row decoder / word line driver 40 may select one of the memory blocks 103 on the memory die 2201 in response to an X-path control signal provided by the control circuit 70. The row decoder / word line driver 40 may transfer a voltage provided by the voltage generator 65 to the word lines in response to the X-path control signal. During read and program operations, the row decoder / word line driver 40 may select a read voltage V in accordance with the X-path control signal received from the control circuit 70. read and the program voltage V pgm to the selected word line, and the pass voltage V pass can be transferred to the unselected word lines.

[0151] The column decoder / bit line driver 52 generates an inhibit voltage V inhibitto the unselected bit lines and connect the selected bit lines to ground. In other words, the column decoder / bit line driver 52 may be configured to select or deselect one or more memory strings 212 according to the Y-path control signal from the control circuit 70. The page buffer / sense amplifier 50 may be configured to read and program (write) data to and from the memory block 103 according to the control signal Y-path control from the control circuit 70. For example, the page buffer / sense amplifier 50 may store a page of data to be programmed in one memory page 432. In another example, the page buffer / sense amplifier 50 may perform a verify operation to ensure that the data has been properly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sense amplifier 50 may sense the current flowing through the bit lines 341, which reflects the logic state (i.e., data) of the memory cells 340, and amplify the small signal by a measurable factor.

[0152] Input / output buffer 55 can transfer I / O data to and from page buffer / sense amplifier 50 as well as addresses ADDR or commands CMD to control circuitry 70. In some embodiments, input / output buffer 55 can serve as an interface between memory controller 20 (FIG. 1) and memory die 2201 on memory chip 25.

[0153] The control circuit 70 can control the page buffer / sense amplifier 50 and the row decoder / word line driver 40 in response to the command CMD forwarded by the input / output buffer 55. During a program operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to program a selected memory cell. During a read operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that can be used to identify a selected memory cell in the memory block 103. The row address X-ADDR can include a page index, a block index, and a plane index to identify the memory page 432, the memory block 103, and the memory plane 101 (in the case of FIG. 1), respectively. The column address Y-ADDR can identify a byte or word in the data of the memory page 432.

[0154] The voltage generator 65 can generate voltages to be supplied to the word lines and bit lines under the control of the control circuit 70. The voltage generated by the voltage generator 65 is a read voltage V read , program voltage V pgm , pass voltage V pass , inhibit voltage V inhibit etc.

[0155] In summary, the present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate, and forming a step structure and a divider wall in the alternating dielectric stack. The step structure and the divider wall extend in a second direction parallel to the substrate, and the divider wall is adjacent to the step structure. The method also includes forming, in sequence, a first barrier layer on the step structure and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the divider wall. The GLS opening penetrates the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction.

[0156] The present disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having alternating conductive layers and first dielectric layers on a substrate in a first direction perpendicular to the substrate. The 3D memory device also includes a step-like structure disposed in the film stack and extending in a second direction parallel to the substrate, and a dividing wall extending in the second direction and disposed adjacent to the step-like structure. The three-dimensional memory device further includes a gate line slit (GLS) disposed in the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction. The 3D memory device also includes a first barrier layer disposed on the step-like structure, and a second barrier layer disposed on the first barrier layer in a first region of the step-like structure, the second barrier layer being different from the first barrier layer and being far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction.

[0157] The present disclosure further provides a memory storage system including a three-dimensional memory device, the three-dimensional memory device including the features described above.

[0158] In the present disclosure, the second barrier layer (e.g., silicon nitride) can be used as an etch stop layer to form a contact opening for the stepped structure. By using a block mask, a portion of the second barrier layer disposed around the gate line slit can be removed before removing the second dielectric layer (e.g., silicon nitride) in the alternating dielectric stack. After pulling back the second barrier layer from the gate line slit, the second barrier layer is not replaced by a conductive layer, thereby avoiding potential conductive paths. The thickness of the second barrier layer is also not limited by the replacement process. Therefore, the performance and reliability of the 3D memory device can be improved.

[0159] The present disclosure also provides a three-dimensional (3D) memory die including a 3D memory device and peripheral circuits. The 3D memory device includes a film stack having alternating conductive layers and a first dielectric layer on a substrate in a first direction perpendicular to the substrate, a step-like structure disposed in the film stack and extending in a second direction parallel to the substrate, and a partition wall extending in the second direction and disposed adjacent to the step-like structure. The 3D memory device also includes a gate line slit (GLS) disposed in the partition wall, the GLS penetrating the film stack in the first direction and extending in the second direction, a first barrier layer disposed on the step-like structure, and a second barrier layer disposed on the first barrier layer in a first region of the step-like structure. The second barrier layer, different from the first barrier layer, is distant from the GLS in a third direction parallel to the substrate and perpendicular to the second direction. The peripheral circuits are coupled to the 3D memory device and configured to support operation of the 3D memory device. For example, the peripheral circuits can include functional devices such as page buffer / sense amplifiers 50, column decoders / bit line drivers 52, I / O buffers 55, voltage generators 65, control circuits 70, row decoders 40, etc.

[0160] The foregoing description of specific embodiments will fully reveal the general nature of the present disclosure so that those skilled in the art may easily modify and / or adapt such specific embodiments to various applications without departing from the general concept of the present disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It will be understood that the phrases or terms used herein are for purposes of description and not for purposes of limitation, and thus should be interpreted by those skilled in the art in light of the disclosure and guidance.

[0161] The embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating implementation forms of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0162] The Summary and Abstract sections may define one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and thus are not intended to limit the disclosure and the appended claims in any way.

[0163] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0164] S1 System 10 Storage Systems 15 Host Computer 20 Memory Controller 21 Firmware 22 processors 23 Memory 24 Memory card connector 25 Memory Chips 25-1, 25-2, 25-3, ..., 25-n Semiconductor memory chips 26 Memory Card 27 SSD 28 SSD connector 30 memory channels 30-1, 30-2, 30-3, ..., 30-n memory channels 40 Row Decoder / Word Line Driver 50 Page Buffer / Sense Amplifier 52 Column Decoder / Bit Line Driver 55 Input / Output Buffer, I / O Buffer 65 Voltage Generator 70 Control circuit 100 Three-dimensional (3D) memory devices, 3D NAND memory 101 Memory Plane 103 Memory Blocks 105 Surrounding Areas 108 areas 210 Stepped area 211 Channel structure region 212 Memory String 214 Contact structure 216 Slit structure (also called gate line slit) 216-1 and 216-2 Slit Structure 218 Memory Finger 222 Dummy memory string 224 Memory Slices 300 Memory Array Structure 330 Substrate 330f front 331 Insulating film 332 Bottom Select Gate (BSG) 332-T Bottom Select Transistor 333 Control Gate 333 Word Line 333-1, 333-2, 333-3 Control gate 334 Top Select Gate (TSG) 334-T Top Select Transistor 335 Film Stack 336 Channel Hall 337 Memory Film 338 Channel Layer 339 Core-filled film 340 memory cells 340-1, 340-2, and 340-3 memory cells 341 Bit Line (BL) 343 Metal Interconnect Wire 344 doped source line region 400 ways 432 memory pages 450 alternating dielectric stack 452 First Dielectric Layer 454 Second Dielectric Layer 500 3D memory structure 600 3D memory structure 656 First Step Structure 658 First Step 700 3D memory structure 760 Second Staircase 762 Second Staircase 863 Split area 865 dividing wall 1000 3D Memory Structure 1064 First Barrier Layer 1072 Conductive layer 1100 3D memory structure 1166 Second Barrier Layer 1200 3D memory structure 1270 Block Mask 1272 First Region 1274 Second Area 1276 Exposed structure 1300 3D memory structure 1400 3D memory structure 1480 Insulating layer 1500 3D memory structure 1582 Gate line slit (GLS) opening 1600 3D memory structure 1684 and 2184 Side Tunnels 1700 3D memory structure 1760 Third Step Structure 1762 Third Step 1785 Gate Dielectric Layer 1786 Conductive layer 1800 3D memory structure 1888 GLS Filler 1900 3D memory structure 1990 Contact opening 1992 Second conductive material 2000 3D Memory Structure 2184 Tunnel 2186 Conductive layer 2201 Memory Die

Claims

1. 1. A method for forming a three dimensional memory device, comprising: providing an alternating dielectric stack, the alternating dielectric stack including first and second dielectric layers alternately stacked on a substrate in a first direction perpendicular to the substrate; forming a step structure and a divider wall in the alternating dielectric stack, the step structure and the divider wall extending in a second direction parallel to the substrate, the divider wall adjacent to the step structure; forming, in sequence, a first barrier layer and a second barrier layer different from the first barrier layer on the stepped structure; forming gate line slit (GLS) openings in the dividing walls, the GLS openings extending through the alternating dielectric stack in the first direction and away from the second barrier layer in a third direction parallel to the substrate and perpendicular to the second direction; A method comprising:

2. 2. The method of claim 1, wherein the step of forming the first barrier layer on the staircase structure further comprises disposing the first barrier layer to cover at least sidewalls of staircase steps of the staircase structure.

3. The step of forming the second barrier layer on the stepped structure further comprises: disposing a dielectric material on the stepped structure and the dividing wall; and removing a first portion of the dielectric material disposed on the divider wall.

4. removing a second portion of the dielectric material disposed in a second region of the staircase structure adjacent to the dividing wall to form the second barrier layer in a first region of the staircase structure, the first region and the second region extending in the second direction, the first region being at a center of the staircase structure; The method of claim 3 further comprising:

5. providing a block mask to expose the dividing wall and the second region of the staircase structure adjacent to the dividing wall; The method of claim 4 further comprising:

6. disposing a GLS filler inside the GLS opening to form a GLS, the GLS filler comprising an insulating material; The method of claim 1 further comprising:

7. removing the second dielectric layer from between the first dielectric layer through the GLS opening to form a lateral tunnel; disposing a first conductive material inside the side tunnel to form a film stack including alternating conductive layers and the first dielectric layer; The method of claim 1 further comprising:

8. 8. The method of claim 7, wherein the step of removing the second dielectric layer comprises etching the second dielectric layer selectively with respect to the first dielectric layer and the first barrier layer.

9. disposing an insulating layer on the second barrier layer above the stepped structure; The method of claim 7 further comprising:

10. forming a contact structure for contacting one of the conductive layers in the film stack; The method of claim 9 further comprising:

11. 11. The method of claim 10, wherein the forming the contact structure comprises forming a contact opening through the insulating layer in the first direction to expose a portion of the one of the conductive layers.

12. 12. The method of claim 11, wherein the step of forming the contact structure further comprises disposing a second conductive material inside the contact opening to contact the exposed portion of the one of the conductive layers.

13. 12. The method of claim 11, wherein the forming the contact opening comprises etching the insulating layer selectively with respect to the second barrier layer.

14. 1. A memory device comprising:

1. A film stack comprising: a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate; a step structure extending in a second direction parallel to the substrate; a film stack including a divider wall extending in the second direction and disposed adjacent to the stepped structure; a gate line slit (GLS) disposed in the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction; a first barrier layer disposed on the stepped structure; a second barrier layer disposed on the first barrier layer in a first region of the stepped structure, the second barrier layer being different from the first barrier layer, the second barrier layer being far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction; A memory device comprising:

15. The memory device of claim 14 , wherein the first barrier layer covers at least sidewalls of the stair-like steps of the stair-like structure.

16. an insulating layer disposed on the second barrier layer so as to cover the top surface and sidewalls of the second barrier layer; The memory device of claim 14 further comprising:

17. a contact structure penetrating the insulating layer, the second barrier layer, and the first barrier layer in the first direction, the contact structure contacting one of the conductive layers of the film stack. The memory device of claim 16 further comprising:

18. The memory device of claim 14 , wherein the first region is at a center of the staircase structure and extends in the second direction.

19. 20. The memory device of claim 18, wherein the staircase structure further comprises a second region, the second region of the staircase structure extending in the second direction and positioned between the dividing wall and the first region.

20. 15. The memory device of claim 14, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

21. The memory device of claim 14 , wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

22. The memory device of claim 14 , wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

23. 15. The memory device of claim 14, wherein the GLS comprises an insulating material and is configured to divide a storage unit into sub-storage units that independently perform read or program operations.

24. 1. A memory storage system, comprising: A three-dimensional memory device, comprising:

1. A film stack comprising: a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate; a step structure extending in a second direction parallel to the substrate; a film stack including a divider wall extending in the second direction and disposed adjacent to the stepped structure; a gate line slit (GLS) disposed in the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction; a first barrier layer disposed on the stepped structure; a second barrier layer disposed on the first barrier layer in a first region of the stepped structure, the second barrier layer being different from the first barrier layer, the second barrier layer being far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction; a memory controller configured to control operation of the three-dimensional memory device, the controller coupled to the three-dimensional memory device; A memory storage system comprising:

25. 25. The memory storage system of claim 24, wherein the first barrier layer covers at least sidewalls of the stair-like steps of the stair-like structure.

26. an insulating layer disposed on the second barrier layer so as to cover the top surface and sidewalls of the second barrier layer; 25. The memory storage system of claim 24, further comprising:

27. a contact structure penetrating the insulating layer, the second barrier layer, and the first barrier layer in the first direction, the contact structure contacting one of the conductive layers of the film stack.

27. The memory storage system of claim 26, further comprising:

28. 25. The memory storage system of claim 24, wherein the first region is at the center of the staircase structure and extends in the second direction.

29. 30. The memory storage system of claim 28, wherein the staircase structure further comprises a second region, the second region of the staircase structure extending in the second direction and positioned between the dividing wall and the first region.

30. 25. The memory storage system of claim 24, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

31. 25. The memory storage system of claim 24, wherein the first barrier layer has a thickness in the range of 10 nm to 100 nm.

32. 25. The memory storage system of claim 24, wherein the second barrier layer has a thickness in the range of 50 nm to 500 nm.

33. 25. The memory storage system of claim 24, wherein the GLS comprises an insulating material and is configured to divide a storage unit into sub-storage units that independently perform read or program operations.

34. 1. A three dimensional (3D) memory die, comprising:

1. A 3D memory device, comprising:

1. A film stack comprising: a conductive layer and a first dielectric layer alternately stacked on a substrate in a first direction perpendicular to the substrate; a step structure extending in a second direction parallel to the substrate; a film stack including a divider wall extending in the second direction and disposed adjacent to the stepped structure; a gate line slit (GLS) disposed in the dividing wall, the GLS penetrating the film stack in the first direction and extending in the second direction; a first barrier layer disposed on the stepped structure; a second barrier layer disposed on the first barrier layer in a first region of the stepped structure, the second barrier layer being different from the first barrier layer, the second barrier layer being far from the GLS in a third direction parallel to the substrate and perpendicular to the second direction; peripheral circuitry coupled to the 3D memory device and configured to support operation of the 3D memory device; 1. A three dimensional (3D) memory die comprising:

35. 35. The 3D memory die of claim 34, wherein the first barrier layer covers at least sidewalls of stair-like steps of the stair-like structure.

36. an insulating layer disposed on the second barrier layer so as to cover the top surface and sidewalls of the second barrier layer; 35. The 3D memory die of claim 34 further comprising:

37. a contact structure penetrating the insulating layer, the second barrier layer, and the first barrier layer in the first direction, the contact structure contacting one of the conductive layers of the film stack.

37. The 3D memory die of claim 36 further comprising:

38. 35. The 3D memory die of claim 34, wherein the first region is at a center of the staircase structure and extends in the second direction.

39. 39. The 3D memory die of claim 38, wherein the staircase structure further comprises a second region, the second region of the staircase structure extending in the second direction and positioned between the dividing wall and the first region.

40. 35. The 3D memory die of claim 34, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride.

41. 35. The 3D memory die of claim 34, wherein the first barrier layer comprises a thickness in a range of 10 nm to 100 nm.

42. 35. The 3D memory die of claim 34, wherein the second barrier layer comprises a thickness in a range of 50 nm to 500 nm.

43. 35. The 3D memory die of claim 34, wherein the GLS comprises an insulating material and is configured to divide a storage unit into sub-storage units that independently perform read or program operations.

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