Gate-all-around backside power rail with diffusion blocking

Abstract

A semiconductor device and method for its manufacture are described. The method includes forming a diffusion blocking opening in a backside surface and filling it with a diffusion blocking material that acts as a planarization stop. In some embodiments, a single diffusion blocking opening is formed. In other embodiments, a mixed diffusion blocking opening is formed.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) devices that include a diffusion blocking material as a planarization stop for GAA backside power rail formation. [Background technology]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so high-speed transistors generally require large gate widths. Thus, a trade-off exists between transistor size and speed, and to address the conflicting goals of a transistor with maximum drive current and minimum size, the "fin" field-effect transistor (FinFET) was developed. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's mounting area, and are currently being applied in many integrated circuits. However, FinFETs have their own drawbacks.

[0003] As transistor device feature sizes continue to shrink to achieve increased circuit density and performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and gate-all-around (GAA) structures. The GAA device structure contains several lattice-matched channels suspended in a stack configuration and connected by source / drain regions. The GAA structure offers good electrostatic control and has been widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004] The semiconductor connection to the power rail is typically made on the front side of the cell, requiring significant cell area. In the formation of the backside power rail, the wafer thickness is reduced after the front side processing using a chemical mechanical planarization (CMP) process that does not have an etch stop layer. This creates over-polishing during CMP and some characterization issues regarding the wafer thickness. In the formation of the backside power rail, a via etch is performed through the silicon from the backside of the wafer to gain access to the source-epi. This process does not have an etch stop layer, resulting in over-etching, which creates shorts, or under-etching, which creates opens. Thus, there is a need for improved semiconductor devices and manufacturing methods. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a gate structure on a superlattice structure, the superlattice structure being on a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged in alternating stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; depositing a bottom dielectric insulating layer in the plurality of source trenches and the plurality of drain trenches; forming a resist on the gate structure; patterning the resist to form a diffusion blocking opening; depositing a diffusion blocking material in the diffusion blocking opening; planarizing the device; etching to form a plurality of via openings extending to the bottom dielectric insulating layer; and depositing a metal in the plurality of via openings and in the openings to form a plurality of vias.

[0006] Additional embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a plurality of source trenches and a plurality of drain trenches adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged in alternating stacked pairs; forming a gate structure on the top surface of the superlattice structure; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a bottom dielectric insulating layer in the source cavity and the drain cavity; forming a resist on the gate structure; patterning the resist to form at least one diffusion blocking opening; depositing a diffusion blocking material in the at least one diffusion blocking opening; rotating the semiconductor device 180 degrees; planarizing the semiconductor device; forming a backside power rail via to the bottom dielectric insulating layer in the substrate; and depositing metal in the backside power rail via.

[0007] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the accompanying drawings, in which it is to be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure, and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1 is a process flow diagram of a method according to one or more embodiments. [Figure 1B] FIG. 1 is a process flow diagram of a method according to one or more embodiments. [Figure 1C] FIG. 1 is a process flow diagram of a method according to one or more embodiments. [Figure 2A] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2B] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2C] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2D] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2E] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2F] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2G] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2H] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2I] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 2J] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3A] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3B] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3C] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3D] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3E] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3F] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3G] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3H] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3I] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 3J] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4A] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4B] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4C] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4D] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4E] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4F] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4G] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4H] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4I] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Figure 4J] 1 is a cross-sectional view of a device according to the method of one or more embodiments. [Diagram 5] FIG. 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] To facilitate understanding, the same reference numbers are used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0010] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011] As used herein and in the appended claims, the term "substrate" is used to refer to a surface or a portion of a surface on which processing is performed. Those skilled in the art will also understand that reference to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0012] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft targeted chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises depends on which film is being deposited as well as the particular chemistry used.

[0013] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0014] A transistor is a component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors are formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region of the substrate.

[0015] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel; the drain (D), where carriers exit the channel; and the gate (G), which is the terminal that adjusts the conductivity of the channel. Typically, the current entering the channel at the source (S) is I S and the current entering the channel at the drain (D) is I D The drain to source voltage is V DS By applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0016] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET). It has an insulated gate, the voltage across which determines the conductivity of the device. This ability to change conductivity depending on the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by a metal oxide semiconductor (MOS) capacitance between a body electrode and a gate electrode that sits above the body and is insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET has two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but both can be of the same type, opposite to the body region. The source and drain are highly doped (unlike the body) and are denoted by a "+" sign after the type of doping.

[0017] If the MOSFET is n-channel or nMOSFET, the source and drain will be n+ regions and the body will be a p region. If the MOSFET is p-channel or pMOSFET, the source and drain will be p+ regions and the body will be an n region. The source is so called because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0018] As used herein, the term "Fin Field Effect Transistor (FinFET)" refers to a MOSFET transistor built on a substrate with gates located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the common name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0019] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire, or a nanoslab, or a nanosheet, a bar-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0020] As used herein, the term "nanowire" refers to a wire having a diameter of nanometers (10 -9 Nanowires refer to nanostructures with a length to width ratio of greater than 1000. Alternatively, nanowires can be defined as structures with a thickness or diameter limited to tens of nanometers or less, and no length restriction. Nanowires are used in transistors and some laser applications, and in one or more embodiments are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness scale ranging from about 0.1 nm to about 1000 nm.

[0021] Embodiments of the present disclosure are described with reference to figures that show devices (e.g., transistors) and processes for forming transistors in accordance with one or more embodiments of the present disclosure. The processes shown are merely exemplary possible uses of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications shown.

[0022] One or more embodiments of the present disclosure are described with reference to the figures. In the method of one or more embodiments, a transistor, such as a gate-all-around transistor, is fabricated using standard process flows. In some embodiments, the diffusion barrier fill material is used as a planarization stop layer for backside wafer polishing to achieve a backside power rail. In one or more embodiments, the diffusion barrier fill material acts as an effective etch stop layer for the backside wafer polishing process and connects the NMOS and PMOS source-epi bottoms. As a result, the height and aspect ratio of the BPR-vias are reduced, which aids in the BPR-via etching and filling process.

[0023] In the method of one or more embodiments, a transistor, such as a gate-all-around transistor, is fabricated using a standard process flow as shown in Figures 2A through 2H. Fabrication proceeds with inner spacer formation, source / drain epitaxy, and interlevel dielectric formation. Next, resist is deposited and patterned, followed by deposition of a diffusion blocking material. Fabrication then proceeds with the formation of replacement metal gates, CT, V0, M0, M x V x etc. The substrate is then flipped and planarized, stopping on the diffusion barrier fill material. The backside power rail vias are then patterned. In some embodiments, the diffusion barrier is a single diffusion barrier. In other embodiments, the diffusion barrier is a mixed diffusion barrier.

[0024] In one or more embodiments, the term "diffusion break" refers to an isolation material disposed between two active areas. As used herein, the term "double diffusion break (DDB)" refers to an isolation structure in which the lateral width between two active areas corresponds approximately to the lateral width of the source and drain structures of a FET device, e.g., a GAA device. As used herein, the term "single diffusion break (SDB)" refers to an isolation structure in which the lateral width between two active areas is less than the lateral width of the gate structure of a FET device. As used herein, the term "mixed diffusion break (MDB)" refers to the combined use of SDB and DDB at different locations of a wafer in a process flow.

[0025] FIG. 1A shows a standard process flow diagram of a method 6A for forming a semiconductor device according to some embodiments of the present disclosure. FIGS. 2A-2H show stages of fabricating a semiconductor structure according to the standard process flow of FIG. 1A. FIG. 1B shows a process flow diagram of a method 6B for forming a semiconductor device according to some embodiments of the present disclosure, where a single diffusion barrier is used. FIGS. 3A-3J show stages of fabricating a semiconductor structure according to FIG. 1B, where a single diffusion barrier is used. FIG. 1C shows a process flow diagram of a method 6C for forming a semiconductor device according to some embodiments of the present disclosure, where a mixed diffusion barrier is used. FIGS. 4A-4J show stages of fabricating a semiconductor structure according to FIG. 1C, where a mixed diffusion barrier is used.

[0026] Methods 6A, 6B, and 6C are described below with respect to Figures 2A-2H, 3A-3J, and 4A-4J. Figures 2A-2H, 3A-3J, and 4A-4J are cross-sectional views of an electronic device (e.g., GAA) according to one or more embodiments. Methods 6A, 6B, and 6C may be part of a multi-step manufacturing process of a semiconductor device. Thus, methods 6A, 6B, and 6C may be performed in any suitable processing chamber coupled to a cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or other suitable chambers used in manufacturing semiconductor devices.

[0027] 2A-2I are manufacturing steps from acts 8 to 30 of FIG. 1A. Referring to FIG. 1A, a method 6A of forming a device 100 begins in act 8 by providing a substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. A bulk semiconductor substrate may be composed of any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which the substrate can be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be constructed is within the spirit and scope of the present disclosure.

[0028] In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor that is created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to a positive charge (or hole) in the well. In contrast to n-type semiconductors, p-type semiconductors have a hole concentration that is greater than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0029] 1A and 2A, in some embodiments, in operation 10, an etch stop layer 103 may be formed on the top surface of the substrate. The etch stop layer 103 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the etch stop layer 103 comprises silicon germanium (SiGe). In one or more embodiments, the etch stop layer 103 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including in the range of 35% to 45%. Without wishing to be bound by theory, it is believed that a germanium content in the range of 30% to 50% improves the selectivity of the etch stop layer and minimizes stress defects. In one or more embodiments, the etch stop layer has a thickness in the range of 5 nm to 30 nm. The etch stop layer 103 may function as an etch stop for planarization (e.g., CMP), dry etching, or wet etching during backside processing.

[0030] In one or more non-illustrated embodiments, in operation 12, an epitaxial layer, such as epitaxial silicon, may be deposited on the etch stop layer 103. The epitaxial layer may have a thickness in the range of 20 nm to 100 nm.

[0031] 1A and 2A, in one or more embodiments, in operation 14, at least one superlattice structure 101 is formed on the top surface of the substrate 102 or on the top surfaces of the etch stop layer 103 and the epitaxial layer. The superlattice structure 101 includes a plurality of semiconductor material layers 104 and a corresponding plurality of horizontal channel layers 106, alternating in a plurality of stacked pairs. In some embodiments, the plurality of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of semiconductor material layers 104 includes silicon germanium (SiGe) and the plurality of horizontal channel layers 106 includes silicon (Si). In other embodiments, the plurality of horizontal channel layers 106 includes silicon germanium (SiGe) and the plurality of semiconductor material layers 106 includes silicon (Si).

[0032] In some embodiments, the plurality of semiconductor material layers 104 and the corresponding plurality of horizontal channel layers 106 may include any number of lattice-matched material pairs suitable for forming a superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 104 and the corresponding plurality of horizontal channel layers 106 include from about 2 to about 50 lattice-matched material pairs.

[0033] In one or more embodiments, the thickness of the semiconductor material layers 104 and the horizontal channel layers 106 is in the range from about 2 nm to about 50 nm, from about 3 nm to about 20 nm, or from about 2 nm to about 15 nm.

[0034] 1A and 2B, in one or more embodiments, in operation 16, the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105. Patterning can be done by any suitable means known to one of skill in the art. As used in this regard, the term "opening" refers to any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two sidewalls, and a bottom. The openings can have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or more.

[0035] 1A and 2C, in operation 18, shallow trench isolation (STI) 110 is formed. As used herein, the term "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, the STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill the trench or opening 108 and removing excess dielectric using a technique such as chemical mechanical planarization.

[0036] 1A and 2D, in some embodiments, a dummy gate structure 113 is formed on and adjacent to the superlattice structure 101. The dummy gate structure 113 defines a channel region of a transistor device. The dummy gate structure 113 may be formed using any suitable conventional deposition and patterning process known in the art.

[0037] In one or more embodiments, the dummy gate structure 113 includes one or more of a gate material 114 and a polysilicon layer 112. In some embodiments, the dummy gate structure 113 may also include a dielectric layer 109 between the superlattice structure and the polysilicon layer 112.

[0038] 1A and 2E, in some embodiments, in operation 22, sidewall spacers 116 are formed on the superlattice 101 along the outer sidewalls of the dummy gate structures 113. The sidewall spacers 116 may include any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or isotropic deposition.

[0039] 1A and 2F, in operation 24, in one or more embodiments, source / drain trenches 118 are formed adjacent to (ie, on either side of) the superlattice structure 101.

[0040] 1A and 2G, in operation 26, in one or more embodiments, the source / drain trenches 118 are deepened and widened by a lateral etch to form a cavity 119 below the superlattice structure 101. The cavity 119 may have any suitable depth and width. In one or more embodiments, the cavity 119 extends through the shallow trench isolation 110 and into the substrate 102. In one or more embodiments, the etch stop layer 103 is etched away during formation of the cavity 119, such that the cavity 119 extends into the substrate 102.

[0041] The cavity 119 may be formed by any suitable means known to one of ordinary skill in the art. The etching process of operation 26 may include any suitable etching process that is selective to the source drain trenches 118. In some embodiments, the etching process of operation 26 includes one or more of a wet etching process or a dry etching process. The etching process may be a directional etch.

[0042] In some embodiments, the dry etching process may include a conventional plasma etch or a remote plasma assisted dry etching process, such as the SiCoNi™ etch process available from Applied Materials, Inc., Santa Clara, Calif., USA. In the SiCoNi™ etch process, the device is exposed to H2, NF3, and / or NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, the device may be exposed to H2, NF3, and NH3 plasma simultaneously. The SiCoNi™ etch process may be performed in a SiCoNi™ pre-clean chamber, which may be integrated into one of a variety of multi-processing platforms, including the Centura™, Dual ACP, Producer™ GT, and Endura™ platforms available from Applied Materials®. The wet etching process may include a hydrofluoric (HF) acid last process, or a so-called "HF last" process, in which the surface is HF etched, leaving the surface hydrogen terminated. Alternatively, any other liquid-based epitaxial pre-clean process may be employed. In some embodiments, the process includes a sublimation etch to remove the native oxide. The etching process can be plasma-based or thermal-based. The plasma process can be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0043] 1A and 2H, in operation 28, a bottom dielectric insulation (BDI) layer 120 is deposited in the cavity 119. The bottom dielectric insulation (BDI) layer 120 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the bottom dielectric insulation (BDI) layer 120 may include any suitable material having an etch rate different from that of the shallow trench isolation 110, as well as crystalline silicon and crystalline silicon germanium (SiGe). In one or more embodiments, the bottom dielectric insulation (BDI) layer 120 includes a dielectric material. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material comprises one or more of an oxide, a carbon doped oxide, silicon dioxide (SiO2), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). In one or more embodiments, the bottom dielectric insulation (BDI) layer 120 comprises a silicon oxide (SiO x ), silicon nitride (SiN), silicon carbide (SiC), boron doped silicon, silicon doped boron, metals, metal oxides, metal silicides, metal carbides, and high-k materials. In some embodiments, the high-k material is selected from one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), and the like. In one or more particular embodiments, the bottom dielectric insulation (BDI) layer 120 is silicon oxide (SiO x ).

[0044] In some embodiments, a bottom dielectric insulation (BDI) layer 120 is deposited on the substrate 102 using conventional chemical vapor deposition techniques.

[0045] 2I and 1A, in operation 30, in some embodiments, buried source / drain 121a, 121b regions are formed in source / drain trench 118. In some embodiments, buried source 121a is formed adjacent a first end of superlattice structure 101 and drain 121b is formed adjacent a second opposing end of superlattice structure 101. In some embodiments, source / drain 121a, 121b regions are formed from any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphide (SiP), silicon arsenide (SiAs). In some embodiments, source / drain 121a, 121b regions can be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source / drain 121a, 121b regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0046] 1A and 2J, in operation 32, an inter-layer dielectric (ILD) layer 122 is blanket deposited over the substrate 102, the dummy gate structure 113, and the sidewall spacers 116. The ILD layer 122 can be deposited using conventional chemical vapor deposition techniques (e.g., plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one or more embodiments, the ILD layer 122 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 122 is then polished using conventional chemical mechanical planarization techniques to expose the tops of the dummy gate structure 113. In some embodiments, the ILD layer 122 is polished to expose the tops of the dummy gate structure 113 and the tops of the sidewall spacers 116, as shown in FIG. 3A.

[0047] 3A-3J are fabrication steps from acts 32 through 52 of FIG. 1B illustrating the formation of a single diffusion block (SDB).

[0048] 1B and 3B, in operation 34 , a resist material 124 is formed on top of the dummy gate structure 113 and patterned to form a single diffusion block opening 126 .

[0049] 1B and 3C, in operation 36, in one or more embodiments, the dummy gate structure 101 and the resist material 124 may be etched to expose the superlattice structure 101. The ILD layer 122 protects the source and drain regions during removal of the dummy gate structure 113. The dummy gate structure 113 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the superlattice structure 101 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0050] 1B and 3D, in operation 38, resist material 124 is stripped away to expose the top surface of device 100.

[0051] 1B and 3E, in operation 40, a diffusion blocking fill material 128 is deposited in the single diffusion blocking opening 126 adjacent to the superlattice structure 101. The diffusion blocking fill material 128 may include any suitable material known to those skilled in the art. In one or more embodiments, the diffusion blocking material 128 includes a dielectric material. In other embodiments, the diffusion blocking fill material 128 includes one or more of a dielectric material and a metal. In such embodiments where the diffusion blocking fill material 128 includes a dielectric material and a metal, the metal has a thickness / height in the range of about 5 nm to about 60 nm, or in the range of about 10 nm to about 50 nm, and the metal is disposed at the bottom of the diffusion blocking fill material 128. In other words, the metal is disposed in contact with the STI layer 110 and in contact with the substrate 102. In one or more embodiments, the dielectric material constitutes the remainder of the diffusion blocking fill material 128 such that the dielectric material has a thickness in the range of 80 nm to 90 nm.

[0052] In one or more non-illustrated embodiments, the formation of the semiconductor device, e.g., GAA, continues according to conventional procedures involving the release of nanosheets and the formation of replacement metal gates. Specifically, in one or more non-illustrated embodiments, the semiconductor material layers 104 are selectively etched between the horizontal channel layers 106 in the superlattice structure 101. For example, if the superlattice structure 101 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 104, e.g., silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the horizontal channel layers 106, which etches the semiconductor material layers 104 at a rate significantly faster than the horizontal channel layers 106. In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, when the horizontal channel layers 106 are silicon (Si) and the semiconductor material layers 104 are silicon germanium (SiGe), the silicon germanium layers can be selectively removed using wet etchants such as, but not limited to, aqueous carboxylic acid / nitric acid / HF and aqueous citric acid / nitric acid / HF solutions. Removal of the semiconductor material layers 104 leaves voids between the horizontal channel layers 106. The voids between the horizontal channel layers 106 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 106 form a vertical array of channel nanowires connected to the source / drain 121a, 121b regions. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0053] In one or more non-illustrated embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to one of skill in the art. The high-k dielectric in some embodiments includes hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), aluminum (Al), etc., is deposited on the high-k dielectric to form an alternative metal gate. The conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer having a uniform thickness is formed around each of the multiple channel layers.

[0054] In one or more non-illustrated embodiments, drain contacts (CT) and gate contacts (CG) to the transistors are formed, and further, metal (M0) and metal (M1) lines are formed and electrically connected to the vias (V1).

[0055] Referring to FIG. 3F, in act 42 of FIG. 1B, device 100 is rotated or flipped 180 degrees so that substrate 102 is at the top of the figure.

[0056] 1B and 3H, in operation 44, the device 100 is planarized, stopping at the diffusion blocking fill material 128, and not planarizing the substrate 102 and the bottom dielectric insulating layer 120. The planarization can be any suitable planarization process known to one of ordinary skill in the art, including but not limited to chemical mechanical planarization (CMP). In some embodiments, an advanced chemical mechanical planarization (CMP) process uses the diffusion blocking fill material 128 as an etch stop layer for backside wafer polishing to achieve a backside power rail. Advanced CMP uses endpoint detection (EDP). Precise process control and EPD are required to minimize dishing and erosion of structures. Conventional CMP does not use endpoint detection (EDP). In one or more embodiments, if the diffusion blocking fill material 128 is comprised of a metal, the metal is removed after planarization, leaving behind the diffusion blocking fill material 128 comprised of a dielectric material.

[0057] 1B, in one or more embodiments, an interlayer dielectric material 130 is deposited on the backside of the substrate 102 and the diffusion barrier material 128, as shown in FIG. 3H. The interlayer dielectric material 130 may be deposited by any suitable means known to one of ordinary skill in the art. The interlayer dielectric material 130 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the interlayer dielectric material 130 includes one or more of silicon nitride (SiN), carbide, or boron carbide to enable high aspect ratio etching and metallization.

[0058] In one or more embodiments, in operation 46, a backside via 152 is patterned. The via 152 may be formed by any suitable means known to one of ordinary skill in the art. In one or more embodiments, the via 152 may be formed by patterning and etching the interlayer dielectric material 130. Once patterned, the via 152 extends from a top surface of the interlayer dielectric material 130 to the bottom dielectric insulation (BDI) layer 120. Thus, in one or more embodiments, the bottom dielectric insulation (BDI) layer 120 acts as an etch stop layer. In some embodiments, the aspect ratio of the via 152 is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or more.

[0059] In operation 48 of FIG. 1B, device 100 is silicided and a barrier layer 158 is deposited in via 152, as shown in FIG. 3I. Barrier layer 158 may comprise any suitable material known to one of skill in the art. In some embodiments, barrier layer 158 comprises titanium nitride (TiN) or tantalum nitride (TaN). In operation 50, metal 160 is deposited in via 152 on barrier layer 158. Metal 160 may comprise any suitable metal known to one of skill in the art. In one or more embodiments, metal 160 is selected from one or more of tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0060] 1B and 3J, in operation 52, the backside metal line (M0) 162 is formed. Without wishing to be bound by theory, it is believed that by placing the power rail on the backside, the area of ​​the cell can be increased by between 20% and 30%.

[0061] 4A-4J are manufacturing steps of acts 54 through 74 of FIG. 1C, which may be performed after the standard manufacturing steps shown in FIGS. 1A and 2A-2H, including the formation of a mixed diffusion barrier (MDB).

[0062] 1C and 4A, in operation 54, an inter-layer dielectric (ILD) layer 122 is blanket deposited over the substrate 102, the dummy gate structure 113, and the sidewall spacers 116. The ILD layer 122 can be deposited using conventional chemical vapor deposition techniques (e.g., plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one or more embodiments, the ILD layer 122 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 122 is then polished using conventional chemical mechanical planarization techniques to expose the tops of the dummy gate structure 113. In some embodiments, the ILD layer 122 is polished to expose the tops of the dummy gate structure 113 and the tops of the sidewall spacers 116.

[0063] 1C and 4B, in operation 56, a resist material 144 is formed on top of the dummy gate structure 113 and patterned to form mixed diffusion barrier openings 140, 142. In one or more embodiments, a single diffusion barrier opening 142 is formed adjacent to the superlattice structure 101 and a dual diffusion barrier opening 140 is formed over the source / drain regions.

[0064] 1C and 4C, in operation 58, in one or more embodiments, the dummy gate structure 101 and resist material 144 are etched to expose the channel region of the superlattice structure 101 and extend the double diffusion barrier opening 140 over the source / drain regions and down to the BDI layer 120 to form an extended double diffusion barrier opening 148.

[0065] The resist material 144 protects the source and drain regions during removal of the dummy gate structure 113. The dummy gate structure 113 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the superlattice structure 101 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0066] 1C and 4D, in operation 60, resist material 144 is stripped away to expose the top surface of device 100.

[0067] 1C and 4E, in operation 62, a mixed diffusion barrier fill material 150 is deposited in the single diffusion barrier opening 142 adjacent to the superlattice structure 101 and in the extended double diffusion barrier opening 148. The mixed diffusion barrier fill material 150 may include any suitable material known to those skilled in the art. In one or more embodiments, the mixed diffusion barrier fill material 150 includes a dielectric material. In other embodiments, the mixed diffusion barrier fill material 150 includes one or more of a dielectric material and a metal. In such embodiments where the diffusion barrier fill material 150 includes a dielectric material and a metal, the metal has a thickness / height in the range of about 5 nm to about 60 nm, or in the range of about 10 nm to about 50 nm, and the metal is disposed at the bottom of the diffusion barrier fill material 150. In other words, the metal is disposed in contact with the STI layer 110 and in contact with the substrate 102. In one or more embodiments, the dielectric material constitutes the remainder of the diffusion barrier fill material 150 such that the dielectric material has a thickness in the range of 80 nm to 90 nm.

[0068] In one or more non-illustrated embodiments, the formation of the semiconductor device, e.g., GAA, continues according to conventional procedures involving the release of nanosheets and the formation of replacement metal gates. Specifically, in one or more non-illustrated embodiments, the semiconductor material layers 104 are selectively etched between the horizontal channel layers 106 in the superlattice structure 101. For example, if the superlattice structure 101 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 104, e.g., silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the horizontal channel layers 106, which etches the semiconductor material layers 104 at a rate significantly faster than the horizontal channel layers 106. In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, when the horizontal channel layers 106 are silicon (Si) and the semiconductor material layers 104 are silicon germanium (SiGe), the silicon germanium layers can be selectively removed using wet etchants such as, but not limited to, aqueous carboxylic acid / nitric acid / HF and aqueous citric acid / nitric acid / HF solutions. Removal of the semiconductor material layers 104 leaves voids between the horizontal channel layers 106. The voids between the horizontal channel layers 106 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 106 form a vertical array of channel nanowires connected to the source / drain 121a, 121b regions. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0069] In one or more non-illustrated embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to one of skill in the art. The high-k dielectric in some embodiments includes hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), aluminum (Al), etc., is deposited on the high-k dielectric to form an alternative metal gate. The conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer having a uniform thickness is formed around each of the multiple channel layers.

[0070] In one or more non-illustrated embodiments, drain contacts (CT) and gate contacts (CG) to the transistors are formed, and further, metal (M0) and metal (M1) lines are formed and electrically connected to the vias (V1).

[0071] Referring to FIG. 4F, in act 64 of FIG. 1C, device 100 is rotated or flipped 180 degrees so that substrate 102 is at the top of the figure.

[0072] 1C and 4G, in operation 64, the device 100 is planarized, stopping on the mixed diffusion barrier fill material 150. The planarization can be any suitable planarization process known to one of ordinary skill in the art, including but not limited to chemical mechanical planarization (CMP). In some embodiments, an advanced chemical mechanical planarization (CMP) process uses the mixed diffusion barrier fill material 150 as an etch stop layer for backside wafer polishing to achieve a backside power rail. Advanced CMP uses endpoint detection (EDP). Precise process control and EPD are required to minimize dishing and erosion of structures. Conventional CMP does not use endpoint detection (EDP).

[0073] 4H, in operation 66, an interlayer dielectric material 130 is deposited on the backside. The interlayer dielectric material 130 may be deposited by any suitable means known to those of skill in the art. The interlayer dielectric material 130 may include any suitable material known to those of skill in the art. In one or more embodiments, the interlayer dielectric material 130 includes one or more of silicon nitride (SiN), carbide, or boron carbide to enable high aspect ratio etching and metallization.

[0074] As shown in FIG. 4H, in operation 68 of FIG. 1C, in one or more embodiments, a backside via 152 is patterned. The via 152 may be formed by any suitable means known to one of ordinary skill in the art. In one or more embodiments, the via 152 may be formed by patterning and etching the interlayer dielectric material 130. Once patterned, the via 152 extends from the top surface of the interlayer dielectric material 130 to the bottom dielectric insulation (BDI) layer 120. Thus, in one or more embodiments, the bottom dielectric insulation (BDI) layer 120 serves as an etch stop layer. In some embodiments, the aspect ratio of the via 152 is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or more.

[0075] In operation 70 of FIG. 1C, device 100 is silicided and a barrier layer 158 is deposited in via 152, as shown in FIG. 4I. Barrier layer 158 may comprise any suitable material known to one of skill in the art. In some embodiments, barrier layer 158 comprises titanium nitride (TiN) or tantalum nitride (TaN). In operation 72, metal 160 is deposited in via 152 on barrier layer 158. Metal 160 may comprise any suitable metal known to one of skill in the art. In one or more embodiments, metal 160 is selected from one or more of tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0076] 1C and 4J, in operation 74, the backside metal line (M0) 162 is formed. Without wishing to be bound by theory, it is believed that by placing the power rail on the backside, the area of ​​the cell can be increased by between 20% and 30%.

[0077] An additional embodiment of the present disclosure is directed to a processing tool 300 for forming the described GAA device and method, as shown in FIG. 5. Various multi-processing platforms available from Applied Materials®, such as Reflexion® CMP, Selectra® Etch, Centura®, Dual ACP, Producer® GT, and Endura® platforms, as well as other processing systems, can be utilized. The cluster tool 300 includes at least one central transfer station 314 with multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move the robot blade and wafer to each of the multiple sides.

[0078] The cluster tool 300 includes multiple processing chambers 308, 310, and 312, also referred to as processing stations, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent processing stations. The processing chambers may be any suitable chambers, including, but not limited to, pre-clean chambers, deposition chambers, annealing chambers, etch chambers, etc. The particular arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0079] 5, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading at a front 319 of the factory interface 318.

[0080] The size and shape of the loading and unloading chambers 302 can vary depending on, for example, the substrates being processed in the cluster tool 300. In the embodiment shown, the loading and unloading chambers 302 are sized to hold a wafer cassette with multiple wafers positioned within the cassette.

[0081] The robot 304 resides in a factory interface 318 and can move between the loading chamber and the unloading chamber 302. The robot 304 can transfer wafers from a cassette in the loading chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 can also transfer wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unloading chamber 302.

[0082] The robot 316 in some embodiments is a multi-arm robot capable of independently moving multiple wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0083] A system controller 357 communicates with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, suitable circuitry 398, and storage.

[0084] The processes can generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) that is remote from the hardware being controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the processes can be implemented in software and can also be performed using, for example, a computer system in hardware, as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into an application specific computer (controller) that controls the operation of the chamber to perform the processes.

[0085] In some embodiments, the system controller 357 is configured to control the rapid thermal processing chamber to crystallize the template material.

[0086] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move the wafer; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area isolated from the processing areas of adjacent processing stations, the plurality of processing stations including a template deposition chamber and a template crystallization chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller configured to activate the robot to move the wafer between the processing stations and to control the processing performed at each of the processing stations.

[0087] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better illuminate the materials and methods, and does not impose limitations on the scope of the claims unless otherwise specified. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0088] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in an embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0089] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a gate structure on a superlattice structure, the superlattice structure overlying a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding layers of semiconductor material interleaved into a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches on the substrate adjacent to the superlattice structure; depositing a bottom dielectric insulating layer within the plurality of source trenches and the plurality of drain trenches; forming a resist over the gate structure; patterning the resist to form a diffusion blocking opening; depositing a diffusion blocking material within the diffusion blocking opening; planarizing the device; etching to form a plurality of via openings extending to the bottom dielectric insulating layer; and depositing metal into the plurality of via openings and within the openings to form a plurality of vias; A method comprising:

2. The method of claim 1 , wherein the diffusion barrier material comprises one or more of a dielectric material and a metal.

3. The method of claim 1 , wherein the diffusion block opening comprises a single diffusion block opening.

4. The method of claim 1 , wherein the diffusion block openings include a single diffusion block opening and a double diffusion block opening.

5. The method of claim 2 , wherein the dielectric material has a thickness in the range of 80 nm to 90 nm and the metal has a thickness in the range of 10 nm to 50 nm.

6. The method of claim 1 , further comprising widening at least one of the plurality of source trenches and at least one of the plurality of drain trenches.

7. The method of claim 6 , wherein the expanding comprises lateral etching.

8. 2. The method of claim 1, wherein the plurality of semiconductor material layers comprises silicon germanium (SiGe) and the plurality of horizontal channel layers comprises silicon (Si).

9. 2. The method of claim 1, wherein the plurality of semiconductor material layers comprises silicon (Si) and the plurality of horizontal channel layers comprises silicon germanium (SiGe).

10. 2. The method of claim 1, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon.

11. The method of claim 1 , wherein the method is performed in a processing chamber without breaking vacuum.

12. 1. A method of forming a semiconductor device, comprising: forming a plurality of source trenches and a plurality of drain trenches adjacent to a superlattice structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and corresponding layers of semiconductor material arranged in alternating stacked pairs; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a bottom dielectric insulating layer within the source cavity and within the drain cavity; forming a resist on a gate structure, the gate structure being adjacent to the superlattice structure on the substrate; patterning the resist to form at least one diffusion blocking opening; depositing a diffusion blocking material in the at least one diffusion blocking opening; rotating the semiconductor device by 180 degrees; planarizing the semiconductor device; forming a backside power rail via in the substrate to the bottom dielectric isolation layer; and depositing metal into said backside power rail vias; A method comprising:

13. The method of claim 12 , wherein the diffusion barrier material comprises one or more of a dielectric material and a metal.

14. The method of claim 12 , wherein the at least one diffusion block opening comprises a single diffusion block opening.

15. The method of claim 12 , wherein the at least one diffusion block opening includes a single diffusion block opening and a double diffusion block opening.

16. The method of claim 13 , wherein the dielectric material has a thickness in the range of 80 nm to 90 nm and the metal has a thickness in the range of 10 nm to 50 nm.

17. The method of claim 12 , wherein extending at least one of the source trenches and at least one of the drain trenches comprises a lateral etch.

18. the plurality of semiconductor material layers comprises silicon germanium (SiGe) and the plurality of horizontal channel layers comprises silicon (Si); or the plurality of semiconductor material layers comprises silicon (Si) and the plurality of horizontal channel layers comprises silicon germanium (SiGe); The method of claim 12.

19. 13. The method of claim 12, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon.

20. The method of claim 12 , wherein the method is performed in a processing chamber without breaking vacuum.

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