Error-robust quantum compiler

Abstract

A method is provided herein for generating error-robust quantum circuits from quantum algorithms. The method determines properties of quantum hardware that are used to implement the quantum algorithm and inform the deterministic dynamic error suppression routines that are implemented. The method also takes into account the compiled quantum circuit, because the quantum circuit provides information about the context of the operations performed on the qubits, which is a key factor in the fidelity of the quantum gates and therefore the success of the algorithm. The method then uses the properties and context to apply deterministic error correction.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from Australian Provisional Patent Application No. 2022 / 900597, filed on March 11, 2022, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to compiling quantum algorithms on quantum hardware using error correction. [Background technology]

[0003] Quantum computers offer enormous opportunities for solving problems that are difficult to solve using existing classical hardware based on binary bits. Quantum computers use quantum bits ("qubits"), which can hold a superposition of states and can become entangled.

[0004] However, one of the major obstacles on the road to widespread quantum computing is the relative instability of qubits, which means that for most practical computations, the quantum state is quickly lost. Quantum error-correcting codes, such as surface codes, are difficult to implement because they consume additional resources to provide protection against errors and use many more qubits than are currently available.

[0005] Dynamic error suppression is another approach to stabilizing the quantum state of a qubit. It involves individual operations that effectively correct for errors without requiring additional qubits. It may be called dynamic decoupling when referring to an idling qubit (memory), or dynamically corrected gates when applied to the active operation of one or more qubits. Dynamic error suppression is deterministic in that it does not require additional resources such as multiple measurement operations that must be combined to obtain a benefit. Dynamic error suppression can be performed successfully on single qubits, or lone pair qubits, but it is difficult to apply dynamic error suppression to an entire quantum circuit with multiple qubits that implements a quantum algorithm.

[0006] Any discussion of documents, acts, materials, devices, articles or the like which has been included in this specification shall not be construed as an admission that any or all of such matters form part of the prior art base or are common general knowledge in the fields relevant to this disclosure as they existed prior to the respective priority dates of the appended claims.

[0007] Throughout this specification the term "comprise" or variations such as "comprises" or "comprising" will be understood to mean the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not to the exclusion of any other element, integer or step, or group of elements, integers or steps. Summary of the Invention [Means for solving the problem]

[0008] Provided herein is a method for generating error-robust quantum circuits from quantum algorithms. The method determines properties of quantum hardware that are used to implement the quantum algorithm and inform the deterministic dynamic error suppression routines that are implemented. The method also takes into account the compiled quantum circuit, as it provides information about the context of the operations performed on the qubits, which is a key factor in the fidelity of the quantum gates and ultimately the success of the algorithm. The method then uses the properties and context to apply deterministic error correction.

[0009] A method for generating an error-corrected quantum circuit is Compiling the quantum algorithm into quantum hardware using a plurality of qubits to generate a quantum circuit; determining quantum relationships between the plurality of qubits and between the plurality of qubits and an external environment as a result of implementing the quantum circuit in the quantum hardware; and determining a deterministic error correction protocol for each of the plurality of qubits and for interactions between the plurality of qubits using quantum relationships between the plurality of qubits and between the plurality of qubits and an external environment, the deterministic error correction protocol being specific to the quantum circuit and specific to the quantum hardware for each of the plurality of qubits and for interactions between the plurality of qubits.

[0010] In some embodiments, the method further includes performing multiple measurements on qubits of the quantum hardware to determine an error signature of the quantum hardware based on a topology of the quantum hardware.

[0011] In some embodiments, the error characterization includes one or more of individual gate errors based on the topology of the quantum hardware, decoherence processing, measurement errors, and crosstalk between qubits.

[0012] In some embodiments, compiling includes selecting one or more quantum blocks for each of a plurality of logical quantum operations in the quantum algorithm to implement the quantum algorithm on quantum hardware, where each of the quantum blocks implements a logical function of that logical quantum operation.

[0013] In some embodiments, the method further includes determining an error correction protocol for each of the quantum blocks, the error correction protocol including error correction for errors identified in the error characterization and specific to the selected one or more quantum blocks for implementing the quantum algorithm.

[0014] In some embodiments, the method further includes implementing a quantum algorithm on the quantum hardware using the selected quantum blocks and the deterministic error correction protocol to obtain qubit measurements.

[0015] In some embodiments, the method further includes reducing measurement error in the qubit measurements by applying an error reduction operation based on the error characteristic estimate.

[0016] A method for characterizing errors in quantum hardware including a plurality of qubits includes determining groups of qubits to minimize inter-group correlation based on a topology of the quantum hardware, performing a plurality of measurements to approximate a confusion matrix for individual qubit readouts, and repeating the plurality of measurements for the qubit groups to determine an error characterization of the hardware.

[0017] In some embodiments, the group of qubits includes qubit pairs having low mutual coupling between the pair.

[0018] In some embodiments, the error characterization includes one or more of individual gate fidelity, noise spectrum, and crosstalk intensity.

[0019] In some embodiments, the method further includes using machine learning to automate the determination of the error signature estimate.

[0020] In some embodiments, the method further includes optimizing parameters of the quantum gate using the qubits to maximize the fidelity of the quantum gate.

[0021] In some embodiments, fidelity is maximized for gates where the qubits in a group are in parallel.

[0022] A method for compiling a quantum algorithm onto quantum hardware having a native gate set includes: performing a first compilation process to map the quantum algorithm to quantum hardware and a set of native gates; using the output of the first compilation process as input to perform a second compilation process, different from the first compilation process, to maximize the use of low-error quantum bits identified by the error characterization process.

[0023] The quantum error correction method for quantum hardware is as follows: partitioning qubits of the quantum hardware into groups based on a topology of the quantum hardware; dividing the qubits into blocks based on a quantum circuit compiled into quantum hardware; applying a driving single qubit operation to correct for quantum errors that occur during a coincidence operation that relies on a quantum circuit compiled into quantum hardware; determining a time shift of the driving single qubit operation to compensate for mutual coupling and suppress decoherence for each of the groups and blocks in the coincidence operation.

[0024] In some embodiments, the method further includes redefining the non-matching operation to compensate for the error process identified via the error characteristic evaluation via time domain modulation of the control signal used to implement the non-matching operation.

[0025] In some embodiments, the method further includes time modulating the control signal in the plurality of qubits in a continuous or discontinuous manner.

[0026] In some embodiments, the method further includes assembling blocks from a library of error-corrected quantum gates based on the error characterization.

[0027] The method of error correction compilation for correcting the error sources identified in the error characterization process comprises: receiving a compiled circuit compatible with the hardware device topology and gate set; replacing quantum logic gates in the compiled circuit having uncorrected errors above a tolerance threshold with error-corrected alternatives derived using an error characterization process; and outputting a definition of the circuit having all the permutation gate definitions in a format for hardware implementation including match and non-match operations.

[0028] In some embodiments, the method comprises: Identifying non-matching gates that are prone to errors; Replacing error-prone non-matched gates with auto-calibrated gates; replacing the coincidence gates in the compiled quantum circuit with error-corrected coincidence gates that include an error correction protocol; and assembling the output error-robust circuit, including the auto-calibrated gate and the error-corrected coincident gate, into a circuit representation for implementation in quantum hardware.

[0029] A method for correcting errors in quantum measurements of quantum circuits in quantum hardware is Receiving a measurement result; and using the approximated confusion matrix from the error feature estimate to reduce the tensor based on groups of qubits; Converting tensors into probability distributions, correcting errors in quantum measurements of a quantum circuit on quantum hardware as indicated by a probability distribution; and outputting the measurement error correction result.

[0030] In some embodiments, the method further includes partitioning the quantum circuit into groups of qubits to minimize inter-group correlation based on a topology of the quantum hardware, and reordering the tensors based on the groups of qubits.

[0031] In some embodiments, the method further includes adding a dimension to the tensor of unmeasured qubits.

[0032] In some embodiments, the method further includes applying a neural network to the measurements based on the error feature estimate to restore correlations ignored by tensor reduction.

[0033] The Internet server is providing a web interface including input elements for inputting quantum algorithms and quantum hardware characterizations; receiving, via a web interface, an incomplete description of the quantum algorithm and the quantum hardware; Performing an error characterization or retrieving a previously performed error characterization for the target quantum hardware; generating a decorated quantum circuit description for implementing a quantum algorithm on quantum hardware, the decorated quantum circuit description including quantum logic blocks that are error-corrected based on the feature evaluation; Output the quantum circuit description, It is configured to receive raw output data from the quantum hardware and analyze it using full characterization.

[0034] In some embodiments, outputting the quantum circuit description includes sending the decorated quantum circuit description to a user via a web interface, or sending the decorated quantum circuit description to quantum hardware for implementation on the quantum hardware.

[0035] In some embodiments, receiving and analyzing the raw output data includes receiving the raw output data from a user via a web interface for analysis or receiving the raw output data from quantum hardware for analysis.

[0036] The optional features provided above with reference to one of the methods or Internet servers are equivalent to the optional features of the other methods and Internet servers. [Brief description of the drawings]

[0037] [Figure 1] We present a dynamic decoupling (DD) motif. (a,b) We present two motifs that realize a single qubit DD. As long as the idle time between two bit flips is equal to the remaining idle time, the effect of phase scrambling is suppressed. (c) Since each bit flip reverses the ZZ effect, applying two flips simultaneously leaves the ZZ coupling unchanged. Thus, the motif in (c) suppresses the T2 effect on both qubits, but does not mitigate the ZZ effect. (d) Combining the two motifs in (a) and (b) leads to the mitigation of ZZ. Since the X gate (bit flip) is not instantaneous, the asymmetry parameter δ can be optimized to achieve optimal ZZ cancellation. [Diagram 2] An example of a compiled circuit is shown. On the left is a snapshot of a 7-qubit algorithm that has already been compiled into native gates available on the device. The disclosed method takes the compiled circuit and device connectivity as input and returns a decorated circuit with an optimal DD embedded, as shown on the right. [Diagram 3]An example of DD embedding is provided. The input circuit on top is the compiled circuit, and the output circuit on the bottom is the original circuit with the optimal DD structure embedded in it, with the circuit of the disclosed automation scheme. The embedded DD structure contains X operations at a particular time, as calculated by the input circuit and the error correction protocol specific to the quantum hardware. Note that this diagram is simplified for illustrative purposes, which means that the temporal (horizontal) location of the DD operations may not be precise. [Figure 4] An example is shown of groups of 4 qubits that minimizes inter-group correlation in the measurement readout. [Diagram 5] Figure 1 shows the success probability of the disclosed method. A fixed number of qubits are prepared in the |1> state, as given by the x-axis, and the qubits are measured. The plot shows the success probability of measuring the correct bit string. The shallow circuit depth ensures that decoherence does not affect the success probability. Due to readout errors, the success probability drops rapidly as the number of qubits increases. However, the disclosed tensor mitigation protocol adequately mitigates the readout errors. [Figure 6] We present an example of a neural network architecture for measurement error correction on a 7-qubit quantum computer. [Figure 7] Figure 2 shows a comparison of the measurement error exhibited by the Hellinger loss, averaged over 2000 random probability distributions on a 7 qubit quantum computer. [Figure 8a]The different compilation methods are compared using QFT circuits. Method A is a probabilistic method, and therefore the figure presents 50 examples of the method. The total number of CX gates and the total circuit duration are used as comparison functions. As can be seen, the hybrid method typically finds shorter circuits with a smaller number of entangled gates. Although the plot does not demonstrate it, the hybrid method avoids low-quality qubits better. In the above case, Q3 has higher spam and CX error than the device average. The hybrid method avoids this qubit completely for circuits with less than 11 qubits. As a comparison, for a 10-qubit QFT, 70% of the circuits created with Method A contain problematic qubits. [Figure 8b] The different compilation methods are compared using QFT circuits. Method A is a probabilistic method, and therefore the figure presents 50 examples of the method. The total number of CX gates and the total circuit duration are used as comparison functions. As can be seen, the hybrid method typically finds shorter circuits with a smaller number of entangled gates. Although the plot does not demonstrate it, the hybrid method avoids low-quality qubits better. In the above case, Q3 has higher spam and CX error than the device average. The hybrid method avoids this qubit completely for circuits with less than 11 qubits. As a comparison, for a 10-qubit QFT, 70% of the circuits created with Method A contain problematic qubits. [Figure 9] By partitioning the quantum circuit, we show that full device calibration can be performed in parallel, which requires a fixed number of steps depending on the device connectivity. The Heavy Hex topology can be tuned in as few as four steps, independent of the device size. [Figure 10]Probability of success of the Bernstein-Vazirani algorithm on a 16 qubit device. The black data corresponds to the best compilation available by the hardware provider, the grey data has a similar compilation to the black data with the latest DD scheme and measurement error mitigation available by the hardware provider. The purple data shows the performance using the software tools in this document. [Figure 11] We present a method for generating error-corrected quantum circuits. [Figure 12] A method for characterizing errors in quantum hardware containing multiple qubits is presented. [Figure 13] We show how to compile quantum algorithms to quantum hardware with a native gate set. [Figure 14] A method for quantum error correction in quantum hardware is presented. [Figure 15] A method for error-correcting compilation is shown. [Figure 16] A method for correcting errors in quantum measurements is presented. [Figure 17] Indicates an Internet server. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] As mentioned above, the methods disclosed herein relate to quantum algorithms implemented by multiple qubits on a particular quantum hardware. Unlike classical digital computers, where electronic properties are abstracted into stable binary bit values, quantum hardware cannot provide this level of abstraction without unrealistic imprecision. This means that each quantum hardware has significantly different properties with respect to the qubits. In particular, the relationship between the qubits, as well as the relationship between the qubits and the environment, is different for every different quantum hardware and even for the circuits running on that hardware. As a result, hardware-independent error correction leads to poor results. Furthermore, error correction that does not take into account the compiled circuit structure leads to high error rates.

[0039] Dynamic error suppression can be used to stabilize individual qubits or to improve the fidelity of isolated quantum logic gates between pairs of qubits. One exemplary protocol involves stabilization of qubits during idle time periods. This is known as dynamic decoupling. During this period, additional rotations can be applied to the qubit states to offset accumulated errors. However, in multi-qubit quantum circuits, the idle times of multiple qubits are not identical, and the qubits also interact with each other. Therefore, applying individual dynamic decoupling is difficult, and error correction depends on the hardware characteristics and the compiled circuit.

[0040] Compilation in this context means mapping a quantum algorithm to quantum hardware, taking into account the connectivity between qubits that differs from the available physical operations. Note that such quantum hardware often has a native gate set that may be unique to that quantum hardware, so the compiled quantum circuit uses the available gate set, with additional gates being introduced. Compilation may also involve optimizing the quantum circuit to reduce the number of gates, for example, through exploitation of mathematical relationships between gates.

[0041] Similar to algorithms on classical computers, quantum algorithms are step-by-step procedures, each of which can be executed on a quantum computer. Each step is an operation on a quantum state in the algorithm. During compilation, these steps are mapped to qubit operations called gates. Examples of quantum algorithms include Shor's Algorithm, Variational Quantum Eigensolver, Grover's Algorithm, and even Quantum Error Correction, although many other quantum algorithms can be implemented using the methods disclosed herein. It should be noted that the methods disclosed herein are applicable to a wide range of different qubit types, including nitrogen vacancies, trapped ions, silicon qubits, superconducting qubits, and many others.

[0042] It should also be noted that the methods disclosed herein are performed by a classical computer, which is a classical digital processor that implements the software, performs the compilation, processes the error measurements, optimizes and selects gates, determines the error correction protocol, and processes the output measurements, etc.

[0043] The usefulness of a quantum computer is ultimately determined by its ability to successfully implement meaningful quantum algorithms. Although ideal implementation of quantum algorithms is not possible on current quantum hardware, being able to run algorithms with a high probability of success may provide a path to quantum supremacy in the near future. The quality of a quantum algorithm is influenced not only by the quality of the individual building blocks, e.g., qubits, gates and measurements, but also by global device and algorithm properties such as device topology, multi-qubit correlations and algorithm structure. The present disclosure provides an automated method for the optimization of different components and the incorporation of deterministic error suppression techniques that ultimately affect the quality of an algorithm implementation on a given quantum hardware. The disclosed method provides improvements across different algorithms and quantum devices.

[0044] Summary of the Invention The disclosed protocol is a procedure for improving the performance of quantum algorithms on quantum hardware based on deterministic error correction methods. A user provides a quantum circuit via a website or application programming interface (API), and the disclosed protocol performs a series of optimization and error correction steps and outputs a measurement result of the quantum algorithm.

[0045] The workflow of the protocol is as follows:

[0046] Accepts circuits: Given a quantum circuit, it is first converted into an appropriate intermediate representation. This allows for a robust and hardware-independent compilation procedure.

[0047] ● Front-end compilation, which uses a series of compiler passes to reduce the depth (gate count) of the quantum circuit.

[0048] Hardware-specific back-end compilation: The logic operations in the circuit are mapped to native gates available in the hardware. An additional hardware-specific compilation pass is performed to account for device topology, gate errors, parallel gate crosstalk, etc.

[0049] ● Reduction of idling and crosstalk errors through DD decoration. Dynamic decoupling (DD) sequences are incorporated to mitigate various idling errors including dephasing and ZZ crosstalk at the algorithm level depending on the device characteristics and the circuit returned by the compiler. This disclosure relates to a method to automatically incorporate the best DD sequence into an algorithm for implementation, rather than a specific sequence design.

[0050] ● Gate error reduction through system-wide AI-driven auto-calibration. An AI-driven optimizer is used to perform pulse-level calibration across the quantum computer, including optimizing multiple gates in parallel. These optimized pulses are used to implement higher fidelity gates for use in the circuit. There are advantages to approaches and methods that use AI to perform system-wide calibration and automation of gate optimization. The process can be automated prior to user interaction. In one example, all relevant error-prone gates are replaced with these optimized gates.

[0051] Implement the algorithm on quantum hardware: the final definition of the circuit is output in a format compatible with hardware execution. This can be achieved by returning "new" commands to the user for implementation, or through a direct connection to a hardware backend (locally or in the cloud).

[0052] ● Measurement error reduction through efficient AI-enhanced readout error mitigation. Measured probability distributions from the implementation of algorithms on quantum devices contain measurement errors. These errors are corrected in post-processing using an efficient AI-enhanced measurement error mitigation protocol. This disclosure provides an approach as part of an overall workflow that efficiently suppresses the errors.

[0053] ● Return solutions with increased likelihood of algorithmic success. The “answer” from the implementation of the quantum algorithm is returned with an increased confidence level of success.

[0054] These processes may be integrated locally into the hardware system or connected to a cloud-accessible machine through an API. The user does not need to incur any direct overhead. Maximum performance is achieved with a single pass through the toolchain. This compares favorably with other known approaches to circuit-level error suppression.

[0055] These approaches may be used to improve the performance of either direct algorithm implementations or quantum error correction (QEC). QEC augmented by deterministic circuit-level error suppression via this protocol would be advantageous. In addition, improving the performance of quantum algorithms without requiring full quantum error correction is another advantage.

[0056] These approaches are relevant to any quantum computing architecture and are not specific to a single qubit type.

[0057] Background on noise and error processing Quantum systems are subject to various kinds of noise. These noise processes affect the building blocks of quantum circuits, such as gates and measurements. These operations can be optimized to mitigate the effects of noise and imperfections. However, standard gate calibration techniques typically keep spectator (non-participating) qubits in the ground state. Applying algorithms can result in more complex context-dependent noise processes that can introduce different kinds of errors.

[0058] Single-qubit decoherence At any given moment during a multi-qubit algorithm, several qubits are idle: even in the presence of perfect gates and measurements, in a wide and deep circuit, the idling errors alone are enough to completely randomize the quantum circuit and render the quantum algorithm useless.

[0059] The quantum state of a single qubit can be represented by a complex superposition of its internal states, A|0>+B exp{iφ}|1>, where A 2 +B 2≦1. Quantum gates purposefully steer quantum states towards desired targets, but quantum noise and unwanted couplings can steer quantum states as well. For example, noise processing can result from energy loss to the environment causing a qubit state |1> to decay to |0>. This processing is characterized by a typical time scale known as T1. This type of error can only be mitigated by reducing the total circuit duration. However, as hardware quality improves, T1 times longer, and for mid-scale algorithms this processing is typically not the bottleneck.

[0060] Another noise process is phase dephasing, in which the phase is scrambled by φ and the quantum state loses its phase information. This process is characterized by a typical time scale known as T2. In the presence of nearby excitations, T2 is much shorter than T1 and can dominate the overall algorithm performance.

[0061] Crosstalk While the above two processes arise due to coupling between the system and the environment, idling errors can also arise due to unwanted coupling between nearby qubits. The most common idling error is due to an unwanted coupling known as the ZZ error. In this process, a qubit acquires an unwanted phase that depends both on its state and on the state of its neighboring qubits. This unwanted coupling exists between a pair of coupled qubits and has a constant static part that depends only on the parameters of the system, and a dynamic part that depends on the excitation we apply in the circuit.

[0062] Gate Error Universal quantum computing can be achieved with any single qubit gate and two qubit entangled gate. Both single qubit and two qubit gates are typically realized by illuminating the qubits with shaped packet (pulse) waves. In addition to T1 and T2 errors as described above, gates are prone to other types of errors as well. Gate implementations are characterized by their pulse parameters. An ideal gate implementation has certain ideal pulse parameters, and deviations of these parameters, known as rotation, detuning, or other types, lead to performance degradation. Such deviations arise due to failure of the calibration (optimization) process, extrinsic time-varying noise, or drift of system parameters. Another type of error is control error, where the parameters of the pulses can deviate due to nonlinear transfer functions of the control chain and amplitude / phase noise in the pulse generator. These deviations result in coherent gate errors similar to over-rotation. Qubit decoherence further reduces the fidelity of the gate. While phase change errors can often be mitigated by optimal pulse shaping, errors due to qubit mitigation can only be reduced with faster gates. Fast gates, however, are prone to another type of error known as leakage, where the system is excited into states outside the computational space that degrades the fidelity of the circuit.

[0063] Measurement and Reading Errors Measuring qubits projects them onto observable eigenvalues. Typically, it will project the qubits onto either ground or excited states, and ideally, repeated measurements of the same observable should give the same result. Measurement errors arise due to noise in the readout chain, qubit backaction, qubit relaxation, and correlations between multi-qubit measurements. Errors in measurements result in a large overhead for quantum error correction.

[0064] Overview of Dynamic Decoupling of Device Recognition Algorithms Dynamic decoupling (DD) is an open-loop quantum control technique that aims to suppress errors in idle qubits. In its simplest form, DD is implemented by a periodic sequence of control pulses (gates), whose net effect is to substantially cancel the undesired coupling. Most DD protocols are designed to counter this T2 processing, but different schemes exist to design DD protocols for specific error reduction tasks. For example, ZZ errors can be mitigated by DD protocols. However, protocols to mitigate ZZ errors can vary dramatically from one algorithm to another and from one device to another, depending on the device topology, connectivity, and the ability to parallelize different layers of the algorithm. A substantial amount of literature exists on different approaches to design DD sequences for different physical settings.

[0065] The present disclosure provides a method for designing protocols that can be efficiently automated, hardware and circuit context aware, and applicable to general algorithms and a wide range of quantum hardware. The ability to construct a well-designed protocol for a given algorithm can make it useful.

[0066] Automated Delivery Scheme Basic DD motif The disclosed automated scheme takes as input the quantum circuit and device topology (Figure 2) and returns a new circuit in which the optimal DD protocol is embedded in the original circuit.

[0067] The guiding principle of DD is to replace idle periods with coincident operations consisting of one or more qubit operations that have no net change to the qubit state. Such examples are shown in Fig. 1(a,b). In these examples, the idle periods are replaced by two applications (bit flips) of the X gate. Two consecutive bit flips are equivalent to no operation at all. However, each application of the X gate reverses the direction of the T2-related (stochastic) phase diffusion. Thus, by matching the idle time between two bit flips with the remaining idle time, the effect of T2 errors is suppressed (statistically cancelled out). As the intermediate idle time t gets shorter, the statistical cancellation improves. Therefore, if the total idle time is long, it may be beneficial to replace it with several repetitions of the basic motif. Since the application of the X gate is not ideal, there exists an optimal number of such repetitions. This number depends on the quality of the qubits (T2 times and X gate errors) and the strength of the ZZ coupling.

[0068] For pairs of coupled qubits, there is a ZZ idling error on top of the T2 error. Individual bit flips reverse the direction of the ZZ coupling. Thus, simultaneous application of bit flips leaves the ZZ coupling unchanged, as shown in Fig. 1(c). To include the ZZ mitigation, a relative shift of the two DD schemes is required. Since the application of the X gate is not instantaneous, the asymmetry parameter δ can be optimized to achieve optimal ZZ cancellation. This motif is the basic building block of our method, as shown in Fig. 1(d). A more complex motif can be derived when more than two qubits are all mutually coupled, and alternative couplings (such as XX) can be cancelled using different sequences of operations.

[0069] Containing a basic motif for a set of completely idle qubits is a relatively easy task that requires only finding the optimal δ parameter and the optimal number of motif repetitions. However, finding the optimal embedding of this motif in any algorithm (Figure 2) does not have a clear solution.

[0070] Automatic Embedding of DD Motifs into Arbitrary Circuits In this section, the disclosure provides details on an automated scheme for embedding DD motifs in generic circuits. The method is designed to cancel T2 and ZZ errors as much as possible (complete cancellation is usually not possible) while keeping the number of X gates as small as possible. Very dense DD schemes (with many operations in a short period of time) can do more harm than good due to the individual errors and heating effects of each X gate.

[0071] FIG. 3 shows an example of a compiled circuit with an input circuit at the top and a DD embedded at the bottom.

[0072] The automated protocol is as follows.

[0073] 1. Given a device topology, the protocol divides qubits into N groups by solving a graph coloring problem. Most hardware providers use N=2, i.e., all qubits belong to one of two possible groups. Qubits in one group experience a δ-shifted DD, while qubits in the other group experience a non-shifted 2t-2tDD structure. See Figure 1(d) for the distinction between the two groups.

[0074] 2. Given a compiled circuit, the protocol slices the circuit into non-overlapping "global blocks" that encompass the entire circuit. A block is the longest period during which a set of idle qubits is not modified. Each block contains an initial and final time, [t i , t f ], as well as a set of idle qubits.

[0075] 3. Given the block structure, the total number of DDX gates can be calculated. Using this number along with the X gate error obtained from the backend, the protocol can calculate the X index. If this index is lower than a given threshold, the protocol does not change the block structure and skips step 4. Otherwise, the protocol proceeds to step 4.

[0076] 4. The protocol divides the circuit into 4 non-overlapping groups of the maximum size of connected qubits. The protocol then applies the block slice described in 2 separately to each group to find a new block structure ("local block"). This method dramatically reduces the total number of X gates, at the expense of ZZ correction on some links. The grouping of qubits is not necessarily unique, but is optimized to reduce the number of X gates and ZZ correction mismatch in the circuit. Given the device topology and the set of active qubits, the optimal grouping structure is fully automated.

[0077] 5. Given a block structure (global or local), the protocol implements a set of block merging rules to reduce the number of X-gates. Our merging rules handle distinct short blocks (less than twice the X-gate duration), blocks of qubits with connectivity 1, and consecutive blocks with some similarity rules.

[0078] 6. Given the final block structure, the protocol applies an optimal number of DD motifs (suitable for the block duration) to all idle qubits in the block according to their group, as determined in 1. Qubits are considered idle and will only be driven after joining the circuit for the first time.

[0079] See Fig. 3 for an example of an input / output circuit. This scheme is based on the fact that within each global block, the DD motif optimally reduces both the T2 and ZZ effects. However, in practice, the gates in the circuit are not synchronized and have different durations, so some blocks may be too short to implement the DD motif or two short to implement the full motif. Also, since the X gates are not ideal, a full embedding of the DD motif is insufficient and a DD scheme with an extreme load of X gates is likely to perform poorly. Steps 3 and 4 aim to find a compromise that optimizes the performance of a particular algorithm on a particular device.

[0080] The above procedure is hardware independent and fully automated. Given the compiled circuit, device topology, and back-end data, it returns the optimal DD embedded circuit. The method does not require pulse-level access. As long as the quantum hardware API accepts timed schedules of gates, the method is applicable. The ideal δ parameter and the optimal motif application number can be found in automated preliminary experiments.

[0081] Scalable Measurement Error Mitigation Overview Any quantum state is measured by projecting it onto the observable. This task can be reduced to finding its probability distribution over a set of all exponentially large basis states. The quantum circuit is operated multiple times to generate the statistics necessary to construct the probability distribution. The overall measurement error grows exponentially with the number of qubits due to compounding of the readout errors from each individual qubit.

[0082] We measure the error of the read assignment of a single qubit by the confusion matrix (C 1Q ),

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[0083] Automatic measurement correction Tensor reduction The disclosed method addresses the above-mentioned problems by dividing quantum devices into smaller groups of qubits that can then be efficiently corrected through tensor algebra. The groups are automatically selected in a way that minimizes inter-group correlations between measurements based on the topology of a given quantum computer. An example of such grouping is shown in FIG. 4.

[0084] The disclosed method ensures that all combined groups span the entire quantum computer (or at least all measured qubits in the quantum circuit). g is the number of groups,

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[0085] N q The measured probability vector for the qubits corresponds to each bit string

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[0086] The number of calibration experiments for this method is

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[0087] The effectiveness of the disclosed mitigation can be seen in Figure 5. The disclosed formalism deals directly with sparse distributions. This results in a scalable, fast and competitively accurate protocol. Finally, the method incorporates small corrections from long-range / inter-group correlations by processing the output probabilities with a custom neural network, as explained below.

[0088] Neural Networks for Multi-qubit Correlation In the disclosed method, the output from the tensor reduction described above is used as input to a neural network (NN). The goal of the NN is to restore correlations previously ignored (at group boundaries) and to account for nonlinear effects and contextual errors not captured in the confusion matrix formalism. Since the method is looking for small changes to the match transformation, the method uses a ResNet-like architecture for the NN. The number of tunable parameters in the NN scales with the number of qubits (N q ) This approach minimizes the amount of training data required. An example of a 7-qubit neural network is shown in Figure 6.

[0089] Disclosed herein is an automated approach for seamlessly incorporating both the disclosed tensor reduction method and the disclosed neural network approach. Figure 7 shows that the neural network provides additional improvement over and above that provided by the subset tensor reduction protocol. Furthermore, the trained network continues to provide improvement for at least up to 15 days without additional training data. The disclosed method is also applicable to reduce errors in observable expectations.

[0090] Quantum Compilation Quantum compilers are used to find more efficient ways to execute programs on quantum devices. They use a sequence of "compiler passes" to handle the mapping of circuits to device gate sets and topologies, as well as simplifying the circuit instructions. This includes passes that remove unnecessary gates, reduce the depth of the circuit, and move gates to qubits with lower error rates. Simplifying the logic of a circuit is the first step in reducing the effects of noise during program execution. Fewer operations means fewer opportunities for error, or certain error-prone operations or qubits can be removed from the circuit.

[0091] However, a delicate balance is found between these compiler passes to optimally compile the circuit. For example, moving a single qubit gate to a qubit with a low error rate requires inserting SWAP operations into the circuit. These SWAP gates increase the depth of the circuit because they are composed of two qubit gates (e.g., CNOT, CZ), and these gates are typically also prone to ZZ errors. Thus, while some errors resulting from single qubit gates are mitigated, new sources of error with two qubit gates are introduced. It is these diminishing returns between each compiler pass that can be weighted for any given algorithm and device.

[0092] Crosstalk-aware compilation As highlighted above, finding the correct sequence of compiler passes is not trivial and depends on both the device and the algorithm. There are several open source quantum compilers that can be used as a basis to automate this procedure. Custom plugins can be written to TKET (https: / / github.com / CQCL / tket) and qiskit (https: / / qiskit.org / ) to adjust the compiler flow based on the error characteristics of the device. The "vanilla" procedure works as follows: 1. Run the first "gate pass" to map the circuit to the device gates. 2. Map the circuit onto the device topology using a specified "topology path", which may include inserting SWAP gates into the circuit. 3. Place the circuit into the desired form using the specified "routing path," which involves moving circuit instructions to qubits with lower gate error, which may involve inserting SWAP gates. 4. Run a "swap reduction pass" which iteratively minimizes the number of swap gates in the circuit. 5. Make another gate pass work. 6. Operate a specified sequence of isomorphic reductions ("simplification passes") on the circuit. This may involve removing redundant gates, minimizing two-qubit operations, and replacing certain gate sequences with simpler, known definitions. 7. A "two-qubit gate rerouting path" is used to avoid parallel operation of certain gates. 8. Before undoing the circuit, run the final gate and topology pass.

[0093] While this vanilla approach has generally been moderately successful, certain algorithms may require a more tailored approach to maximize error mitigation. Critical to this are the topology, routing, and simplification paths that are operated on the circuit.

[0094] In particular, the behavior of the topology and routing paths depends heavily on circuit properties such as depth, density, and amount of two-qubit gates. One undesirable consequence of these paths is the insertion of excessive SWAP gates: for N SWAP gates, 3N two-qubit gates are needed to implement them. Too much rerouting from the original circuit arrangement can negatively impact performance. In addition, the behavior of the simplification paths depends heavily on the circuit format: two circuits can be isomorphic but simplified differently due to differences in their gate operations.

[0095] To alleviate this, disclosed herein is a hybrid compilation routine that alternates between different topology, routing, and simplification passes. More specifically, the disclosed method compiles an initial circuit using three distinct procedures. 1. Run the vanilla approach using topology path A, routing path A, and simplified path sequence A ("routine A"). 2. Run the vanilla approach using topology path B, routing path B, and simplified path sequence B ("routine B"). 3. Run the vanilla approach "M" times sequentially, passing the output of routine A to routine B, and returning until convergence (a "hybrid routine"). 4. Avoid parallelizing certain gates when necessary.

[0096] In a hybrid approach, the disclosed method alternates between two different sets of paths, which alone may only be moderately effective. However, by operating them back and forth, the disclosed method effectively exposes them to different initial conditions (topologies, formats, and gates) each time. This allows the disclosed method to extract as much benefit as possible from each path. The final step is performed in the case of strong crosstalk, where the application of two gates simultaneously has a much lower quality than a conservative individual implementation of the two gates.

[0097] Once the disclosed method runs all three of these routines, the method uses a heuristic to select the "best" based on the number of two-qubit operations in each circuit. This approach allows for the selection of an optimally compiled circuit every time, independent of the algorithm and device. A comparison of the three different routines is provided in FIG. 8 for QFT. The selected circuit is finally embedded with the DD motif described above, using a custom set of "decoupling paths".

[0098] Automated full device gate optimization and calibration Quantum gates are the building blocks of any quantum circuit. Maintaining a consistently high quality (low error) set of base gates is a challenge facing all hardware providers. Reducing gate error can be achieved by manipulating a set of accessible experimental control probes. The exact details depend on the hardware details.

[0099] The disclosed method can provide a low-level implementation of a quantum gate based solely on measured system responses, without requiring a priori knowledge of the specific device model or its underlying error process.

[0100] The black-box optimization protocol is based on a series of iterative experiments in which the disclosed method extracts gate errors from an error amplification protocol. One such protocol fits the estimated average infidelity versus the number of gate iterations N. For each value of N, the method performs N iterations of the gate under test with two or more different initial states. batch For example, the method evaluates the quality of a particular CX gate implementation by applying it to initial states |+0> and |+1>.

[0101] After each operation, a full-state tomography is performed and an estimate of the misfidelity relative to the ideal target state is calculated. By applying a linear fit to the average misfidelity as a function of N, an effective measure of the error per gate is extracted, which provides a measure of the gate error at the lower error limit.

[0102] The above procedure constructs a cost function that assigns a quality measure to a particular gate implementation. This is not the only approach to determining the error, and measurement routines such as randomized benchmarks, gate set tomography, etc. may be incorporated to construct the cost function. An automated optimization procedure is designed to interact with the system to generate better gate implementations. Details can be found in Y. Baum, M. Amico, S. Howell, M. Hush, M. Liuzzi, P. Mundada, T. Merkh, ARCarvalho, and M. J Biercuk, Experimental deep reinforcement learning for error robust gate-set design on a superconducting quantum computer, PRX Quantum 2, 040324 (2021). In particular, the method uses a form of optimization such as deep reinforcement learning to design a universal set of quantum logic gates that are error-robust at runtime without requiring knowledge of a particular Hamiltonian model of the system, its control, or its underlying error handling. More specifically, the method applies closed-loop control techniques such as autonomous deep reinforcement learning to discover the best control signals to drive the state evolution through iterative interactions with a quantum computer. This provides new waveforms that define a universal gate set that outperforms human-designed solutions. Because the control design process involves direct hardware measurements, all error sources known to a human operator, including leakage, dephasing, crosstalk, RF signal miscalibration, and distortion, are captured in the optimized control.

[0103] The above procedure is applied to pairs of qubits. In general, different pairs that do not share a qubit can be optimized in parallel. In the presence of strong crosstalk effects, it may be beneficial to avoid parallel optimization of adjacent pairs. The method automatically partitions the device into sets of qubit pairs that can be optimized in parallel. Such a partition is depicted in FIG. 9, where 16 pairs are partitioned into four groups due to strong crosstalk effects. This is an exemplary grouping based on the connectivity of an exemplary device. The gates between pairs in each group are optimized in parallel.

[0104] Additional feature estimation routines can be operated to learn about device error sources and noise processes to directly or indirectly inform the gate optimization routines. This can include noise feature estimation or Hamiltonian parameter estimation processes that are useful in informing the definition of a cost function for the optimization.

[0105] Overall Benefits Summary The disclosed method implemented as a software package is hardware and algorithm type agnostic. Given any algorithm and hardware characteristics, such as device topology, connectivity, and back-end data on qubit quality, the disclosed method improves the performance of the algorithm by employing the methods disclosed herein. Other preliminary experiments, such as crosstalk analysis or noise spectroscopy, can be automatically added to achieve further performance improvements. The method includes optimized system-aware compilation, optimal DD embedding, full device gate calibration / optimization, and scalable measurement error mitigation. Figure 10 compares the success probability of the Bernstein-Vazirani algorithm on a 16 qubit device. In this comparison, we compare our automated software tool with the best compilation, DD scheme, and measurement error mitigation available by the hardware provider.

[0106] How to generate error-corrected quantum circuits 11 shows a method 1100 for generating an error-corrected quantum circuit. The method 1100 includes compiling 1101 a quantum algorithm into quantum hardware using a plurality of qubits to generate a quantum circuit. As discussed above, this involves mapping the quantum algorithm to a set of native gates in the quantum hardware and replacing the native gates with error-corrected gates using measurements of previous characterizations.

[0107] The method 1100 then includes determining (1102) quantum relationships (e.g., couplings) between the qubits and between the qubits and the external environment as a result of implementing the quantum circuit in the quantum hardware. This may involve, for example, determining pairs of gates that exhibit crosstalk between them. This may also involve measurements to characterize errors expected to occur as a result of interactions with the environment. This quantum relationship may lead to errors that are specific to the given quantum hardware and to the quantum circuit as produced in the compilation step, because compilation defines which gates are close to each other and the actions applied to adjacent qubits, which may lead to crosstalk. Further details are described above.

[0108] The method 110 then includes determining 1103 a deterministic error correction protocol for each of the plurality of qubits and for interactions between the plurality of qubits using the quantum relationships among the plurality of qubits and between the plurality of qubits and the external environment. For example, as described with reference to Figures 1 and 2, the deterministic error correction includes coincidence gates and time shifts to optimize the correction of ZZ errors, as well as error-robust quantum gates optimized for qubit pairs and individual qubits.

[0109] How to characterize the error

[0013] Figure 12 shows a method 1200 for characterizing errors in quantum hardware including multiple qubits. This can be viewed as a more detailed version of step 1102 of Figure 11. Method 1200 provides a measured system response without requiring a priori knowledge of a particular device model or its underlying process. That is, method 1200 is part of a black-box optimization method, where the actual quantum hardware is treated as a black box with minimal knowledge of how the quantum hardware is constructed.

[0110] Method 1200 includes determining 1201 groups of qubits to minimize inter-group correlation based on the topology of the quantum hardware, and then performing 1202 multiple measurements to approximate a confusion matrix for individual qubit readouts. Method 1200 includes repeating the multiple measurements on the qubit groups to determine an error signature of the hardware. In some embodiments, the above procedure is applied to pairs of qubits. In general, different pairs that do not share qubits can be optimized in parallel, as shown in FIG.

[0111] How to compile Figure 13 shows a method 1300 of compiling a quantum algorithm onto quantum hardware having a native gate set. The method 1300 includes steps 1301 of performing a first compilation process to map the quantum algorithm onto quantum hardware and a native gate set, and 1302 of using an output of the first compilation process as an input to perform a second compilation process, different from the first compilation process, performing the iterative steps to maximize the use of low-error qubits identified by the error characterization process described above with reference to Figures 8a and 8b.

[0112] Quantum error correction method FIG. 14 illustrates a method 1400 of quantum error correction of quantum hardware as described above with reference to the DD motif. The method 1400 includes dividing qubits of the quantum hardware into groups based on the topology of the quantum hardware (1401). The method 1400 then includes dividing the qubits into blocks based on the quantum circuits compiled into the quantum hardware (1402). The method 1400 further includes applying driving single qubit operations to correct quantum errors occurring during a coincidence operation that depends on the quantum circuits compiled into the quantum hardware (1403). Finally, the method 1400 includes determining a time shift of the driving single qubit operations to correct mutual coupling for each of the groups and blocks during the coincidence operation and suppress decoherence (1404), as described with reference to FIG. 1 and FIG. 2.

[0113] Additional error correction may be achieved using gates that have been optimized for error robustness using the aforementioned methods. More specifically, a method of gate set optimization for quantum hardware is provided. The method includes performing measurements on the quantum hardware to determine a quality measure for the gate implementation on the quantum hardware. The method then includes applying an optimization procedure to iteratively adjust the gate characteristics and repeating the measurements to move toward reducing the error of the quantum gate. The gate characteristics may involve waveforms for controlling qubits in the quantum hardware. The method may further include performing an optimization procedure to define a universal gate set. Additionally, the measurements are representative of multiple error sources such as leakage, dephasing, crosstalk, miscalibration of the RF signal, and distortion. Additionally, the measurement and optimization procedure may be applied to the quantum hardware without knowledge of the details of the quantum hardware such as the actual Hamiltonian of the physical device.

[0114] Error correction compilation method 15 illustrates a method 1500 of error-corrected compilation to correct error sources identified in the error signature process. The method includes receiving 1501 a compiled circuit and a gate set compatible with the error signature and hardware device topology, and replacing 1502 quantum logic gates in the compiled circuit that have uncorrected errors above a tolerance threshold, derived using the error signature process, with error-calibrated alternatives. Finally, the method 1500 includes outputting 1503 a definition of the circuit including all replacement gate definitions in a format for hardware implementation including matched and non-matched operations.

[0115] Method for correcting errors in quantum measurements 16 shows a method 1600 for correcting errors in quantum measurements of a quantum circuit on quantum hardware. The method 1600 includes receiving 1601 a measurement result, and reducing 1602 a tensor based on a group of qubits using an approximated confusion matrix from the error signature evaluation. The method 1600 then includes converting 1603 the tensor to a probability distribution, and correcting 1604 the error in the quantum measurement as indicated by the probability distribution. Finally, the method 1600 includes outputting 1605 a measurement error correction result.

[0116] Internet Server 17 shows an Internet server 1700, which is a computer system connected to the Internet and which transmits and receives data to various other computer systems via the Internet. In particular, the Internet server 1700 is connected through the Internet to user client computers and quantum hardware interface computers. The Internet server 1700 is a classical digital electronic computer system, and includes a processor 1701, program memory 1702, data memory 1703, and communication ports 1704.

[0117] The program memory 1702 is a non-volatile computer-readable medium that stores program code that, when executed by the processor 1701, causes the processor to perform the methods disclosed in this specification, including the methods disclosed in Figures 11-16.

[0118] The internet server 1700 is configured by program code installed in the program memory 1702 to provide or expose a web interface. The web interface comprises input elements for inputting quantum algorithms and quantum hardware characterizations. The web interface may be a graphical user interface with graphical input elements for data entry or file upload, or may be an application programming interface (API) with syntactic input elements such as XML or JSON fields.

[0119] Thus, internet server 1700 is configured to receive, via a web interface, an incomplete description of the quantum algorithm and the quantum hardware. The quantum algorithm and incomplete description may be provided by the same user, by different users, or the incomplete description may be provided by a vendor or provider of the quantum hardware. The description is considered "incomplete" because it includes an abstract description of the quantum hardware (such as a native gate set), but does not include error characterizations of individual gates or circuit blocks.

[0120] Thus, internet server 1700 is further configured to perform error characterization on the target quantum hardware, e.g., from data memory 1703, or to retrieve a previously performed error characterization. The error characterization may involve communication with the quantum hardware to initiate qubits having quantum values ​​as described above, perform quantum operations, receive measurements, and characterize errors.

[0121] The internet server 1700 is further configured to generate decorated quantum circuit descriptions that implement the quantum algorithms in quantum hardware. "Decorated" in this context means that the quantum circuit includes quantum gates as well as control protocols for error correction. Additionally, the decorated quantum circuit description includes quantum logic blocks that are error corrected based on error characterization, as described above as gate calibration.

[0122] The internet server 1700 is further configured to output the quantum circuit description. This may be done to a user so that the user can send the description to quantum hardware for implementation. In another example, the internet server 1700 sends the description directly to quantum hardware, such as to a hardware provider's API, for immediate implementation.

[0123] Once the quantum algorithms are executed on the quantum hardware, the internet server 1700 receives the raw output data from the quantum hardware and analyzes it using full characterization, including the measurement error correction described above.

[0124] As a result of the methods disclosed herein, deterministic error correction protocols are applied to quantum hardware and error correction gates are used in conjunction with measurement error correction, which in combination lead to significant reductions in error rates that were previously unattainable.

[0125] It will be understood by those skilled in the art that numerous variations and / or modifications may be made to the above-described embodiments without departing from the broad general scope of the present disclosure, and the present embodiments are therefore to be considered in all respects as illustrative and not restrictive. [Explanation of symbols]

[0126] 1700 Internet Server 1701 Processor 1702 Program Memory 1703 Data Memory 1704 communication port

Claims

1. receiving an incomplete description of a quantum algorithm and quantum hardware; performing an error characterization or retrieving a previously performed error characterization for the target quantum hardware; generating an initial quantum circuit description for implementing the quantum algorithm on the quantum hardware; generating an embellished quantum circuit description based on the initial quantum circuit description, the embellished quantum circuit description including quantum logic blocks that are error-corrected based on the error characteristic evaluation; generating error characteristic estimates that are specific to the initial quantum circuit description and to the quantum hardware; outputting a quantum circuit description; receiving raw output data from said quantum hardware and analyzing it using full characterization; A method comprising:

2. 2. The method of claim 1 , wherein the step of generating an initial quantum circuit outputs adjacent qubits and actions applied to the adjacent qubits, and the error feature evaluation is indicative of crosstalk between the adjacent qubits as a result of the actions applied to the adjacent qubits.

3. compiling the quantum algorithm into quantum hardware using a plurality of qubits to generate a quantum circuit; determining quantum relationships among the plurality of qubits and between the plurality of qubits and an external environment as a result of implementing the quantum circuit in the quantum hardware; using the quantum relationships between the qubits and between the qubits and an external environment to determine a deterministic error correction protocol for each of the qubits and for interactions between the qubits, the deterministic error correction protocol being specific to the quantum circuit and specific to the quantum hardware; The method of claim 1 or 2, further comprising:

4. 4. The method of claim 1, further comprising the step of performing a plurality of measurements on qubits of the quantum hardware to determine an error signature of the quantum hardware based on a topology of the quantum hardware.

5. 5. The method of claim 3 or 4, wherein the error characterization includes one or more of individual gate errors based on the topology of the quantum hardware, decoherence processing, measurement errors, and crosstalk between qubits.

6. The method of any one of claims 3 to 5, wherein compiling comprises selecting one or more quantum blocks for each of a plurality of logical quantum operations in the quantum algorithm to implement the quantum algorithm on the quantum hardware, each of the quantum blocks implementing a logical function of that logical quantum operation.

7. 7. The method of claim 3, further comprising: determining an error correction protocol for each of the quantum blocks, the error correction protocol including error correction for errors identified in the error characterization and specific to one or more selected quantum blocks for implementing the quantum algorithm.

8. 8. The method of claim 3, further comprising: executing the quantum algorithm on the quantum hardware using selected quantum blocks and the deterministic error correction protocol to obtain qubit measurements.

9. 9. The method of claim 3, further comprising: performing a step of reducing a measurement error in the qubit measurements by applying an error reduction operation based on the error characteristic estimate.

10. determining groups of qubits based on a topology of the quantum hardware to minimize correlation between groups; performing multiple measurements to approximate a confusion matrix for the readout of individual qubits; 10. The method of claim 1, further comprising: characterizing an error in quantum hardware comprising a plurality of qubits by performing a step of: repeating the measurements on the group of qubits to determine the error characterization of the hardware.

11. The method of claim 10 , wherein the group of qubits comprises qubit pairs having low mutual coupling between the pair.

12. The method of claim 10 or 11, wherein the error characterization comprises one or more of individual gate fidelity, noise spectrum, and crosstalk intensity.

13. The method of any one of claims 10 to 12, further configured to perform the step of using machine learning to automate the determining of the error signature estimate.

14. 14. The method of claim 10, further comprising performing the step of optimizing parameters of a quantum gate using the qubits to maximize the fidelity of the quantum gate.

15. 15. The method of any one of claims 10 to 14, wherein fidelity is maximized for gates where qubits in the group are in parallel.

16. Quantum algorithms on quantum hardware with native gate sets, performing a first compilation process to map the quantum algorithm to the quantum hardware and the native gate set; using an output of the first compilation process as an input to perform a second compilation process, different from the first compilation process, to maximize usage of low-error qubits identified by an error characterization process; The method of any one of claims 1 to 15, further comprising compiling by repeatedly executing:

17. dividing qubits of the quantum hardware into groups based on a topology of the quantum hardware; dividing the qubits into blocks based on a quantum circuit compiled into the quantum hardware; applying a driving single qubit operation to correct for quantum errors occurring during a coincidence operation that relies on the quantum circuit compiled into the quantum hardware; determining a time shift of the driving single qubit operation to compensate for mutual coupling and suppress decoherence for each of the groups and blocks during a coincidence operation; The method of any one of claims 1 to 16, further configured to perform quantum error correction of the quantum hardware by executing:

18. 20. The method of claim 17, further comprising performing the step of redefining a non-coincident operation to compensate for an error process identified via error characteristic evaluation via a time domain modulation of a control signal used to implement the non-coincident operation.

19. 19. The method of claim 17 or 18, further configured to perform the step of time modulating the control signals in the plurality of qubits in a continuous or discontinuous manner.

20. 20. The method of any one of claims 17 to 19, further comprising performing the step of assembling the blocks from a library of error-corrected quantum gates based on error characterization.

21. receiving a compiled circuit compatible with the hardware device topology and gate set; replacing quantum logic gates in the compiled circuit having uncorrected errors above a tolerance threshold with error-corrected alternatives derived using an error characterization process; outputting a definition of said circuit having all permutation gate definitions in a format for hardware implementation including match and non-match operations; 21. The method of claim 1, further comprising: performing an error correction compilation to correct error sources identified in the error characterization process by performing:

22. identifying non-matching gates that are prone to errors; replacing error-prone non-matched gates with auto-calibrated gates; replacing the coincidence gates in the compiled quantum circuit with error-corrected coincidence gates that include an error correction protocol; assembling an output error robust circuit including the auto-calibrated gate and the error corrected coincidence gate into a circuit representation for implementation on the quantum hardware; 22. The method of claim 21, further configured to perform:

23. The error in the quantum measurement of a quantum circuit on quantum hardware is receiving a measurement result; using the approximated confusion matrix from the error feature estimates to reduce a tensor based on the groups of qubits; converting the tensor into a probability distribution; correcting the error in the quantum measurement as indicated by the probability distribution; outputting a measurement error correction result; The method of any one of claims 1 to 22, further comprising:

24. partitioning the quantum circuit into groups of qubits to minimize inter-group correlation based on a topology of the quantum hardware; 24. The method of claim 23, further configured to perform the step of: reordering the tensors based on the groups of qubits.

25. 25. The method of claim 24, further configured to perform the step of adding a dimension to a tensor of unmeasured qubits.

26. The method according to any one of claims 23 to 25, further comprising the step of applying a neural network to the measurements based on an error feature estimate to restore correlations ignored by tensor reduction.

27. 1. An internet server comprising: providing a web interface including input elements for inputting quantum algorithms and quantum hardware characterizations; receiving, via the web interface, an incomplete description of the quantum algorithm and the quantum hardware; Performing an error characterization or retrieving a previously performed error characterization for the target quantum hardware; generating an decorated quantum circuit description for implementing the quantum algorithm on the quantum hardware, the decorated quantum circuit description including quantum logic blocks that are error corrected based on the feature evaluation; Outputting the quantum circuit description; Receive raw output data from the quantum hardware and analyze it using full characterization. An Internet server that is configured to:

28. outputting the quantum circuit description, transmitting the decorated quantum circuit description to a user via the web interface; or 28. The internet server of claim 27, further comprising: transmitting the decorated quantum circuit description to the quantum hardware for execution on the quantum hardware.

29. receiving and analyzing the raw output data; receiving the raw output data from the user via the web interface for analysis; or 29. The internet server of claim 27 or 28, further comprising: receiving the raw output data from the quantum hardware for analysis.

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