Phase-change memory cells with twice the active volume

Abstract

a first phase change material layer vertically aligned over the bottom electrode, a dielectric layer vertically aligned over the first phase change material layer, a second phase change material layer vertically aligned over the dielectric layer, an internal electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the internal electrode being surrounded by the dielectric layer, a top electrode vertically aligned over the second phase change material layer, a first phase change material layer vertically aligned over the bottom electrode, a filament layer vertically aligned over the first phase change material layer, a second phase change material layer vertically aligned over the filament layer, an internal break in the filament layer connecting the first phase change material layer and the second phase change material layer, and a top electrode vertically aligned over the second phase change material layer.

Description

[Technical field]

[0001] The present invention relates generally to phase change memory cells, and more particularly to a phase change memory cell having double active volume. [Background technology]

[0002] Phase change memory cells can be used for data storage. Phase change memory cells are non-volatile random access memories. A typical configuration of a phase change memory cell can include a phase change material disposed between and coupled to at least two electrodes. When a phase change memory cell is in use, the phase change material can be operated in one of at least two reversibly convertible phases: amorphous and crystalline. The amorphous and crystalline phases are distinct from one another. In the amorphous phase, the phase change material has a visibly higher resistance compared to the crystalline phase. To facilitate the phase transition, energy capable of achieving the desired phase transition is supplied to the phase change material, such as electrical energy, thermal energy, any other suitable form of energy or a combination thereof. Summary of the Invention

[0003] According to one embodiment of the present invention, a structure is provided, which may include a first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an internal electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the internal electrode being surrounded by the dielectric layer, and a top electrode vertically aligned above the second phase change material layer.

[0004] A further embodiment in which the lateral diameter of the inner electrode is smaller than the lateral diameter of the bottom electrode.An embodiment further comprising a first projection liner vertically aligned between the first phase change material layer and the dielectric layer and a second projection liner vertically aligned between the second phase change material layer and the dielectric layer.An embodiment further comprising a first thermal barrier layer vertically aligned between the first phase change material layer and the dielectric layer and a first thermal barrier layer vertically aligned between the second phase change material layer and the dielectric layer.An embodiment further comprising a first adhesion layer vertically aligned between the first phase change material layer and the dielectric layer and a first adhesion layer vertically aligned between the second phase change material layer and the dielectric layer.

[0005] According to one embodiment of the present invention, there is provided a structure including a first phase change material layer aligned over a first portion of an internal electrode, a first external electrode vertically aligned over the first phase change material layer, a second phase change material layer aligned over a second portion of the internal electrode, a second external electrode vertically aligned over the second phase change material layer, and a dielectric layer vertically separating the first phase change material layer and the first external electrode from the second phase change material layer and the second external electrode, both physically and electrically.

[0006] According to one embodiment of the present invention, there is provided a structure including a first phase change material layer aligned over a first external electrode, an internal electrode physically and electrically connected between the first phase change material layer and a second phase change material layer, a second external electrode vertically aligned over the second phase change material layer, and a dielectric layer vertically physically and electrically separating the first phase change material layer and the first external electrode from the second phase change material layer and the second external electrode.

[0007] According to one embodiment of the present invention, a structure is provided, including a first phase change material layer vertically aligned over a bottom electrode, a filament layer vertically aligned over the first phase change material layer, a second phase change material layer vertically aligned over the filament layer, an internal break in the filament layer connecting the first and second phase change material layers, and a top electrode vertically aligned over the second phase change material layer.

[0008] Further embodiments, in which the filament layer comprises a high-k dielectric. One embodiment, in which the filament layer comprises a mixed ionic-electronic conducting filament. One embodiment, in which the filament layer further comprises a first liner vertically aligned between the first phase change material layer and the filament layer, and a second liner vertically aligned between the second phase change material layer and the filament layer. One embodiment, in which the first liner and the second liner are each projection layers. One embodiment, in which the first liner and the second liner are each thermal barrier layers. One embodiment, in which the first liner and the second liner are each adhesion layers. One embodiment, in which the filament layer further comprises a first liner vertically aligned between the first phase change material layer and the bottom electrode, and a second liner vertically aligned between the second phase change material layer and the top electrode. One embodiment, in which the first liner and the second liner are each projection layers. One embodiment, in which the first liner and the second liner are each thermal barrier layers. In one embodiment, the first liner and the second liner are each an adhesive layer.

[0009] According to one embodiment of the present invention, a method is provided, which may include forming a first phase change material layer on a bottom electrode, forming a dielectric layer on the first phase change material layer, forming an internal electrode in the dielectric layer, forming a second phase change material layer on the dielectric layer, where the internal electrode is physically and electrically connected to both the first phase change material layer and the second phase change material layer, and forming a top electrode on the second phase change material layer.

[0010] A further embodiment further comprising providing a high voltage pulse to the dielectric layer to form the internal electrodes, the dielectric layer having a dielectric constant of 5.0 or greater.One embodiment further comprising resetting the structure to an amorphous phase by applying a current to the internal electrodes.One embodiment further comprising reading the memory state of the structure by applying a voltage between the bottom electrode and the top electrode.

[0011] DETAILED DESCRIPTION The following detailed descriptions are given by way of example and are not intended to be merely limiting of the invention, and are best understood in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0012] [Figure 1] 1A-1D are cross-sectional views of a semiconductor structure at an intermediate stage of fabrication in accordance with an illustrative embodiment. [Diagram 2] 4A-4C are cross-sectional views of a semiconductor structure illustrating depositing a first external electrode and forming a first phase change material layer according to an exemplary embodiment. [Diagram 3] 1A-1C are cross-sectional views of a semiconductor structure illustrating patterning of internal electrodes according to exemplary embodiments. [Figure 4] 4A-4C are cross-sectional views of a semiconductor structure illustrating forming a second phase change material layer and forming a second external electrode according to an exemplary embodiment. [Diagram 5] 1A-1C are cross-sectional views of a semiconductor structure illustrating selective removal of portions of the semiconductor structure in accordance with an exemplary embodiment. [Figure 6] 1 is a cross-sectional view of a semiconductor structure illustrating depositing a dielectric and a top contact in accordance with an exemplary embodiment. [Figure 7] FIG. 7 illustrates a cross-sectional view of the semiconductor structure of FIG. 6, illustrating a symmetric amorphous configuration, in accordance with an exemplary embodiment. [Figure 8] 4A-4C are cross-sectional views of a second semiconductor structure at an intermediate stage of fabrication in accordance with an illustrative embodiment. [Figure 9]4 is a cross-sectional view of a second semiconductor structure illustrating forming a liner, forming a second phase change material layer, and forming a second external electrode in accordance with an exemplary embodiment. [Figure 10] 1 is a cross-sectional view of a second semiconductor structure illustrating selective removal of portions of the semiconductor structure in accordance with an exemplary embodiment. [Figure 11] 4 is a cross-sectional view of a second semiconductor structure illustrating depositing a dielectric and a top contact according to an exemplary embodiment. [Figure 12] FIG. 12 illustrates a cross-sectional view of the second semiconductor structure of FIG. 11 in accordance with an exemplary embodiment, illustrating a symmetric amorphous configuration. [Figure 13] FIG. 2 is a cross-sectional view of a third semiconductor structure according to one embodiment. [Figure 14] FIG. 2 is a cross-sectional view of a fourth semiconductor structure according to one embodiment. [Figure 15] FIG. 13 is a cross-sectional view of a fifth semiconductor structure according to one embodiment. [Figure 16] FIG. 13 is a cross-sectional view of a sixth semiconductor structure according to an embodiment. [Figure 17] FIG. 13 is a cross-sectional view of a seventh semiconductor structure according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. Within the drawings, like numbers refer to like elements.

[0014] Although detailed embodiments of the claimed structures and methods are disclosed, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the present description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0015] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," and "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, and that an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0016] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for presentation and illustration purposes, and in some instances may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the unique features or elements of various embodiments of the present invention.

[0017] FIELD OF THE DISCLOSURE Embodiments of the present invention relate generally to phase change memory cells, and more particularly to phase change memory cells having double active volume.

[0018] As mentioned above, a typical configuration of a phase change memory cell may include a phase change material disposed between and coupled to at least two electrodes. The bottom contact and the top contact may each be connected to one of the two electrodes. The phase change material may be used as a phase change memory to store data by controlling the resistance state of the phase change material. A low resistance state causes the phase change material to be fully crystalline. A high resistance state causes the phase change material to be amorphized. The phase change material may be amorphized by providing the phase change material with energy that can achieve a desired phase transition, such as electrical energy, thermal energy, any other suitable form of energy or a combination thereof. For example, a current pulse may be applied to either of the two electrodes from either the top or bottom contact, which may be referred to as a heater electrode. For more than two memory states, such as for analog computing, the amount of amorphous volume may be controlled for a range of resistance states that may be programmed.

[0019] When a phase change material is energized to change to an amorphous state, the portion of the phase change material that becomes amorphous typically expands into a "mushroom shape" starting from where the current pulse is applied and into the amorphous state. This results in a semicircular or mushroom shaped portion of the phase change material that is amorphous and the remaining portion of the phase change material that is crystallized. This memory cell may be referred to as a mushroom cell. Mushroom cells exhibit read bias polarity asymmetry. Measuring the resistance of a mushroom cell may vary depending on the polarity of the read voltage applied, resulting in different values. The polarity dependence of mushroom cells limits the speed, power efficiency, and accuracy of neuromorphic computing using phase change memory cells. Neuromorphic computing or neuromorphic engineering is used in artificial intelligence.

[0020] Additionally, the bottom electrode or heater of the phase change material needs to be made as small as possible with good repeatability to allow high current flux and to minimize the overall programming current required to reset the phase change material to the highly resistive amorphous state.

[0021] To solve these problems, a physically symmetric mushroom cell device is proposed. The physically symmetric mushroom cell device has little to no polarity dependence due to its symmetric amorphous configuration, and reduces programming current due to improved thermal confinement from the phase change material both above and below the heater electrode, and reduces power consumption during analog computing due to the higher SET / RESET resistance of the structure changing between amorphous and crystalline states. Both the SET and RESET resistances can be up to twice that of a single active area device. These resistances can be tuned by changing the thickness of the phase change material layer.

[0022] In the present invention, a first phase change material layer may be formed, a dielectric layer with an internal electrode may be formed, and a second phase change material layer may be formed. The additional layers of the internal electrode and second phase change material layer improve heat confinement from the phase change material both above and below the internal electrode, resulting in a physically symmetric mushroom cell device with reduced programming current and reduced power consumption during analog computing. The internal electrode may be referred to as a heater electrode. The physically symmetric mushroom cell device allows for bidirectional read operations such that individual cells may be read in either direction, saving time and power in reading the device.

[0023] In one embodiment, a first liner is formed between the first phase change material layer, the dielectric layer and the internal electrode layer, and a second liner is formed between the dielectric layer, the internal electrode layer and the second phase change material layer.

[0024] In one embodiment, a filament layer can be formed between the first and second phase change material layers, and a portion of the filament layer can be broken to form a contact between the first and second phase change material layers, similar to an internal electrode.

[0025] In one embodiment, a first liner is formed between the first phase change material layer and the filament layer, and a second liner is formed between the filament layer and the second phase change material layer.

[0026] In one embodiment, a first liner is formed between the first phase change material layer and the first external electrode, and a second liner is formed between the second external electrode and the second phase change material layer.

[0027] The liner may include one or more layers and may include a thermal barrier layer, an adhesion layer, and a projection liner to reduce programming current and drift.

[0028] The internal electrodes and filament layers may each be considered as atomically thin heaters that help reduce the programming current of the individual cells. The integration of the internal electrodes or filament layers helps provide a symmetric read of the individual cells independent of the read polarity. In artificial intelligence applications, the resistance of the device corresponds to a weight that may be positive or negative. The positive component of the weight for the device may be labeled G+ and the negative component of the weight for the device may be labeled G-. If the devices have no asymmetry, both devices may be read simultaneously by applying a positive voltage to one device and a negative voltage to the other device, causing the currents to cancel out. This may improve the speed and energy efficiency of the architecture.

[0029] The internal electrode and filament layers may offer easier integration, avoiding the unusual heater mask by using a filament instead of a patterned heater. Normally, when a heater via is patterned into the dielectric, some gouge is left in the material underneath. In this structure, it may damage the bottom PCM layer. Instead of patterning the heater, when the dielectric is exposed to a large electric field, it may cause a dielectric breakdown and form a conductive filament through the dielectric. This effectively creates a very narrow heater without the need to explicitly pattern a via.

[0030] The internal electrode and filament layers each provide a self-aligning feature when forming these layers, making these manufacturing steps easier to perform.

[0031] A method for forming a phase change memory cell having double active volume according to an illustrative embodiment is described in detail below with reference to the accompanying drawings in FIGS.

[0032] 1, a semiconductor structure (hereafter "structure") 100 is shown at an intermediate step in fabrication, according to one embodiment. Structure 100 includes a stack of layers formed on a substrate 102, which are subsequently patterned into individual cells. Structure 100 includes, for example, substrate 102, dielectric layer 104, and bottom contact 106.

[0033] Substrate 102 may be, for example, a silicon substrate with connections and structures, such as transistors and isolation, built thereon. For example, substrate 102 may be a bulk substrate that may be made from any of several known semiconductor materials, such as, for example, silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Typically, substrate 102 may be on the order of several hundred microns thick, but is not limited thereto.

[0034] The dielectric layer 104 may be deposited on the structure 100 as a blanket layer using any known deposition technique, such as, for example, chemical vapor deposition, atomic layer deposition, physical layer deposition, or some combination thereof. The dielectric layer 104 may include a material such as, for example, an oxide, a nitride, or some combination thereof. In one embodiment, the dielectric layer 104 may include an oxide, such as silicon oxide. In an alternative embodiment, the dielectric layer 104 may include a nitride, such as silicon nitride. Chemical mechanical planarization techniques may optionally be used to polish the dielectric layer 104 to provide a substantially smooth and uniform surface in preparation for subsequent processing techniques.

[0035] A conductive material layer of the bottom contact 106 is deposited in a groove (not shown) formed in the dielectric layer 104. The bottom contact 106 may be formed from a conductive material layer such as, for example, copper, tungsten, cobalt, or aluminum. The conductive material layer may be deposited using typical deposition techniques, for example, atomic layer deposition, molecular layer deposition, and chemical vapor deposition. In one embodiment, the bottom contact 106 may have a thickness ranging from about 10 nm to about 100 nm, although thicknesses less than 10 nm and greater than 100 nm may also be acceptable. A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 to provide a uniform horizontal surface.

[0036] 2, a structure 100 is shown according to one embodiment. A first external electrode 110 and a first phase change material layer 112 may be formed.

[0037] The conductive material layer of the first external electrode 110 may be blanket deposited over the structure 100, i.e., over the bottom contact 106 and over the dielectric layer 104. The first external electrode 110 may be formed as described for the bottom contact 106. The first external electrode 110 may alternatively be deposited in a groove on the structure 100.

[0038] The first phase change material layer 112 may be blanket deposited on the structure 100 directly on the top surface of the conductive material layer of the first external electrode 110. Conventional deposition processes such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, or a combination of methods may be used to deposit the first phase change material layer 112 on the first external electrode 110. According to an embodiment of the present invention, the first phase change material layer 112 may be formed from a mixture of gallium (Ga) and antimony (Sb), and at least one of tellurium (Te), silicon (Si), germanium (Ge), arsenic (As), selenium (Se), indium (In), tin (Sn), bismuth (Bi), silver (Ag), gold (Au), and antimony (Sb). It should be understood that the above list is merely illustrative, and thus other elements may also be used to form the first phase change material layer 112 while maintaining the spirit of the principles disclosed herein. In one embodiment, the first phase change material layer 112 may be made of a chalcogenide alloy, such as germanium antimony tellurium (GST). According to another embodiment, the first phase change material layer 112 may also be made of a transition metal oxide having multiple resistance states. For example, the first phase change material layer 112 may be made of at least one material selected from the group consisting of NiO, TiO2, HfO, Nb2O5, ZnO, WO3, and CoO or GST (Ge2Sb2Te5) or PCMO (PrxCa1-xMnO3). In yet another embodiment, the first phase change material layer 112 may be a compound including one or more elements selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), germanium (Ge), tin (Sn), indium (In), and silver (Ag). In one embodiment, first phase change material layer 112 may have a thickness ranging from about 10 nm to about 100 nm, although thicknesses less than 10 nm and greater than 100 nm are also acceptable.

[0039] A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of structure 100 to provide a uniform, level surface.

[0040] 3, a structure 100 is shown, according to one embodiment. A dielectric layer 120 and an internal electrode 122 may be formed.

[0041] A dielectric layer 120 is formed over the first phase change material layer 112 and may be formed in a manner similar to that described for the dielectric layer 104. An opening (not shown) may be formed in the dielectric layer 120 to expose a portion of a top surface of the first phase change material layer 112. The opening may be formed by methods known in the art. An internal electrode 122 may be formed in the opening (not shown). The internal electrode 122 may be formed in a manner similar to that described for the first external electrode 110. The internal electrode 122 may be referred to as a heater element.

[0042] A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 to provide a uniform, level surface for the internal electrodes 122 and the dielectric layer 120 .

[0043] 4, a structure 100 is shown, according to one embodiment. A second phase change material layer 130 and a second external electrode 110 may be formed.

[0044] A second phase change material layer 130 may be formed as described for first phase change material layer 112 over internal electrode 122 and dielectric layer 120. A second outer electrode 132 is formed over second phase change material layer 130 and may be formed as described for first outer electrode 110.

[0045] A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 to provide a uniform, level surface for the second external electrode 132 .

[0046] 5, a structure 100 is shown according to one embodiment. The structure 100 can be patterned into individual cells.

[0047] After the above-mentioned layers and materials are formed or deposited, they are patterned into individual cells as shown. The individual cells may be formed using patterning techniques known in the art. More specifically, a portion of the second external electrode 132, a portion of the second phase change material layer 130, a portion of the dielectric layer 120, a portion of the first phase change material layer 112, and a portion of the first external electrode 110 may be selectively removed using anisotropic etching techniques, such as, for example, reactive ion etching. A cell may include vertically aligned portions of the second external electrode 132, the second phase change material layer 130, the dielectric layer 120, the first phase change material layer 112, and the first external electrode 110. Preferably, the top surface of the dielectric layer 104 is exposed as a result of patterning the above-mentioned layers. In general, the footprint of the individual cells is similar to existing phase change memory pillar cells and may be similarly limited based on the function of the phase change memory pillar cells. For example, a typical phase change memory pillar cell may have a lateral width or diameter ranging from about 10 nm to about 200 nm.

[0048] The width or diameter Wa of the inner electrode 122 is substantially smaller than the width or diameter Wb of the first and second outer electrodes 110, 132. In one embodiment, Wa is 5 times smaller than Wb. In one embodiment, Wa may be 5 to 50 times smaller than Wb. In one embodiment, Wa is smaller than Wb of each of the first and second outer electrodes 110, 132. In one embodiment, the first and second outer electrodes 110, 132 may each have a smaller width or diameter than the other.

[0049] 6 and 7, a structure 100 is shown, according to one embodiment. A dielectric layer 140 and a top contact 142 may be formed.

[0050] The dielectric layer 140 may be formed as described for the dielectric layer 104. A second opening (not shown) may be formed in the dielectric layer 140 exposing a portion of the top surface of the second external electrode 132. The second opening may be formed by methods known in the art. The top contact 142 may be formed in the second opening (not shown). The top contact 142 may be formed as described for the bottom contact 106.

[0051] A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 100 to provide a uniform, level surface of the dielectric layer 140 and top contact 142 .

[0052] 7, a portion of each of first phase change material layer 112 and second phase change material layer 130 is shown with a dotted line. The dotted portions indicate mushroom-shaped portions that may be initially amorphized when a current is applied to internal electrode 122 (which may be referred to as a heater electrode).

[0053] A conventional phase change memory cell may include a bottom contact 106, a first external electrode 110 (which may be referred to as a bottom electrode), a first phase change material layer 112, a top electrode directly above the phase change material layer 112, and a top contact on the top electrode. In the present invention, an internal electrode 122 and a second phase change material layer 130 are added between the first phase change material layer 112 and the first external electrode 110 (which may be referred to as a top electrode).

[0054] The additional layers of inner electrode 122 and second phase change material layer 130 provide a physically symmetric mushroom cell device, improving heat containment from the phase change material both above and below the heater electrode, thereby reducing programming currents and reducing power consumption during analog computing.

[0055] It should be noted that although only one cell is shown, structure 100 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0056] 8-12, an alternative embodiment is shown.

[0057] 8, a semiconductor structure (hereafter "structure") 200 is shown at an intermediate step in fabrication, according to one embodiment. Structure 200 includes a stack of layers formed on a substrate 202, which may be subsequently patterned into individual cells. Structure 200 includes, for example, a dielectric layer 204, a bottom contact 206, a first outer electrode 210, a first phase change material layer 212, a first liner 218, a dielectric layer 220, and an inner electrode 222.

[0058] Similar named items, including substrate 202, dielectric layer 204, bottom contact 206, first outer electrode 210 and first phase change material layer 212, dielectric layer 220 and inner electrode 222, are formed as described above.

[0059] The first liner 218 may be a blanket deposited on the first phase change material layer 212. The first liner 218 may include any suitable barrier material known in the art, such as titanium nitride (TiN), tantalum nitride (TaN), cobalt, ruthenium, carbon (C), amorphous carbon, titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), tantalum aluminum carbon (TaAlC), hafnium nitride (HfN), or tungsten nitride (WN), either alone or in combination with other suitable barrier materials. The first liner 218 may also be referred to as an etch stop. This is because when patterning the vias for the internal electrodes 222, the etch used to create the openings for the internal electrodes 222e may stop when it reaches the first liner 218. Thus, even though the first liner 218 has an electrical use due to its conductivity, it may also aid processing by acting as an etch stop.

[0060] The first liner 218 may include one or more layers, including a thermal barrier layer, an adhesion layer, and a projection liner to reduce programming current and drift.

[0061] A dielectric layer 220 is formed over the first liner 218 and may be formed as described for the dielectric layer 104. An internal electrode 222 is formed in a third opening (not shown) in the dielectric layer 220 and may be formed as described for the internal electrode 122. A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of the structure 200 to provide a uniform, level surface.

[0062] 9, a structure 200 is shown according to one embodiment. A second liner 224, a second phase change material layer 230, and a second outer electrode 210 may be formed.

[0063] A second liner 224 may be formed over the dielectric layer 220 and the inner electrode 222. The second liner 224 may be formed as described for the first liner 218. The second outer electrode 210 may be formed over the second liner 224 as described for the first outer electrode 110.

[0064] According to this embodiment, the first liner 218 acts as a barrier that physically separates the first phase change material layer 212 from subsequent layers formed thereon. The second liner 224 acts as a barrier that physically separates the second phase change material layer 230 from the dielectric layer 220 and the inner electrode 222. In one embodiment, the first liner 218 and the second liner 224 may each have a thickness ranging from about 1 nm to about 30 nm, although thicknesses less than 1 nm and greater than 30 nm may be acceptable.

[0065] 10, a structure 200 is shown, according to one embodiment. The structure 200 can be patterned into individual cells.

[0066] After the layers and materials described above are formed or deposited, they are patterned into individual cells as shown. The individual cells may be formed using patterning techniques known in the art. More specifically, a portion of the second outer electrode 232, a portion of the second phase change material layer 230, a portion of the second liner 224, a portion of the dielectric layer 220, a portion of the first liner 218, a portion of the first phase change material layer 212, and a portion of the first outer electrode 210 may be selectively removed using anisotropic etching techniques, such as, for example, reactive ion etching. A cell may include vertically aligned portions of the second outer electrode 232, the second phase change material layer 230, the second liner 224, the dielectric layer 220, the first liner 218, the first phase change material layer 212, and the first outer electrode 210. Preferably, the top surface of the dielectric layer 204 is exposed as a result of patterning the layers described above. In general, the footprint of an individual cell will be similar to existing phase change memory pillar cells and may be similarly limited based on the functionality of the phase change memory pillar cell. For example, a typical phase change memory pillar cell may have a lateral width or diameter ranging from about 10 nm to about 200 nm.

[0067] 11 and 12, a structure 200 is shown, according to one embodiment. A dielectric layer 240 and a top contact 242 may be formed.

[0068] The dielectric layer 240 may be formed as described for the dielectric layer 104. A fourth opening (not shown) may be formed in the dielectric layer 240 exposing a portion of the top surface of the second outer electrode 232. The fourth opening may be formed by methods known in the art. The top contact 242 may be formed in the fourth opening (not shown). The top contact 242 may be formed as described for the bottom contact 106.

[0069] A chemical mechanical polishing (CMP) technique may be used to remove excess material and polish the top surface of structure 200 to provide a uniform, level surface for dielectric layer 240 and top contact 242 .

[0070] 12, a portion of each of first phase change material layer 212 and second phase change material layer 230 is shown with a dotted line. The dotted line portions indicate mushroom-shaped portions that may be initially amorphized when a current may be applied to internal electrode 222 (which may be referred to as a heater electrode).

[0071] The additional layers of inner electrode 222 and second phase change material layer 230 provide a physically symmetric mushroom cell device, improving heat containment from the phase change material both above and below the heater electrode, thereby reducing programming currents and reducing power consumption during analog computing.

[0072] In comparing the structure 100 of Figures 7 and 8 and the structure 200 of Figures 11 and 12, the second liner 224 and the first liner 218 are additional layers of the structure 200. The first liner 218 and the second liner 224 act as barriers that physically separate the first and second change material layers 212, 230 from the dielectric layer 220 and the internal electrode 222, respectively.

[0073] It should be noted that although only one cell is shown, structure 200 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0074] Referring now to FIG. 13, an alternative embodiment is shown.

[0075] 13, a semiconductor structure (hereafter "structure") 300 is shown at an intermediate step in fabrication, according to one embodiment. Structure 300 includes a stack of layers formed on a substrate 302, which may be subsequently patterned into individual cells. Structure 300 includes, for example, a dielectric layer 304, a first outer electrode 310, a first phase change material layer 312, a dielectric layer 340, a second phase change material layer 330, a second outer electrode 342, and an inner electrode 322.

[0076] Similar named items, including substrate 302, dielectric layer 304, first outer electrode 310, first phase change material layer 312, dielectric layer 340, second phase change material layer 330, second outer electrode 342, and inner electrode 322, are formed as described above.

[0077] The internal electrode 322 may be formed in the dielectric layer 304, with a portion of the internal electrode 322 embedded in the dielectric layer 304 and two separate portions extending to a top surface that is flush with the top surface of the dielectric layer 304. A phase change material layer (not shown) may be formed on the dielectric layer 304 and the internal electrode 322. An electrode layer (not shown) may be formed on the phase change material layer (not shown). The phase change material layer (not shown) and the electrode layer (not shown) may be patterned into a vertically aligned first external electrode 310 and first phase change material layer 312, and a separately vertically aligned second external electrode 332 and second phase change material layer 330. A dielectric layer 340 may be formed surrounding the first external electrode 310 vertically aligned with the first phase change material layer 312, and the second external electrode 332 separately vertically aligned with the second phase change material layer 330. Contacts (not shown) may be formed to each of the first external electrode 310 and the second external electrode 342. The vertically aligned first external electrode 310 and first phase change material layer 312 may be aligned over a first portion of the internal electrode that is flush with the top surface of the dielectric layer 304. The vertically aligned second external electrode 332 and second phase change material layer 330 may be aligned over a second portion of the internal electrode that is flush with the top surface of the dielectric layer 304.

[0078] Structure 300 may be an individual cell, although it should be noted that while only one cell is shown, structure 300 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0079] Structure 300 provides a physically symmetric mushroom cell device with reduced programming current due to improved thermal confinement from the phase change material both above and below the heater electrode, resulting in reduced power consumption during analog computing.

[0080] In comparing structure 100 of FIGS. 7 and 8 and structure 300 of FIG. 13, structure 300 may be easier to manufacture, but structure 300 may consume more surface area for wiring.

[0081] 14, a semiconductor structure (hereafter "structure") 400 is shown at an intermediate step in fabrication, according to one embodiment. Structure 400 includes a stack of layers formed on a substrate 402, which may be subsequently patterned into individual cells. Structure 400 includes, for example, a dielectric layer 404, a first outer electrode 410, a dielectric layer 420, a first phase change material layer 412, a second phase change material layer 430, a dielectric layer 440, a second outer electrode 432, and an inner electrode 422.

[0082] Similar named items, including substrate 402, dielectric layer 404, first outer electrode 410, dielectric layer 420, first phase change material layer 412, dielectric layer 440, second phase change material layer 430, second outer electrode 432, and inner electrode 422, are formed as described above.

[0083] A first external electrode 410 may be formed in the dielectric layer 404. A phase change material layer (not shown) may be formed on the dielectric layer 404 and the internal electrode 422. The phase change material layer (not shown) may be patterned into a first phase change material layer 412 and a second phase change material layer 430, with the first phase change material layer 412 aligned over and connected to the first external electrode 410. An internal spacer 442 may be formed on the dielectric layer 404 and connecting the first phase change material layer 412 and the second phase change material layer 430. A dielectric layer 420 may be formed surrounding the first phase change material layer 412, the internal electrode 422, and the second phase change material layer 430. A dielectric layer 440 may be formed. A fifth opening (not shown) may be formed in the dielectric layer 440 to expose a portion of the top surface of the second phase change material layer 430. A second external electrode 432 may be formed in a fifth opening (not shown) and aligned with and physically connected to the second phase change material layer 430. Contacts (not shown) may be formed to each of the first external electrode 410 and the second external electrode 432.

[0084] Structure 400 may be an individual cell, although it should be noted that while only one cell is shown, structure 400 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0085] The structure 400 provides a physically symmetric mushroom cell device with improved heat confinement from the phase change material both above and below the heater electrode, reduced programming currents, and reduced power consumption during analog computing.

[0086] In comparing structure 100 of Figures 7 and 8, structure 300 of Figure 13, and structure 400 of Figure 14, structure 400 may be easier to manufacture, but structure 300 may consume more surface area for wiring.

[0087] 15-17, an alternative embodiment is shown and described using a conductive filament between two phase change material layers rather than an internal electrode. There are two embodiments for forming the conductive filament. The conductive filament can be formed by using a high-k dielectric layer that is collapsed to form the conductive filament. Alternatively, a mixed ionic electronic conductive filament device can be used.

[0088] 15, a semiconductor structure (hereafter "structure") 500 is shown at an intermediate step in fabrication, according to one embodiment. Structure 500 includes a stack of layers formed on a substrate 502, which may be subsequently patterned into individual cells. Structure 500 includes, for example, a dielectric layer 504, a bottom contact 506, a first external electrode 510, a first phase change material layer 512, a second phase change material layer 530, a dielectric layer 540, a second external electrode 532, and a top contact 542.

[0089] Structure 500 also includes, for example, filament layer 550 and filament layer break 552. Filament layer 550 and filament layer break 552 are not present in previous embodiments.

[0090] Similar named items, including substrate 502, dielectric layer 504, bottom contact 506, first external electrode 510, first phase change material layer 512, second phase change material layer 530, dielectric layer 540, second external electrode 532, and top contact 542, are formed as described above.

[0091] The filament layer 550 may be conformally formed on the first phase change material layer 512. The filament layer 550 may include a high-k dielectric layer, for example, a metal oxide semiconductor (MOX) such as tantalum oxide (Ta2O5) and hafnium oxide (HfO2). The filament layer 550 may include one or more layers of one or more materials. The filament layer 550 may be formed by physical vapor deposition (PVD). The thickness of the filament layer 550 may be between 1 nm and 50 nm, although the thickness may be less than 1 nm or greater than 50 nm. The filament layer 550 may include one or more layers of one or more materials. In one embodiment, the filament layer 550 includes a material having a dielectric constant of 3.9 or greater.

[0092] In one embodiment, the dielectric layer 504 and the dielectric layer 540 may include a material having a dielectric constant of 3.9 or greater. In one embodiment, the dielectric layer 504 and the dielectric layer 540 may each have a lower dielectric constant than the filament layer 550.

[0093] In one embodiment, the filament layer 550 may include a mixed ionic electronic conducting (MIEC) filament, such as silicon (Si) or silver (Ag) with an ion barrier. An ion barrier is an energy barrier for ions to move in physical space. The ions remain in place until sufficient energy (e.g., an electric field) overcomes the barrier.

[0094] A second phase change material layer 530 may be conformally formed over the filamentary layer 550. The structure 500 may be patterned into individual cells as described above.

[0095] A portion of the filament layer 550 can become a filament layer break 552 by a high voltage pulse or by applying an electric field large enough to induce a dielectric breakdown within the filament layer 550 to form a conductive bridge.

[0096] Filament layer break 552 is a conductive path between first phase change material layer 512 and second phase change material layer 530 .

[0097] Structure 500 may be an individual cell, although it is noted that while only one cell is shown, structure 500 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0098] The structure 500 provides a physically symmetric mushroom cell device with improved heat containment from the phase change material both above and below the filament layer break 552, reducing programming currents and reducing power consumption during analog computing.

[0099] 15, a portion of each of first phase change material layer 512 and second phase change material layer 530 is shown in dotted lines. The dotted portions indicate mushroom-shaped portions that may be initially amorphized when current is applied to filament layer break 552 (which may be referred to as a heater electrode).

[0100] 16, a semiconductor structure (hereafter "structure") 600 is shown at an intermediate step in fabrication, according to one embodiment. Structure 600 includes a stack of layers formed on a substrate 602, which may be subsequently patterned into individual cells. Structure 600 includes, for example, a dielectric layer 604, a bottom contact 606, a first external electrode 610, a first phase change material layer 612, a second phase change material layer 630, a dielectric layer 640, a second external electrode 632, and a top contact 642. Structure 600 also includes, for example, a filament layer 650, a filament layer break 652, a first liner 648, and a second liner 654.

[0101] Similarly named items, including substrate 602, dielectric layer 604, bottom contact 606, first external electrode 610, first phase change material layer 612, second phase change material layer 630, dielectric layer 640, second external electrode 632, top contact 642, filament layer 650, and filament layer break 652, are formed as described above.

[0102] A first liner 648 may be formed over the first phase change material layer 612. The first liner 648 may be formed as described for the first liner 218. A filament layer 650 may be conformally formed over the first liner 648. A second liner 654 may be formed over the filament layer 650. The second liner 654 may be formed as described for the first liner 218. A second phase change material layer 630 may be conformally formed over the filament layer 650.

[0103] The structure 600 can be patterned into individual cells as described above. The dielectric layer 640 and top contact 642 can be formed as described above.

[0104] A portion of the filament layer 650 can become a filament layer break 652, as described for filament break 552. Filament layer break 652 is a conductive path between first phase change material layer 612 and second phase change material layer 630.

[0105] Structure 600 may be an individual cell, although it is noted that while only one cell is shown, structure 600 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0106] The structure 600 provides a physically symmetric mushroom cell device with reduced programming current due to improved thermal confinement from the phase change material both above and below the filament layer break 652 and has lower power consumption during analog computing.

[0107] According to this embodiment, first liner 648 acts as a barrier that physically separates first phase change material layer 612 from subsequent layers formed thereon. Second liner 654 acts as a barrier that physically separates second phase change material layer 630 from filament layer 650 and filament layer break 652. In one embodiment, first liner 648 and second liner 654 may each have a thickness ranging from about 1 nm to about 30 nm, although thicknesses less than 1 nm and greater than 30 nm may be acceptable.

[0108] The structure 600 provides a physically symmetric mushroom cell device with reduced programming current due to improved heat containment from the phase change material both above and below the filament layer break 652, resulting in reduced power consumption during analog computing.

[0109] 16, a portion of each of first phase change material layer 612 and second phase change material layer 630 is shown in dotted lines. The dotted portions indicate mushroom-shaped portions that may be initially amorphized when current is applied to filament layer break 652 (which may be referred to as a heater electrode).

[0110] 17, a semiconductor structure (hereafter "structure") 700 is shown at an intermediate step in fabrication, according to one embodiment. Structure 700 includes a stack of layers formed on a substrate 702, which may be subsequently patterned into individual cells. Structure 700 includes, for example, a dielectric layer 704, a bottom contact 706, a first external electrode 710, a first phase change material layer 712, a second phase change material layer 730, a dielectric layer 740, a second external electrode 732, and a top contact 742. Structure 700 also includes, for example, a filament layer 750, a filament layer break 752, a first liner 748, and a second liner 754.

[0111] Similar named items, including substrate 702, dielectric layer 704, bottom contact 706 and first external electrode 710, first phase change material layer 712, second phase change material layer 730, dielectric layer 740, second external electrode 732, top contact 742, filament layer 750, filament layer break 752, first liner 748, and second liner 754, are formed as described above.

[0112] A first liner 748 may be formed over the first external electrode 710. A first phase change material layer 712 may be formed over the first liner 748. A filament layer 750 may be conformally formed over the first phase change material layer 712. A second liner 754 may be over the filament layer 750.

[0113] The structure 700 can be patterned into individual cells as described above. A dielectric layer 740 and a top contact 742 can be formed.

[0114] A portion of the filament layer 750 can be a filament layer break 752. The filament layer break 752 is a conductive path between the first phase change material layer 712 and the second phase change material layer 730.

[0115] Structure 700 may be an individual cell, although it should be noted that while only one cell is shown, structure 700 may typically include an array of thousands of cells, all formed according to the methods disclosed herein.

[0116] The structure 700 provides a physically symmetric mushroom cell device with improved heat containment from the phase change material both above and below the filament layer break 752, reducing programming currents and reducing power consumption during analog computing.

[0117] In this embodiment, the first liner 748 acts as a barrier that physically separates the first phase change material layer 712 from the first outer electrode 710. The second liner 754 acts as a barrier that physically separates the second phase change material layer 730 from the second outer electrode 732.

[0118] The structure 7600 provides a physically symmetric mushroom cell device with reduced programming current due to improved heat containment from the phase change material both above and below the filament layer break 752, resulting in reduced power consumption during analog computing.

[0119] 17, a portion of each of first phase change material layer 712 and second phase change material layer 730 is shown in dotted lines. The dotted portions indicate mushroom-shaped portions that may be initially amorphized when current is applied to filament layer break 752 (which may be referred to as a heater electrode).

[0120] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exclusive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, and to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a first phase change material layer vertically aligned over the bottom electrode; a dielectric layer vertically aligned over the first phase change material layer; a second phase change material layer vertically aligned over the dielectric layer; an internal electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the internal electrode being surrounded by the dielectric layer; a top electrode vertically aligned over the second phase change material layer.

2. The structure of claim 1 , wherein the inner electrode has a lateral diameter smaller than a lateral diameter of the bottom electrode.

3. a first projection liner vertically aligned between the first phase change material layer and the dielectric layer; 10. The structure of claim 1 further comprising: a second projection liner vertically aligned between the second phase change material layer and the dielectric layer.

4. a first thermal barrier layer vertically aligned between the first phase change material layer and the dielectric layer; 10. The structure of claim 1, further comprising: a first thermal barrier layer vertically aligned between the second phase change material layer and the dielectric layer.

5. a first adhesion layer vertically aligned between the first phase change material layer and the dielectric layer; 10. The structure of claim 1, further comprising: a first adhesion layer vertically aligned between the second phase change material layer and the dielectric layer.

6. A structure comprising: a first phase change material layer aligned over a first portion of the internal electrode; a first external electrode vertically aligned over the first phase change material layer; a second phase change material layer aligned over a second portion of the internal electrode; a second external electrode vertically aligned over the second phase change material layer; a dielectric layer that physically and electrically vertically separates the first phase change material layer and the first external electrode from the second phase change material layer and the second external electrode.

7. A structure comprising: a first phase change material layer aligned over the first external electrode; an internal electrode physically and electrically connected between the first phase change material layer and the second phase change material layer; a second external electrode vertically aligned over the second phase change material layer; a dielectric layer that physically and electrically vertically separates the first phase change material layer and the first external electrode from the second phase change material layer and the second external electrode.

8. A structure comprising: a first phase change material layer vertically aligned over the bottom electrode; a filament layer vertically aligned over the first phase change material layer; a second phase change material layer vertically aligned over the filament layer; an internal break in the filament layer connecting the first phase change material layer and the second phase change material layer; a top electrode vertically aligned over the second phase change material layer.

9. The structure of claim 8 , wherein the filament layer comprises a high-k dielectric.

10. 10. The structure of claim 8, wherein the filament layer comprises mixed ionic and electronic conducting filaments.

11. a first liner vertically aligned between the first phase change material layer and the filament layer; 9. The structure of claim 8, further comprising: a second liner vertically aligned between the second phase change material layer and the filament layer.

12. The structure of claim 11 , wherein the first liner and the second liner are each a projection layer.

13. The structure of claim 11 , wherein the first liner and the second liner are each a thermal barrier layer.

14. The structure of claim 11 , wherein the first liner and the second liner are each an adhesive layer.

15. a first liner vertically aligned between the first phase change material layer and the bottom electrode; 10. The structure of claim 9, further comprising: a second liner vertically aligned between the second phase change material layer and the top electrode.

16. 16. The structure of claim 15, wherein the first liner and the second liner are each a projection layer.

17. 16. The structure of claim 15, wherein the first liner and the second liner are each a thermal barrier layer.

18. 16. The structure of claim 15, wherein the first liner and the second liner are each an adhesive layer.

19. 1. A method of forming a structure, comprising: forming a first phase change material layer over the bottom electrode; forming a dielectric layer over the first phase change material layer; forming an internal electrode within the dielectric layer; forming a second phase change material layer on the dielectric layer, the internal electrodes being physically and electrically connected to both the first phase change material layer and the second phase change material layer; forming a top electrode over the second phase change material layer.

20. 20. The method of claim 19, further comprising providing a high voltage pulse to the dielectric layer to form the internal electrodes, the dielectric layer having a dielectric constant of 5.0 or greater.

21. 20. The method of claim 19, further comprising resetting the structure to an amorphous stage by applying a current to the internal electrodes.

22. 20. The method of claim 19, further comprising reading the memory state of the structure by applying a voltage between the bottom electrode and the top electrode.

Images