MEMORY DEVICE AND ITS PROGRAM OPERATION

Abstract

In some embodiments, a memory device includes an array of memory cells and peripheral circuitry coupled to the array of memory cells, at least one of the memory cells including two memory cells each corresponding to an element of N-bit data. N The peripheral circuitry applies a first program voltage to a selected row of memory cells, and after applying the first program voltage, the peripheral circuitry applies a second program voltage to the selected row of memory cells. N The method is configured to perform a first verification of the selected row of memory cells at a final level of the levels, perform a first VFC based on a result of the first verification and a first verify fail count (VFC) criterion, apply a second program voltage higher than the first program voltage to the selected row of memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion during the period in which the second program voltage is applied.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 63 / 436,441, filed December 30, 2022, which is incorporated by reference herein in its entirety.

[0002] The present disclosure relates to memory devices and methods of operating the same. [Background technology]

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations such as read, program (write), and erase can be performed by flash memory. For NAND flash memory, erase operations can be performed at the block level, and program or read operations can be performed at the page level. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a memory device includes an array of memory cells and peripheral circuitry coupled to the array of memory cells. At least one of the memory cells has two bits corresponding to an element of N-bit data. N The peripheral circuitry applies a first program voltage to a selected row of memory cells, and after applying the first program voltage, the peripheral circuitry applies a second program voltage to the selected row of memory cells. NThe peripheral circuitry is configured to perform a first verification of the selected row of memory cells at a final one of the levels. The peripheral circuitry is also configured to perform a first VFC based on a result of the first verification and a first verify fail count (VFC) criterion. After performing the first VFC, the peripheral circuitry is further configured to apply a second program voltage higher than the first program voltage to the selected row of memory cells and perform a second VFC based on a result of the first verification and a second VFC criterion different from the first VFC criterion during application of the second program voltage.

[0005] In some implementations, the peripheral circuitry is configured to apply a second program voltage in response to the result of the first verify not meeting the first VFC criterion.

[0006] In some implementations, the peripheral circuitry is further configured to perform a second verification of the selected row of memory cells at the final level in response to the result of the first verification not satisfying the second VFC criteria, and to perform a third VFC based on the result of the second verification and the third VFC criteria.

[0007] In some implementations, the peripheral circuitry is further configured to skip the second verification and the third VFC in response to the result of the first verification satisfying the second VFC criterion.

[0008] In some implementations, the third VFC criterion is the same as the first VFC criterion.

[0009] In some implementations, the memory device further includes word lines each coupled to a row of memory cells. In some implementations, to perform the first verification, the peripheral circuitry includes a word line driver configured to apply a verify voltage to a selected word line of the word line coupled to the selected row of memory cells, the verify voltage being 2 N This corresponds to the final level of the levels.

[0010] In some implementations, to perform the first VFC, the peripheral circuitry includes a page buffer configured to obtain a number of failed memory cells in a selected row of memory cells that do not pass the first verification, and control logic configured to compare the number of failed memory cells against a first VFC criterion.

[0011] In some implementations, the second VFC criterion is less strict than the first VFC criterion.

[0012] In another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells and peripheral circuits coupled to the array of memory cells. At least one of the memory cells includes 2 memory cells corresponding to an element of N-bit data. N The peripheral circuitry applies a first program voltage to a selected row of memory cells, and after applying the first program voltage, the peripheral circuitry applies a second program voltage to the selected row of memory cells. N The peripheral circuitry is further configured to, in response to a result of the first verification not satisfying the first VFC criterion, after performing the first VFC, apply a second program voltage higher than the first program voltage to the selected row of memory cells, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion during the application of the second program voltage.

[0013] In some implementations, the peripheral circuitry is further configured to perform a second verification of the selected row of memory cells at the final level in response to the result of the first verification not satisfying the second VFC criteria, and to perform a third VFC based on the result of the second verification and the third VFC criteria.

[0014] In some implementations, the peripheral circuitry is further configured to skip the second verification and the third VFC in response to the result of the first verification satisfying the second VFC criterion.

[0015] In some implementations, the third VFC criterion is the same as the first VFC criterion.

[0016] In some implementations, to perform the first VFC, the peripheral circuitry includes a page buffer configured to obtain a number of failed memory cells in a selected row of memory cells that do not pass the first verification, and control logic configured to compare the number of failed memory cells against a first VFC criterion.

[0017] In some implementations, the second VFC criterion is less strict than the first VFC criterion.

[0018] In yet another aspect, a method is provided for programming a memory device, the memory device including a row of memory cells, at least one of which stores two bits corresponding to an element of N-bit data. N A first program voltage is applied to the selected row of memory cells, where N is an integer greater than 1. After applying the first program voltage, the selected row of memory cells is set to one of two levels. N A first verification is performed on the selected row at a final level of the levels. A first VFC is performed based on a result of the first verification and a first VFC criterion. After performing the first VFC, a second program voltage higher than the first program voltage is applied to the selected row. During the application of the second program voltage, a second VFC is performed based on a result of the first verification and a second VFC criterion different from the first VFC criterion.

[0019] In some implementations, a second program voltage is applied in response to the first verify result not meeting the first VFC criterion.

[0020] In some implementations, a second verification of the selected row is performed at the final level in response to the result of the first verification not satisfying the second VFC criteria, and a third VFC is performed based on the result of the second verification and the third VFC criteria.

[0021] In some implementations, the second validation and the third VFC are skipped in response to the result of the first validation satisfying the second VFC criteria.

[0022] In some implementations, the third VFC criterion is the same as the first VFC criterion.

[0023] In some implementations, to perform the first verification, N A verify voltage corresponding to the last of the levels is applied to the selected row.

[0024] In some implementations, to perform the first VFC, a number of failed memory cells in a selected row that do not pass the first verification is obtained, and the number of failed memory cells is compared against a first VFC criterion.

[0025] In some implementations, the second VFC criterion is less strict than the first VFC criterion.

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure. [Brief description of the drawings]

[0027] [Figure 1] FIG. 2 is a schematic diagram of a memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Diagram 2] 1 is a cross-sectional side view of a memory cell array including a NAND memory string according to some aspects of the present disclosure. [Diagram 3]FIG. 1 is a block diagram of a memory device including a memory cell array and peripheral circuits in accordance with some aspects of the disclosure. [Figure 4] FIG. 2 illustrates threshold voltage distributions of memory cells during a program operation in accordance with some aspects of the present disclosure. [Figure 5A] FIG. 2 illustrates a waveform of a word line voltage applied to a selected word line in a program operation in accordance with some aspects of the present disclosure. [Figure 5B] FIG. 2 illustrates a waveform of a word line voltage applied to a selected word line in a program operation in accordance with some aspects of the present disclosure. [Figure 6A] FIG. 1 illustrates a standard final level verify fail count (VFC) scheme in a program operation. [Figure 6B] FIG. 1 illustrates a standard final level verify fail count (VFC) scheme in a program operation. [Figure 7A] FIG. 1 illustrates a predicted last level VFC scheme in a program operation. [Figure 7B] FIG. 1 illustrates a predicted last level VFC scheme in a program operation. [Figure 8A] FIG. 1 illustrates an adaptive last-level VFC scheme in a program operation in accordance with some aspects of the present disclosure. [Figure 8B] FIG. 1 illustrates an adaptive last-level VFC scheme in a program operation in accordance with some aspects of the present disclosure. [Figure 8C] FIG. 1 illustrates an adaptive last-level VFC scheme in a program operation in accordance with some aspects of the present disclosure. [Figure 9] FIG. 1 illustrates a threshold voltage distribution of memory cells with respect to a VFC in a program operation in accordance with some aspects of the present disclosure. [Figure 10] FIG. 4 is a detailed block diagram of the peripheral circuitry in FIG. 3 in accordance with some aspects of the present disclosure. [Figure 11] 1 is a flowchart of a method for programming a memory device according to some aspects of the present disclosure. [Figure 12] FIG. 1 is a block diagram of a system having a memory device in accordance with some aspects of the present disclosure. [Figure 13A] FIG. 2 is a diagram of a memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 13B] FIG. 1 is a diagram of a solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The present disclosure will be described with reference to the accompanying drawings.

[0029] In general, terms may be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein may be used to refer to any feature, structure, or characteristic in the singular sense, or may be used to refer to a combination of features, structures, or characteristics in the plural sense, at least in part depending on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey either the singular use or the plural use, again at least in part depending on the context. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily being expressly represented, again at least in part depending on the context.

[0030] Memory devices such as NAND flash memory devices can store more than a single bit of information in each memory cell with multiple states to increase storage capacity and lower the cost per bit. In a program operation, data is written to the memory cell over a program time (t PROGTo save 1000 MHz, the NAND flash memory devices may be initially programmed (written) into single-level cell (SLC) blocks and later combined into xLC blocks, such as multi-level cell (MLC) blocks, triple-level cell (TLC) blocks, quad-level cell (QLC) blocks, etc. A program operation of a NAND flash memory device involves several program and verify cycles and can be terminated after either the program or verify cycles depending on the particular last-level VFC scheme employed by the program operation. Thus, the program time of a program operation may be affected by the last-level VFC scheme, which determines when the program operation is terminated. Some last-level VFC schemes (also called standard last-level VFC schemes) always perform a last-level VFC after a verify cycle to terminate the program operation. To save program time, some final level VFC schemes (also called predicted final level VFC schemes) may skip the final verify cycle and terminate the program operation after the program cycle by performing a final level VFC within the program cycle using a predicted VFC criterion that is less strict (e.g., has a larger fail bit threshold) than the standard VFC criterion, which predicts whether the next program cycle will be the final program cycle of the program operation.

[0031] Meanwhile, there is a limit to the maximum number of fail bits (VFC) that can be counted by the peripheral circuitry of the memory device. Due to the VFC capability and / or the variation between word lines, the predicted last level VFC scheme can skip the last verify cycle, thereby shortening the program time only when the VFC capability is sufficient to cover the memory cells that passed the last verification. Otherwise, the program operation will require extra program / verify cycles, which effectively lengthens the program time.

[0032] To address one or more of the above-mentioned problems, the present disclosure introduces an adaptive final level VFC scheme that can adaptively switch between a standard final level VFC scheme and a predicted final level VFC scheme based on the VFC capability of the peripheral circuits. If the VFC capability is sufficient to cover the memory cells that have passed the last verify, the adaptive final level VFC scheme can skip the final verify cycle and terminate the program operation after the program cycle by performing the final level VFC in the program cycle using the predicted VFC criteria, and if the VFC capability is not sufficient to cover the memory cells that have passed the last verify, the adaptive final level VFC scheme can perform the final level VFC after the verify cycle to terminate the program operation, thereby avoiding bringing extra program / verify cycles into the program operation. In some implementations, the final level VFC is performed after the verify cycle using the standard VFC criteria and is performed in the program cycle using the predicted VFC criteria, so that the program operation can be terminated either after the verify cycle or after the program cycle. That is, the timing at which the program operation is terminated can be adaptive to the VFC capability and the variation between word lines. As a result, the average program time across different word lines using the adaptive final-level VFC scheme disclosed herein may be reduced compared to either the standard final-level VFC scheme or the predicted final-level VFC scheme.

[0033] FIG. 1 shows a schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the disclosure. The memory device 100 can include a memory cell array 101 and peripheral circuits 102 coupled to the memory cell array 101. The memory cell array 101 can be a NAND flash memory cell array in which memory cells 106 are provided in the form of an array of NAND memory strings 108, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 can hold a continuous analog value, such as a voltage or charge that depends on the number of electrons trapped within the area of ​​the memory cell 106. Each memory cell 106 can be either a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

[0034] In some implementations, each memory cell 106 is an SLC, which has two possible levels (memory states) and can therefore store one bit of data. For example, a first level, "0," can correspond to a first range of threshold voltages and a second level, "1," can correspond to a second range of threshold voltages. In some implementations, each memory cell 106 is an xLC, which can store more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC has two of the possible nominal storage values ​​(i.e., two of the N bits of data). N In some implementations, at least one of the memory cells 106 can be programmed to exhibit a range of 2 corresponding to an element of N-bit data. N The level is set to one of N levels, where N is an integer greater than 1.

[0035] As shown in FIG. 1, each NAND memory string 108 may also include a source select gate (SSG) transistor 110 at its source end and a drain select gate (DSG) transistor 112 at its drain end. The SSG transistor 110 and the DSG transistor 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 108 in the same block 104 are coupled through the same source line (SL) 114, e.g., a common SL. In other words, all the NAND memory strings 108 in the same block 104 have an array common source (ACS) according to some implementations. The drains of each NAND memory string 108 are coupled to respective bit lines 116 from which data can be read or written via an output bus (not shown) according to some implementations. In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage or deselect voltage to the gate of each DSG transistor 112 via one or more DSG lines 113 and / or by applying a select voltage or deselect voltage to the gate of each SSG transistor 110 via one or more SSG lines 115.

[0036] As shown in FIG. 1, the NAND memory strings 108 may be organized into multiple blocks 104, each of which may have a common source line 114, for example, coupled to an ACS. In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 as well as to unselected blocks 104 in the same plane as the selected block 104 may be biased with an erase voltage (Vers), such as a positive high bias voltage (e.g., 20V or more). The memory cells 106 of adjacent NAND memory strings 108 may be coupled through word lines 118 that select which row of memory cells 106 is acted upon by read and program operations. In some implementations, each word line 118 is coupled to a page 120 of memory cells 106, which is the basic data unit for read and program operations. The size of a page 120 in bits can relate to the number of NAND memory strings 108 coupled by word lines 118 in a block 104. Each word line 118 can include multiple control gates (gate electrodes) in each memory cell 106 in the respective page 120 and gate lines coupling the control gates.

[0037] 1, the memory cell array 101 may include an array of memory cells 106 in rows and columns within each block 104. According to some implementations, a row of memory cells 106 corresponds to one or more pages 120 and a column of memory cells corresponds to a NAND memory string 108. The rows of memory cells 106 may each be coupled to a word line 118, and the columns of memory cells 106 may each be coupled to a bit line 116. Peripheral circuits 102 may be coupled to the memory cell array 101 through the bit lines 116 and the word lines 118.

[0038] 2 illustrates a cross-sectional side view of a memory cell array 101 including a NAND memory string 108, according to some aspects of the disclosure. As illustrated in FIG. 2, the NAND memory string 108 can extend vertically through the memory stacks 204 above a substrate 202. The substrate 202 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0039] The memory stack 204 may include interleaved gate conductive layers 206 and inter-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and inter-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, a gate of a DSG transistor 112, or a gate of an SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0040] As shown in Figure 2, the NAND memory string 108 includes a channel structure that extends vertically through the memory stack 204. In some implementations, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). Although not shown in Figure 2, it is understood that additional components of the memory cell array 101 may be formed, including, but not limited to, gate line slit / source contacts, local contacts, interconnect layers, etc.

[0041] Referring again to FIG. 1, the peripheral circuitry 102 may be coupled to the memory cell array 101 through bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 101 by applying and sensing voltage and / or current signals to and from each selected memory cell 106 through the bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuitry 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 3 illustrates several exemplary peripheral circuits including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It will be appreciated that in some examples, additional peripheral circuitry not shown in FIG. 3 may also be included.

[0042] The page buffer / sense amplifier 304 may be configured to sense (read) and program (write) data to and from the memory cell array 101 according to control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 may store a page of program data (write data, referred to herein as a "data page") to be programmed into one page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may verify a selected programmed memory cell 106 during each program / verify cycle in a program operation to ensure that data is properly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense low power signals from the bit lines 116 representing data bits stored in the memory cells 106 and may amplify small voltage swings to discernible logic levels in a read operation. As described in more detail below, during a program operation, the page buffer / sense amplifiers 304 may include modules for recording and counting the number of memory cells 106 that do not pass verification, i.e., the number of failed memory cells (also called fail bits), during a program / verify cycle.

[0043] The column decoder / bitline driver 306 may be controlled by the control logic 312 and configured to select one or more NAND memory strings 108 by applying a bitline voltage generated from the voltage generator 310. The row decoder / wordline driver 308 may be controlled by the control logic 312 and the select / deselect block 104 of the memory cell array 101 and configured to select / deselect wordlines 118 of the block 104. The row decoder / wordline driver 308 may further be configured to drive the wordlines 118 using a wordline voltage generated from the voltage generator 310. In some implementations, the row decoder / wordline driver 308 may also select / deselect and drive the SSG line 115 and the DSG line 113 as well. The voltage generator 310 may be controlled by the control logic 312 and configured to generate wordline voltages (e.g., read voltages, program voltages, channel pass voltages, local voltages, verify voltages, etc.), bitline voltages, and source line voltages to be supplied to the memory cell array 101.

[0044] The control logic 312 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. As described below in detail and consistent with the scope of this disclosure, in a program operation, the control logic 312 may include modules for performing VFC based on the number of failed memory cells and VFC criteria that are adaptive to its VFC capabilities.

[0045] The registers 314 may be coupled to the control logic 312 and may include status registers, command registers, and address registers for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each peripheral circuit. The interface 316 may be coupled to the control logic 312 and may act as a control buffer for buffering and relaying control commands received from a memory controller (not shown) and / or a host (not shown) to the control logic 312, and for buffering and relaying status information received from the control logic 312 to the memory controller and / or the host. The interface 316 may also be coupled to the column decoder / bit line driver 306 via a data bus 318 and may act as a data input / output (I / O) interface and data buffer for buffering and relaying data to and from the memory cell array 101.

[0046] 4 illustrates a distribution of threshold voltages of memory cells during a program operation, according to some aspects of the disclosure. In some implementations, each memory cell 106 has two memory cells 106a and 106b corresponding to an element of N-bit data. N Each level can be set to one of two levels, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). NTaking a TLC with N=3, for example, as shown in FIG. 4, the memory cells 106 may be programmed to one of eight levels (L0-L7), including one level (L0) of an erased state and seven levels (L1-L7) of a programmed state. Each level may correspond to a respective threshold voltage (Vth) range of the memory cells 106. For example, the level corresponding to the lowest threshold voltage range (the leftmost threshold voltage distribution in FIG. 4) may be considered as level 0 (L0), the level corresponding to the second lowest threshold voltage range (the second threshold voltage distribution from the left in FIG. 4) may be considered as level 1 (L1), and so on up to level 7 (L7) corresponding to the highest threshold voltage range (the rightmost threshold voltage distribution in FIG. 4). As described herein, two N The final level of the levels is also referred to herein as level K (Lk), and includes levels (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 109, 108, 109, 108, 109, 109, 110, 111, 112, 113, 114, 115, N -1), where K=2 N On the other hand, each level is 2 of the N bits of data to be stored in the selected memory cell 106. N In some implementations, the N-bit data may correspond to one of two elements. N The elements are divided into 2 based on the Gray code. N Gray code (also called reflected binary code (RBC) or reflected binary (RB)) is an ordering of the binary number system such that two consecutive values ​​differ by one bit (binary digit).

[0047] In addition to the page buffer / sense amplifiers 304 providing a corresponding element of the N-bit data to each selected memory cell 106 to perform a program operation, the row decoder / word line drivers 308 may be configured to apply program and verify voltages to a selected word line 118 coupled to a selected row of memory cells 106 in one or more program / verify cycles to raise the threshold voltage of each selected memory cell 106 to a desired level (within a desired range of threshold voltages) based on the corresponding element of the N-bit data. For example, Figures 5A and 5B show waveforms of word line voltages applied to a selected word line in a program operation according to some aspects of the present disclosure.

[0048] As shown in FIG. 5A, a program operation includes one or more program / verify cycles (also referred to as loops) 502. As shown in FIG. 5B, during each program / verify cycle 502, the row decoder / word line driver 308 may be configured to apply a program voltage (Vpgm) on a selected word line 118 to a selected row of memory cells 106 during a program cycle 504, and sequentially apply one or more verify voltages (Vvfy) with incremental changes in voltage level to verify the selected row of memory cells 106 during a verify cycle 506. That is, after applying a program voltage during a program cycle 504, the peripheral circuit 102 may perform verification of the selected row of memory cells 106 at one or more levels during a verify cycle 506. The number of verify voltages applied during a verify cycle 506 depends on the level being programmed by a particular program / verify cycle 502, according to some implementations. Taking a TLC with N=3, for example, during a program / verify cycle 502 corresponding to level 6 (L6), two verify voltages (L6 Vvfy and L7 Vvfy) may be applied by the peripheral circuit 102 to verify the selected memory cell 106 at level 6 (L6) and level 7 (L7) successively, and during a program / verify cycle 502 corresponding to the final level, i.e., level 7 (L7), only one verify voltage (L7 Vvfy) may be applied by the peripheral circuit 102 to verify the selected memory cell 106 at level 7 (L7). As a result, at the end of the program operation, the selected memory cell 106 may be configured to have two verify voltages (L6 Vvfy and L7 Vvfy) based on the corresponding N bits of data to be stored in the selected memory cell 106. N The input can be programmed to one of two levels.

[0049] 6A and 6B show a standard last level VFC scheme in a program operation. As shown in FIG. 6A and 6B, an Nth program voltage (Vpgm_n) is applied by the word line driver 308 of the peripheral circuit 102 on the selected word line 118, followed by two verify (L(k-1) vfy and Lk vfy) corresponding to the last two levels (L(k-1) and L(k)). Then, an (N+1)th program voltage (Vpgm_n+1), which is higher than the Nth program voltage, is applied by the word line driver 308 on the selected word line 118. For example, during the application of the (N+1)th program voltage, a penultimate level VFC (L(k-1) vfc) is performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 in parallel with the (N+1)th program voltage. In response to the penultimate level VFC (shown as a filled box) meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that fail the penultimate level verify (L(k-1) vfy) does not exceed the standard fail bit threshold, the penultimate level verify is passed and only the final level verify (Lk vfy) needs to be performed after the (N+1)th program voltage.

[0050] As shown in Figures 6A and 6B, rather than waiting to apply the next (N+2)th program voltage (Vpgm_n+2), a final level VFC (Lk vfc) is performed after performing the final level verify and before applying the next (N+2)th program voltage. As shown in Figure 6A, in response to the final level VFC (shown as a filled box) meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that fail the final level verify (Lk vfy) does not exceed the standard fail bit threshold, the final level verify is passed and the program operation is terminated without needing to apply the (N+2)th program voltage. In contrast, as shown in FIG. 6B, in response to the final level VFC (shown as a dotted box) not meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify (Lk vfy) exceeds the standard fail bit threshold, the final level verify fails and the program operation must continue by applying a (N+2)th program voltage (Vpgm_n+2) that is higher than the (N+1)th program voltage. Again, after applying the (N+2)th program voltage, another final level verify (Lk vfy) must be performed, followed by another final level VFC (Lk vfc) after applying the (N+2)th program voltage to determine whether the final level VFC now meets the standard VFC criteria. As shown in FIG. 6B, in response to the second final level VFC (shown as a solid box) meeting the standard VFC criteria, the second final level verify passes and the program operation ends without the need to apply a (N+3)th program voltage. If not, the (N+3)th program voltage may need to be run again along with a third final level verify and a third final level VFC (not shown) or the program operation may be aborted as unsuccessful.

[0051] 7A and 7B show a predicted last level VFC scheme in a program operation. As shown in FIG. 7A and 7B, an Nth program voltage (Vpgm_n) is applied by the word line driver 308 of the peripheral circuit 102 on the selected word line 118, followed by two verify (L(k-1) vfy and Lk vfy) corresponding to the last two levels (L(k-1) and L(k)). Then, an (N+1)th program voltage (Vpgm_n+1), which is higher than the Nth program voltage, is applied by the word line driver 308 on the selected word line 118. For example, during the application of the (N+1)th program voltage, a penultimate level VFC (L(k-1) vfc) is performed by the page buffer 304 and the control logic 312 of the peripheral circuit 102 in parallel with the (N+1)th program voltage. In response to the penultimate level VFC (shown as a filled box) meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that fail the penultimate level verify (L(k-1) vfy) does not exceed the standard fail bit threshold, the penultimate level verify is passed and only the final level verify (Lk vfy) needs to be performed after the (N+1)th program voltage.

[0052] Unlike the standard final level VFC scheme in Figures 6A and 6B, where the final level VFC (Lk vfc) is performed using the same standard VFC criteria before applying the next (N+2)th program voltage, in the predicted final level VFC scheme shown in Figures 7A and 7B, for example, during the application of the (N+2)th program voltage, the predicted final level VFC (Lk vfc_p) is performed in parallel with the (N+2)th program voltage (Vpgm_n+2) which is higher than the (N+1)th program voltage. Moreover, since the higher program voltage (Vpgm_n+2) that can be drawn has been applied after the first final level verify, it is reasonable to assume that more selected memory cells 106 have passed the final level verify. Therefore, the predicted final level VFC (Lk vfc_p) is implemented with predicted VFC criteria that are less stringent than the standard VFC criteria (e.g., used by the penultimate level VFC), e.g., a larger fail bit threshold for passing the final level VFC, making it easier for the final level VFC to meet the predicted VFC criteria.

[0053] As shown in Figure 7A, in response to the final level VFC (shown as a filled box) meeting the predicted VFC criteria, e.g., the number of selected memory cells 106 that fail the final level verify (Lk vfy) does not exceed a larger fail bit threshold, the final level verify is passed and the program operation is terminated after applying the (N+2)th program voltage without needing to perform a second final level verify as shown in Figure 6B. That is, compared to the standard final level VFC scheme, the predicted final level VFC scheme may skip the second final level verify and the second final level VFC.

[0054] However, as shown in FIG. 7B, in response to the final level VFC (shown as a dotted box) not meeting the predicted VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify (Lk vfy) still exceeds the larger fail bit threshold, the final level verify fails and the program operation needs to continue by performing another final level verify (Lk vfy) and applying a (N+3)th program voltage (Vpgm_n+3) that is higher than the (N+2)th program voltage. Again, after applying the (N+3)th program voltage, another predicted final level VFC (Lk vfc_p) needs to be performed in parallel with applying the (N+3)th program voltage to determine whether the final level VFC now meets the predicted VFC criteria. As shown in FIG. 7B, in response to the second final level VFC (shown as a solid box) meeting the predicted VFC criteria, the second final level verify passes and the program operation ends without the need to perform a third final level verify. If not, the third final level verify, the third predicted final level VFC, and the (N+4)th program voltage may need to be performed again (not shown) or the program operation may be aborted as unsuccessful.

[0055] It is understood that due to various reasons, such as the VFC capability of the peripheral circuit 102 is not enough to cover the relaxed predicted VFC criteria (e.g., too many memory cells 106 to be counted) and / or word line-to-word line variations (e.g., causing a larger number of fail bits among some rows of memory cells 106), the final level VFC may not meet the predicted VFC criteria as shown in FIG. 7B. Thus, the predicted final level VFC scheme may shorten the program operation time in some situations (e.g., comparing FIG. 7A with FIG. 6B), but may lengthen the program operation time in some other situations. Moreover, also due to word line-to-word line variations, it is difficult to find the optimal predicted VFC criteria for programming different rows of memory cells 106.

[0056] To combine the advantages of both the standard and predicted final level VFC schemes described above consistent with the scope of the present disclosure, Figures 8A-8C illustrate an adaptive final level VFC scheme in a program operation according to some aspects of the present disclosure. To implement the adaptive final level VFC scheme, for example, Figure 10 illustrates a detailed block diagram of the peripheral circuitry 102 in Figure 3, including the control logic 312, the page buffer 304, and the word line driver 308, according to some aspects of the present disclosure.

[0057] 3 and 10, in some implementations, the peripheral circuits 102, including the control logic 312, the row decoder / word line driver 308, the voltage generator 310, the page buffer / sense amplifier 304, the register 314, and any other suitable components (e.g., the column decoder / bit line driver 306), function together to perform a program operation on a selected memory cell 106 in the memory cell array 101 coupled to a selected word line 118. To perform the program operation, the page buffer 304 may include a counter 1004 and a latch 1006, along with any other suitable components not shown in FIG. 10. The counter 1004 and the latch 1006 may be digital, analog, and / or mixed-signal circuits, as described in more detail below. To perform program operations, the control logic 312 may include a program / verify controller 1008 and a VFC controller 1010, along with any other suitable components not shown in FIG. 10, such as a processor (e.g., a microcontroller unit (MCU)) and memory (e.g., random access memory (RAM)). Each of the program / verify controller 1008 and the VFC controller 1010 may be implemented as a firmware module stored in RAM and executed by the MCU. Each of the program / verify controller 1008 and the VFC controller 1010 may also be implemented as an application specific integrated circuit (ASIC) including digital, analog, and / or mixed signal circuits.

[0058] To perform a program operation, the peripheral circuitry 102 may be configured to apply a program voltage to a row of selected memory cells 106 coupled to a selected word line 118 and perform verification of the selected row of memory cells at various levels after applying the program voltage. In some implementations, as shown in FIG. 10, a program / verify controller 1008 of the control logic 312 sends commands to the voltage generator 310 to control the voltage generator 310 to generate a series of program voltages and provide the program voltages to the word line drivers 308. The voltage levels of the program voltages can be stored in a register 314 and retrieved by the control logic 312. The control logic 312 can also send commands to the word line drivers 308 to control the word line drivers 308 to apply the program voltages to the selected word lines 118. In some implementations, the program / verify controller 1008 of the control logic 312 sends commands to the voltage generator 310 to control the voltage generator 310 to generate a series of verify voltages and provide the verify voltages to the word line drivers 308. The voltage level of the verify voltage may correspond to a preferred level to which the selected memory cell 106 is set. The control logic 312 may also send a command to the word line driver 308 to control the word line driver 308 to apply one or more verify voltages to the selected word line 118 after applying each program voltage to the selected word line 118 to perform the verify.

[0059] 10, the program / verify controller 1008 of the control logic 312 also sends a command to the page buffer / sense amplifier 304 to check whether the threshold voltage of each selected programmed memory cell 106 reaches a verify voltage after the word line driver 308 applies the verify voltage. For example, the page buffer / sense amplifier 304 may determine whether the threshold voltage of each selected programmed memory cell 106 reaches a certain voltage by detecting a current flow through each bit line 116 coupled to the selected programmed memory cell 106, i.e., a current flow indicating whether the voltage is equal to or greater than the threshold voltage for turning on each selected programmed memory cell 106. That is, the page buffer / sense amplifier 304 may be configured to continuously check whether the threshold voltage of each selected programmed memory cell 106 reaches a verify voltage after the word line driver 308 applies the verify voltage.

[0060] As shown in FIG. 8A-8C, for example, an Nth program voltage (Vpgm_n), such as a voltage pulse signal, may be applied to a selected row of memory cells 106 by the word line driver 308 of the peripheral circuit 102 via the selected word line 118. The Nth program voltage may be applied to the control gate of each selected memory cell 106 to program the selected memory cell 106. After applying the Nth program voltage, two verify voltages (L(k-1) vfy and Lk vfy) of the selected row of memory cells 106 may be performed by the peripheral circuit 102 by successively applying two verify voltages, such as two voltage pulse signals, corresponding to the last two levels (L(k-1) and L(k)) to the selected word line 118 by the word line driver 308. A verify voltage may be applied to the control gate of each selected memory cell 106 to compare the threshold voltage of each selected programmed memory cell 106 with the verify voltage by checking whether the verify voltage can turn on each selected programmed memory cell 106. Then, an (N+1)th program voltage (Vpgm_n+1), which is higher than the Nth program voltage, may be applied on the selected word line 118 by the word line driver 308.

[0061] To execute the program operation, the peripheral circuit 102 may be configured to execute the VFC based on the verification result and the VFC criteria, for example, whether the verification result meets the VFC criteria. In some implementations, as shown in FIG. 10, the VFC controller 1010 of the control logic 312 controls the page buffer 304 to send a command to the page buffer 304 to obtain the number of failed memory cells in the selected row of the memory cells 106 that do not pass the verification (also referred to as the number of verification-failed memory cells). In response, the latch 1006 of the page buffer 304 can record each time that the threshold voltage of the programmed selected memory cell 106 is lower than the verify voltage (for example, Vth < Vvfy). Each latch 1006 can be responsible for recording events according to some sets of conditions. In some examples, it is understood that a single latch 1006 may be used in a time-division multiplexing (TDM) manner to achieve the same function as a plurality of latches 1006. The counter 1004 of the page buffer 304 can be coupled to the latch 1006 and can count the number of recorded times that is the number of verification-failed memory cells. As shown in FIG. 9, the shaded area 900 defined by the verify voltage (Vvfy) of the threshold voltage distribution at the final level (Lk) may indicate all the programmed selected memory cells 106 that do not pass the verification when their threshold voltages do not reach the verify voltage (lower than it) (for example, Vth < Vvfy at Lk).

[0062] In some implementations, as shown in FIG. 10, the VFC controller 1010 of the control logic 312 obtains the number of verify-failed memory cells from the counter 1004 of the page buffer 304 and the VFC criteria 1012, stored, for example, in the register 314. In some implementations, the VFC controller 1010 then compares the number of verify-failed memory cells against the VFC criteria to determine whether the verification passes or fails. The VFC criteria 1012, according to some implementations, include any suitable criteria used to determine whether the result of the verification (e.g., the number of verify-failed memory cells) indicates whether the verification passes or fails. For example, the VFC criteria 1012 may be a fail bit threshold indicating a maximum number of verify-failed memory cells that pass the verification. As described herein, the VFC criteria 1012 may include standard VFC criteria and predicted VFC criteria that are less stringent than the standard VFC criteria, i.e., relaxed VFC criteria. According to some implementations, the predicted VFC criteria are used for the final level VFC, while the standard VFC criteria are used for the other levels of VFC. For example, the standard VFC criterion may be a first fail bit threshold and the predicted VFC criterion may be a second fail bit threshold that is greater than the first fail bit threshold.

[0063] As shown in FIGS. 8A-8C , for example, a penultimate level of VFC (L(k-1) vfc) may be performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 in parallel with the (N+1)th program voltage, for example, during application of the (N+1)th program voltage. In response to the penultimate level of VFC (shown as a filled box) meeting standard VFC criteria, e.g., the number of selected memory cells 106 that do not pass the penultimate level of verify (L(k-1) vfy) does not exceed a standard fail bit threshold, the penultimate level of verify is passed and only the final level verify (Lk vfy) needs to be performed after the (N+1)th program voltage.

[0064] As shown in FIGS. 8A-8C, for example, a final level verify (Lk vfy) may be performed by the word line driver 308 and the page buffer 304 of the peripheral circuit 102. After applying the (N+1)th program voltage and performing the penultimate level VFC, a verify (Lk vfy) of one of the selected rows of memory cells 106 at the final level (Lk) may be performed by the peripheral circuit 102 by applying a verify voltage corresponding to the final level, such as a voltage pulse signal, to the selected word line 118 by the word line driver 308. A verify voltage may be applied to the control gate of each selected memory cell 106 to compare the threshold voltage of each selected programmed memory cell 106 with the verify voltage by checking whether the verify voltage can turn on each selected programmed memory cell 106.

[0065] As shown in FIGS. 8A-8C, for example, a standard final level VFC (Lk vfc) may be performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 after performing the final level verify and before applying the (N+2)th program voltage, rather than waiting to apply the next (N+2)th program voltage (Vpgm_n+2). As shown in FIG. 8A, in response to the standard final level VFC (shown as a filled box) meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify does not exceed a standard fail bit threshold, the final level verify may be passed and the program operation may terminate without needing to apply the (N+2)th program voltage. In this case, the adaptive final level VFC scheme employs a standard final level VFC scheme (compare FIG. 8A with FIG. 6A) that, according to some implementations, shortens the program operation time by eliminating the (N+2)th program voltage.

[0066] In contrast, as shown in Figures 8B and 8C, in response to the standard final level VFC (shown as a dotted box) not meeting the standard VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify exceeds the standard fail bit threshold, the final level verify may fail and the program operation may need to continue by applying an (N+2)th program voltage (Vpgm_n+2) that is higher than the (N+1)th program voltage.

[0067] As shown in FIG. 8B and FIG. 8C, for example, during the application of the (N+2)th program voltage, a predicted final level VFC (Lk vfc_p) may be performed, for example, by the page buffer 304 and the control logic 312 of the peripheral circuit 102 in parallel with the (N+2)th program voltage. Moreover, since a higher program voltage (Vpgm_n+2) that can be drawn is applied after the first final level verify, it is reasonable to assume that more selected memory cells 106 have passed the final level verify. Therefore, the predicted final level VFC (Lk vfc_p) is performed with a predicted VFC criterion that is less stringent than the standard VFC criterion (for example, used by the standard final level VFC), for example, a larger fail bit threshold for passing the final level VFC, making it easier for the final level VFC to meet the predicted VFC criterion.

[0068] As shown in Figure 8B, in response to the predicted final level VFC (shown as a filled box) meeting the predicted VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify (Lk vfy) does not exceed a larger fail bit threshold, the final level verify passes and the program operation ends after applying the (N+2)th program voltage without needing to perform the second final level verify again. In this case, the adaptive final level VFC scheme employs a predicted final level VFC scheme (compare Figure 8B with Figure 7A) that, according to some implementations, shortens the program operation time by eliminating the second final level verify (e.g., in Figure 6B).

[0069] In contrast, as shown in FIG. 8C, in response to the predicted final level VFC (shown as a dotted box) not meeting the predicted VFC criteria, e.g., the number of selected memory cells 106 that do not pass the final level verify (Lk vfy) still exceeds the larger fail bit threshold, the final level verify again fails and the program operation needs to continue by performing yet another final level verify (Lk vfy). However, rather than waiting to apply the next (N+3)th program voltage (Vpgm_n+3, as shown in FIG. 7B of the predicted final level VFC scheme), another standard final level VFC (Lk vfc) may be performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 after performing the second final level verify and before applying the (N+3)th program voltage. Similar to the first standard final level VFC, the second standard final level VFC may be performed by comparing the result of the second final level verify against the standard VFC criteria. For example, the two standard VFC references used by the first and second standard end-level VFCs may be the same.

[0070] As shown in FIG. 8C, in response to the second standard final level VFC (shown as a filled box) meeting the standard VFC criteria, the second final level verify passes and the program operation ends without needing to apply the next (N+3)th program voltage. If not, the (N+3)th program voltage may need to be applied, a second predicted final level VFC may need to be performed in parallel with the (N+3)th program voltage (not shown), or the program operation may be aborted as a failure. In this case, the adaptive final level VFC scheme, according to some implementations, employs a standard final level VFC scheme that shortens the program operation time by eliminating the (N+3)th program voltage (e.g., in FIG. 7B).

[0071] As shown in Figures 8A-8C, the standard final level VFC (Lk vfc) between verifying and applying the program voltage and the predicted final level VFC (Lk vfc_p) in parallel with applying the program voltage can be alternated according to an adaptive final level VFC scheme to terminate the program operation as soon as the verify is passed. Unlike the standard final level VFC scheme that always terminates the program operation after verifying (e.g., in Figures 6A and 6B) and the predicted final level VFC scheme that always terminates the program operation after applying the program voltage (e.g., in Figures 7A and 7B), the adaptive final level VFC scheme disclosed herein can flexibly terminate the program operation by switching between the standard final level VFC scheme and the predicted final level VFC scheme.

[0072] FIG. 11 illustrates a flowchart of a method 1100 for programming a memory device according to some aspects of the disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. Method 1100 may be performed by peripheral circuits 102, such as row decoder / word line driver 308, page buffer / sense amplifier 304, and control logic 312. It is understood that the operations illustrated in method 1100 may not be exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations as well. Additionally, some of the operations may be performed simultaneously or in a different order than illustrated in FIG. 11.

[0073] 11, the method 1100 begins at operation 1102 where a first program voltage is applied to a selected row of memory cells. At least one of the memory cells is programmed with two program voltages corresponding to an element of N-bit data. Nlevels, where N is an integer greater than 1. For example, as shown in Figures 8A-8C and 10, in a program operation, a (N+1)th program voltage (Vpgm_n+1, "first program voltage") may be applied by a word line driver 308 of the peripheral circuitry 102 to a selected row of memory cells 106 via a selected word line 118.

[0074] The method 1100 applies a first programming voltage, as shown in FIG. N The process proceeds to operation 1104, where a first validation of the selected row is performed at the final one of the levels. In some implementations, to perform the first validation, two N A verify voltage corresponding to the final level of the levels is applied to the selected row. For example, as shown in FIGS. 8A-8C and 10, in a program operation, after the word line driver 308 and the page buffer 304 of the peripheral circuit 102 apply the (N+1)th program voltage, a first final level verify (Lk vfy, “2 N In this case, a "first verification at the final level of the levels" may be performed.

[0075] The method 1100 proceeds to operation 1106, where a first VFC is performed based on the result of the first verification and the first VFC criteria, as shown in FIG. 11. In some implementations, to perform the first VFC, a number of failed memory cells in the selected row that do not pass the first verification is obtained, and the number of failed memory cells is compared against the first VFC criteria. In some implementations, when the result of the first verification meets the first VFC criteria, the first verification passes, and when the result of the first verification does not meet the first VFC criteria, the first verification fails. 8A-8C and 10, in a program operation, after the first final level verify but before applying the next (N+2)th program voltage by the page buffer 304 and control logic 312 of the peripheral circuit 102, a first standard final level VFC (Lk vfc, “first VFC”) may be performed based on the result of the first final level verify and a standard VFC criterion (“first VFC criterion”). In one example, the number of memory cells that fail the verify of the first final level verify may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against the default VFC criterion 1012 to determine whether the first final level verify passes or fails by the VFC controller 1010 of the control logic 312.

[0076] The method 1100 proceeds to operation 1108, where a second program voltage higher than the first program voltage is applied to the selected row after performing the first VFC, as shown in FIG. 11. The second program voltage may be applied in response to the result of the first verification not meeting the first VFC criteria. Otherwise, the second program voltage may be skipped to end the program operation. For example, as shown in FIG. 8B, FIG. 8C, and FIG. 10, in a program operation, when the result of the first final level verification (shown as a dotted box, i.e., first final level verification fails) does not meet the standard VFC criteria, after performing the first standard final level VFC, a (N+2)th program voltage (Vpgm_n+2, “second program voltage”) higher than the (N+1)th program voltage may be applied to the selected row of memory cells 106 via the selected word line 118 by the word line driver 308 of the peripheral circuit 102. Otherwise, as shown in Figures 8A and 10, in a program operation, when the result of the first final level verify (shown as a filled box, i.e., passing the first final level verify) meets the standard VFC criteria, the (N+2)th program voltage may be skipped after performing the first standard final level VFC to terminate the program operation.

[0077] The method 1100 proceeds to operation 1110, in which a second VFC is applied based on the result of the first verify and a second VFC criterion different from the first VFC criterion during the application of the second program voltage, as shown in FIG. 11. The second VFC criterion may be less stringent than the first VFC criterion. For example, as shown in FIG. 8B, FIG. 8C, and FIG. 10, in a program operation, a first predicted final level VFC (Lk vfc_p, “second VFC”) may be performed based on the result of the first final level verify and a predicted VFC criterion (“second VFC criterion”) during the application of the (N+2)th program voltage by the page buffer 304 and the control logic 312 of the peripheral circuit 102. The predicted VFC criterion may be less stringent than the standard VFC criterion, for example, having a larger fail bit threshold. In one example, the number of memory cells that fail the first final level verification may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against relaxed VFC criteria 1012 by the VFC controller 1010 of the control logic 312 to determine whether the first final level verification passes or fails.

[0078] The method 1100 proceeds to operation 1112, where a second verify of the selected row at the final level is performed in response to the result of the first verify not meeting the second VFC criteria, as shown in Figure 11. For example, as shown in Figures 8C and 10, in a program operation, when the result of the first final level verify does not meet the expected VFC criteria (shown as a dotted box, i.e., failing the first final level verify again under relaxed VFC criteria after applying the (N+2)th program voltage), a second final level verify (Lk vfy, "second verify at final level") may be performed after applying the (N+2)th program voltage by the word line driver 308 and page buffer 304 of the peripheral circuit 102.

[0079] The method 1100 proceeds to operation 1114, where a third VFC is performed based on the result of the second verification and a third VFC criterion, as shown in FIG. 11. In some implementations, the third VFC criterion is the same as the first VFC criterion. For example, as shown in FIG. 8C and FIG. 10, in a program operation, after the second final level verification, but before applying the next (N+3)th program voltage by the page buffer 304 and the control logic 312 of the peripheral circuit 102, a second standard final level VFC (Lk vfc, "third VFC") may be performed based on the result of the second final level verification and a standard VFC criterion ("third VFC criterion"). The standard VFC criterion may be the same for the first and second standard final level VFCs. In one example, the number of memory cells that fail the second final level verification may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against a default VFC criterion 1012 by the VFC controller 1010 of the control logic 312 to determine whether the first final level verification passes or fails.

[0080] In some implementations, the second verify and the third VFC are skipped in response to the result of the first verify satisfying the second VFC criteria. For example, as shown in FIG. 8B and FIG. 10, in a program operation, when the result of the first final level verify (shown as a filled box, i.e., passing the first final level verify under relaxed VFC criteria after applying the (N+2)th program voltage) satisfies the predicted VFC criteria, the second final level verify and the second standard final level VFC may be skipped after performing the first predicted final level VFC to finish the program operation.

[0081] FIG. 12 illustrates a block diagram of a system 1200 having a memory device according to some aspects of the disclosure. The system 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming machine, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 12, the system 1200 may include a memory system 1202 having a host 1208, as well as one or more memory devices 100 (shown in FIG. 1) and a memory controller 1206. The host 1208 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC) such as an application processor (AP). The host 1208 may be configured to send or receive data to or from the memory device 100.

[0082] The memory device 100 may be any memory device disclosed in this disclosure. According to some implementations, the memory controller 1206 is coupled to the memory device 100 and the host 1208 and configured to control the memory device 100. The memory controller 1206 can manage data stored in the memory device 100 and communicate with the host 1208. In some implementations, the memory controller 1206 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 1206 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptop computers, and enterprise storage arrays. The memory controller 1206 may be configured to control operations of the memory device 100, such as read operations, erase operations, and program operations. The memory controller 1206 may also be configured to manage various functions related to data stored or to be stored in the memory device 100, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 1206 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 100. Any other suitable functions, such as formatting the memory device 100, may also be performed by the memory controller 1206. The memory controller 1206 may communicate with an external device (e.g., a host 1208) according to a particular communication protocol.For example, the memory controller 1206 may communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small-Scale Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0083] The memory controller 1206 and one or more memory devices 100 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 1202 may be implemented and packaged into different types of end electronic products. In one example, as shown in FIG. 13A, the memory controller 1206 and a single memory device 100 may be integrated into a memory card 1302. The memory card 1302 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may further include a memory card connector 1304 that couples the memory card 1302 with a host (e.g., the host 1208 in FIG. 12). 13B, the memory controller 1206 and multiple memory devices 100 may be integrated into an SSD 1306. The SSD 1306 may further include an SSD connector 1308 that couples the SSD 1306 with a host (e.g., the host 1208 in FIG. 12). In some implementations, the storage capacity and / or operating speed of the SSD 1306 is greater than the storage capacity and / or operating speed of the memory card 1302.

[0084] The above description of specific implementations may be readily modified and / or adapted for various applications. As such, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0085] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0086] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. Also, the subject matter as described in this disclosure may be used in a variety of other applications as well. The functional and structural features as described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with one another and the scope of the present disclosure. [Explanation of symbols]

[0087] 100 Memory Devices 101 Memory cell array 102 Peripheral Circuit 104 Block 106 memory cells 108 NAND memory strings 110 Source Select Gate (SSG) Transistor 112 Drain Select Gate (DSG) Transistor 113 DSG Line 114 Source Line (SL) 115 SSG Line 116 bit lines 118 Word Line 120 pages 202 Substrate 204 Memory Stack 206 Gate Conductive Layer 208 Inter-gate dielectric layer 304 Page Buffer / Sense Amplifier 306 Column Decoder / Bit Line Driver 308 Row Decoder / Word Line Driver 310 Voltage Generator 312 Control Logic 314 Registers 316 Interface (I / F) 318 Data Bus 502 Program / Verify Cycles 504 Program Cycle 506 Verify Cycle 1004 Counter 1006 Latch 1008 Program / Verify Controller 1010 VFC Controller 1012 VFC Standard 1200 System 1202 Memory System 1206 Memory Controller 1208 Host 1302 Memory Card 1304 Memory card connector 1306 SSD 1308 SSD Connector

Claims

1. 1. A memory device comprising: An array of memory cells, at least one of the memory cells having two bits corresponding to an element of N-bit data. Ｎ an array of memory cells each set to one of N levels, where N is an integer greater than 1; and peripheral circuitry coupled to the array of memory cells, the peripheral circuitry comprising: applying a first program voltage to a selected row of the memory cells; After applying the first program voltage, Ｎ performing a first verify of the selected row of memory cells at a final one of the levels; performing a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion; applying a second program voltage to the selected row of memory cells after performing the first VFC, the second program voltage being greater than the first program voltage; performing a second VFC based on the result of the first verification and a second VFC standard different from the first VFC standard during a period during which the second program voltage is applied; Memory device.

2. 2. The memory device of claim 1, wherein the peripheral circuitry is configured to apply the second program voltage in response to the result of the first verify not meeting the first VFC standard.

3. The peripheral circuit is performing a second verify of the selected row of memory cells at the final level in response to the result of the first verify not meeting the second VFC criterion; and performing a third VFC based on a result of the second verification and a third VFC criterion. The memory device of claim 2 .

4. The peripheral circuit is and further configured to skip the second verification and the third VFC in response to the result of the first verification satisfying the second VFC criterion. The memory device of claim 3 .

5. The memory device of claim 3 or 4, wherein the third VFC reference is the same as the first VFC reference.

6. each of the memory cells further comprising a word line coupled to a row of the memory cells; To perform the first verification, the peripheral circuitry includes a word line driver configured to apply a verify voltage to a selected word line of the word line coupled to the selected row of the memory cells, the verify voltage being a voltage greater than or equal to the second verify voltage. Ｎ corresponding to the final level of the levels, A memory device according to any one of claims 1 to 5.

7. To implement the first VFC, the peripheral circuitry a page buffer configured to obtain a number of failed memory cells in the selected row of memory cells that do not pass the first verification; and and control logic configured to compare the number of failed memory cells against the first VFC standard. A memory device according to any one of claims 1 to 6.

8. The memory device of claim 1 , wherein the second VFC standard is less stringent than the first VFC standard.

9. 1. A memory device configured to store data, comprising: An array of rows of memory cells, at least one of the memory cells having two bits corresponding to an element of N-bit data. Ｎ an array of memory cells each set to one of N levels, where N is an integer greater than 1; a peripheral circuit coupled to the array of memory cells, applying a first program voltage to a selected row of the memory cells; After applying the first program voltage, Ｎ performing a first verify of the selected row of memory cells at a final one of the levels; performing a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion; applying a second program voltage to the selected row of memory cells after performing the first VFC in response to the result of the first verify not meeting the first VFC criterion, the second program voltage being greater than the first program voltage; a peripheral circuit configured to perform a second VFC based on the result of the first verification and a second VFC standard different from the first VFC standard during a period during which the second program voltage is applied; and a memory controller coupled to the memory device and configured to control the memory device; A system comprising:

10. The peripheral circuit is performing a second verify of the selected row of memory cells at the final level in response to the result of the first verify not meeting the second VFC criterion; and performing a third VFC based on a result of the second verification and a third VFC criterion. The system of claim 9.

11. The peripheral circuit is and further configured to skip the second verification and the third VFC in response to the result of the first verification satisfying the second VFC criterion. The system of claim 10.

12. To implement the first VFC, the peripheral circuitry a page buffer configured to obtain a number of failed memory cells in the selected row of memory cells that do not pass the first verification; and and control logic configured to compare the number of failed memory cells against the first VFC standard. A system according to any one of claims 9 to 11.

13. 13. The system of claim 9, wherein the second VFC standard is less stringent than the first VFC standard.

14. 13. A method of programming a memory device, the memory device comprising a row of memory cells, at least one of the memory cells including two bits corresponding to an element of N-bit data, the method comprising: Ｎ levels, where N is an integer greater than 1, and the method further comprises: applying a first program voltage to a selected one of the rows of memory cells; After applying the first program voltage, Ｎ performing a first validation of the selected row at a final one of the levels; performing a first verify failure count (VFC) based on a result of the first verification and a first VFC criterion; applying a second program voltage to the selected row after performing the first VFC, the second program voltage being higher than the first program voltage; and performing a second VFC based on the result of the first verification and a second VFC standard different from the first VFC standard during a period during which the second program voltage is applied. method.

15. 15. The method of claim 14, wherein the second program voltage is applied in response to the result of the first verify not meeting the first VFC criterion.

16. performing a second verification of the selected row at the final level in response to the result of the first verification not meeting the second VFC criterion; performing a third VFC based on a result of the second verification and a third VFC criterion; The method of claim 15 further comprising:

17. skipping the second verification and the third VFC in response to the result of the first verification satisfying the second VFC criteria.

20. The method of claim 16, further comprising:

18. 18. The method of claim 16 or 17, wherein the third VFC standard is the same as the first VFC standard.

19. The step of performing the first verification includes the step of applying a verify voltage to the selected row, the verify voltage being a voltage that is greater than or equal to the second verify voltage. Ｎ 19. The method of claim 14, wherein the final level of the levels corresponds to said final level.

20. The step of executing the first VFC comprises: obtaining a number of failed memory cells in the selected row that do not pass the first verification; comparing the number of failed memory cells against the first VFC standard.

20. The method according to any one of claims 14 to 19.

21. 21. The method of any one of claims 14 to 20, wherein the second VFC standard is less stringent than the first VFC standard.

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