Data Storage Circuit

Abstract

The present invention discloses a data storage circuit comprising a plurality of configuration registers (CONFIG_REG_i) provided for storing configuration data (WRDATAIN(31...0)), and an error detection unit configured to detect an error in the configuration data (WRDATAIN(31...0)) after storing the configuration data (WRDATAIN(31...0)) in the respective configuration registers (CONFIG_REG_i) and / or when checking the stored configuration data (WRDATAIN(31...0)) from the respective configuration registers (CONFIG_REG_i). A plurality of error detection units are also provided, where each configuration register (CONFIG_REG_i) is connected to a respective error detection unit to form a pair of associated functional units, or where a set of the same bit positions in the configuration registers (CONFIG_REG_i) are connected to a respective error detection unit to form a pair of associated functional units.

Description

[Technical field]

[0001] The present invention relates to a data storage circuit comprising a plurality of configuration registers provided for storing configuration data, wherein an error detection unit is configured to detect errors in the configuration data after storing the configuration data in the respective configuration registers and / or when checking the stored configuration data from the respective configuration registers. [Background technology]

[0002] Memories and registers must be protected against permanent and transient faults in safety-critical applications according to ISO standard 26262. Therefore, implementing safety mechanisms to detect and report such faults has been state of the art for many years.

[0003] EP 0 013 885 B1 discloses a method for preventing undesired parity error signals in a parity check of a register. A data field in the register is provided for storing a data byte including an associated parity bit. To provide a more flexible method, the register field has an associated parity bit latch arrangement with one respective further parity bit position for the register into which the digital bit is read prior to the parity check.

[0004] In contrast to registers that only temporarily store data, configuration registers are typically written to only once and configure critical functions in those systems-on-chips (SoCs), so errors occurring in these configuration registers can have catastrophic consequences with regard to functional safety according to ISO 26262.

[0005] In a system-on-chip, registers are typically written with data via a system bus. If these registers are to be protected, a parity bit is generated via the write data and the register is extended with this parity bit, which is written to the register together with the write data.

[0006] When reading a register, the read data and the read parity bits are checked by a parity checker. An error signal PERR is set for every one-bit error that occurs in the read parity bits or in the register data.

[0007] It is an object of the present invention to provide an improved data storage circuit that makes it possible to detect multiple faults in configuration registers, either due to hardware failures or due to unintentional writing of the configuration registers.

[0008] This object is achieved by a data storage circuit with the features of claim 1. Preferred embodiments are set out in the dependent claims. Summary of the Invention

[0009] According to the present invention, a plurality of error detection units are provided, where each configuration register is connected to a respective error detection unit to form a pair of associated functional units, or where a set of the same bit positions in the configuration register are connected to a respective error detection unit to form a pair of associated functional units.

[0010] In the case where the parity bit generated for each configuration data is written into the configuration register together with the associated configuration data, an error detection unit is connected downstream of each configuration register. The register data and the read parity bit are checked in each cycle by the associated error detection unit (parity checker). An error signal is set for every one-bit error that occurs in the read parity bit or in the register. This allows automatic recognition in real time that an error has occurred without software overhead. The configuration register is protected against one-bit errors by generating a parity bit via the write data and expanding the configuration register with this parity bit that is written into the register together with the write configuration data.

[0011] The advantage of this is that the register data is automatically checked every cycle without any software overhead and errors are detected in real time. Error correcting codes can be used as an extension of this procedure to make it possible to detect double-bit errors.

[0012] Alternatively, the same set of bit positions in the configuration registers can be connected to each error detection unit to form an associated pair of functional units. As before, a set of error detection units is connected downstream of each configuration register, such that each error detection unit is connected to a specific bit position of bits in the set of configuration registers. This allows the register data to be automatically checked every cycle to detect all multiple-bit errors without software overhead.

[0013] A parity generation unit may be provided for generating a parity bit for the configuration data, wherein the data storage circuit is configured to store the generated parity bit together with the associated configuration data in a respective configuration register, and the error detection unit is configured to read the stored parity bit in the associated configuration data, recalculate the parity bit for the read configuration data, and compare the stored parity bit with the recalculated parity bit to detect errors in the read configuration data or the read parity bit.

[0014] Thus, the configuration registers are extended with parity bits generated for the configuration data stored in the respective configuration register. When reading the stored parity bits and the associated configuration data, the error detection unit is able to detect faults in the configuration registers. Such faults may occur, for example, due to hardware faults or due to unintentional writing to the configuration registers. Fault detection may be performed by recalculating the parity bits for the read configuration data and comparing the stored parity bits read from the configuration data together with the associated configuration data with the recalculated parity bits in order to detect errors in the read configuration data or the read parity bits.

[0015] Multiple error detection units, each for an associated configuration register, allow real-time parity checking.

[0016] The error detection unit may also be configured to detect errors by the use of an error correction code, which may be a parity bit or may be a more complex code, which may allow for the correction of a detected error.

[0017] The error detection unit may be designed to include: - a parity generation unit arranged to generate a parity bit for a set of bits in the same position of the set of configuration registers; - a parity bit storage unit arranged to store each parity bit generated by an associated parity generation unit; a parity check unit for comparing the parity bit generated by the parity generation unit with a stored parity bit previously generated and stored in the parity bit storage unit to detect errors in the configuration data.

[0018] This allows for the recognition of all errors, including multiple errors, in real time.

[0019] A number of error detection units connected downstream of the configuration registers each combine the same bit position from the outputs of all the configuration registers, so that each bit position in all the configuration registers of the set of configuration registers is combined into an associated parity generation unit to generate a parity bit for the set of bits of all the configuration registers at the same bit position.

[0020] The parity bit is stored at the end of a write cycle of configuration data when the configuration data has been written to all or a portion of the configuration registers. The write cycle can be terminated after the set of configuration registers has been modified with the desired configuration data. This does not necessarily require that all configuration registers are written with their respective configuration data. It is sufficient to correct only those configuration data in the respective configuration registers that do not correspond to the desired configuration data.

[0021] When checking the configuration data from the configuration register, the parity check unit compares the parity bit generated by the parity generation unit for the read configuration data with the stored parity bit previously generated and stored in the parity bit storage unit to detect errors in the configuration data.

[0022] As before, a parity generation unit forms a functional unit with a set of bits in the same bit position in a set of configuration registers, as does a parity bit storage unit provided for storing respective parity bits for the sets of bits in the configuration registers having the same bit position.

[0023] This data storage circuit may be easily implemented and allow real-time detection of multi-bit errors.

[0024] The data storage units may be configured to store in the respective parity bit storage units the parity bits generated by the parity generation units immediately after the configuration data is written to all or a portion of the configuration registers, so that the generation of the parity bits may be performed when all the configuration data is available and stored in the configuration registers in the set of configuration registers.

[0025] The parity bit storage unit may be formed by a flip-flop provided for the set of error detection units, or it is also possible to use a register or any other suitable data memory to store the parity bit.

[0026] The error detection units may be configured to provide error flags at their outputs such that each of the error detection units provides a respective error flag indicative of an error when reading configuration data from the configuration register and comparing a stored parity bit for a set of bits in the same bit positions of a set of configuration data with a recalculated parity bit for the set of bits in the same bit positions.

[0027] Unintentional writing of at least one of the configuration registers CONFIG_REG_i may be inhibited by use of a gated clock clk_cfg for the configuration register CONFIG_REG_i to allow writing of control data to the respective configuration register CONFIG_REG_i only if the gated clock clk_cfg is enabled.

[0028] A clock gate CG2 may be provided to generate a clock signal clk_cfg from the system clock signal at the input of the clock gate CG2 and a configuration active signal CACT. A configuration active register CACT_REG is provided to store the configuration active signal CACT for the intended write cycle.

[0029] After configuration, the configuration active signal CACT in the configuration active register CACT_REG will be set to "0", with the consequence that all unintended accesses to one of the configuration registers CONFIG_REG_i are prohibited.

[0030] The invention is explained in more detail by means of exemplary embodiments in the enclosed drawings. [Brief description of the drawings]

[0031] [Figure 1] FIG. 1 is a block diagram of a conventional data storage unit according to the prior art. [Diagram 2]FIG. 2 is a block diagram of a first embodiment of a data storage circuit with an error detection unit for each configuration register. [Diagram 3] FIG. 3 is a block diagram of a second embodiment of a data storage unit. [Figure 4] FIG. 4 is a table of parity bits calculated from bits in the same bit position of the configuration register. [Diagram 5] FIG. 5 shows a block diagram of a third embodiment of a data storage unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] In the following, a bit width (i.e., register width) of 32 bits is merely an example, and the data storage unit may be appropriately designed for any other bit width and respective width of the registers without departing from the technical solution.

[0033] FIG. 1 shows a block diagram of a conventional data storage unit according to the prior art. Configuration data is written via a data bus BUS, where the configuration data WRDATAIN(31...0) is provided to a parity generator Parity_GEN for generating a parity bit P from the configuration data. Furthermore, the configuration data WRDATAIN(31...0) is written to respective configuration registers CONFIG_REG_0,...,CONFIG_REG_n. The configuration registers CONFIG_REG_0,...,CONFIG_REG_n can be accessed by respective individual register addresses. Each of the configuration registers comprises storage capacity for bits of configuration data, e.g., bits 0...31. Furthermore, the parity bit P generated by the parity generator for each configuration data WRDATAIN(31...0) is written to the respective configuration register CONFIG_REG_i.

[0034] When reading configuration data from the respective configuration register CONFIG_REG_i, the configuration data is provided to a data bus BUS. The read configuration data DOUT(31...0) is further forwarded to a parity check unit Parity_CHECK. The parity check unit Parity_CHECK is configured to recalculate a parity bit for the configuration data DOUT(31...0) and to compare this recalculated parity bit with a parity bit P also read from the configuration register CONFIG_REG_i. In case of a mismatch between the stored and read parity bit P and the recalculated parity bit, an error flag PERR_i is set at the output of the parity check unit Parity_CHECK.

[0035] The selection of the configuration register CONFIG_REG_i for reading the configuration data DOUT(31...0) is performed by a multiplexer Read_Mux. Each configuration register CONFIG_REG_i is connected to a respective input of the multiplexer Read_Mux, where the output of the multiplexer Read_Mux is connected to the output data bus BUS and to the parity check unit Parity_CHECK.

[0036] 2 shows a first embodiment of a data storage unit, also comprising a bus for carrying configuration data. The bus is connected to a set of configuration registers CONFIG_REG_0, ..., CONFIG_REG_n for storing configuration data WRDATAIN(31...0) in each assigned configuration register CONFIG_REG_i.

[0037] As before, a parity generation unit Parity_GEN is provided for generating parity bits for the configuration data WRDATAIN(31...0) for writing a respective parity bit P together with the associated configuration data WRDATAIN(31...0) to an associated configuration register CONFIG_REG_i.

[0038] This corresponds to the conventional data storage unit shown in FIG.

[0039] To read configuration data from a configuration register CONFIG_REG_i, the input of the multiplexer Read_Mux is again connected to the respective configuration register CONFIG_REG_i for transferring the configuration data DOUT(31...0) from the configuration register CONFIG_REG_i to the data bus BUS.

[0040] A parity check for one selected configuration register CONFIG_REG_i may also be performed in the bus system.

[0041] Downstream, i.e. at the output of each configuration register CONFIG_REG_i, an error detection unit Parity_CHECK_i is provided to read the stored parity bit P in the respective configuration register CONFIG_REG_i and to recalculate the parity bit from the stored and read configuration data DOUTi(31...0) stored in the respective configuration register CONFIG_REG_i. Each error detection unit may be designed in the form of a check unit Parity_CHECK_i to compare the parity bit P stored in the configuration register CONFIG_REG_i with the recalculated parity bit and to provide a parity error flag PERR_i at the output of the error detection unit Parity_CHECK_i.

[0042] This allows to indicate in real time, without any software support, the setting of the parity error flag PERR_i for each of the configuration registers CONFIG_REG_i. Using the Parity-Bit, only one bit error will be detected, but an ECC code can also be used to detect two bit errors.

[0043] FIG. 3 shows a second embodiment of a data storage circuit that allows detection of multi-bit errors.

[0044] As before, the configuration registers CONFIG_REG_i are connected to a data bus BUS for writing configuration data WRDATAIN(31...0) provided on the data bus to each assigned configuration register CONFIG_REG_i. The configuration registers CONFIG_REG_i have storage capacity for bits of configuration data, e.g., 0 to 31 for 32 bits. The invention is not limited to this 32 bit example and may be used for any other bit length of configuration data.

[0045] After the set of configuration data is written to the configuration register CONFIG_REG_i, the end of this write cycle is indicated by the bit WRDATAIN(0), which is transferred to the bit register CEND_REG. This indicates that the write cycle is finalized, meaning that all the configuration data has been written to all or part of the configuration registers so that it is available in the set of configuration registers. By using a clock gate CG1, whose inputs are the system clock signal sys_clock and a bit provided with a configuration end signal CEND from the configuration end register CEND_REG, the output of this clock gate CG1 provides the clock clk_par for writing the parity bit storage unit.

[0046] The configuration end signal CEND is only active for one cycle since it is constructed from the configuration end register CEND_REG and the respective WE signals (write enable) of the bit error detection units.

[0047] A set of error detection units, each comprising a parity generation unit Parity_GEN_i, allows generating parity bits for a set of bits at the same bit position in a set of configuration registers CONFIG_REG_0,...,CONFIG_REG_n. Thus, a parity bit for the first bit of all configuration data stored in configuration registers CONFIG_REG_0 to n is calculated and provided at the output of each parity generation unit Parity_GEN_i for the respective bit position. For example, a parity bit generation unit Parity_GEN_0 is connected to the 1st bit position of all configuration registers CONFIG_REG_0 to n, while a parity generation unit Parity_GEN_31 is connected to the 31st bit position of all configuration registers CONFIG_REG_0 to n.

[0048] The output of each parity generation unit Parity_GEN_i is connected to a respective storage unit, for example flip-flops FF0, . . . , FF31, which will store the recalculated parity bit with CEND only.

[0049] Each storage unit FF0, ..., FF31 is controlled by the clock clk_par to store the respective parity bit generated by the associated parity generation unit Parity_GEN_i when the write cycle is completed and new configuration data is written to the last configuration register CONFIG_REG_n to be written in the write cycle.

[0050] The output of each storage unit FFi is connected to an associated parity check unit EXOR0, ..., EXORi, ..., EXOR31 (exclusive OR) for comparing the parity bit provided at the output of the associated parity generation unit Parity_GEN_i with the parity bit stored in the parity bit storage unit FFi. For example, the parity check unit Parity_CHECK can be designed as an EXOR gate. The output is an error flag PERR_i.

[0051] The parity generation units Parity_GEN_i are connected (hardwired) to the output of a set of configuration registers CONFIG_REG_i. The configuration data stored in each configuration register CONFIG_REG_i is "always" present as digital information (high or low voltage) at the input of the parity generation unit Parity_GEN_i due to the hardwired connection. A parity check can be performed in real time every time a configuration register changes. The stored configuration data is always present at the input of the parity generation unit Parity_GEN_i due to the hardwired connection. The parity generation units Parity_GEN_i are capable of providing a respective parity bit Pi at their respective output by combining a set of input bits selected from the configuration data, as shown, for example, in FIG. 4. Thus, every time any bit in the configuration data stored in the configuration registers CONFIG_REG_0 to CONFIG_REG_n changes due to a new write or a failure of configuration data to at least one configuration register CONFIG_REG_i, at least one parity bit Pi changes, so that this change can be detected in real time.

[0052] Storing the pre-generated parity bit Pi in the flip-flop FFi protects the configuration register CONFIG_REG_i from unintended write operations and disturbances of the configuration register CONFIG_REG_i.

[0053] 4 shows a table of the relationship of the parity bits P0, P1, ..., P31 provided for each of the bit positions 0, i, ..., 31. Each parity bit is calculated by combining the bits in the same bit position in all of the configuration registers CONFIG_REG_0, ..., n.

[0054] For example, the parity bit P0 for bit position zero is calculated from bit position 0 of all configuration registers, namely, CONFIG_REG_0(000), CONFIG_REG_1(0), CONFIG_REG_2(0), ..., CONFIG_REG_n(0).

[0055] The parity bit P31 for the last bit position 31 is calculated from the 31st bits in all configuration registers, namely CONFIG_REG_0(31), CONFIG_REG_1(31), ..., CONFIG_REG_n(31).

[0056] 5 shows a block diagram of a third embodiment of a data storage unit. The design provided for parity checking by using a parity generation unit Parity_GEN_i and a flip-flop unit FFi corresponds to the first embodiment shown in FIG. 2 or, as an example, corresponds to the second embodiment shown in FIG. 3.

[0057] A write of a configuration register CONFIG_REG_i necessarily requires a write clock signal clk_cfg at the clock input of each of the configuration registers CONFIG_REG_0 to CONFIG_REG_n, where n is an integer number of maximum number of configuration registers. The write clock signal clk_cfg is generated at the output of clock gate CG2 from the system clock signal sys_clock and the configuration active CACT signal at the inputs of clock gate CG2.

[0058] The configuration active registers CACT_REG are connected to the data bus BUS and write WRDATAIN(i) presented on the data bus to their respective assigned configuration active registers CACT_REG.

[0059] For example, the first bit WRDATAIN(0) is used to set the configuration active signal CACT in the configuration active register CACT_REG.

[0060] During an active CACT signal, the clock signal clk_cfg is enabled so that the configuration registers CONFIG_REG_i can be modified.

[0061] During the configuration cycle, the generation of the error flag PERR_i may be gated by the configuration active signal CACT.

[0062] After all intended configuration register modifications, the configuration active signal CACT in the configuration active register CACT_REG should be set to the inactive state.

[0063] Thus, unintentional writing of at least one of the configuration registers CONFIG_REG_i is inhibited by gating the clock signal clk_cfg with an inactive configuration active signal CACT at clock gate CG2.

Claims

1. 1. A data storage circuit comprising a plurality of configuration registers (CONFIG_REG_i) arranged for storing configuration data (WRDATAIN(31...0)), wherein an error detection unit is arranged to detect an error in said configuration data (WRDATAIN(31...0)) after storing said configuration data (WRDATAIN(31...0)) in said respective configuration register (CONFIG_REG_i) and / or when checking said stored configuration data (WRDATAIN(31...0)) from said respective configuration register (CONFIG_REG_i), A data storage circuit comprising a plurality of error detection units, wherein each configuration register (CONFIG_REG_i) is connected to a respective error detection unit to form a pair of associated functional units, or wherein a set of the same bit positions in the configuration register (CONFIG_REG_i) are connected to a respective error detection unit to form a pair of associated functional units.

2. The data storage circuit is characterized by a parity generation unit (Parity_GEN_i) arranged to generate a parity bit (P) for configuration data (WRDATAIN(31...0)), wherein the data storage circuit is arranged to store the generated parity bit (P) together with the associated configuration data (WRDATAIN(31...0)) in the respective configuration register (CONFIG_REG_i), wherein the error detection unit detects the stored parity bit (P).

2. The data storage circuit of claim 1, configured to read a parity bit (P) and the associated configuration data (WRDATAIN(31 . . . 0)), recalculate the parity bit (P) for the read configuration data (DOUT(31 . . . 0)), and compare the stored parity bit (P) with the recalculated parity bit (P) to detect errors in the read configuration data (DOUT(31 . . . 0)) or the read parity bit (P).

3. 3. A data storage circuit as claimed in claim 1 or 2, characterized in that the error detection unit is arranged to detect errors by use of an error correcting code.

4. Each error detection unit: a parity generation unit (Parity_GEN_i) arranged to generate a parity bit (P) for said set of bits in said same position of said set of configuration registers (CONFIG_REG_i); a parity bit (P) storage unit arranged to store each parity bit (P) generated by said associated parity generation unit (Parity_GEN_i); a parity check unit (Parity_CHECK) for comparing the parity bit (P) generated by the parity generation unit (Parity_GEN_i) with the stored parity bit (P) previously generated and stored in the parity bit storage unit in order to detect errors in the configuration data (WRDATAIN(31..0)), 2. The data storage circuit according to claim 1, comprising:

5. 5. The data storage unit of claim 4, wherein the data storage circuit is configured to store the parity bit (P) generated by the parity generation unit (Parity_GEN_i) in the respective parity bit storage unit once in a write cycle immediately after configuration data (WRDATAIN(31...0)) is written to all configuration registers (CONFIG_REG_i) or to a portion of the configuration registers (CONFIG_REG_i).

6. 6. A data storage unit as claimed in claim 5, characterized in that a clock gate (CG1) is provided for generating a clock signal (clk_par) from a system clock signal (sys_clock) and a configuration end signal (CEND) at the input of said clock gate (CG1), and a configuration end register (CEND_REG) is provided for storing said configuration end signal (CEND) for exactly one cycle.

7. 7. A data storage circuit according to claim 4, 5 or 6, characterized in that the parity bit storage unit is formed by a flip-flop (FFi) provided for the set of error detection units.

8. A data storage circuit as claimed in any one of the preceding claims, characterised in that each error detection unit provides an error flag (PERR_i) at the output of each of said error detection units.

9. 9. The data storage circuit of claim 8, wherein each error detection unit provides an error flag (PERR_i) at the output of each of the error detection units only if a configuration active signal (CACT) is inactive, where an active configuration active signal (CACT) indicates an ongoing write cycle and an inactive configuration active signal (CACT) indicates the end of a write cycle.

10. 10. The data storage circuit of claim 9, wherein an AND gate (&) is provided for disabling the provision of the error flag (PERR_i) during configuration.

11. 11. A data storage circuit as claimed in any one of claims 1 to 10, characterized in that the configuration registers (CONFIG_REG_i) comprise a configuration clock input (clk_cfg) for enabling the writing of control data to the respective configuration register (CONFIG_REG_i), wherein a clock gate (CG2) is provided for generating the clock signal (clk_cfg) from a system clock signal (sys_clock) and a configuration active signal (CACT) at the input of the clock gate (CG2), and wherein a configuration active register (CACT_REG) is provided for storing the configuration active signal (CACT) for an intended write cycle.

Images